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Fri, 3 Nov 2023 21:53:31 GMT Received: from hyd-lablnx450.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Fri, 3 Nov 2023 14:53:26 -0700 From: Bibek Kumar Patro To: , , , , , , , , CC: , , , , "Bibek Kumar Patro" Subject: [PATCH 1/3] iommu/arm-smmu: introduction of ACTLR for custom prefetcher settings Date: Sat, 4 Nov 2023 03:21:22 +0530 Message-ID: <20231103215124.1095-2-quic_bibekkum@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231103215124.1095-1-quic_bibekkum@quicinc.com> References: <20231103215124.1095-1-quic_bibekkum@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 4br19zr-C73j-Ru4uY_2cLuQkRIe6WOj X-Proofpoint-GUID: 4br19zr-C73j-Ru4uY_2cLuQkRIe6WOj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-03_21,2023-11-02_03,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 adultscore=0 priorityscore=1501 lowpriorityscore=0 mlxlogscore=999 impostorscore=0 suspectscore=0 clxscore=1015 bulkscore=0 spamscore=0 malwarescore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2310240000 definitions=main-2311030185 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231103_145341_234392_90743941 X-CRM114-Status: GOOD ( 26.73 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Currently in Qualcomm SoCs the default prefetch is set to 1 which allows the TLB to fetch just the next page table. MMU-500 features ACTLR register which is implementation defined and is used for Qualcomm SoCs to have a prefetch setting of 1/3/7/15 enabling TLB to prefetch the next set of page tables accordingly allowing for faster translations. ACTLR value is unique for each SMR (Stream matching register) and stored in a pre-populated table. This value is set to the register during context bank initialisation. Signed-off-by: Bibek Kumar Patro --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 34 ++++++++++++++++++++++ drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h | 2 ++ drivers/iommu/arm/arm-smmu/arm-smmu.c | 5 ++-- drivers/iommu/arm/arm-smmu/arm-smmu.h | 5 ++++ 4 files changed, 44 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index ae7cae015193..68c1f4908473 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -14,6 +14,17 @@ #define QCOM_DUMMY_VAL -1 +struct actlr_config { + const struct actlr_data *adata; + u32 size; +}; + +struct actlr_data { + u16 sid; + u16 mask; + u32 actlr; +}; + static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu) { return container_of(smmu, struct qcom_smmu, smmu); @@ -270,6 +281,26 @@ static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = { static int qcom_smmu_init_context(struct arm_smmu_domain *smmu_domain, struct io_pgtable_cfg *pgtbl_cfg, struct device *dev) { + struct arm_smmu_device *smmu = smmu_domain->smmu; + struct qcom_smmu *qsmmu = to_qcom_smmu(smmu); + const struct actlr_config *actlrcfg; + struct arm_smmu_smr *smr = smmu->smrs; + int idx = smmu_domain->cfg.cbndx; + int i; + u16 id; + u16 mask; + + if (qsmmu->actlrcfg) { + actlrcfg = qsmmu->actlrcfg; + for (i = 0; i < actlrcfg->size; ++i) { + id = actlrcfg->adata[i].sid; + mask = actlrcfg->adata[i].mask; + if (!smr_is_subset(*smr, id, mask)) + arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_ACTLR, + actlrcfg->adata[i].actlr); + } + } + smmu_domain->cfg.flush_walk_prefer_tlbiasid = true; return 0; @@ -459,6 +490,9 @@ static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu, qsmmu->smmu.impl = impl; qsmmu->cfg = data->cfg; + if (data->actlrcfg && (data->actlrcfg->size)) + qsmmu->actlrcfg = data->actlrcfg; + return &qsmmu->smmu; } diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h index 593910567b88..4b6862715070 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h @@ -9,6 +9,7 @@ struct qcom_smmu { struct arm_smmu_device smmu; const struct qcom_smmu_config *cfg; + const struct actlr_config *actlrcfg; bool bypass_quirk; u8 bypass_cbndx; u32 stall_enabled; @@ -25,6 +26,7 @@ struct qcom_smmu_config { }; struct qcom_smmu_match_data { + const struct actlr_config *actlrcfg; const struct qcom_smmu_config *cfg; const struct arm_smmu_impl *impl; const struct arm_smmu_impl *adreno_impl; diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c index 4c79ef6f4c75..38ac1cbc799b 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c @@ -992,9 +992,10 @@ static int arm_smmu_find_sme(struct arm_smmu_device *smmu, u16 id, u16 mask) * expect simply identical entries for this case, but there's * no harm in accommodating the generalisation. */ - if ((mask & smrs[i].mask) == mask && - !((id ^ smrs[i].id) & ~smrs[i].mask)) + + if (smr_is_subset(smrs[i], id, mask)) return i; + /* * If the new entry has any other overlap with an existing one, * though, then there always exists at least one stream ID diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h index 703fd5817ec1..b1638bbc41d4 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h @@ -501,6 +501,11 @@ static inline void arm_smmu_writeq(struct arm_smmu_device *smmu, int page, writeq_relaxed(val, arm_smmu_page(smmu, page) + offset); } +static inline bool smr_is_subset(struct arm_smmu_smr smrs, u16 id, u16 mask) +{ + return (mask & smrs.mask) == mask && !((id ^ smrs.id) & ~smrs.mask); +} + #define ARM_SMMU_GR0 0 #define ARM_SMMU_GR1 1 #define ARM_SMMU_CB(s, n) ((s)->numpage + (n)) From patchwork Fri Nov 3 21:51:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bibek Kumar Patro X-Patchwork-Id: 13445174 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D2106C4332F for ; Fri, 3 Nov 2023 21:54:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Fri, 3 Nov 2023 21:53:36 GMT Received: from hyd-lablnx450.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Fri, 3 Nov 2023 14:53:31 -0700 From: Bibek Kumar Patro To: , , , , , , , , CC: , , , , "Bibek Kumar Patro" Subject: [PATCH 2/3] iommu/arm-smmu: add ACTLR data and support for SM8550 Date: Sat, 4 Nov 2023 03:21:23 +0530 Message-ID: <20231103215124.1095-3-quic_bibekkum@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231103215124.1095-1-quic_bibekkum@quicinc.com> References: <20231103215124.1095-1-quic_bibekkum@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: M2pdkuPqEFYEHa-TVOAKW_7vv2q7NHzx X-Proofpoint-ORIG-GUID: M2pdkuPqEFYEHa-TVOAKW_7vv2q7NHzx X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-03_20,2023-11-02_03,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 impostorscore=0 suspectscore=0 priorityscore=1501 malwarescore=0 mlxlogscore=999 spamscore=0 bulkscore=0 lowpriorityscore=0 clxscore=1015 mlxscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2310240000 definitions=main-2311030185 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231103_145345_453923_1CA6E144 X-CRM114-Status: GOOD ( 19.28 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add ACTLR data table for SM8550 along with support for same including SM8550 specific implementation operations. Signed-off-by: Bibek Kumar Patro --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 85 +++++++++++++++++++++- 1 file changed, 81 insertions(+), 4 deletions(-) -- 2.17.1 diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index 68c1f4908473..590b7c285299 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -25,6 +25,64 @@ struct actlr_data { u32 actlr; }; +static const struct actlr_data sm8550_apps_actlr_data[] = { + { 0x18a0, 0x0000, 0x00000103 }, + { 0x18e0, 0x0000, 0x00000103 }, + { 0x0800, 0x0020, 0x00000001 }, + { 0x1800, 0x00c0, 0x00000001 }, + { 0x1820, 0x0000, 0x00000001 }, + { 0x1860, 0x0000, 0x00000001 }, + { 0x0c01, 0x0020, 0x00000303 }, + { 0x0c02, 0x0020, 0x00000303 }, + { 0x0c03, 0x0020, 0x00000303 }, + { 0x0c04, 0x0020, 0x00000303 }, + { 0x0c05, 0x0020, 0x00000303 }, + { 0x0c06, 0x0020, 0x00000303 }, + { 0x0c07, 0x0020, 0x00000303 }, + { 0x0c08, 0x0020, 0x00000303 }, + { 0x0c09, 0x0020, 0x00000303 }, + { 0x0c0c, 0x0020, 0x00000303 }, + { 0x0c0d, 0x0020, 0x00000303 }, + { 0x0c0e, 0x0020, 0x00000303 }, + { 0x0c0f, 0x0020, 0x00000303 }, + { 0x1961, 0x0000, 0x00000303 }, + { 0x1962, 0x0000, 0x00000303 }, + { 0x1963, 0x0000, 0x00000303 }, + { 0x1964, 0x0000, 0x00000303 }, + { 0x1965, 0x0000, 0x00000303 }, + { 0x1966, 0x0000, 0x00000303 }, + { 0x1967, 0x0000, 0x00000303 }, + { 0x1968, 0x0000, 0x00000303 }, + { 0x1969, 0x0000, 0x00000303 }, + { 0x196c, 0x0000, 0x00000303 }, + { 0x196d, 0x0000, 0x00000303 }, + { 0x196e, 0x0000, 0x00000303 }, + { 0x196f, 0x0000, 0x00000303 }, + { 0x19c1, 0x0010, 0x00000303 }, + { 0x19c2, 0x0010, 0x00000303 }, + { 0x19c3, 0x0010, 0x00000303 }, + { 0x19c4, 0x0010, 0x00000303 }, + { 0x19c5, 0x0010, 0x00000303 }, + { 0x19c6, 0x0010, 0x00000303 }, + { 0x19c7, 0x0010, 0x00000303 }, + { 0x19c8, 0x0010, 0x00000303 }, + { 0x19c9, 0x0010, 0x00000303 }, + { 0x19cc, 0x0010, 0x00000303 }, + { 0x19cd, 0x0010, 0x00000303 }, + { 0x19ce, 0x0010, 0x00000303 }, + { 0x19cf, 0x0010, 0x00000303 }, + { 0x1c00, 0x0002, 0x00000103 }, + { 0x1c01, 0x0000, 0x00000001 }, + { 0x1920, 0x0000, 0x00000103 }, + { 0x1923, 0x0000, 0x00000103 }, + { 0x1924, 0x0000, 0x00000103 }, + { 0x1940, 0x0000, 0x00000103 }, + { 0x1941, 0x0004, 0x00000103 }, + { 0x1943, 0x0000, 0x00000103 }, + { 0x1944, 0x0000, 0x00000103 }, + { 0x1947, 0x0000, 0x00000103 }, +}; + static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu) { return container_of(smmu, struct qcom_smmu, smmu); @@ -444,6 +502,16 @@ static const struct arm_smmu_impl sdm845_smmu_500_impl = { .tlb_sync = qcom_smmu_tlb_sync, }; + +static const struct arm_smmu_impl sm8550_smmu_500_impl = { + .init_context = qcom_smmu_init_context, + .cfg_probe = qcom_smmu_cfg_probe, + .def_domain_type = qcom_smmu_def_domain_type, + .reset = arm_mmu500_reset, + .write_s2cr = qcom_smmu_write_s2cr, + .tlb_sync = qcom_smmu_tlb_sync, +}; + static const struct arm_smmu_impl qcom_adreno_smmu_v2_impl = { .init_context = qcom_adreno_smmu_init_context, .def_domain_type = qcom_smmu_def_domain_type, @@ -507,6 +575,11 @@ static const struct qcom_smmu_config qcom_smmu_impl0_cfg = { .reg_offset = qcom_smmu_impl0_reg_offset, }; +static const struct actlr_config sm8550_actlrcfg = { + .adata = sm8550_apps_actlr_data, + .size = ARRAY_SIZE(sm8550_apps_actlr_data), +}; + /* * It is not yet possible to use MDP SMMU with the bypass quirk on the msm8996, * there are not enough context banks. @@ -530,16 +603,20 @@ static const struct qcom_smmu_match_data sdm845_smmu_500_data = { /* Also no debug configuration. */ }; + +static const struct qcom_smmu_match_data sm8550_smmu_500_impl0_data = { + .impl = &sm8550_smmu_500_impl, + .adreno_impl = &qcom_adreno_smmu_500_impl, + .cfg = &qcom_smmu_impl0_cfg, + .actlrcfg = &sm8550_actlrcfg, +}; + static const struct qcom_smmu_match_data qcom_smmu_500_impl0_data = { .impl = &qcom_smmu_500_impl, .adreno_impl = &qcom_adreno_smmu_500_impl, .cfg = &qcom_smmu_impl0_cfg, }; -/* - * Do not add any more qcom,SOC-smmu-500 entries to this list, unless they need - * special handling and can not be covered by the qcom,smmu-500 entry. - */ static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = { { .compatible = "qcom,msm8996-smmu-v2", .data = &msm8996_smmu_data }, { .compatible = "qcom,msm8998-smmu-v2", .data = &qcom_smmu_v2_data }, From patchwork Fri Nov 3 21:51:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bibek Kumar Patro X-Patchwork-Id: 13445175 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9CC4AC4332F for ; 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Fri, 03 Nov 2023 21:53:43 +0000 Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3A3Lrgl1003873 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 3 Nov 2023 21:53:42 GMT Received: from hyd-lablnx450.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Fri, 3 Nov 2023 14:53:37 -0700 From: Bibek Kumar Patro To: , , , , , , , , CC: , , , , "Bibek Kumar Patro" Subject: [PATCH 3/3] iommu/arm-smmu: re-enable context caching in smmu reset operation Date: Sat, 4 Nov 2023 03:21:24 +0530 Message-ID: <20231103215124.1095-4-quic_bibekkum@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231103215124.1095-1-quic_bibekkum@quicinc.com> References: <20231103215124.1095-1-quic_bibekkum@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: Ka13ShKkXK6Ou-x76CJAWjncfLG9z9jS X-Proofpoint-GUID: Ka13ShKkXK6Ou-x76CJAWjncfLG9z9jS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-03_21,2023-11-02_03,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 mlxscore=0 spamscore=0 malwarescore=0 suspectscore=0 impostorscore=0 mlxlogscore=999 bulkscore=0 lowpriorityscore=0 adultscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2310240000 definitions=main-2311030185 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231103_145351_656914_876CC067 X-CRM114-Status: GOOD ( 18.84 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Context caching is re-enabled in the prefetch buffer for Qualcomm SoCs through SoC specific reset ops, which is disabled in the default MMU-500 reset ops, but is expected for context banks using ACTLR register to retain the prefetch value during reset and runtime suspend. Signed-off-by: Bibek Kumar Patro --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 26 ++++++++++++++++++---- 1 file changed, 22 insertions(+), 4 deletions(-) -- 2.17.1 diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index 590b7c285299..f342b4778cf1 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -457,11 +457,29 @@ static int qcom_smmu_def_domain_type(struct device *dev) return match ? IOMMU_DOMAIN_IDENTITY : 0; } +#define ARM_MMU500_ACTLR_CPRE BIT(1) + +static int qcom_smmu500_reset(struct arm_smmu_device *smmu) +{ + int i; + u32 reg; + + arm_mmu500_reset(smmu); + + for (i = 0; i < smmu->num_context_banks; ++i) { + reg = arm_smmu_cb_read(smmu, i, ARM_SMMU_CB_ACTLR); + reg |= ARM_MMU500_ACTLR_CPRE; + arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_ACTLR, reg); + } + + return 0; +} + static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu) { int ret; - arm_mmu500_reset(smmu); + qcom_smmu500_reset(smmu); /* * To address performance degradation in non-real time clients, @@ -488,7 +506,7 @@ static const struct arm_smmu_impl qcom_smmu_500_impl = { .init_context = qcom_smmu_init_context, .cfg_probe = qcom_smmu_cfg_probe, .def_domain_type = qcom_smmu_def_domain_type, - .reset = arm_mmu500_reset, + .reset = qcom_smmu500_reset, .write_s2cr = qcom_smmu_write_s2cr, .tlb_sync = qcom_smmu_tlb_sync, }; @@ -507,7 +525,7 @@ static const struct arm_smmu_impl sm8550_smmu_500_impl = { .init_context = qcom_smmu_init_context, .cfg_probe = qcom_smmu_cfg_probe, .def_domain_type = qcom_smmu_def_domain_type, - .reset = arm_mmu500_reset, + .reset = qcom_smmu500_reset, .write_s2cr = qcom_smmu_write_s2cr, .tlb_sync = qcom_smmu_tlb_sync, }; @@ -523,7 +541,7 @@ static const struct arm_smmu_impl qcom_adreno_smmu_v2_impl = { static const struct arm_smmu_impl qcom_adreno_smmu_500_impl = { .init_context = qcom_adreno_smmu_init_context, .def_domain_type = qcom_smmu_def_domain_type, - .reset = arm_mmu500_reset, + .reset = qcom_smmu500_reset, .alloc_context_bank = qcom_adreno_smmu_alloc_context_bank, .write_sctlr = qcom_adreno_smmu_write_sctlr, .tlb_sync = qcom_smmu_tlb_sync,