From patchwork Mon Nov 6 11:02:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13446617 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BEA011A5A3 for ; Mon, 6 Nov 2023 11:03:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="A3eVwSza" Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [IPv6:2a00:1450:4864:20::32e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 53F36D8 for ; Mon, 6 Nov 2023 03:03:48 -0800 (PST) Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-407da05f05aso30502905e9.3 for ; Mon, 06 Nov 2023 03:03:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699268627; x=1699873427; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1L9VmGyQhU2xkGMEVSpI4IfVFp3akp+nAwSDeWPJyrs=; b=A3eVwSzaSYki1dGnz2ik6DHSo85yBr67k49znaAOTpN9kUL1wSaxUhRhMrjGuiTx+z 0bN7E2lanESedXbvj1djYwmvq4dynv7pIG7LSYfwW0GOkpVeVc82l3yNvHAzTDz/0eI2 hFhgwon72PHbTP7SLX8sqE9vAo8tZVsYHVw1SKpNkHX5aHMJ5qH/gOLSvnU5NgdVa5f2 3Ae2nBC5lfKmhb81cm2vbyOVHk8t59OoLkvP4i2CWJXUoj1dzL/YlgWundR6cgOaaSNy G5oSSCRxAN8apqRwoN/8isIMH6v5IZViFuEg3+Ynth1YplDeKp+yGfTs6Ukm8g1au/H2 Fypg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699268627; x=1699873427; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1L9VmGyQhU2xkGMEVSpI4IfVFp3akp+nAwSDeWPJyrs=; b=VflNn19oZJXRdj8y8rcYwUgikiZ2vSdCJOGoQuXzaCMPUubsmgWggtPdNBYeV2NS7r IjZAh/MVnoJxSBxGHKJsAiqcwkrgBGUOtyEShek5qS65q+bRTjwwRQdOMBPqXs6fzE16 AQCkYbZ0sqRhY7WhJy/E2j7l4D+qQQRk6s5CpkuUBWyPHTAtecGk1+WfQbaWoMELyad0 5Pn+szm1z2CGQSKMDpkv7+Ri/hjli5qknPJ6ztf1FqOggBvlx3ErhKd35PlD/T80Fzjf nxPNtoQnDDcWqA5aJzdJps/4yzgSxkJlY9Tu+wQk5TbtDo2z5v3lGQEZpI3lPXQ+j7ad TEvA== X-Gm-Message-State: AOJu0YxZBhpv7ZzuCiw7rHITVMlMM84kUb3Xgs4tB8TGfhl3oytRcVBI cfREB9lnhZ2tO8lnQFYe501c00st7cFVcf/12MI= X-Google-Smtp-Source: AGHT+IGVsR41OZiJW09UO8f2QQjHedYyrhNpAeIFY/pbatQ8PPEnpOP8OnIgt0CWNcPde4ZS+yy1Rw== X-Received: by 2002:a05:600c:19ca:b0:406:8c7a:9520 with SMTP id u10-20020a05600c19ca00b004068c7a9520mr22789124wmq.36.1699268625910; Mon, 06 Nov 2023 03:03:45 -0800 (PST) Received: from m1x-phil.lan (176-131-220-199.abo.bbox.fr. [176.131.220.199]) by smtp.gmail.com with ESMTPSA id q8-20020a05600c46c800b0040776008abdsm11817395wmo.40.2023.11.06.03.03.44 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:03:45 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Akihiko Odaki , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Paolo Bonzini Subject: [PULL 01/60] vl: Free machine list Date: Mon, 6 Nov 2023 12:02:33 +0100 Message-ID: <20231106110336.358-2-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Akihiko Odaki Free machine list and make LeakSanitizer happy. Signed-off-by: Akihiko Odaki Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20230722062641.18505-1-akihiko.odaki@daynix.com> Signed-off-by: Philippe Mathieu-Daudé --- system/vl.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/system/vl.c b/system/vl.c index 3fb569254a..ff76eb0d07 100644 --- a/system/vl.c +++ b/system/vl.c @@ -1529,7 +1529,8 @@ static gint machine_class_cmp(gconstpointer a, gconstpointer b) static void machine_help_func(const QDict *qdict) { - GSList *machines, *el; + g_autoptr(GSList) machines = NULL; + GSList *el; const char *type = qdict_get_try_str(qdict, "type"); machines = object_class_get_list(TYPE_MACHINE, false); From patchwork Mon Nov 6 11:02:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13446618 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 65D0F1EB29 for ; Mon, 6 Nov 2023 11:03:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="BaU0smQd" Received: from mail-lf1-x12a.google.com (mail-lf1-x12a.google.com [IPv6:2a00:1450:4864:20::12a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 04E8DBB for ; Mon, 6 Nov 2023 03:03:55 -0800 (PST) Received: by mail-lf1-x12a.google.com with SMTP id 2adb3069b0e04-509109104e2so5570680e87.3 for ; Mon, 06 Nov 2023 03:03:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699268633; x=1699873433; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=d9nIh4jZ3rUpsBw4LSZSNiaZI1TuJJRNoEVBCo+5kN8=; b=BaU0smQdlIyA05qINXOo4to7vqfUT3jnu+wuKPcKFYEq2Y28PbNBKjo3CcbEAFLNTn D5ySEE31D8PfBRkEYvTfB5G554LLBRfzekDQSI09Cec3CvTS9ecp43SvJQr6iRgetcfk Ybxtlf3hwyfk1WLpSk0348Nxy2W2qRcc+oYXcRKDypAvtrQUeCPe1W7TOqmh1C2PSTFq EPcNmtSkMtDXmq/T/K+XLOz7FviBFBidt14iRiqHKILBQ9mp1BN6G8cV8LS64C2pMfi/ t42QhuPyhH6icvv9a72lGCUDFJdi2twmwgVVcYF0TSfm1EfDoXjuAieLfkk6V1Xf3QYB 8K6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699268633; x=1699873433; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=d9nIh4jZ3rUpsBw4LSZSNiaZI1TuJJRNoEVBCo+5kN8=; b=Ae5X/V/fC2a7AKb5g/uqsl9Gp8EazAQQyeSLvzHdKv5jQtIckhc05WyUc75Kj0NFn+ u6KzRvxJghNTzvVYzK6kvq3f3ri9FLGCLHwRIEzdwSMm32KsHz+uI+uWln5PDa9Jhovl VQix1uq+Qafdp6gNl9ydZqqJy42kKp3yNs1OsIipGgzG7cOLpvDP6LqGt9yMdkEiM0py s8KmyXloH79rLNQcQRf3clvOdImXMC9ewXgQNZ1kop78jDZaj9LXGXgbWV1991oOo1eG 6STreswYcDmLyKWj39esBfDmCidpQD7hE5bdrhpJfkPdGzmmItFr9OB7sYvEUGuW/eXt WoxA== X-Gm-Message-State: AOJu0YxpaLNNhz76ElKc0LORYInqmBNkq1XsTCMO5EskjQN3aLS7KP/O l1+atREJ9IYIjLysY1Nf8kUoHL7mlGQHP+0sK9Y= X-Google-Smtp-Source: AGHT+IExKZ0rki8Pzt9Fq9bSXa3p5OpCW6d2acd5GD6zgVvNcXpLdpP4uLK9kjEGGioQ4HTvFd820g== X-Received: by 2002:ac2:51b0:0:b0:500:b7ed:105a with SMTP id f16-20020ac251b0000000b00500b7ed105amr19847445lfk.29.1699268633369; Mon, 06 Nov 2023 03:03:53 -0800 (PST) Received: from m1x-phil.lan (176-131-220-199.abo.bbox.fr. [176.131.220.199]) by smtp.gmail.com with ESMTPSA id p12-20020adfce0c000000b0032dc1fc84f2sm9188671wrn.46.2023.11.06.03.03.51 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:03:53 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini Subject: [PULL 02/60] vl: constify default_list Date: Mon, 6 Nov 2023 12:02:34 +0100 Message-ID: <20231106110336.358-3-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Marc-André Lureau It's not modified, let's make it const. Signed-off-by: Marc-André Lureau Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20231030101529.105266-1-marcandre.lureau@redhat.com> Signed-off-by: Philippe Mathieu-Daudé --- system/vl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/system/vl.c b/system/vl.c index ff76eb0d07..8c803228f4 100644 --- a/system/vl.c +++ b/system/vl.c @@ -194,7 +194,7 @@ static int default_sdcard = 1; static int default_vga = 1; static int default_net = 1; -static struct { +static const struct { const char *driver; int *flag; } default_list[] = { From patchwork Mon Nov 6 11:02:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13446619 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DE2D71EB38 for ; Mon, 6 Nov 2023 11:04:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="jCSQ8K4g" Received: from mail-lf1-x12a.google.com (mail-lf1-x12a.google.com [IPv6:2a00:1450:4864:20::12a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1D127FA for ; Mon, 6 Nov 2023 03:04:02 -0800 (PST) Received: by mail-lf1-x12a.google.com with SMTP id 2adb3069b0e04-50943ccbbaeso6157739e87.2 for ; Mon, 06 Nov 2023 03:04:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699268640; x=1699873440; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OPtEnXMJWXTavrW+hTGrjLz6IdGpJzROhuSvymabGIo=; b=jCSQ8K4gcPRRXf+WzgIn4jYDdAK+tWrGHgCpc09cU432occoDcDnMdGghmtvgT5NBK T6Z6zxcjhgoOg1PjJD7X4H17XYT+yneIRJLOgLbJOTpTwP+uJIv7DSzKstqHhCGqqgWS 2AEkppI5yLt9rAw3EDS6K8EXN4l6D5h6mFLgVQcNIPmm4lKkEyzaZVQWtNRqhQHHJRJA tIjWaNvsub97b+GRXUk1lxNt9G7pObGuVESQ/YaZ1pzovdtkji6TherXM9mIHAMtTB+T HbWkGT5c/+t55Qa1rLvlXVkXSqs7heG49sjNyuGZokdLZ2asrqtFRjR2e4hvsVvcsiPa ItPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699268640; x=1699873440; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OPtEnXMJWXTavrW+hTGrjLz6IdGpJzROhuSvymabGIo=; b=RCeqccSmQzZAj5usk6t2GYJ7JCS01E6RxIbx9dhs+qqVeW1Upjyx3tKb1LVoN/N5+g u7K21OP3Jv1MSePDGbQ4nq8ntHsGOZn6jIQLUFWNV/12F0lepTa/IauI3ippbrSSxVa5 wBv3+EcHrl1ccHhRLnnpF/mQrqcD1V4FOQ4UpefiGLhgmBl/MJsr+UzZoHOH/wXixx1J 7dX8eLJmIas25nv0jQFAmQw1vhVvtkfGkO6ACrPYKr41aQIpGg6okghHvJYaNSZN++mx L8ZD1yWQmrAYmcUMPYSbwOVERt6mMjze8/qhnoMP21/AHKIoLf1hKz/NNzjxaGbZ+NKy RtKA== X-Gm-Message-State: AOJu0YzYJrQ1a/eAA8JSPqoCGU6GgSs+C4fVxc3KCk1RACDnKlCyxXas oLSUN9+hLlwv89oI9+ijcFLsTQ== X-Google-Smtp-Source: AGHT+IHnmaFN+GKLxd2N49xPwJp/PkOfW8YFcpTs0zHKDnkUPvcBfxvj2jLWyUiBIPgGTifMjl5zjg== X-Received: by 2002:a05:6512:1282:b0:505:6ede:20a9 with SMTP id u2-20020a056512128200b005056ede20a9mr26978590lfs.65.1699268640437; Mon, 06 Nov 2023 03:04:00 -0800 (PST) Received: from m1x-phil.lan (176-131-220-199.abo.bbox.fr. [176.131.220.199]) by smtp.gmail.com with ESMTPSA id l10-20020adff48a000000b0032fdcbfb093sm19447wro.81.2023.11.06.03.03.58 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:04:00 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Alex?= =?utf-8?q?_Benn=C3=A9e?= , Richard Henderson , Thomas Huth , Wainer dos Santos Moschetta , Beraldo Leal Subject: [PULL 03/60] tests/vm/ubuntu.aarch64: Correct comment about TCG specific delay Date: Mon, 6 Nov 2023 12:02:35 +0100 Message-ID: <20231106110336.358-4-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Wether we use a software MMU or not to set the SSH timeout isn't really relevant. What we want to know is if we use a hardware or software accelerator (TCG). Replace the 'softmmu' mention by 'TCG'. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée Reviewed-by: Richard Henderson Message-Id: <20231002145104.52193-2-philmd@linaro.org> --- tests/vm/ubuntu.aarch64 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/vm/ubuntu.aarch64 b/tests/vm/ubuntu.aarch64 index 666947393b..eeda281f87 100755 --- a/tests/vm/ubuntu.aarch64 +++ b/tests/vm/ubuntu.aarch64 @@ -25,7 +25,7 @@ DEFAULT_CONFIG = { "apt-get install -y libfdt-dev pkg-config language-pack-en ninja-build", # We increase beyond the default time since during boot # it can take some time (many seconds) to log into the VM - # especially using softmmu. + # especially using TCG. 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id k13-20020a5d6e8d000000b003196b1bb528sm9094731wrz.64.2023.11.06.03.04.05 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:04:06 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , =?utf-8?q?Daniel_P=2E_Ber?= =?utf-8?q?rang=C3=A9?= Subject: [PULL 04/60] tests/unit/test-seccomp: Remove mentions of softmmu in test names Date: Mon, 6 Nov 2023 12:02:36 +0100 Message-ID: <20231106110336.358-5-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Wether we are using a software MMU or not is irrelevant for the seccomp facility. The facility is restricted to system emulation, but such detail isn't really helpful, so directly drop the 'softmmu' mention from the test names. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20231002145104.52193-3-philmd@linaro.org> --- tests/unit/test-seccomp.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/tests/unit/test-seccomp.c b/tests/unit/test-seccomp.c index f02c79cafd..bab93fd6da 100644 --- a/tests/unit/test-seccomp.c +++ b/tests/unit/test-seccomp.c @@ -229,26 +229,26 @@ int main(int argc, char **argv) g_test_init(&argc, &argv, NULL); if (can_play_with_seccomp()) { #ifdef SYS_fork - g_test_add_func("/softmmu/seccomp/sys-fork/on", + g_test_add_func("/seccomp/sys-fork/on", test_seccomp_sys_fork_on); - g_test_add_func("/softmmu/seccomp/sys-fork/on-nospawn", + g_test_add_func("/seccomp/sys-fork/on-nospawn", test_seccomp_sys_fork_on_nospawn); - g_test_add_func("/softmmu/seccomp/sys-fork/off", + g_test_add_func("/seccomp/sys-fork/off", test_seccomp_sys_fork_off); #endif - g_test_add_func("/softmmu/seccomp/fork/on", + g_test_add_func("/seccomp/fork/on", test_seccomp_fork_on); - g_test_add_func("/softmmu/seccomp/fork/on-nospawn", + g_test_add_func("/seccomp/fork/on-nospawn", test_seccomp_fork_on_nospawn); - g_test_add_func("/softmmu/seccomp/fork/off", + g_test_add_func("/seccomp/fork/off", test_seccomp_fork_off); - g_test_add_func("/softmmu/seccomp/thread/on", + g_test_add_func("/seccomp/thread/on", test_seccomp_thread_on); - g_test_add_func("/softmmu/seccomp/thread/on-nospawn", + g_test_add_func("/seccomp/thread/on-nospawn", test_seccomp_thread_on_nospawn); - g_test_add_func("/softmmu/seccomp/thread/off", + g_test_add_func("/seccomp/thread/off", test_seccomp_thread_off); if (doit_sched() == 0) { @@ -256,11 +256,11 @@ int main(int argc, char **argv) * musl doesn't impl sched_setscheduler, hence * we check above if it works first */ - g_test_add_func("/softmmu/seccomp/sched/on", + g_test_add_func("/seccomp/sched/on", test_seccomp_sched_on); - g_test_add_func("/softmmu/seccomp/sched/on-nores", + g_test_add_func("/seccomp/sched/on-nores", test_seccomp_sched_on_nores); - g_test_add_func("/softmmu/seccomp/sched/off", + g_test_add_func("/seccomp/sched/off", test_seccomp_sched_off); } } From patchwork Mon Nov 6 11:02:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13446621 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CCC0D1EB2B for ; Mon, 6 Nov 2023 11:04:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="uEsYRuZZ" Received: from mail-wm1-x334.google.com (mail-wm1-x334.google.com [IPv6:2a00:1450:4864:20::334]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 899CDBB for ; Mon, 6 Nov 2023 03:04:15 -0800 (PST) Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-40859c466efso32045885e9.3 for ; Mon, 06 Nov 2023 03:04:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699268654; x=1699873454; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=e2dhS3KlkYuIzlj4JyHbDi+Agmw3+gkCUCmK+83aHSA=; b=uEsYRuZZ80LyI8nKheQ+1NrUGJo3TAAsS7lwA0NVRLdIommUMjkbnETS/DHaykVyph rDX3ltunMFKuCHd/6T45RK+t6etMSNX6QCHfF6hywGdJz1rpSrH8K6fJD+6aRJ5C+vf9 JZHhfHU7PDH0TAs1J2HBiLnAdVaJKX0Yf9agkUlNUTq7LwBsDgnHU+yWJQbKoiTsdsTV QnGrxfD12jErvYo7vUKblpQuBCYaBgUE5M9pGgxx4aaBW6Y4Qj+0qOgh6uxQVeVDPq1g SX/+0YvN+kbiH3wgRs4kFcud4u3qRssxyj6x6ps6amCq/c/DYroQYFx994oFzdR4pqik 77mQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699268654; x=1699873454; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=e2dhS3KlkYuIzlj4JyHbDi+Agmw3+gkCUCmK+83aHSA=; b=ovk4gJA5XCKNoRSTaqeySui0Mxj22aQ2/C53LIO3UKtKjPx+dSIjoSHWjCH79wlM93 jkq7jaCLt0P/ifQpeiUq6SdozHv+YJvTse19JTx4lLYF5o0AbgYKwEJVjItKkvIAa6kb TOIKXhgPO61bYrQu4SCLXfvgh8GbI7fsoTd84Amtrk+wXlvKPP64Jyv0zx6EbBoSxQOh T7KxaZ/dKjXgcLybJS8jKlmkFq5n0CRxjlZVyfz5bTLEtEbZ/6tGJbZy8tnqO2756B3u 5yDbPoQZienSpbtN6uJCuoS4HdyzU2QGmER9ipZxpJbhnW1gNlld9RMUS5K2GNw/M1sm D/kQ== X-Gm-Message-State: AOJu0YxPJlUc+uKbhVyVI1vJhv+/PY4Tqku7eDM6r0GsH0CgYIDBxADy 5O7huJD/h2z23gXv3maTXrk0yQ== X-Google-Smtp-Source: AGHT+IEBVIn/0r+UoLYA97Mnp+piCsSmfP4bBhuQ8Q479GVHXuAJkDevEs+mH3EZ9a+ZFr4LoWGeXw== X-Received: by 2002:a05:600c:5116:b0:409:2825:6dd5 with SMTP id o22-20020a05600c511600b0040928256dd5mr23574505wms.13.1699268653839; Mon, 06 Nov 2023 03:04:13 -0800 (PST) Received: from m1x-phil.lan (176-131-220-199.abo.bbox.fr. [176.131.220.199]) by smtp.gmail.com with ESMTPSA id n26-20020a1c721a000000b0040849ce7116sm11652236wmc.43.2023.11.06.03.04.11 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:04:13 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Anton Johansson , Richard Henderson , Paolo Bonzini , =?utf-8?q?Alex_Benn=C3=A9e?= , Alexandre Iooss , Mahmoud Mandour Subject: [PULL 05/60] accel/tcg: Declare tcg_flush_jmp_cache() in 'exec/tb-flush.h' Date: Mon, 6 Nov 2023 12:02:37 +0100 Message-ID: <20231106110336.358-6-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 "exec/cpu-common.h" is meant to contain the declarations related to CPU usable with any accelerator / target combination. tcg_flush_jmp_cache() is specific to TCG, so restrict its declaration by moving it to "exec/tb-flush.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Anton Johansson Reviewed-by: Richard Henderson Message-Id: <20230918104153.24433-2-philmd@linaro.org> --- include/exec/cpu-common.h | 1 - include/exec/tb-flush.h | 2 ++ accel/tcg/cputlb.c | 1 + accel/tcg/tcg-accel-ops.c | 1 + hw/core/cpu-common.c | 1 + plugins/core.c | 1 - 6 files changed, 5 insertions(+), 2 deletions(-) diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index 30c376a4de..f700071d12 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -46,7 +46,6 @@ void cpu_list_unlock(void); unsigned int cpu_list_generation_id_get(void); void tcg_flush_softmmu_tlb(CPUState *cs); -void tcg_flush_jmp_cache(CPUState *cs); void tcg_iommu_init_notifier_list(CPUState *cpu); void tcg_iommu_free_notifier_list(CPUState *cpu); diff --git a/include/exec/tb-flush.h b/include/exec/tb-flush.h index d92d06565b..142c240d94 100644 --- a/include/exec/tb-flush.h +++ b/include/exec/tb-flush.h @@ -23,4 +23,6 @@ */ void tb_flush(CPUState *cs); +void tcg_flush_jmp_cache(CPUState *cs); + #endif /* _TB_FLUSH_H_ */ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index b8c5e345b8..6ea95ca03c 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -24,6 +24,7 @@ #include "exec/memory.h" #include "exec/cpu_ldst.h" #include "exec/cputlb.h" +#include "exec/tb-flush.h" #include "exec/memory-internal.h" #include "exec/ram_addr.h" #include "tcg/tcg.h" diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c index d885cc1d3c..7ddb05c332 100644 --- a/accel/tcg/tcg-accel-ops.c +++ b/accel/tcg/tcg-accel-ops.c @@ -34,6 +34,7 @@ #include "qemu/timer.h" #include "exec/exec-all.h" #include "exec/hwaddr.h" +#include "exec/tb-flush.h" #include "exec/gdbstub.h" #include "tcg-accel-ops.h" diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c index bab8942c30..29c917c5dc 100644 --- a/hw/core/cpu-common.c +++ b/hw/core/cpu-common.c @@ -27,6 +27,7 @@ #include "qemu/main-loop.h" #include "exec/log.h" #include "exec/cpu-common.h" +#include "exec/tb-flush.h" #include "qemu/error-report.h" #include "qemu/qemu-print.h" #include "sysemu/tcg.h" diff --git a/plugins/core.c b/plugins/core.c index fcd33a2bff..49588285dd 100644 --- a/plugins/core.c +++ b/plugins/core.c @@ -21,7 +21,6 @@ #include "qemu/xxhash.h" #include "qemu/rcu.h" #include "hw/core/cpu.h" -#include "exec/cpu-common.h" #include "exec/exec-all.h" #include "exec/tb-flush.h" From patchwork Mon Nov 6 11:02:38 2023 Content-Type: text/plain; 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id g20-20020a05600c4ed400b003fee8793911sm12010027wmq.44.2023.11.06.03.04.18 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:04:20 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Anton Johansson , Richard Henderson , Riku Voipio , Paolo Bonzini , Eduardo Habkost , Marcel Apfelbaum , Yanan Wang Subject: [PULL 06/60] accel: Introduce cpu_exec_reset_hold() Date: Mon, 6 Nov 2023 12:02:38 +0100 Message-ID: <20231106110336.358-7-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Introduce cpu_exec_reset_hold() which call an accelerator specific AccelOpsClass::cpu_reset_hold() handler. Define a stub on TCG user emulation, because CPU reset is irrelevant there. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Anton Johansson Reviewed-by: Richard Henderson Message-Id: <20230918104153.24433-3-philmd@linaro.org> --- include/hw/core/cpu.h | 1 + include/sysemu/accel-ops.h | 1 + accel/tcg/user-exec-stub.c | 4 ++++ hw/core/cpu-common.c | 1 + system/cpus.c | 7 +++++++ 5 files changed, 14 insertions(+) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 18593db5b2..6373aa4501 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -1153,6 +1153,7 @@ void cpu_class_init_props(DeviceClass *dc); void cpu_exec_initfn(CPUState *cpu); void cpu_exec_realizefn(CPUState *cpu, Error **errp); void cpu_exec_unrealizefn(CPUState *cpu); +void cpu_exec_reset_hold(CPUState *cpu); /** * target_words_bigendian: diff --git a/include/sysemu/accel-ops.h b/include/sysemu/accel-ops.h index 3c1fab4b1e..ef91fc28bb 100644 --- a/include/sysemu/accel-ops.h +++ b/include/sysemu/accel-ops.h @@ -30,6 +30,7 @@ struct AccelOpsClass { void (*ops_init)(AccelOpsClass *ops); bool (*cpus_are_resettable)(void); + void (*cpu_reset_hold)(CPUState *cpu); void (*create_vcpu_thread)(CPUState *cpu); /* MANDATORY NON-NULL */ void (*kick_vcpu_thread)(CPUState *cpu); diff --git a/accel/tcg/user-exec-stub.c b/accel/tcg/user-exec-stub.c index 2dc6fd9c4e..4fbe2dbdc8 100644 --- a/accel/tcg/user-exec-stub.c +++ b/accel/tcg/user-exec-stub.c @@ -14,6 +14,10 @@ void qemu_init_vcpu(CPUState *cpu) { } +void cpu_exec_reset_hold(CPUState *cpu) +{ +} + /* User mode emulation does not support record/replay yet. */ bool replay_exception(void) diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c index 29c917c5dc..7d266c36ac 100644 --- a/hw/core/cpu-common.c +++ b/hw/core/cpu-common.c @@ -137,6 +137,7 @@ static void cpu_common_reset_hold(Object *obj) cpu->crash_occurred = false; cpu->cflags_next_tb = -1; + cpu_exec_reset_hold(cpu); if (tcg_enabled()) { tcg_flush_jmp_cache(cpu); tcg_flush_softmmu_tlb(cpu); diff --git a/system/cpus.c b/system/cpus.c index 0848e0dbdb..952f15868c 100644 --- a/system/cpus.c +++ b/system/cpus.c @@ -201,6 +201,13 @@ bool cpus_are_resettable(void) return true; } +void cpu_exec_reset_hold(CPUState *cpu) +{ + if (cpus_accel->cpu_reset_hold) { + cpus_accel->cpu_reset_hold(cpu); + } +} + int64_t cpus_get_virtual_clock(void) { /* From patchwork Mon Nov 6 11:02:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13446623 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AAF601EB2B for ; Mon, 6 Nov 2023 11:04:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="NUkHd2UD" Received: from mail-wm1-x329.google.com (mail-wm1-x329.google.com [IPv6:2a00:1450:4864:20::329]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 02A11125 for ; Mon, 6 Nov 2023 03:04:29 -0800 (PST) Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-40790b0a224so32901035e9.0 for ; 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id s7-20020a05600c45c700b003fc16ee2864sm11816561wmo.48.2023.11.06.03.04.25 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:04:26 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Anton Johansson , Richard Henderson , Paolo Bonzini Subject: [PULL 07/60] accel/tcg: Factor tcg_cpu_reset_hold() out Date: Mon, 6 Nov 2023 12:02:39 +0100 Message-ID: <20231106110336.358-8-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Factor the TCG specific code from cpu_common_reset_hold() to tcg_cpu_reset_hold() within tcg-accel-ops.c. Since this file is sysemu specific, we can inline tcg_flush_softmmu_tlb(), removing its declaration in "exec/cpu-common.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Anton Johansson Reviewed-by: Richard Henderson Message-Id: <20230918104153.24433-4-philmd@linaro.org> --- include/exec/cpu-common.h | 2 -- accel/stubs/tcg-stub.c | 4 ---- accel/tcg/tcg-accel-ops.c | 8 ++++++++ accel/tcg/translate-all.c | 8 -------- hw/core/cpu-common.c | 5 ----- 5 files changed, 8 insertions(+), 19 deletions(-) diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index f700071d12..41115d8919 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -45,8 +45,6 @@ void cpu_list_lock(void); void cpu_list_unlock(void); unsigned int cpu_list_generation_id_get(void); -void tcg_flush_softmmu_tlb(CPUState *cs); - void tcg_iommu_init_notifier_list(CPUState *cpu); void tcg_iommu_free_notifier_list(CPUState *cpu); diff --git a/accel/stubs/tcg-stub.c b/accel/stubs/tcg-stub.c index a9e7a2d5b4..8a496a2a6f 100644 --- a/accel/stubs/tcg-stub.c +++ b/accel/stubs/tcg-stub.c @@ -22,10 +22,6 @@ void tlb_set_dirty(CPUState *cpu, vaddr vaddr) { } -void tcg_flush_jmp_cache(CPUState *cpu) -{ -} - int probe_access_flags(CPUArchState *env, vaddr addr, int size, MMUAccessType access_type, int mmu_idx, bool nonfault, void **phost, uintptr_t retaddr) diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c index 7ddb05c332..1b57290682 100644 --- a/accel/tcg/tcg-accel-ops.c +++ b/accel/tcg/tcg-accel-ops.c @@ -78,6 +78,13 @@ int tcg_cpus_exec(CPUState *cpu) return ret; } +static void tcg_cpu_reset_hold(CPUState *cpu) +{ + tcg_flush_jmp_cache(cpu); + + tlb_flush(cpu); +} + /* mask must never be zero, except for A20 change call */ void tcg_handle_interrupt(CPUState *cpu, int mask) { @@ -206,6 +213,7 @@ static void tcg_accel_ops_init(AccelOpsClass *ops) } } + ops->cpu_reset_hold = tcg_cpu_reset_hold; ops->supports_guest_debug = tcg_supports_guest_debug; ops->insert_breakpoint = tcg_insert_breakpoint; ops->remove_breakpoint = tcg_remove_breakpoint; diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 8cb6ad3511..27e8152f0a 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -800,11 +800,3 @@ void tcg_flush_jmp_cache(CPUState *cpu) qatomic_set(&jc->array[i].tb, NULL); } } - -/* This is a wrapper for common code that can not use CONFIG_SOFTMMU */ -void tcg_flush_softmmu_tlb(CPUState *cs) -{ -#ifdef CONFIG_SOFTMMU - tlb_flush(cs); -#endif -} diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c index 7d266c36ac..baa6d28b64 100644 --- a/hw/core/cpu-common.c +++ b/hw/core/cpu-common.c @@ -27,7 +27,6 @@ #include "qemu/main-loop.h" #include "exec/log.h" #include "exec/cpu-common.h" -#include "exec/tb-flush.h" #include "qemu/error-report.h" #include "qemu/qemu-print.h" #include "sysemu/tcg.h" @@ -138,10 +137,6 @@ static void cpu_common_reset_hold(Object *obj) cpu->cflags_next_tb = -1; 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id m9-20020adfe949000000b003253523d767sm120250wrn.109.2023.11.06.03.04.31 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:04:36 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Zhao Liu , Peter Maydell , Michael Rolnik , "Edgar E. Iglesias" , Brian Cain , Song Gao , Laurent Vivier , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Chris Wulff , Marek Vasut , Stafford Horne , Nicholas Piggin , Daniel Henrique Barboza , =?utf-8?q?C=C3=A9dric_Le_G?= =?utf-8?q?oater?= , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Liu Zhiwei , Yoshinori Sato , Thomas Huth , David Hildenbrand , Ilya Leoshkevich , Mark Cave-Ayland , Artyom Tarasenko , Bastian Koppelmann , Max Filippov Subject: [PULL 08/60] target: Unify QOM style Date: Mon, 6 Nov 2023 12:02:40 +0100 Message-ID: <20231106110336.358-9-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Enforce the style described by commit 067109a11c ("docs/devel: mention the spacing requirement for QOM"): The first declaration of a storage or class structure should always be the parent and leave a visual space between that declaration and the new code. It is also useful to separate backing for properties (options driven by the user) and internal state to make navigation easier. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Zhao Liu Message-Id: <20231013140116.255-2-philmd@linaro.org> --- target/alpha/cpu-qom.h | 2 -- target/alpha/cpu.h | 2 -- target/arm/cpu-qom.h | 4 ---- target/arm/cpu.h | 2 -- target/avr/cpu-qom.h | 3 +-- target/avr/cpu.h | 2 -- target/cris/cpu-qom.h | 2 -- target/cris/cpu.h | 2 -- target/hexagon/cpu.h | 5 +---- target/hppa/cpu-qom.h | 2 -- target/hppa/cpu.h | 2 -- target/i386/cpu-qom.h | 2 -- target/i386/cpu.h | 2 -- target/loongarch/cpu.h | 4 ---- target/m68k/cpu-qom.h | 2 -- target/m68k/cpu.h | 2 -- target/microblaze/cpu-qom.h | 2 -- target/microblaze/cpu.h | 2 -- target/mips/cpu-qom.h | 2 -- target/mips/cpu.h | 2 -- target/nios2/cpu.h | 4 ---- target/openrisc/cpu.h | 4 ---- target/ppc/cpu.h | 2 -- target/riscv/cpu-qom.h | 3 +-- target/riscv/cpu.h | 2 -- target/rx/cpu-qom.h | 2 -- target/rx/cpu.h | 2 -- target/s390x/cpu-qom.h | 3 +-- target/s390x/cpu.h | 2 -- target/sh4/cpu-qom.h | 2 -- target/sh4/cpu.h | 2 -- target/sparc/cpu-qom.h | 2 -- target/sparc/cpu.h | 2 -- target/tricore/cpu-qom.h | 2 -- target/tricore/cpu.h | 2 -- target/xtensa/cpu-qom.h | 2 -- target/xtensa/cpu.h | 2 -- 37 files changed, 4 insertions(+), 84 deletions(-) diff --git a/target/alpha/cpu-qom.h b/target/alpha/cpu-qom.h index 1f200724b6..c5fbd8f11a 100644 --- a/target/alpha/cpu-qom.h +++ b/target/alpha/cpu-qom.h @@ -35,9 +35,7 @@ OBJECT_DECLARE_CPU_TYPE(AlphaCPU, AlphaCPUClass, ALPHA_CPU) * An Alpha CPU model. */ struct AlphaCPUClass { - /*< private >*/ CPUClass parent_class; - /*< public >*/ DeviceRealize parent_realize; DeviceReset parent_reset; diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index e2a467ec17..c8d97ac27a 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -259,9 +259,7 @@ typedef struct CPUArchState { * An Alpha CPU. */ struct ArchCPU { - /*< private >*/ CPUState parent_obj; - /*< public >*/ CPUAlphaState env; diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h index d06c08a734..153865d1bb 100644 --- a/target/arm/cpu-qom.h +++ b/target/arm/cpu-qom.h @@ -46,9 +46,7 @@ void aarch64_cpu_register(const ARMCPUInfo *info); * An ARM CPU model. */ struct ARMCPUClass { - /*< private >*/ CPUClass parent_class; - /*< public >*/ const ARMCPUInfo *info; DeviceRealize parent_realize; @@ -62,9 +60,7 @@ DECLARE_CLASS_CHECKERS(AArch64CPUClass, AARCH64_CPU, TYPE_AARCH64_CPU) struct AArch64CPUClass { - /*< private >*/ ARMCPUClass parent_class; - /*< public >*/ }; void register_cp_regs_for_features(ARMCPU *cpu); diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d51dfe48db..2f7ab22169 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -852,9 +852,7 @@ typedef struct { * An ARM CPU core. */ struct ArchCPU { - /*< private >*/ CPUState parent_obj; - /*< public >*/ CPUARMState env; diff --git a/target/avr/cpu-qom.h b/target/avr/cpu-qom.h index 01ea5f160b..d89be01e0f 100644 --- a/target/avr/cpu-qom.h +++ b/target/avr/cpu-qom.h @@ -36,9 +36,8 @@ OBJECT_DECLARE_CPU_TYPE(AVRCPU, AVRCPUClass, AVR_CPU) * A AVR CPU model. */ struct AVRCPUClass { - /*< private >*/ CPUClass parent_class; - /*< public >*/ + DeviceRealize parent_realize; ResettablePhases parent_phases; }; diff --git a/target/avr/cpu.h b/target/avr/cpu.h index 4ce22d8e4f..f8b065ed79 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -144,9 +144,7 @@ typedef struct CPUArchState { * A AVR CPU. */ struct ArchCPU { - /*< private >*/ CPUState parent_obj; - /*< public >*/ CPUAVRState env; }; diff --git a/target/cris/cpu-qom.h b/target/cris/cpu-qom.h index 431a1d536a..c2fee242f4 100644 --- a/target/cris/cpu-qom.h +++ b/target/cris/cpu-qom.h @@ -36,9 +36,7 @@ OBJECT_DECLARE_CPU_TYPE(CRISCPU, CRISCPUClass, CRIS_CPU) * A CRIS CPU model. */ struct CRISCPUClass { - /*< private >*/ CPUClass parent_class; - /*< public >*/ DeviceRealize parent_realize; ResettablePhases parent_phases; diff --git a/target/cris/cpu.h b/target/cris/cpu.h index 676b8e93ca..6aa445348f 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -174,9 +174,7 @@ typedef struct CPUArchState { * A CRIS CPU. */ struct ArchCPU { - /*< private >*/ CPUState parent_obj; - /*< public >*/ CPUCRISState env; }; diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 10cd1efd57..035ac4fb6d 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -130,17 +130,14 @@ typedef struct CPUArchState { OBJECT_DECLARE_CPU_TYPE(HexagonCPU, HexagonCPUClass, HEXAGON_CPU) typedef struct HexagonCPUClass { - /*< private >*/ CPUClass parent_class; - /*< public >*/ + DeviceRealize parent_realize; ResettablePhases parent_phases; } HexagonCPUClass; struct ArchCPU { - /*< private >*/ CPUState parent_obj; - /*< public >*/ CPUHexagonState env; diff --git a/target/hppa/cpu-qom.h b/target/hppa/cpu-qom.h index b96e0318c7..67f12422c4 100644 --- a/target/hppa/cpu-qom.h +++ b/target/hppa/cpu-qom.h @@ -35,9 +35,7 @@ OBJECT_DECLARE_CPU_TYPE(HPPACPU, HPPACPUClass, HPPA_CPU) * An HPPA CPU model. */ struct HPPACPUClass { - /*< private >*/ CPUClass parent_class; - /*< public >*/ DeviceRealize parent_realize; DeviceReset parent_reset; diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 798d0c26d7..518ea94f4f 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -233,9 +233,7 @@ typedef struct CPUArchState { * An HPPA CPU. */ struct ArchCPU { - /*< private >*/ CPUState parent_obj; - /*< public >*/ CPUHPPAState env; QEMUTimer *alarm_timer; diff --git a/target/i386/cpu-qom.h b/target/i386/cpu-qom.h index 2350f4ae60..58145717ef 100644 --- a/target/i386/cpu-qom.h +++ b/target/i386/cpu-qom.h @@ -47,9 +47,7 @@ typedef struct X86CPUModel X86CPUModel; * An x86 CPU model or family. */ struct X86CPUClass { - /*< private >*/ CPUClass parent_class; - /*< public >*/ /* CPU definition, automatically loaded by instance_init if not NULL. * Should be eventually replaced by subclass-specific property defaults. diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 471e71dbc5..096f85483e 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1897,9 +1897,7 @@ struct kvm_msrs; * An x86 CPU. */ struct ArchCPU { - /*< private >*/ CPUState parent_obj; - /*< public >*/ CPUX86State env; VMChangeStateEntry *vmsentry; diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 8b54cf109c..8f0e9f0182 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -371,9 +371,7 @@ typedef struct CPUArchState { * A LoongArch CPU. */ struct ArchCPU { - /*< private >*/ CPUState parent_obj; - /*< public >*/ CPULoongArchState env; QEMUTimer timer; @@ -398,9 +396,7 @@ OBJECT_DECLARE_CPU_TYPE(LoongArchCPU, LoongArchCPUClass, * A LoongArch CPU model. */ struct LoongArchCPUClass { - /*< private >*/ CPUClass parent_class; - /*< public >*/ DeviceRealize parent_realize; ResettablePhases parent_phases; diff --git a/target/m68k/cpu-qom.h b/target/m68k/cpu-qom.h index 0ec7750a92..13d94c9fe3 100644 --- a/target/m68k/cpu-qom.h +++ b/target/m68k/cpu-qom.h @@ -35,9 +35,7 @@ OBJECT_DECLARE_CPU_TYPE(M68kCPU, M68kCPUClass, M68K_CPU) * A Motorola 68k CPU model. */ struct M68kCPUClass { - /*< private >*/ CPUClass parent_class; - /*< public >*/ DeviceRealize parent_realize; ResettablePhases parent_phases; diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 20afb0c94d..9ea18028ad 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -164,9 +164,7 @@ typedef struct CPUArchState { * A Motorola 68k CPU. */ struct ArchCPU { - /*< private >*/ CPUState parent_obj; - /*< public >*/ CPUM68KState env; }; diff --git a/target/microblaze/cpu-qom.h b/target/microblaze/cpu-qom.h index cda9220fa9..2a734e644d 100644 --- a/target/microblaze/cpu-qom.h +++ b/target/microblaze/cpu-qom.h @@ -35,9 +35,7 @@ OBJECT_DECLARE_CPU_TYPE(MicroBlazeCPU, MicroBlazeCPUClass, MICROBLAZE_CPU) * A MicroBlaze CPU model. */ struct MicroBlazeCPUClass { - /*< private >*/ CPUClass parent_class; - /*< public >*/ DeviceRealize parent_realize; ResettablePhases parent_phases; diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index e43c49d4af..e8000237d8 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -343,9 +343,7 @@ typedef struct { * A MicroBlaze CPU. */ struct ArchCPU { - /*< private >*/ CPUState parent_obj; - /*< public >*/ CPUMBState env; diff --git a/target/mips/cpu-qom.h b/target/mips/cpu-qom.h index 0dffab453b..c70b4a34be 100644 --- a/target/mips/cpu-qom.h +++ b/target/mips/cpu-qom.h @@ -39,9 +39,7 @@ OBJECT_DECLARE_CPU_TYPE(MIPSCPU, MIPSCPUClass, MIPS_CPU) * A MIPS CPU model. */ struct MIPSCPUClass { - /*< private >*/ CPUClass parent_class; - /*< public >*/ DeviceRealize parent_realize; ResettablePhases parent_phases; diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 5fddceff3a..617c373797 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1209,9 +1209,7 @@ typedef struct CPUArchState { * A MIPS CPU. */ struct ArchCPU { - /*< private >*/ CPUState parent_obj; - /*< public >*/ CPUMIPSState env; diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 70b6377a4f..ede1ba2140 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -42,9 +42,7 @@ OBJECT_DECLARE_CPU_TYPE(Nios2CPU, Nios2CPUClass, NIOS2_CPU) * A Nios2 CPU model. */ struct Nios2CPUClass { - /*< private >*/ CPUClass parent_class; - /*< public >*/ DeviceRealize parent_realize; ResettablePhases parent_phases; @@ -214,9 +212,7 @@ typedef struct { * A Nios2 CPU. */ struct ArchCPU { - /*< private >*/ CPUState parent_obj; - /*< public >*/ CPUNios2State env; diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 334997e9a1..29cda7279c 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -39,9 +39,7 @@ OBJECT_DECLARE_CPU_TYPE(OpenRISCCPU, OpenRISCCPUClass, OPENRISC_CPU) * A OpenRISC CPU model. */ struct OpenRISCCPUClass { - /*< private >*/ CPUClass parent_class; - /*< public >*/ DeviceRealize parent_realize; ResettablePhases parent_phases; @@ -301,9 +299,7 @@ typedef struct CPUArchState { * A OpenRISC CPU. */ struct ArchCPU { - /*< private >*/ CPUState parent_obj; - /*< public >*/ CPUOpenRISCState env; }; diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 30392ebeee..24dd6b1b0a 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1313,9 +1313,7 @@ typedef struct PPCVirtualHypervisorClass PPCVirtualHypervisorClass; * A PowerPC CPU. */ struct ArchCPU { - /*< private >*/ CPUState parent_obj; - /*< public >*/ CPUPPCState env; diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index f3fbe37a2c..b9164a8e5b 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -63,9 +63,8 @@ OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) * A RISCV CPU model. */ struct RISCVCPUClass { - /*< private >*/ CPUClass parent_class; - /*< public >*/ + DeviceRealize parent_realize; ResettablePhases parent_phases; }; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index f8ffa5ee38..f0dc257a75 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -389,9 +389,7 @@ struct CPUArchState { * A RISCV CPU. */ struct ArchCPU { - /* < private > */ CPUState parent_obj; - /* < public > */ CPURISCVState env; diff --git a/target/rx/cpu-qom.h b/target/rx/cpu-qom.h index 1c8466a187..f4cd5664e5 100644 --- a/target/rx/cpu-qom.h +++ b/target/rx/cpu-qom.h @@ -36,9 +36,7 @@ OBJECT_DECLARE_CPU_TYPE(RXCPU, RXCPUClass, RX_CPU) * A RX CPU model. */ struct RXCPUClass { - /*< private >*/ CPUClass parent_class; - /*< public >*/ DeviceRealize parent_realize; ResettablePhases parent_phases; diff --git a/target/rx/cpu.h b/target/rx/cpu.h index f66754eb8a..8379f4a150 100644 --- a/target/rx/cpu.h +++ b/target/rx/cpu.h @@ -107,9 +107,7 @@ typedef struct CPUArchState { * A RX CPU */ struct ArchCPU { - /*< private >*/ CPUState parent_obj; - /*< public >*/ CPURXState env; }; diff --git a/target/s390x/cpu-qom.h b/target/s390x/cpu-qom.h index 00cae2b131..1088965fd5 100644 --- a/target/s390x/cpu-qom.h +++ b/target/s390x/cpu-qom.h @@ -49,9 +49,8 @@ typedef enum cpu_reset_type { * An S/390 CPU model. */ struct S390CPUClass { - /*< private >*/ CPUClass parent_class; - /*< public >*/ + const S390CPUDef *cpu_def; bool kvm_required; bool is_static; diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 40c5cedd0e..4f366f9e4e 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -172,9 +172,7 @@ static inline uint64_t *get_freg(CPUS390XState *cs, int nr) * An S/390 CPU. */ struct ArchCPU { - /*< private >*/ CPUState parent_obj; - /*< public >*/ CPUS390XState env; S390CPUModel *model; diff --git a/target/sh4/cpu-qom.h b/target/sh4/cpu-qom.h index 89785a90f0..08fbebc996 100644 --- a/target/sh4/cpu-qom.h +++ b/target/sh4/cpu-qom.h @@ -42,9 +42,7 @@ OBJECT_DECLARE_CPU_TYPE(SuperHCPU, SuperHCPUClass, SUPERH_CPU) * A SuperH CPU model. */ struct SuperHCPUClass { - /*< private >*/ CPUClass parent_class; - /*< public >*/ DeviceRealize parent_realize; ResettablePhases parent_phases; diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index f75a235973..dc0561b73b 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -204,9 +204,7 @@ typedef struct CPUArchState { * A SuperH CPU. */ struct ArchCPU { - /*< private >*/ CPUState parent_obj; - /*< public >*/ CPUSH4State env; }; diff --git a/target/sparc/cpu-qom.h b/target/sparc/cpu-qom.h index 78bf00b9a2..b4a0db84ce 100644 --- a/target/sparc/cpu-qom.h +++ b/target/sparc/cpu-qom.h @@ -40,9 +40,7 @@ typedef struct sparc_def_t sparc_def_t; * A SPARC CPU model. */ struct SPARCCPUClass { - /*< private >*/ CPUClass parent_class; - /*< public >*/ DeviceRealize parent_realize; ResettablePhases parent_phases; diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 758a4e8aaa..84a030e406 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -569,9 +569,7 @@ struct CPUArchState { * A SPARC CPU. */ struct ArchCPU { - /*< private >*/ CPUState parent_obj; - /*< public >*/ CPUSPARCState env; }; diff --git a/target/tricore/cpu-qom.h b/target/tricore/cpu-qom.h index 612731daa0..b3b6c75a3a 100644 --- a/target/tricore/cpu-qom.h +++ b/target/tricore/cpu-qom.h @@ -27,9 +27,7 @@ OBJECT_DECLARE_CPU_TYPE(TriCoreCPU, TriCoreCPUClass, TRICORE_CPU) struct TriCoreCPUClass { - /*< private >*/ CPUClass parent_class; - /*< public >*/ DeviceRealize parent_realize; ResettablePhases parent_phases; diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index a357b573f2..b4a6ab141d 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -63,9 +63,7 @@ typedef struct CPUArchState { * A TriCore CPU. */ struct ArchCPU { - /*< private >*/ CPUState parent_obj; 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id y3-20020adfe6c3000000b003140f47224csm9111991wrm.15.2023.11.06.03.04.41 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:04:42 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Peter Maydell , "Edgar E. Iglesias" Subject: [PULL 09/60] target: Mention 'cpu-qom.h' is target agnostic Date: Mon, 6 Nov 2023 12:02:41 +0100 Message-ID: <20231106110336.358-10-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 "target/foo/cpu-qom.h" is supposed to be target agnostic (include-able by any target). Add such mention in the header. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20231013140116.255-3-philmd@linaro.org> --- target/arm/cpu-qom.h | 2 +- target/hppa/cpu-qom.h | 2 +- target/microblaze/cpu-qom.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h index 153865d1bb..dfb9d5b827 100644 --- a/target/arm/cpu-qom.h +++ b/target/arm/cpu-qom.h @@ -1,5 +1,5 @@ /* - * QEMU ARM CPU + * QEMU ARM CPU QOM header (target agnostic) * * Copyright (c) 2012 SUSE LINUX Products GmbH * diff --git a/target/hppa/cpu-qom.h b/target/hppa/cpu-qom.h index 67f12422c4..4b1d48f7ca 100644 --- a/target/hppa/cpu-qom.h +++ b/target/hppa/cpu-qom.h @@ -1,5 +1,5 @@ /* - * QEMU HPPA CPU + * QEMU HPPA CPU QOM header (target agnostic) * * Copyright (c) 2016 Richard Henderson * diff --git a/target/microblaze/cpu-qom.h b/target/microblaze/cpu-qom.h index 2a734e644d..78f549b57d 100644 --- a/target/microblaze/cpu-qom.h +++ b/target/microblaze/cpu-qom.h @@ -1,5 +1,5 @@ /* - * QEMU MicroBlaze CPU + * QEMU MicroBlaze CPU QOM header (target agnostic) * * Copyright (c) 2012 SUSE LINUX Products GmbH * From patchwork Mon Nov 6 11:02:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13446626 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 90C3A18B0C for ; Mon, 6 Nov 2023 11:04:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="UE9FceSP" Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [IPv6:2a00:1450:4864:20::32e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A646AC6 for ; Mon, 6 Nov 2023 03:04:50 -0800 (PST) Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-40839652b97so32700295e9.3 for ; Mon, 06 Nov 2023 03:04:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699268689; x=1699873489; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5wOkrsA8z2Hole9awlJYsNuk4oh7gPmhIjtphAMJsw8=; b=UE9FceSPlDMJk7CZToEJXS87GfXMmOG3kbFD9fAAg/A+oGcelQRpbFg7rjagIs4K0i b3tmhol6+seysAXNM2H+10oFjuqWk+laVF/Qq3etBjYynBovtq7nDlM3he6uS4w7Xn5D DC/DfrTD5WexzvJ+ZmTl6h91+hkqnv2XPvb8rw7je8sC4G2bEiaPkfeiTjcOLzJcfnEE mL3Ix4kPdukOwUaklW9w2QDxQskmCqtjG4G2VnKLY4wejRMH9i2dlzhS8mesVpS1ZleW 0xxaw+6iniMXopqkZYAxAl/EtdnBrvrX7JzFfhYaVSU/XH1KM6k6rFZDTShlP0ihD6bZ Wsfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699268689; x=1699873489; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5wOkrsA8z2Hole9awlJYsNuk4oh7gPmhIjtphAMJsw8=; b=FZynxwxkTSYCT2nJwD9spsOu0eW7y0TCcBWVO7CvYNWSrl1lMg0eeW1rWkAI9ksCLW bTGaeyNYF3CoTWisMqO3r3bxaGJj3hfC3Np+lvw0d8+75qtTjFpJcTe3n096nS39hJ06 QWYqFFKmWMvh2TOb8bHRLpnRdpime2JRqFjnZI/+YEzfzsK34uTI2YqKsNmsawQTbXDm RnWAMr60tQdUv9npwBrWWfP2vg3PXEtTA/GK/DnUr8wHFbYiAHt5AfT0XqOBk8/QcO/d 9xtv87KK+/EIXjKCz7OTO4o1RJcmYhqBK94CNLf4aswbfnswAt33YzcDnUFuNPtSSRFs jYwQ== X-Gm-Message-State: AOJu0YwYdZtNMo5PfyUmS+COTe3LJDgiXplkbR18yQFNyg1pQ6XkFk/X R4btkM1Ay3XNdqjpBNcCx1as/A== X-Google-Smtp-Source: AGHT+IECfFst9YsrR74+b52RmZLy9M9KXPMfA+PoNFzuGn/ZVvte53NMfTf9ib4YmQOSoxKMcxtfzw== X-Received: by 2002:a05:6000:18a9:b0:32f:9a39:777f with SMTP id b9-20020a05600018a900b0032f9a39777fmr15067192wri.62.1699268689108; Mon, 06 Nov 2023 03:04:49 -0800 (PST) Received: from m1x-phil.lan (176-131-220-199.abo.bbox.fr. [176.131.220.199]) by smtp.gmail.com with ESMTPSA id z2-20020a5d6402000000b0032d9caeab0fsm9209526wru.77.2023.11.06.03.04.47 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:04:48 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Peter Maydell Subject: [PULL 10/60] target/arm: Move internal declarations from 'cpu-qom.h' to 'cpu.h' Date: Mon, 6 Nov 2023 12:02:42 +0100 Message-ID: <20231106110336.358-11-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 These definitions and declarations are only used by target/arm/, no need to expose them to generic hw/. Reviewed-by: Richard Henderson Message-Id: <20231013140116.255-4-philmd@linaro.org> Signed-off-by: Philippe Mathieu-Daudé Message-Id: --- target/arm/cpu-qom.h | 28 ---------------------------- target/arm/cpu.h | 22 ++++++++++++++++++++++ target/arm/internals.h | 6 ++++++ 3 files changed, 28 insertions(+), 28 deletions(-) diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h index dfb9d5b827..35c3b0924e 100644 --- a/target/arm/cpu-qom.h +++ b/target/arm/cpu-qom.h @@ -35,9 +35,6 @@ typedef struct ARMCPUInfo { void (*class_init)(ObjectClass *oc, void *data); } ARMCPUInfo; -void arm_cpu_register(const ARMCPUInfo *info); -void aarch64_cpu_register(const ARMCPUInfo *info); - /** * ARMCPUClass: * @parent_realize: The parent class' realize handler. @@ -63,29 +60,4 @@ struct AArch64CPUClass { ARMCPUClass parent_class; }; -void register_cp_regs_for_features(ARMCPU *cpu); -void init_cpreg_list(ARMCPU *cpu); - -/* Callback functions for the generic timer's timers. */ -void arm_gt_ptimer_cb(void *opaque); -void arm_gt_vtimer_cb(void *opaque); -void arm_gt_htimer_cb(void *opaque); -void arm_gt_stimer_cb(void *opaque); -void arm_gt_hvtimer_cb(void *opaque); - -#define ARM_AFF0_SHIFT 0 -#define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT) -#define ARM_AFF1_SHIFT 8 -#define ARM_AFF1_MASK (0xFFULL << ARM_AFF1_SHIFT) -#define ARM_AFF2_SHIFT 16 -#define ARM_AFF2_MASK (0xFFULL << ARM_AFF2_SHIFT) -#define ARM_AFF3_SHIFT 32 -#define ARM_AFF3_MASK (0xFFULL << ARM_AFF3_SHIFT) -#define ARM_DEFAULT_CPUS_PER_CLUSTER 8 - -#define ARM32_AFFINITY_MASK (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK) -#define ARM64_AFFINITY_MASK \ - (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK|ARM_AFF3_MASK) -#define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK) - #endif diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 2f7ab22169..4a86c8f831 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1116,11 +1116,33 @@ struct ArchCPU { uint64_t gt_cntfrq_hz; }; +/* Callback functions for the generic timer's timers. */ +void arm_gt_ptimer_cb(void *opaque); +void arm_gt_vtimer_cb(void *opaque); +void arm_gt_htimer_cb(void *opaque); +void arm_gt_stimer_cb(void *opaque); +void arm_gt_hvtimer_cb(void *opaque); + unsigned int gt_cntfrq_period_ns(ARMCPU *cpu); void gt_rme_post_el_change(ARMCPU *cpu, void *opaque); void arm_cpu_post_init(Object *obj); +#define ARM_AFF0_SHIFT 0 +#define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT) +#define ARM_AFF1_SHIFT 8 +#define ARM_AFF1_MASK (0xFFULL << ARM_AFF1_SHIFT) +#define ARM_AFF2_SHIFT 16 +#define ARM_AFF2_MASK (0xFFULL << ARM_AFF2_SHIFT) +#define ARM_AFF3_SHIFT 32 +#define ARM_AFF3_MASK (0xFFULL << ARM_AFF3_SHIFT) +#define ARM_DEFAULT_CPUS_PER_CLUSTER 8 + +#define ARM32_AFFINITY_MASK (ARM_AFF0_MASK | ARM_AFF1_MASK | ARM_AFF2_MASK) +#define ARM64_AFFINITY_MASK \ + (ARM_AFF0_MASK | ARM_AFF1_MASK | ARM_AFF2_MASK | ARM_AFF3_MASK) +#define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK) + uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); #ifndef CONFIG_USER_ONLY diff --git a/target/arm/internals.h b/target/arm/internals.h index c837506e44..143d57c0fe 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -183,6 +183,12 @@ static inline int r14_bank_number(int mode) return (mode == ARM_CPU_MODE_HYP) ? BANK_USRSYS : bank_number(mode); } +void arm_cpu_register(const ARMCPUInfo *info); +void aarch64_cpu_register(const ARMCPUInfo *info); + +void register_cp_regs_for_features(ARMCPU *cpu); +void init_cpreg_list(ARMCPU *cpu); + void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu); void arm_translate_init(void); From patchwork Mon Nov 6 11:02:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13446627 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E1273199A7 for ; Mon, 6 Nov 2023 11:04:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="QIG1oeoY" Received: from mail-lf1-x12b.google.com (mail-lf1-x12b.google.com [IPv6:2a00:1450:4864:20::12b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9E5CD98 for ; Mon, 6 Nov 2023 03:04:57 -0800 (PST) Received: by mail-lf1-x12b.google.com with SMTP id 2adb3069b0e04-5094cb3a036so5224991e87.2 for ; Mon, 06 Nov 2023 03:04:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699268696; x=1699873496; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vePePWiaVFUAUv821iwYutEeShxemZReiuwQp7UFnAo=; b=QIG1oeoYYiMyDF8MK5Kh2mQKLT0xhZ/c00lDbEnRoa/CsDQZ+swg4IUmwa7lsR1d+P SQ0JikYTKJ+J9VfS4F3DF3cUBMq25QUQp9nn8OQgnBAutLMVIFAgnfp90zIjGqw2br/4 Vx7XagEOnhtGQwA11s+hGLiueF6UYLsuEGqYlTeJLmvkz58dt7qO8wEXnMqFgzMwoSu8 mPKi9MQGg5j5aSLhEmNdd4Zf5i6EXWyMStqEfCvc97gHPHOsMpNhAWAOYzLvJio3YfKw wKQlD3mHDtlo3r/ffRxFWBRUQNpCSG/6TZMLbFo9rpf5tfrjmOnKAiEPuevW3ZMen198 OkQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699268696; x=1699873496; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vePePWiaVFUAUv821iwYutEeShxemZReiuwQp7UFnAo=; b=MseNM+Spn4b1wbKo7o28Z0TlnRV/Rylw5grr92pqVxbgWSSKeiWMoxeHxwWaN/5365 Qq7wV4tiKJkzYJ4DAAh0YHkkmzIq4DNwew82rmcmWlM4ankBI72KtZ3dlIFill2ktlpY fjKd+5C9VEfybjOogy4zzSbQkODeuZ1nMBebVsAtBlJkjSRrZ4KmwDZvjZcQ/mQsACKy SQqrkj0XAA1K4LqBHN5sX0rNJ2Fo/nO4EcGsH9iSu1IsYqQWB9zz7YdcF93xl8IXP8za C7OerxBxfT879iY5aGUbxMIliclDF6JkoNbAmZogMAxcGxmQX64gv+DoFi+dD89muSRl HWaQ== X-Gm-Message-State: AOJu0YxvK4pn6wUthor4IIa0Ns/B0MUJuh7yu49C7X9mIEHeRUftP4JB wfDBidpAo7fay6ebpdel0Q4aIA== X-Google-Smtp-Source: AGHT+IGU7JDB32d3EmZv97kO2MEntQmcvvGtu7x3AN/j6r3vWH3xlZC+Z5FtDVtjxNdca8AyJOth4A== X-Received: by 2002:ac2:4d93:0:b0:507:b074:ecd4 with SMTP id g19-20020ac24d93000000b00507b074ecd4mr20448646lfe.7.1699268695795; Mon, 06 Nov 2023 03:04:55 -0800 (PST) Received: from m1x-phil.lan (176-131-220-199.abo.bbox.fr. [176.131.220.199]) by smtp.gmail.com with ESMTPSA id p12-20020adfce0c000000b0032dc1fc84f2sm9191301wrn.46.2023.11.06.03.04.53 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:04:55 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Nicholas Piggin , Daniel Henrique Barboza , =?utf-8?q?C=C3=A9dric_Le_G?= =?utf-8?q?oater?= Subject: [PULL 11/60] target/ppc: Remove CPU_RESOLVING_TYPE from 'cpu-qom.h' Date: Mon, 6 Nov 2023 12:02:43 +0100 Message-ID: <20231106110336.358-12-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 CPU_RESOLVING_TYPE is a per-target definition, and is irrelevant for other targets. Move it to "cpu.h". "target/ppc/cpu-qom.h" is supposed to be target agnostic (include-able by any target). Add such mention in the header. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20231013140116.255-5-philmd@linaro.org> --- target/ppc/cpu-qom.h | 3 +-- target/ppc/cpu.h | 2 ++ 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index be33786bd8..41df51269b 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -1,5 +1,5 @@ /* - * QEMU PowerPC CPU + * QEMU PowerPC CPU QOM header (target agnostic) * * Copyright (c) 2012 SUSE LINUX Products GmbH * @@ -33,7 +33,6 @@ OBJECT_DECLARE_CPU_TYPE(PowerPCCPU, PowerPCCPUClass, POWERPC_CPU) #define POWERPC_CPU_TYPE_SUFFIX "-" TYPE_POWERPC_CPU #define POWERPC_CPU_TYPE_NAME(model) model POWERPC_CPU_TYPE_SUFFIX -#define CPU_RESOLVING_TYPE TYPE_POWERPC_CPU #define TYPE_HOST_POWERPC_CPU POWERPC_CPU_TYPE_NAME("host") diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 24dd6b1b0a..02619e5d54 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -27,6 +27,8 @@ #include "qom/object.h" #include "hw/registerfields.h" +#define CPU_RESOLVING_TYPE TYPE_POWERPC_CPU + #define TCG_GUEST_DEFAULT_MO 0 #define TARGET_PAGE_BITS_64K 16 From patchwork Mon Nov 6 11:02:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13446628 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5529F1A598 for ; Mon, 6 Nov 2023 11:05:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="YVnYOCXg" Received: from mail-wm1-x329.google.com (mail-wm1-x329.google.com [IPv6:2a00:1450:4864:20::329]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 09D4298 for ; Mon, 6 Nov 2023 03:05:04 -0800 (PST) Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-4081ccf69dcso31167025e9.0 for ; Mon, 06 Nov 2023 03:05:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699268702; x=1699873502; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RkZROkW3VJc36/l321YGkxp/mj9LkNXWejNsMfklYm4=; b=YVnYOCXgDyvghTY2UF9oGvYb3nezSSWAdUnQHIS/fnUNqSdQqX6lubupYGznln3fJL 9dslcbraBXZwlsllN9GHsdY/N2IhJWZJ+0dxR7Z6s3R4gFGTXP17AzFljDqbOwy8D+28 ZfVsgLzxbgM24v0/q6bX1Tvh07dJM+nO1t7MYbVRG2sy1dUWCnY97afVnaiguS5aDPjZ hz4APexPWcfCmt7Sm0tK1KbplZuA94CcFHvkM2x10a59E4U4KjzsuCgmQAP8JwhQj8Da MX5Jye6QnyA/9sibpNJDaMQENlI9KAac1Go6uVlSBo1pyN2s7xrVK86bzxgI1S2mxhde 0oJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699268702; x=1699873502; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RkZROkW3VJc36/l321YGkxp/mj9LkNXWejNsMfklYm4=; b=Yuh589YnJ6a6SQ0dD0ED5L1++Tosg7NANZVxiYS2E5wBMf4XMVvMMZPutA4ziK4lHM kA+Nh6fmVc/AGWvh0qrZzhcxlh4jxazQGYCqPCpN+wxn1lghsLFRSfevmr4Na/wzrwBr bfJK6Zrzr9sSB0+J/K5xzBzp96lcVZ8VtVwfjLy3RvvJkCbdySUCFgCVm1UUbaw1yAft 3Xxe/j5TMSRFmnkxCrS6mu+NAiqzt9FGul2Tf2mMVWWOXZFlda/m2ej3cYfOIZ1E4vyb k3fzNTS3XNS1pVRBgVswcLQBnOnl8RJ/zeyHA9Lw1kjZGJ+ad3TASMqgiZCb5GDA3ew0 81og== X-Gm-Message-State: AOJu0YyuqRmoba6Fzge4uQ6kcTpWLKbTUAgHxOE6yUzpIVnd3T3Y54n1 3XpyFu3EU/PPMyB0Ju11r9lwN82Vbfo6r8guxrA= X-Google-Smtp-Source: AGHT+IGPi0CoBElw4e4e166oDDPnxqGeqjewSbN0jbUXOO8Wcvzxylrv4M0+O34JS3v7Ej+kyRAkyA== X-Received: by 2002:a05:6000:1845:b0:32d:a431:9045 with SMTP id c5-20020a056000184500b0032da4319045mr10462910wri.30.1699268702575; Mon, 06 Nov 2023 03:05:02 -0800 (PST) Received: from m1x-phil.lan (176-131-220-199.abo.bbox.fr. [176.131.220.199]) by smtp.gmail.com with ESMTPSA id k9-20020a056000004900b0032dbf26e7aesm8956250wrx.65.2023.11.06.03.05.00 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:05:02 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , LIU Zhiwei , Richard Henderson , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza Subject: [PULL 12/60] target/riscv: Remove CPU_RESOLVING_TYPE from 'cpu-qom.h' Date: Mon, 6 Nov 2023 12:02:44 +0100 Message-ID: <20231106110336.358-13-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 CPU_RESOLVING_TYPE is a per-target definition, and is irrelevant for other targets. Move it to "cpu.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: LIU Zhiwei Reviewed-by: Richard Henderson Message-Id: <20231013140116.255-6-philmd@linaro.org> --- target/riscv/cpu-qom.h | 1 - target/riscv/cpu.h | 2 ++ 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index b9164a8e5b..b78169093f 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -27,7 +27,6 @@ #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) -#define CPU_RESOLVING_TYPE TYPE_RISCV_CPU #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") #define TYPE_RISCV_CPU_MAX RISCV_CPU_TYPE_NAME("max") diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index f0dc257a75..144cc94cce 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -32,6 +32,8 @@ #include "qapi/qapi-types-common.h" #include "cpu-qom.h" +#define CPU_RESOLVING_TYPE TYPE_RISCV_CPU + #define TCG_GUEST_DEFAULT_MO 0 /* From patchwork Mon Nov 6 11:02:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13446629 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 22B651A701 for ; Mon, 6 Nov 2023 11:05:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="P+25o6DE" Received: from mail-lj1-x234.google.com (mail-lj1-x234.google.com [IPv6:2a00:1450:4864:20::234]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AA053BB for ; Mon, 6 Nov 2023 03:05:12 -0800 (PST) Received: by mail-lj1-x234.google.com with SMTP id 38308e7fff4ca-2c6efcef4eeso52232321fa.1 for ; Mon, 06 Nov 2023 03:05:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699268711; x=1699873511; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WxUmiCwPV5zJl3mXwLh1MUI3WD6xJyg5vO6bbT+CodM=; b=P+25o6DEOLUViaRGcFEQjg/TKY2Cjuz7z/Z/4lgmT6VQRPoxUVHPPC00MFPkty7m08 7ZhDRSP9MCJf4uoCSBqt6D4BHDukOifLTkZbUTY1+EQDm6xo9teNXv8U48zH6teVLOqA 6tOCQOrjs6pNXQFYpP1qnw6kVkdaKvjrKgXmWbEzhfqA078mk1L2dkKLWrZF4szlm1/O xkFtytUcA8jLD0K0sBMgvIqL9pwCStGhUIU98gJwPnIG0OnoOdtmTj+gSDD+jc18jSRA XO64vAMMpUJT5COkYyWDS94N5fD/k9CjqIfsUWOUMN9eJtYG3FSdERlVGs8CnMrs7B4U IQLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699268711; x=1699873511; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WxUmiCwPV5zJl3mXwLh1MUI3WD6xJyg5vO6bbT+CodM=; b=eSnDHnc6LYvEKEJ/yye8yQdDMryJB9vGQHRnoHVHGB2GbgJArVSimvzKzQ9rHtWJCU njv/5fj6SdF3gGvWd/+ZnD3YKf0nBeEsxpNSvruNiFkAncx+KKzXb0qA4oCBTMJyAjH2 cOsOkTOd2k0kLOi+BfGh4/iL1ZNAXW89rc3W2hQTy/PCIJeftw8BpMRhjj87dSvRd+Gc tEc51RaheCq+vqBIeBbknVzz+dL9H9t3QV81Lbg8l+pSkfy5nNZgTG7ewW4BrecyGE0k vWMdKYIv1vigJlIt3K8SoNsNpjJ9gEumNioApN2po+hodW9/bNOAvNc34GSt/QqxIRHn izjg== X-Gm-Message-State: AOJu0YwEsW0rzX3OzteDY6F/w5KD94x9V2WXo3UCg7QMyLddZ3LnNpsu 88AKbdZsLXeaTW0vkOsjykeOiw== X-Google-Smtp-Source: AGHT+IGesghmwnsW7pNz/cPIy+OAEt0HtfvDXrPkmNh4TvVN2ENKoIeGC2Q+uLhqqoE2yhO8HQohrw== X-Received: by 2002:a2e:b0e5:0:b0:2c5:2813:5538 with SMTP id h5-20020a2eb0e5000000b002c528135538mr22071679ljl.21.1699268710824; Mon, 06 Nov 2023 03:05:10 -0800 (PST) Received: from m1x-phil.lan (176-131-220-199.abo.bbox.fr. [176.131.220.199]) by smtp.gmail.com with ESMTPSA id a11-20020a05600c2d4b00b00405c33a9a12sm6133016wmg.0.2023.11.06.03.05.07 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:05:10 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , LIU Zhiwei , Richard Henderson , Michael Rolnik , "Edgar E. Iglesias" , Laurent Vivier , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Yoshinori Sato , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Bastian Koppelmann , Max Filippov Subject: [PULL 13/60] target: Declare FOO_CPU_TYPE_NAME/SUFFIX in 'cpu-qom.h' Date: Mon, 6 Nov 2023 12:02:45 +0100 Message-ID: <20231106110336.358-14-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Hegerogeneous code needs access to the FOO_CPU_TYPE_NAME() macro to resolve target CPU types. Move the declaration (along with the required FOO_CPU_TYPE_SUFFIX) to "cpu-qom.h". "target/foo/cpu-qom.h" is supposed to be target agnostic (include-able by any target). Add such mention in the header. Signed-off-by: Philippe Mathieu-Daudé Acked-by: LIU Zhiwei Reviewed-by: Richard Henderson Message-Id: <20231013140116.255-7-philmd@linaro.org> --- target/alpha/cpu-qom.h | 5 ++++- target/alpha/cpu.h | 2 -- target/avr/cpu-qom.h | 5 ++++- target/avr/cpu.h | 2 -- target/cris/cpu-qom.h | 5 ++++- target/cris/cpu.h | 2 -- target/i386/cpu-qom.h | 3 +++ target/i386/cpu.h | 2 -- target/m68k/cpu-qom.h | 5 ++++- target/m68k/cpu.h | 2 -- target/mips/cpu-qom.h | 3 +++ target/mips/cpu.h | 2 -- target/rx/cpu-qom.h | 5 ++++- target/rx/cpu.h | 2 -- target/s390x/cpu-qom.h | 5 ++++- target/s390x/cpu.h | 2 -- target/sh4/cpu-qom.h | 5 ++++- target/sh4/cpu.h | 2 -- target/sparc/cpu-qom.h | 5 ++++- target/sparc/cpu.h | 2 -- target/tricore/cpu-qom.h | 5 +++++ target/tricore/cpu.h | 2 -- target/xtensa/cpu-qom.h | 5 ++++- target/xtensa/cpu.h | 2 -- 24 files changed, 47 insertions(+), 33 deletions(-) diff --git a/target/alpha/cpu-qom.h b/target/alpha/cpu-qom.h index c5fbd8f11a..c4a4523993 100644 --- a/target/alpha/cpu-qom.h +++ b/target/alpha/cpu-qom.h @@ -1,5 +1,5 @@ /* - * QEMU Alpha CPU + * QEMU Alpha CPU QOM header (target agnostic) * * Copyright (c) 2012 SUSE LINUX Products GmbH * @@ -27,6 +27,9 @@ OBJECT_DECLARE_CPU_TYPE(AlphaCPU, AlphaCPUClass, ALPHA_CPU) +#define ALPHA_CPU_TYPE_SUFFIX "-" TYPE_ALPHA_CPU +#define ALPHA_CPU_TYPE_NAME(model) model ALPHA_CPU_TYPE_SUFFIX + /** * AlphaCPUClass: * @parent_realize: The parent class' realize handler. diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index c8d97ac27a..3bff56c565 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -426,8 +426,6 @@ enum { void alpha_translate_init(void); -#define ALPHA_CPU_TYPE_SUFFIX "-" TYPE_ALPHA_CPU -#define ALPHA_CPU_TYPE_NAME(model) model ALPHA_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_ALPHA_CPU void alpha_cpu_list(void); diff --git a/target/avr/cpu-qom.h b/target/avr/cpu-qom.h index d89be01e0f..75590cdd97 100644 --- a/target/avr/cpu-qom.h +++ b/target/avr/cpu-qom.h @@ -1,5 +1,5 @@ /* - * QEMU AVR CPU + * QEMU AVR CPU QOM header (target agnostic) * * Copyright (c) 2016-2020 Michael Rolnik * @@ -28,6 +28,9 @@ OBJECT_DECLARE_CPU_TYPE(AVRCPU, AVRCPUClass, AVR_CPU) +#define AVR_CPU_TYPE_SUFFIX "-" TYPE_AVR_CPU +#define AVR_CPU_TYPE_NAME(name) (name AVR_CPU_TYPE_SUFFIX) + /** * AVRCPUClass: * @parent_realize: The parent class' realize handler. diff --git a/target/avr/cpu.h b/target/avr/cpu.h index f8b065ed79..0487399cb2 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -28,8 +28,6 @@ #error "AVR 8-bit does not support user mode" #endif -#define AVR_CPU_TYPE_SUFFIX "-" TYPE_AVR_CPU -#define AVR_CPU_TYPE_NAME(name) (name AVR_CPU_TYPE_SUFFIX) #define CPU_RESOLVING_TYPE TYPE_AVR_CPU #define TCG_GUEST_DEFAULT_MO 0 diff --git a/target/cris/cpu-qom.h b/target/cris/cpu-qom.h index c2fee242f4..d7e5f33e62 100644 --- a/target/cris/cpu-qom.h +++ b/target/cris/cpu-qom.h @@ -1,5 +1,5 @@ /* - * QEMU CRIS CPU + * QEMU CRIS CPU QOM header (target agnostic) * * Copyright (c) 2012 SUSE LINUX Products GmbH * @@ -27,6 +27,9 @@ OBJECT_DECLARE_CPU_TYPE(CRISCPU, CRISCPUClass, CRIS_CPU) +#define CRIS_CPU_TYPE_SUFFIX "-" TYPE_CRIS_CPU +#define CRIS_CPU_TYPE_NAME(name) (name CRIS_CPU_TYPE_SUFFIX) + /** * CRISCPUClass: * @parent_realize: The parent class' realize handler. diff --git a/target/cris/cpu.h b/target/cris/cpu.h index 6aa445348f..b821bb7983 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -240,8 +240,6 @@ enum { /* CRIS uses 8k pages. */ #define MMAP_SHIFT TARGET_PAGE_BITS -#define CRIS_CPU_TYPE_SUFFIX "-" TYPE_CRIS_CPU -#define CRIS_CPU_TYPE_NAME(name) (name CRIS_CPU_TYPE_SUFFIX) #define CPU_RESOLVING_TYPE TYPE_CRIS_CPU /* MMU modes definitions */ diff --git a/target/i386/cpu-qom.h b/target/i386/cpu-qom.h index 58145717ef..dffc74c1ce 100644 --- a/target/i386/cpu-qom.h +++ b/target/i386/cpu-qom.h @@ -32,6 +32,9 @@ OBJECT_DECLARE_CPU_TYPE(X86CPU, X86CPUClass, X86_CPU) +#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU +#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX) + typedef struct X86CPUModel X86CPUModel; /** diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 096f85483e..6c6b066986 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2239,8 +2239,6 @@ void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7); /* hw/pc.c */ uint64_t cpu_get_tsc(CPUX86State *env); -#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU -#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX) #define CPU_RESOLVING_TYPE TYPE_X86_CPU #ifdef TARGET_X86_64 diff --git a/target/m68k/cpu-qom.h b/target/m68k/cpu-qom.h index 13d94c9fe3..df0cc8b7a3 100644 --- a/target/m68k/cpu-qom.h +++ b/target/m68k/cpu-qom.h @@ -1,5 +1,5 @@ /* - * QEMU Motorola 68k CPU + * QEMU Motorola 68k CPU QOM header (target agnostic) * * Copyright (c) 2012 SUSE LINUX Products GmbH * @@ -27,6 +27,9 @@ OBJECT_DECLARE_CPU_TYPE(M68kCPU, M68kCPUClass, M68K_CPU) +#define M68K_CPU_TYPE_SUFFIX "-" TYPE_M68K_CPU +#define M68K_CPU_TYPE_NAME(model) model M68K_CPU_TYPE_SUFFIX + /* * M68kCPUClass: * @parent_realize: The parent class' realize handler. diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 9ea18028ad..7f34686a6f 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -561,8 +561,6 @@ enum { ACCESS_DATA = 0x20, /* Data load/store access */ }; -#define M68K_CPU_TYPE_SUFFIX "-" TYPE_M68K_CPU -#define M68K_CPU_TYPE_NAME(model) model M68K_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_M68K_CPU #define cpu_list m68k_cpu_list diff --git a/target/mips/cpu-qom.h b/target/mips/cpu-qom.h index c70b4a34be..5822dfb1d2 100644 --- a/target/mips/cpu-qom.h +++ b/target/mips/cpu-qom.h @@ -31,6 +31,9 @@ OBJECT_DECLARE_CPU_TYPE(MIPSCPU, MIPSCPUClass, MIPS_CPU) +#define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU +#define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX + /** * MIPSCPUClass: * @parent_realize: The parent class' realize handler. diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 617c373797..12cc1bfafd 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1301,8 +1301,6 @@ enum { */ #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0 -#define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU -#define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_MIPS_CPU bool cpu_type_supports_cps_smp(const char *cpu_type); diff --git a/target/rx/cpu-qom.h b/target/rx/cpu-qom.h index f4cd5664e5..6213d877f7 100644 --- a/target/rx/cpu-qom.h +++ b/target/rx/cpu-qom.h @@ -1,5 +1,5 @@ /* - * RX CPU + * QEMU RX CPU QOM header (target agnostic) * * Copyright (c) 2019 Yoshinori Sato * @@ -28,6 +28,9 @@ OBJECT_DECLARE_CPU_TYPE(RXCPU, RXCPUClass, RX_CPU) +#define RX_CPU_TYPE_SUFFIX "-" TYPE_RX_CPU +#define RX_CPU_TYPE_NAME(model) model RX_CPU_TYPE_SUFFIX + /* * RXCPUClass: * @parent_realize: The parent class' realize handler. diff --git a/target/rx/cpu.h b/target/rx/cpu.h index 8379f4a150..c81613770c 100644 --- a/target/rx/cpu.h +++ b/target/rx/cpu.h @@ -112,8 +112,6 @@ struct ArchCPU { CPURXState env; }; -#define RX_CPU_TYPE_SUFFIX "-" TYPE_RX_CPU -#define RX_CPU_TYPE_NAME(model) model RX_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_RX_CPU const char *rx_crname(uint8_t cr); diff --git a/target/s390x/cpu-qom.h b/target/s390x/cpu-qom.h index 1088965fd5..fcd70daddf 100644 --- a/target/s390x/cpu-qom.h +++ b/target/s390x/cpu-qom.h @@ -1,5 +1,5 @@ /* - * QEMU S/390 CPU + * QEMU S/390 CPU QOM header (target agnostic) * * Copyright (c) 2012 SUSE LINUX Products GmbH * @@ -27,6 +27,9 @@ OBJECT_DECLARE_CPU_TYPE(S390CPU, S390CPUClass, S390_CPU) +#define S390_CPU_TYPE_SUFFIX "-" TYPE_S390_CPU +#define S390_CPU_TYPE_NAME(name) (name S390_CPU_TYPE_SUFFIX) + typedef struct S390CPUModel S390CPUModel; typedef struct S390CPUDef S390CPUDef; diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 4f366f9e4e..38d7197f4c 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -890,8 +890,6 @@ void s390_set_qemu_cpu_model(uint16_t type, uint8_t gen, uint8_t ec_ga, /* helper.c */ -#define S390_CPU_TYPE_SUFFIX "-" TYPE_S390_CPU -#define S390_CPU_TYPE_NAME(name) (name S390_CPU_TYPE_SUFFIX) #define CPU_RESOLVING_TYPE TYPE_S390_CPU /* interrupt.c */ diff --git a/target/sh4/cpu-qom.h b/target/sh4/cpu-qom.h index 08fbebc996..bd0ef49fa1 100644 --- a/target/sh4/cpu-qom.h +++ b/target/sh4/cpu-qom.h @@ -1,5 +1,5 @@ /* - * QEMU SuperH CPU + * QEMU SuperH CPU QOM header (target agnostic) * * Copyright (c) 2012 SUSE LINUX Products GmbH * @@ -31,6 +31,9 @@ OBJECT_DECLARE_CPU_TYPE(SuperHCPU, SuperHCPUClass, SUPERH_CPU) +#define SUPERH_CPU_TYPE_SUFFIX "-" TYPE_SUPERH_CPU +#define SUPERH_CPU_TYPE_NAME(model) model SUPERH_CPU_TYPE_SUFFIX + /** * SuperHCPUClass: * @parent_realize: The parent class' realize handler. diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index dc0561b73b..dbe00e29c2 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -250,8 +250,6 @@ int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr); void cpu_load_tlb(CPUSH4State * env); -#define SUPERH_CPU_TYPE_SUFFIX "-" TYPE_SUPERH_CPU -#define SUPERH_CPU_TYPE_NAME(model) model SUPERH_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_SUPERH_CPU #define cpu_list sh4_cpu_list diff --git a/target/sparc/cpu-qom.h b/target/sparc/cpu-qom.h index b4a0db84ce..aca29415b4 100644 --- a/target/sparc/cpu-qom.h +++ b/target/sparc/cpu-qom.h @@ -1,5 +1,5 @@ /* - * QEMU SPARC CPU + * QEMU SPARC CPU QOM header (target agnostic) * * Copyright (c) 2012 SUSE LINUX Products GmbH * @@ -31,6 +31,9 @@ OBJECT_DECLARE_CPU_TYPE(SPARCCPU, SPARCCPUClass, SPARC_CPU) +#define SPARC_CPU_TYPE_SUFFIX "-" TYPE_SPARC_CPU +#define SPARC_CPU_TYPE_NAME(model) model SPARC_CPU_TYPE_SUFFIX + typedef struct sparc_def_t sparc_def_t; /** * SPARCCPUClass: diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 84a030e406..8c567037cb 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -660,8 +660,6 @@ hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr, #endif #endif -#define SPARC_CPU_TYPE_SUFFIX "-" TYPE_SPARC_CPU -#define SPARC_CPU_TYPE_NAME(model) model SPARC_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_SPARC_CPU #define cpu_list sparc_cpu_list diff --git a/target/tricore/cpu-qom.h b/target/tricore/cpu-qom.h index b3b6c75a3a..2598651008 100644 --- a/target/tricore/cpu-qom.h +++ b/target/tricore/cpu-qom.h @@ -1,4 +1,6 @@ /* + * QEMU TriCore CPU QOM header (target agnostic) + * * Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn * * This library is free software; you can redistribute it and/or @@ -26,6 +28,9 @@ OBJECT_DECLARE_CPU_TYPE(TriCoreCPU, TriCoreCPUClass, TRICORE_CPU) +#define TRICORE_CPU_TYPE_SUFFIX "-" TYPE_TRICORE_CPU +#define TRICORE_CPU_TYPE_NAME(model) model TRICORE_CPU_TYPE_SUFFIX + struct TriCoreCPUClass { CPUClass parent_class; diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index b4a6ab141d..c537a33ee8 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -268,8 +268,6 @@ static inline void cpu_get_tb_cpu_state(CPUTriCoreState *env, vaddr *pc, *flags = new_flags; } -#define TRICORE_CPU_TYPE_SUFFIX "-" TYPE_TRICORE_CPU -#define TRICORE_CPU_TYPE_NAME(model) model TRICORE_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_TRICORE_CPU /* helpers.c */ diff --git a/target/xtensa/cpu-qom.h b/target/xtensa/cpu-qom.h index 424bcbd8dd..03873ea50b 100644 --- a/target/xtensa/cpu-qom.h +++ b/target/xtensa/cpu-qom.h @@ -1,5 +1,5 @@ /* - * QEMU Xtensa CPU + * QEMU Xtensa CPU QOM header (target agnostic) * * Copyright (c) 2012 SUSE LINUX Products GmbH * All rights reserved. @@ -36,6 +36,9 @@ OBJECT_DECLARE_CPU_TYPE(XtensaCPU, XtensaCPUClass, XTENSA_CPU) +#define XTENSA_CPU_TYPE_SUFFIX "-" TYPE_XTENSA_CPU +#define XTENSA_CPU_TYPE_NAME(model) model XTENSA_CPU_TYPE_SUFFIX + typedef struct XtensaConfig XtensaConfig; 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id l9-20020adfe589000000b0032f7d7ec4adsm9108143wrm.92.2023.11.06.03.05.15 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:05:17 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Brian Cain Subject: [PULL 14/60] target/hexagon: Declare QOM definitions in 'cpu-qom.h' Date: Mon, 6 Nov 2023 12:02:46 +0100 Message-ID: <20231106110336.358-15-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 "target/foo/cpu.h" contains the target specific declarations. A heterogeneous setup need to access target agnostic declarations (at least the QOM ones, to instantiate the objects). Our convention is to add such target agnostic QOM declarations in the "target/foo/cpu-qom.h" header. Add a comment clarifying that in the header. Extract QOM definitions from "cpu.h" to "cpu-qom.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Brian Cain Message-Id: <20231013140116.255-8-philmd@linaro.org> --- target/hexagon/cpu-qom.h | 28 ++++++++++++++++++++++++++++ target/hexagon/cpu.h | 15 +-------------- 2 files changed, 29 insertions(+), 14 deletions(-) create mode 100644 target/hexagon/cpu-qom.h diff --git a/target/hexagon/cpu-qom.h b/target/hexagon/cpu-qom.h new file mode 100644 index 0000000000..f02df7ee6f --- /dev/null +++ b/target/hexagon/cpu-qom.h @@ -0,0 +1,28 @@ +/* + * QEMU Hexagon CPU QOM header (target agnostic) + * + * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef QEMU_HEXAGON_CPU_QOM_H +#define QEMU_HEXAGON_CPU_QOM_H + +#include "hw/core/cpu.h" +#include "qom/object.h" + +#define TYPE_HEXAGON_CPU "hexagon-cpu" + +#define HEXAGON_CPU_TYPE_SUFFIX "-" TYPE_HEXAGON_CPU +#define HEXAGON_CPU_TYPE_NAME(name) (name HEXAGON_CPU_TYPE_SUFFIX) + +#define TYPE_HEXAGON_CPU_V67 HEXAGON_CPU_TYPE_NAME("v67") +#define TYPE_HEXAGON_CPU_V68 HEXAGON_CPU_TYPE_NAME("v68") +#define TYPE_HEXAGON_CPU_V69 HEXAGON_CPU_TYPE_NAME("v69") +#define TYPE_HEXAGON_CPU_V71 HEXAGON_CPU_TYPE_NAME("v71") +#define TYPE_HEXAGON_CPU_V73 HEXAGON_CPU_TYPE_NAME("v73") + +OBJECT_DECLARE_CPU_TYPE(HexagonCPU, HexagonCPUClass, HEXAGON_CPU) + +#endif diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 035ac4fb6d..7d16083c6a 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -20,11 +20,10 @@ #include "fpu/softfloat-types.h" +#include "cpu-qom.h" #include "exec/cpu-defs.h" #include "hex_regs.h" #include "mmvec/mmvec.h" -#include "qom/object.h" -#include "hw/core/cpu.h" #include "hw/registerfields.h" #define NUM_PREGS 4 @@ -36,18 +35,8 @@ #define PRED_WRITES_MAX 5 /* 4 insns + endloop */ #define VSTORES_MAX 2 -#define TYPE_HEXAGON_CPU "hexagon-cpu" - -#define HEXAGON_CPU_TYPE_SUFFIX "-" TYPE_HEXAGON_CPU -#define HEXAGON_CPU_TYPE_NAME(name) (name HEXAGON_CPU_TYPE_SUFFIX) #define CPU_RESOLVING_TYPE TYPE_HEXAGON_CPU -#define TYPE_HEXAGON_CPU_V67 HEXAGON_CPU_TYPE_NAME("v67") -#define TYPE_HEXAGON_CPU_V68 HEXAGON_CPU_TYPE_NAME("v68") -#define TYPE_HEXAGON_CPU_V69 HEXAGON_CPU_TYPE_NAME("v69") -#define TYPE_HEXAGON_CPU_V71 HEXAGON_CPU_TYPE_NAME("v71") -#define TYPE_HEXAGON_CPU_V73 HEXAGON_CPU_TYPE_NAME("v73") - void hexagon_cpu_list(void); #define cpu_list hexagon_cpu_list @@ -127,8 +116,6 @@ typedef struct CPUArchState { VTCMStoreLog vtcm_log; } CPUHexagonState; -OBJECT_DECLARE_CPU_TYPE(HexagonCPU, HexagonCPUClass, HEXAGON_CPU) - typedef struct HexagonCPUClass { CPUClass parent_class; From patchwork Mon Nov 6 11:02:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13446631 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 122681C6A3 for ; Mon, 6 Nov 2023 11:05:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="AA4+XnlG" Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2C4141B2 for ; Mon, 6 Nov 2023 03:05:26 -0800 (PST) Received: by mail-wr1-x42c.google.com with SMTP id ffacd0b85a97d-32fb95dfe99so1770946f8f.2 for ; Mon, 06 Nov 2023 03:05:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699268724; x=1699873524; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JXuP88BtphoINz4Bov6u/pkpdXdezQqYli4OVAIpAZI=; b=AA4+XnlG3554s1bGa/aRay++tHiJE7gwBegIEQmofQcGxfg1pLrrI7cw8Uk2Ly/J61 HXkjTwvmhB4YqCIRa3kX2prP9CQjgesrPXrBjN5HMli1BgK5XOIT9PGsoJwzh935tKCm dn8Oe7Tn4Vum8OeyL77+LFxxZyYTD+xJXK8jy8tjNECGRbsKPuWr5KK8bRP6J0p5EDIR 9YP1iigkg1CKyi+W2ZoNtdJsmaNVG17blsoThWjvE4HfpLjwolM4j0NrNZYqqMzND3+3 /LADfVJ5DbI/xyWUPy6LybSWXn65C4zRDyv3fvH6QLrAmopU2MviwF8U+tfPl5OwcJ1S cVRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699268724; x=1699873524; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JXuP88BtphoINz4Bov6u/pkpdXdezQqYli4OVAIpAZI=; b=dhWFXH/r0Ur+7pxwh1E5nLrwP9KfsT5xJ9kLjmbBJovEJGQQoPzFVUt95ulx5C/FK6 rGLbMzBM6NbLfkpdnR/DL6noSQSHA/QOlS6egEXCjO4NdIwNOmTTIG2djZNGAT6rMNge LMp/IJowIWb2zpQh7XPIWs8dSeLHHJIy+5/EWy9FBMCzLCClRx9/RJFFLE+x+qo3zjj8 WB/m7sm+7xXp1re0A1qHQqdzn2UPADfmFgYQAeE/XihMErrfMLGR7RRsiLtBkJ09Nme9 KVuJTwD1LgGubcj2onGl6YacSu/FqGadDQTVlqBlI3pr46QlG4Z2rvsSpCIgoQsrItcH 3YyQ== X-Gm-Message-State: AOJu0YxRKpjbf/UVdsXwW6P+A2j6VpSmpw93V09ChFkW687g9nkUwC2O 4+mNDZl4CCDCwV+bw1SZ3DRlxA== X-Google-Smtp-Source: AGHT+IHaBHUQklVP9Pu5QT4vT7r66jTjw7Yf4RVyFH1CKsmkdCj1+2Bfzei9MwaofGzJpViR1lgQOw== X-Received: by 2002:adf:e6c4:0:b0:32f:adaf:be86 with SMTP id y4-20020adfe6c4000000b0032fadafbe86mr8820884wrm.16.1699268724027; Mon, 06 Nov 2023 03:05:24 -0800 (PST) Received: from m1x-phil.lan (176-131-220-199.abo.bbox.fr. [176.131.220.199]) by smtp.gmail.com with ESMTPSA id f6-20020a5d5686000000b0032f7eaa6e43sm9161653wrv.79.2023.11.06.03.05.22 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:05:23 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Song Gao , Richard Henderson Subject: [PULL 15/60] target/loongarch: Declare QOM definitions in 'cpu-qom.h' Date: Mon, 6 Nov 2023 12:02:47 +0100 Message-ID: <20231106110336.358-16-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 "target/foo/cpu.h" contains the target specific declarations. A heterogeneous setup need to access target agnostic declarations (at least the QOM ones, to instantiate the objects). Our convention is to add such target agnostic QOM declarations in the "target/foo/cpu-qom.h" header. Add a comment clarifying that in the header. Extract QOM definitions from "cpu.h" to "cpu-qom.h". Reviewed-by: Song Gao Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20231013140116.255-9-philmd@linaro.org> --- target/loongarch/cpu-qom.h | 24 ++++++++++++++++++++++++ target/loongarch/cpu.h | 10 +--------- 2 files changed, 25 insertions(+), 9 deletions(-) create mode 100644 target/loongarch/cpu-qom.h diff --git a/target/loongarch/cpu-qom.h b/target/loongarch/cpu-qom.h new file mode 100644 index 0000000000..82c86d146d --- /dev/null +++ b/target/loongarch/cpu-qom.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * QEMU LoongArch CPU QOM header (target agnostic) + * + * Copyright (c) 2021 Loongson Technology Corporation Limited + */ + +#ifndef LOONGARCH_CPU_QOM_H +#define LOONGARCH_CPU_QOM_H + +#include "hw/core/cpu.h" +#include "qom/object.h" + +#define TYPE_LOONGARCH_CPU "loongarch-cpu" +#define TYPE_LOONGARCH32_CPU "loongarch32-cpu" +#define TYPE_LOONGARCH64_CPU "loongarch64-cpu" + +OBJECT_DECLARE_CPU_TYPE(LoongArchCPU, LoongArchCPUClass, + LOONGARCH_CPU) + +#define LOONGARCH_CPU_TYPE_SUFFIX "-" TYPE_LOONGARCH_CPU +#define LOONGARCH_CPU_TYPE_NAME(model) model LOONGARCH_CPU_TYPE_SUFFIX + +#endif diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 8f0e9f0182..c8839f4cff 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -17,6 +17,7 @@ #include "exec/memory.h" #endif #include "cpu-csr.h" +#include "cpu-qom.h" #define IOCSRF_TEMP 0 #define IOCSRF_NODECNT 1 @@ -381,13 +382,6 @@ struct ArchCPU { const char *dtb_compatible; }; -#define TYPE_LOONGARCH_CPU "loongarch-cpu" -#define TYPE_LOONGARCH32_CPU "loongarch32-cpu" -#define TYPE_LOONGARCH64_CPU "loongarch64-cpu" - -OBJECT_DECLARE_CPU_TYPE(LoongArchCPU, LoongArchCPUClass, - LOONGARCH_CPU) - /** * LoongArchCPUClass: * @parent_realize: The parent class' realize handler. @@ -478,8 +472,6 @@ void loongarch_cpu_list(void); #include "exec/cpu-all.h" -#define LOONGARCH_CPU_TYPE_SUFFIX "-" TYPE_LOONGARCH_CPU -#define LOONGARCH_CPU_TYPE_NAME(model) model LOONGARCH_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_LOONGARCH_CPU #endif /* LOONGARCH_CPU_H */ From patchwork Mon Nov 6 11:02:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13446632 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 947F31EB29 for ; Mon, 6 Nov 2023 11:05:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="d34aoMmD" Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [IPv6:2a00:1450:4864:20::32e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B271BB0 for ; Mon, 6 Nov 2023 03:05:32 -0800 (PST) Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-40859c466efso32054395e9.3 for ; Mon, 06 Nov 2023 03:05:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699268731; x=1699873531; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=q3038rtVd/3WYQydMHaBWtXOqOEbAhMugZOF+LS9h+c=; b=d34aoMmDfIIMA7/5qNTponuXAvVYffTv8H7SpF3c0rO/kwnDOiKYZ9gUEZq7SkUTwQ NrOypUKeEpM5ZPZoKa7e7t6cpOokSxdvF1GBJFWjlkYXPdaAOqsFhFmgjk5PvYgk1ALY LChpsWzFJKXhCSbUOar8sehXwMfS/tvehqeH0d+gxtiF8LFkGfRvtCrBdxMPBa2pVAfU NMeLqfuqOKos7XYIFhGtiV5/XCprU5Jobc7GBNjbt3DIw+W+FmjmdJCz8KKP8n7VHLU6 FMxB4mTMoL4/u34pe2qyFy4ed59GhfDNZikZJmZO9/ujgNakhX8XH+eh/ffUugy8qQ4W nAfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699268731; x=1699873531; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=q3038rtVd/3WYQydMHaBWtXOqOEbAhMugZOF+LS9h+c=; b=mZ2X+WxmGAf7ej8N+TE0KpGSvFSj1jRDPy5kr7AFOkSv67/qZDzCEqyVaUzsOt6P2k DavtswuIqCKBaBmCdryTcaB78C5IRijgjvzIdE/4iD/DSy+QdvlwInIZjwNMoLykrnRW cppKq9TORCaGbKs9YlCT2PAwVE5atIMHxBaNWaHiAi2BWxwxrrpwVjGo1vsPUiTyLMOE P3zjP1upRGY13kJajjl9xU9vM3adrwHfvUynnDS/MaWoC2/qUNN5ifoQXPyvy/ClcSVY ZqxaIWAIbnaXU3wXCd+UAL8A7rPoaX/Bl7P46QnvUzB5j+nFs5wcZV1CXTT6aaRPCN7J nemQ== X-Gm-Message-State: AOJu0Yz9T0op3D3Vr698aQsNnCzN7ZfpAAGBuZfSaNnxWlhOPW4gukKP f2iQcC3F47Jf6G5Qg/OpsDB/uQ== X-Google-Smtp-Source: AGHT+IEmOjZD5v1Cylghy37IhDMNKkapCYPdrPhk6W27hiP8WG5JpxCt9Mc0gI0+angLDuM2K899rw== X-Received: by 2002:a05:600c:4897:b0:401:38dc:8916 with SMTP id j23-20020a05600c489700b0040138dc8916mr23234105wmp.10.1699268731199; Mon, 06 Nov 2023 03:05:31 -0800 (PST) Received: from m1x-phil.lan (176-131-220-199.abo.bbox.fr. [176.131.220.199]) by smtp.gmail.com with ESMTPSA id o8-20020a05600c510800b00407752f5ab6sm12025312wms.6.2023.11.06.03.05.29 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:05:30 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Chris Wulff , Marek Vasut Subject: [PULL 16/60] target/nios2: Declare QOM definitions in 'cpu-qom.h' Date: Mon, 6 Nov 2023 12:02:48 +0100 Message-ID: <20231106110336.358-17-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 "target/foo/cpu.h" contains the target specific declarations. A heterogeneous setup need to access target agnostic declarations (at least the QOM ones, to instantiate the objects). Our convention is to add such target agnostic QOM declarations in the "target/foo/cpu-qom.h" header. Add a comment clarifying that in the header. Extract QOM definitions from "cpu.h" to "cpu-qom.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20231013140116.255-10-philmd@linaro.org> --- target/nios2/cpu-qom.h | 19 +++++++++++++++++++ target/nios2/cpu.h | 7 +------ 2 files changed, 20 insertions(+), 6 deletions(-) create mode 100644 target/nios2/cpu-qom.h diff --git a/target/nios2/cpu-qom.h b/target/nios2/cpu-qom.h new file mode 100644 index 0000000000..931bc69b10 --- /dev/null +++ b/target/nios2/cpu-qom.h @@ -0,0 +1,19 @@ +/* + * QEMU Nios II CPU QOM header (target agnostic) + * + * Copyright (c) 2012 Chris Wulff + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#ifndef QEMU_NIOS2_CPU_QOM_H +#define QEMU_NIOS2_CPU_QOM_H + +#include "hw/core/cpu.h" +#include "qom/object.h" + +#define TYPE_NIOS2_CPU "nios2-cpu" + +OBJECT_DECLARE_CPU_TYPE(Nios2CPU, Nios2CPUClass, NIOS2_CPU) + +#endif diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index ede1ba2140..2d79b5b298 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -21,20 +21,15 @@ #ifndef NIOS2_CPU_H #define NIOS2_CPU_H +#include "cpu-qom.h" #include "exec/cpu-defs.h" -#include "hw/core/cpu.h" #include "hw/registerfields.h" -#include "qom/object.h" typedef struct CPUArchState CPUNios2State; #if !defined(CONFIG_USER_ONLY) #include "mmu.h" #endif -#define TYPE_NIOS2_CPU "nios2-cpu" - -OBJECT_DECLARE_CPU_TYPE(Nios2CPU, Nios2CPUClass, NIOS2_CPU) - /** * Nios2CPUClass: * @parent_phases: The parent class' reset phase handlers. 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id o13-20020a05600c4fcd00b0040588d85b3asm11817685wmq.15.2023.11.06.03.05.35 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:05:37 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Stafford Horne Subject: [PULL 17/60] target/openrisc: Declare QOM definitions in 'cpu-qom.h' Date: Mon, 6 Nov 2023 12:02:49 +0100 Message-ID: <20231106110336.358-18-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 "target/foo/cpu.h" contains the target specific declarations. A heterogeneous setup need to access target agnostic declarations (at least the QOM ones, to instantiate the objects). Our convention is to add such target agnostic QOM declarations in the "target/foo/cpu-qom.h" header. Add a comment clarifying that in the header. Extract QOM definitions from "cpu.h" to "cpu-qom.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20231013140116.255-11-philmd@linaro.org> --- target/openrisc/cpu-qom.h | 22 ++++++++++++++++++++++ target/openrisc/cpu.h | 10 +--------- 2 files changed, 23 insertions(+), 9 deletions(-) create mode 100644 target/openrisc/cpu-qom.h diff --git a/target/openrisc/cpu-qom.h b/target/openrisc/cpu-qom.h new file mode 100644 index 0000000000..1ba9fb0a4c --- /dev/null +++ b/target/openrisc/cpu-qom.h @@ -0,0 +1,22 @@ +/* + * QEMU OpenRISC CPU QOM header (target agnostic) + * + * Copyright (c) 2011-2012 Jia Liu + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#ifndef QEMU_OPENRISC_CPU_QOM_H +#define QEMU_OPENRISC_CPU_QOM_H + +#include "hw/core/cpu.h" +#include "qom/object.h" + +#define TYPE_OPENRISC_CPU "or1k-cpu" + +OBJECT_DECLARE_CPU_TYPE(OpenRISCCPU, OpenRISCCPUClass, OPENRISC_CPU) + +#define OPENRISC_CPU_TYPE_SUFFIX "-" TYPE_OPENRISC_CPU +#define OPENRISC_CPU_TYPE_NAME(model) model OPENRISC_CPU_TYPE_SUFFIX + +#endif diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 29cda7279c..dedeb89f8e 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -20,17 +20,12 @@ #ifndef OPENRISC_CPU_H #define OPENRISC_CPU_H +#include "cpu-qom.h" #include "exec/cpu-defs.h" #include "fpu/softfloat-types.h" -#include "hw/core/cpu.h" -#include "qom/object.h" #define TCG_GUEST_DEFAULT_MO (0) -#define TYPE_OPENRISC_CPU "or1k-cpu" - -OBJECT_DECLARE_CPU_TYPE(OpenRISCCPU, OpenRISCCPUClass, OPENRISC_CPU) - /** * OpenRISCCPUClass: * @parent_realize: The parent class' realize handler. @@ -304,7 +299,6 @@ struct ArchCPU { CPUOpenRISCState env; }; - void cpu_openrisc_list(void); void openrisc_cpu_dump_state(CPUState *cpu, FILE *f, int flags); int openrisc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); @@ -339,8 +333,6 @@ void cpu_openrisc_count_start(OpenRISCCPU *cpu); void cpu_openrisc_count_stop(OpenRISCCPU *cpu); #endif -#define OPENRISC_CPU_TYPE_SUFFIX "-" TYPE_OPENRISC_CPU -#define OPENRISC_CPU_TYPE_NAME(model) model OPENRISC_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_OPENRISC_CPU #include "exec/cpu-all.h" From patchwork Mon Nov 6 11:02:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13446634 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C57561EB29 for ; Mon, 6 Nov 2023 11:05:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="PnXLT1eB" Received: from mail-wr1-x433.google.com (mail-wr1-x433.google.com [IPv6:2a00:1450:4864:20::433]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 48805B0 for ; Mon, 6 Nov 2023 03:05:46 -0800 (PST) Received: by mail-wr1-x433.google.com with SMTP id ffacd0b85a97d-32f737deedfso2642022f8f.3 for ; Mon, 06 Nov 2023 03:05:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699268745; x=1699873545; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9TEM4y15WADC11ywrbeYDwNqe54vVpabH+nFuXXR9vo=; b=PnXLT1eBCuQinPJVs97IXV/OXCeaIubvxrdKV2nLnmRWJ0Z3S4VNhygTdPgTesBXPR netZkg0SXXjmtwMJkA1ww5VdyBcLTGuPLyDi2EFA/MYk8/PIGC3n/esI2wooN3PPO3Py 1k72M5T94N6WrStKMS3m2W9iFsOjK5K4Tj84oQnnnjv4WdStFo1XTwmRTPhf0tpnsxAd HaTIsmB0DMeQcPkiAk/grIa+hLOF/HXciMI9lUQ8ZDibpswzXkDXbT/bLymfAh0KOhiL wmvj7D0JKoBiKHpvfkohdZkQIC3qTYkEO2EslSDTGwciJ1+8DxYIR4ng+cy0nLHYrI6f As7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699268745; x=1699873545; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9TEM4y15WADC11ywrbeYDwNqe54vVpabH+nFuXXR9vo=; b=ZzQWkYoT70fTD1D0SGjmsOnJ84NYod29HnpEUdm6cecyWcd93XheUaMPRgTFRJxd8l /GxTKW0/Qcj2+Yl6OCG/pZ/zvhKO3atNQHu6qodjWdfJwVJ1OoPiYBXfDwGB+cldnDZA aYh3ibAC7JdwugIWHV/wHjFiI9BSQ1+C3sHHOp+Lv3cVKAVVkQkoF6OcDE/Z/Ol18EC5 ZRlbvad4C3yJUf1gwM405UcBzTAYROfCtttcgD9JKvmYlh5W5YSZd0KiNWVfS1PpyCRG Dvi7FPA37CIafOD0GPcFkwvDKR/MByGH1ZgIgCVz8waiuhFpgpCSh6if30WMDwUVJSDD 7OJg== X-Gm-Message-State: AOJu0Yxgy/UeFIJalg8MTGoAXXRaCrYLuwIDpdfviQ4AkX4PipbpQ3gj ZSrcr3J2+O2IZfYVyWw57hCI7A== X-Google-Smtp-Source: AGHT+IGOZ/6VrX2QMc3mxuvaPC+0EbE+IDekhwAIoTOTC+UFQrQ0DCYUI0TONme61tWRfDpdV25NAA== X-Received: by 2002:a05:6000:1c0f:b0:32f:ba72:e80b with SMTP id ba15-20020a0560001c0f00b0032fba72e80bmr6504480wrb.54.1699268744791; Mon, 06 Nov 2023 03:05:44 -0800 (PST) Received: from m1x-phil.lan (176-131-220-199.abo.bbox.fr. [176.131.220.199]) by smtp.gmail.com with ESMTPSA id c12-20020adffb0c000000b0032fc5f5abafsm6040847wrr.96.2023.11.06.03.05.42 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:05:44 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , LIU Zhiwei , Alistair Francis , Richard Henderson , Palmer Dabbelt , Bin Meng , Weiwei Li , Daniel Henrique Barboza Subject: [PULL 18/60] target/riscv: Move TYPE_RISCV_CPU_BASE definition to 'cpu.h' Date: Mon, 6 Nov 2023 12:02:50 +0100 Message-ID: <20231106110336.358-19-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 TYPE_RISCV_CPU_BASE depends on the TARGET_RISCV32/TARGET_RISCV64 definitions which are target specific. Such target specific definition taints "cpu-qom.h". Since "cpu-qom.h" must be target agnostic, remove its target specific definition uses by moving TYPE_RISCV_CPU_BASE to "target/riscv/cpu.h". "target/riscv/cpu-qom.h" is now fully target agnostic. Add a comment clarifying that in the header. Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20231013140116.255-12-philmd@linaro.org> --- target/riscv/cpu-qom.h | 8 +------- target/riscv/cpu.h | 6 ++++++ 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index b78169093f..76efb614a6 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -1,5 +1,5 @@ /* - * QEMU RISC-V CPU QOM header + * QEMU RISC-V CPU QOM header (target agnostic) * * Copyright (c) 2023 Ventana Micro Systems Inc. * @@ -44,12 +44,6 @@ #define TYPE_RISCV_CPU_VEYRON_V1 RISCV_CPU_TYPE_NAME("veyron-v1") #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") -#if defined(TARGET_RISCV32) -# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 -#elif defined(TARGET_RISCV64) -# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 -#endif - typedef struct CPUArchState CPURISCVState; OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 144cc94cce..d832696418 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -34,6 +34,12 @@ #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU +#if defined(TARGET_RISCV32) +# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 +#elif defined(TARGET_RISCV64) +# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 +#endif + #define TCG_GUEST_DEFAULT_MO 0 /* From patchwork Mon Nov 6 11:02:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13446635 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 016121EB2E for ; Mon, 6 Nov 2023 11:05:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="qgJaTLaQ" Received: from mail-wm1-x32a.google.com (mail-wm1-x32a.google.com [IPv6:2a00:1450:4864:20::32a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4EC58BB for ; Mon, 6 Nov 2023 03:05:53 -0800 (PST) Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-40806e4106dso25960585e9.1 for ; Mon, 06 Nov 2023 03:05:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699268752; x=1699873552; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oZ4xqFJalLvpzsW1bcHeUL/13mhLi/mzZSAy+mux2v0=; b=qgJaTLaQnrF3FRlgM4dnO8rJSYudacBS92LDmwzpG+ypHUqJwMoi3888ND13yqBoA1 sYVX+pUta4zAHUwNDcNChP+t5DPb0oRB3rxErfi3YovWPL+hscsg6HiCo6xLzEqImgrE XAeYuLBjKdLKlRu2e/WJI0XVU75dnBKfBCZw4krSdKPwV+wBk5PhAyiuM7ueCfxD956e 5hk8UEgod73sYlBc8Xysb5MrU2xaxCP7i5n44Bxt9IUBHOANR3i0vz0bZM+5QKT6oTE+ WaxDlcbxQZj9Ma6/tWXHSw5CdPn/oa3iY9SDrm6MIKpcYVWl2yJuM6toGH+ZtGLxjOTQ nTUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699268752; x=1699873552; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oZ4xqFJalLvpzsW1bcHeUL/13mhLi/mzZSAy+mux2v0=; b=fOptc41xguXY8RPNQ9hLigdj1z2ZvS7q4NoQqkQ03Z86QBJwRMBBRb3THBhEgaBavP +LUMLc2O9rYNZxSwRq2QbZWdDPAHUGbIuGzFSng7nHr0bLk44U00j4XSQ1I7WTd9Kkv6 yMnKg3D10uv4zHcEvu9bR38XTQ3WKwqDWPuL5SsV95c8XFsyFtOgVbRPrRtABHgpaXCC iLt0d9eppbbNHEiwf6ZqBueuvy3cF0JB3FXeHBkgrOAl4joUjwAdg4Sa9gfDyFBkPqEC Ue8dV5IHqBxhqqDpn9Uel00dA7vlJq+56UPa/LH+L6xO/GuQkIbk6PW5yavhClGF+ywX vA7A== X-Gm-Message-State: AOJu0YxPaEjIxU+j8cuEj8c5XahdS5Lxxlpu97Oin3FTDgdSJVqnUXel Bm7gAxlmAgzVEfuke9ICatsLkA== X-Google-Smtp-Source: AGHT+IG9mJw0F90hy4Uu6xuSpQrJC5TM2lMXtp6Q5jTJMspVFVuvMPHpaiGipu7vhxIPNtgi1AXh6Q== X-Received: by 2002:a7b:c7c9:0:b0:406:45c1:4dd with SMTP id z9-20020a7bc7c9000000b0040645c104ddmr10153754wmk.14.1699268751703; Mon, 06 Nov 2023 03:05:51 -0800 (PST) Received: from m1x-phil.lan (176-131-220-199.abo.bbox.fr. [176.131.220.199]) by smtp.gmail.com with ESMTPSA id bh5-20020a05600c3d0500b004094e565e71sm12164949wmb.23.2023.11.06.03.05.49 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:05:51 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Daniel Henrique Barboza , Richard Henderson , Alistair Francis , Nicholas Piggin , Daniel Henrique Barboza , =?utf-8?q?C=C3=A9dric_Le_G?= =?utf-8?q?oater?= Subject: [PULL 19/60] target/ppc: Use env_archcpu() in helper_book3s_msgsndp() Date: Mon, 6 Nov 2023 12:02:51 +0100 Message-ID: <20231106110336.358-20-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 When CPUArchState* is available (here CPUPPCState*), we can use the fast env_archcpu() macro to get ArchCPU* (here PowerPCCPU*). The QOM cast POWERPC_CPU() macro will be slower when building with --enable-qom-cast-debug. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Daniel Henrique Barboza Reviewed-by: Richard Henderson Acked-by: Alistair Francis Message-Id: <20231009110239.66778-2-philmd@linaro.org> --- target/ppc/excp_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 7926114d5c..a42743a3e0 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -3136,7 +3136,7 @@ void helper_book3s_msgclrp(CPUPPCState *env, target_ulong rb) void helper_book3s_msgsndp(CPUPPCState *env, target_ulong rb) { CPUState *cs = env_cpu(env); - PowerPCCPU *cpu = POWERPC_CPU(cs); + PowerPCCPU *cpu = env_archcpu(env); CPUState *ccs; uint32_t nr_threads = cs->nr_threads; int ttir = rb & PPC_BITMASK(57, 63); From patchwork Mon Nov 6 11:02:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13446636 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0BDE91EB2B for ; Mon, 6 Nov 2023 11:06:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="WBE0801e" Received: from mail-wm1-x32b.google.com (mail-wm1-x32b.google.com [IPv6:2a00:1450:4864:20::32b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 70160BB for ; Mon, 6 Nov 2023 03:06:00 -0800 (PST) Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-40850b244beso33448265e9.2 for ; Mon, 06 Nov 2023 03:06:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699268759; x=1699873559; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WdevyuV5vDNMMgKGndHL1Lb3pKI2mM3BGOnKiVXcZMA=; b=WBE0801e4XnuSIlK6JsYwl4jQIIH5PUy/D4CUwckJKbnX+5qROFaBLXMVFpCqynx9T RV9MZ/8hKv3MRHtPHzCe9kE1rBIaSR41OqZSf7dn7Za2pE5+6GTeDn3QYa/fmnw05aPJ h9Actf+0F50QmQ1It/6fi9Rn2YRjx85vgP+8aQ/+pG5GXnzFqZ4i1Tv+ixVFm5cocVqx ROZE38bDnd6hMGva2L5vpo0JaeTSPJhevV8BacMn7Yc/0RAXg0BO9KV6jLb28NYPQLFJ sYZsnc+9yP2lTSibuvyzoN9U12QCmh+zSfd4L47pRUdIotT52jn3Sc/9u30gUVGpPotP Ib7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699268759; x=1699873559; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WdevyuV5vDNMMgKGndHL1Lb3pKI2mM3BGOnKiVXcZMA=; b=pefOmXRuD4nKxotAIQR2DVpUBJCYfewDSGyJ4Kk8cDuZSCeadumI0/VfhB2BN7iM0k FEGjgE60S4wdVJufkti99IONu0XhcD7rC5EqkaHvHA52U4Xq/RAXj2UxtM+4WBOx85bT IXhwZEXwSgNFBx/tm/oZ42WWSDvHeu+fJrJeM9994l0IVpWf9Z3uPaY2C/m2JGUXIcCC QXoC5ESg08feqTNBFxzzhnl41OfgtA9GPPvRO+H9P8Mpz7f3pzajyAs/STTaMAERRDk5 cLQYMl7F2x5fykxgl+V4vZSK62++ntjZDBvCxWMN4V09KMT9L6JsxXfOUCoT3zapX+VS cHhA== X-Gm-Message-State: AOJu0YygL0kHB7Z/+p0B7ZhjrPnHoR/f0eaBqtB0IZkmRTZg6dUrmp+B BFaOYMfDuye7NUenVeURRZ1fwg== X-Google-Smtp-Source: AGHT+IHx5XXxhtGZu6ZCbciI1JQ5kvGzt8XZDokYAdmWLiQ+Wf2MWQYdjQaCgeHE7cevbJyqEkuPhw== X-Received: by 2002:a05:600c:1c9a:b0:401:d803:6243 with SMTP id k26-20020a05600c1c9a00b00401d8036243mr25577656wms.32.1699268759004; Mon, 06 Nov 2023 03:05:59 -0800 (PST) Received: from m1x-phil.lan (176-131-220-199.abo.bbox.fr. [176.131.220.199]) by smtp.gmail.com with ESMTPSA id r13-20020a05600c458d00b00406443c8b4fsm11744176wmo.19.2023.11.06.03.05.56 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:05:58 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , "Richard W . M . Jones" , Daniel Henrique Barboza , LIU Zhiwei , Richard Henderson , Alistair Francis , Palmer Dabbelt , Bin Meng , Weiwei Li Subject: [PULL 20/60] target/riscv: Use env_archcpu() in [check_]nanbox() Date: Mon, 6 Nov 2023 12:02:52 +0100 Message-ID: <20231106110336.358-21-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 When CPUArchState* is available (here CPURISCVState*), we can use the fast env_archcpu() macro to get ArchCPU* (here RISCVCPU*). The QOM cast RISCV_CPU() macro will be slower when building with --enable-qom-cast-debug. Inspired-by: Richard W.M. Jones Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Daniel Henrique Barboza Reviewed-by: LIU Zhiwei Reviewed-by: Richard W.M. Jones Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20231009110239.66778-3-philmd@linaro.org> --- target/riscv/internals.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/riscv/internals.h b/target/riscv/internals.h index b5f823c7ec..8239ae83cc 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -87,7 +87,7 @@ enum { static inline uint64_t nanbox_s(CPURISCVState *env, float32 f) { /* the value is sign-extended instead of NaN-boxing for zfinx */ - if (RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) { + if (env_archcpu(env)->cfg.ext_zfinx) { return (int32_t)f; } else { return f | MAKE_64BIT_MASK(32, 32); @@ -97,7 +97,7 @@ static inline uint64_t nanbox_s(CPURISCVState *env, float32 f) static inline float32 check_nanbox_s(CPURISCVState *env, uint64_t f) { /* Disable NaN-boxing check when enable zfinx */ - if (RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) { + if (env_archcpu(env)->cfg.ext_zfinx) { return (uint32_t)f; } @@ -113,7 +113,7 @@ static inline float32 check_nanbox_s(CPURISCVState *env, uint64_t f) static inline uint64_t nanbox_h(CPURISCVState *env, float16 f) { /* the value is sign-extended instead of NaN-boxing for zfinx */ - if (RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) { + if (env_archcpu(env)->cfg.ext_zfinx) { return (int16_t)f; } else { return f | MAKE_64BIT_MASK(16, 48); @@ -123,7 +123,7 @@ static inline uint64_t nanbox_h(CPURISCVState *env, float16 f) static inline float16 check_nanbox_h(CPURISCVState *env, uint64_t f) { /* Disable nanbox check when enable zfinx */ - if (RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) { + if (env_archcpu(env)->cfg.ext_zfinx) { return (uint16_t)f; } From patchwork Mon Nov 6 11:02:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13446637 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C83321EB2B for ; Mon, 6 Nov 2023 11:06:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="WB8BvWTV" Received: from mail-wm1-x332.google.com (mail-wm1-x332.google.com [IPv6:2a00:1450:4864:20::332]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 55BA698 for ; Mon, 6 Nov 2023 03:06:07 -0800 (PST) Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-40839652b97so32709365e9.3 for ; Mon, 06 Nov 2023 03:06:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699268766; x=1699873566; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=R87QIdTSbuBFqtOuBBqCdN1J8XfSkpLJYhBFwzXT2iA=; b=WB8BvWTVjbblMFHonJ5b+mqiY2CdZBOG48306okf57aSMtiYfazOtZxTj9ijt0twjC 3SdGEj10wS84v8Ras1JBjlsp9kT260OK2tgXsE4GlRjshT+iCVHSwzRwLyjtPPzEiRgq iExstb9hpuwQPyDB8s+4ecbtaYT8HRcuBz/SND0CyRJmj21rRMFzfWVhmoXD+Y9qCsGU V6kasAxfmhQNU+aLz13RVywpoxxNW21kMLjPiUo0Rj7AR6nC7Isx1hc8vSzk/03jT/mj H6zWZQ8EYBZRw53OFoxUhE9ESshX987u1Zgq85EHyJl+mEeT6TLvG2ZViQyN223iVsfP pHpw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699268766; x=1699873566; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=R87QIdTSbuBFqtOuBBqCdN1J8XfSkpLJYhBFwzXT2iA=; b=b1mx4YNBrJzGKokz1DBglby4iJZCAtac9nwYuyxtyxQ4F3y8zlDATumOENOL/bDa2+ kaO8u1CvrJGXA8zKr1nlrgOWCfFaQPkQs2VOGiMmllzBI0z9YX3D6Zxkum0tn18IK3jQ B+E6hz0aAnEu4bCJadUIavule25kVtZKkd/DfUy53IrR4Y1oZ6n5jQA91bEEO2O02xbD UJcoeah60NaQVKzBkRah3h2Bw7oK0saTNETFfFVkofDl4n0d8k0N5/2me/8KjIKjZ6+7 zsWNZJsuo+qWAewkIQW272kNjQ+bMVOCv5XA+c1Jdx/dAu+rRZ6XcqtWc6r8e5aXXXP1 D0MQ== X-Gm-Message-State: AOJu0YyiVD6aCEwLVAeMhvhDdVzDUmRGMFf6WNH+cEWYc598cXxvhg6S mNxcD1Vr/7IhRDZsGsXhx8SOHA== X-Google-Smtp-Source: AGHT+IEAb7mlXjiV+t8xOiAWlZzqIbRP1ddqvYwThww0DxTtH+DpaAZtlEj/6Pj1UY+lnDvwGergOA== X-Received: by 2002:a05:600c:3148:b0:405:1c19:b747 with SMTP id h8-20020a05600c314800b004051c19b747mr24127659wmo.15.1699268765817; Mon, 06 Nov 2023 03:06:05 -0800 (PST) Received: from m1x-phil.lan (176-131-220-199.abo.bbox.fr. [176.131.220.199]) by smtp.gmail.com with ESMTPSA id i20-20020a05600c355400b0040839fcb217sm11896421wmq.8.2023.11.06.03.06.03 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:06:05 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Alistair Francis , David Hildenbrand , Ilya Leoshkevich , Thomas Huth Subject: [PULL 21/60] target/s390x: Use env_archcpu() in handle_diag_308() Date: Mon, 6 Nov 2023 12:02:53 +0100 Message-ID: <20231106110336.358-22-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 When CPUArchState* is available (here CPUS390XState*), we can use the fast env_archcpu() macro to get ArchCPU* (here S390CPU*). The QOM cast S390_CPU() macro will be slower when building with --enable-qom-cast-debug. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Acked-by: Alistair Francis Message-Id: <20231009110239.66778-4-philmd@linaro.org> --- target/s390x/diag.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/s390x/diag.c b/target/s390x/diag.c index 8ce18e08f3..27ffd48576 100644 --- a/target/s390x/diag.c +++ b/target/s390x/diag.c @@ -77,7 +77,7 @@ void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3, uintptr_t ra) { bool valid; CPUState *cs = env_cpu(env); - S390CPU *cpu = S390_CPU(cs); + S390CPU *cpu = env_archcpu(env); uint64_t addr = env->regs[r1]; uint64_t subcode = env->regs[r3]; IplParameterBlock *iplb; From patchwork Mon Nov 6 11:02:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13446638 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA9441EB29 for ; Mon, 6 Nov 2023 11:06:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="Xcdo3m4i" Received: from mail-wm1-x32a.google.com (mail-wm1-x32a.google.com [IPv6:2a00:1450:4864:20::32a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2A42DFA for ; Mon, 6 Nov 2023 03:06:14 -0800 (PST) Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-40859c464daso32128565e9.1 for ; Mon, 06 Nov 2023 03:06:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699268772; x=1699873572; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Kr5DULV07OwGLXl8unpIp7yrXhMhnI+29Dc5ljVlc2w=; b=Xcdo3m4iZcfaKsOyziCQU1We8qFzTG30UDrxZD6p/tBmuPyxn4KrkAIPhItUT9AY4N ZzD7LT7fF56nIAog7MGdKMKxmIDai4m2S73LLcJck3ehwVOc1xgXdILpTrhn9lErmlZo k2TRFXxtJGoayI23wgF2LZ1g08wBoBsLmDr4Dz3kBBu1tePC5sWotiPOO6XK3ogQsw1f 8B3MGj0DIaaIqBsO5cfTiof0iojM3123THHZMaI2FMiH0c88xcgxWmdx6fLIYF2CeSlk NxhueiCP+acZ+3eN3j3j2YxS5Xqq00MRibrLYPGBgoi4NcsapA8cTrgU+r6VwO1k98R/ JO9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699268772; x=1699873572; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Kr5DULV07OwGLXl8unpIp7yrXhMhnI+29Dc5ljVlc2w=; b=t+Kx/sQt+blsDFjbuFae1io1vSdtnRctxDeGNXCM2N6IFtkJblsIFTQk6x7jFM2/R7 4iaz1jSNusgWpkf96NVckCRYnDHB3oEIXtCiYBmDM6aYYf/N+81PmkI5238uQaNoX/ze jyVjWzFiREHDE4QEBhO88hS4Yv3+WX8Co54l/shYMpc/lUakiW8pvvDKZ2euYW0L+P9Z ChTWCjqLi9HuDo1ck1i0YRyq683dob70YsSOkpQEbwu0SYnHpdrZH0FAJzedsuHAvcqo evRpJGMOCpzrbEc6UqOx5TJUIrtsgGQzXVBTzAwD4YUTt52Cn9VMY7Lv+lOqMW7pNrJC c42Q== X-Gm-Message-State: AOJu0YxuUleWEwUN8tzseeVxbWO43+3p1J2KQfUdC4/8hy52bDm4JYTQ O/ldlx1zqK7m3ZQYU60qSsgLOg== X-Google-Smtp-Source: AGHT+IH4BAo69cz3UuA35KFmjUUFhUkRdG+3mGsiR8W5V9QhANt/dkfHrFLlVjuREtmjDOTy7dt7Jw== X-Received: by 2002:a05:600c:35c9:b0:401:73b2:f039 with SMTP id r9-20020a05600c35c900b0040173b2f039mr24065294wmq.7.1699268772505; Mon, 06 Nov 2023 03:06:12 -0800 (PST) Received: from m1x-phil.lan (176-131-220-199.abo.bbox.fr. [176.131.220.199]) by smtp.gmail.com with ESMTPSA id j11-20020a5d618b000000b0032db4825495sm9214037wru.22.2023.11.06.03.06.10 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:06:12 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Alistair Francis , Max Filippov Subject: [PULL 22/60] target/xtensa: Use env_archcpu() in update_c[compare|count]() Date: Mon, 6 Nov 2023 12:02:54 +0100 Message-ID: <20231106110336.358-23-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 When CPUArchState* is available (here CPUXtensaState*), we can use the fast env_archcpu() macro to get ArchCPU* (here XtensaCPU*). The QOM cast XTENSA_CPU() macro will be slower when building with --enable-qom-cast-debug. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Acked-by: Alistair Francis Message-Id: <20231009110239.66778-5-philmd@linaro.org> --- target/xtensa/op_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/xtensa/op_helper.c b/target/xtensa/op_helper.c index 7bb8cd6726..496754ba57 100644 --- a/target/xtensa/op_helper.c +++ b/target/xtensa/op_helper.c @@ -37,7 +37,7 @@ void HELPER(update_ccount)(CPUXtensaState *env) { - XtensaCPU *cpu = XTENSA_CPU(env_cpu(env)); + XtensaCPU *cpu = env_archcpu(env); uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); env->ccount_time = now; @@ -58,7 +58,7 @@ void HELPER(wsr_ccount)(CPUXtensaState *env, uint32_t v) void HELPER(update_ccompare)(CPUXtensaState *env, uint32_t i) { - XtensaCPU *cpu = XTENSA_CPU(env_cpu(env)); + XtensaCPU *cpu = env_archcpu(env); uint64_t dcc; qatomic_and(&env->sregs[INTSET], From patchwork Mon Nov 6 11:02:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13446639 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E72DA1EB29 for ; Mon, 6 Nov 2023 11:06:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="eUm5LyCN" Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [IPv6:2a00:1450:4864:20::32e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6FE95D6F for ; Mon, 6 Nov 2023 03:06:21 -0800 (PST) Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-408002b5b9fso32364755e9.3 for ; Mon, 06 Nov 2023 03:06:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699268779; x=1699873579; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9JKKmt1EY/kf3nircSCgd4NoTIWcG19r0u1T6OQDS20=; b=eUm5LyCNRxVPPiU2LziOuhXPudnk3Oi1pkWbCTIF27q9oU6qxXl9Ai/F6pL7iMzfjW hAIp1mqlTkdHkLxG7ba2IV5mr+prZEXmdMRSeBS6D9D2vBC3EBW6v8l8YPWa6C2PI6n4 0w2zBzkzEkVb0QHsw4Xn4KMLHKVbq+zE9w8ANPmq44py8pPl0NsMuVOT5KmKxMY3Gkud uHcuJ7wAE7Gty640Yrb8Eu2i9uDy4jvIlXaBn4ywsDfRvMBddiX7fjMFbZkqLsXvEu+I c/Z/VR13ytV7KhpxhaTIg+SuqnRbeIaMzW7I2zZtDsNOwhkWYPz7iI6c9ZhQRteJY4Pw nc8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699268779; x=1699873579; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9JKKmt1EY/kf3nircSCgd4NoTIWcG19r0u1T6OQDS20=; b=MXTDJCrpuQ97SZ3vfmUQIReQm+dnSNwr0R+OB6MF/2L4jXdNWG5ewrXnp2i/Hb2EGM +9ThdaeJhD7SAVjZDBj3brQp5DYD8SH4lN64UNHb7+0U1Zvg+iNpXxe5pjHdORk5C9ob KgM4BhxL5Vzyl6HZdXh7Ek8LZu4McAgH4UW78SlpiXjYd0I3X1on1/OSk/mJSvHhAWPK XPRCKgLkibO/59OsKzPMniAlUQlVkpMQjQU3GCJPOCAL+vz8o0iGRFnw9jw6WviaqXg4 aVGK0XWV610/eLZXIQgqJ87dcbiEBEEluGa4cL5yYA+FKDjItyP77YJJq/0q4fOqbw/5 URNA== X-Gm-Message-State: AOJu0YxgEZH39Cz1+1tuiLpOd/Gy+Ha344eHorO1kC94R1NGI3Dqr5hT O4wjULQYPoD4Uv2YS2OpiURHJw== X-Google-Smtp-Source: AGHT+IEfybZ7H2Z3J3gHYnthxWPdDRlfQr2CrB6JP1W6Rr4GrrWr88wGlPvt7oAiYP8kPnl41aGPqw== X-Received: by 2002:a05:600c:1913:b0:409:351:873d with SMTP id j19-20020a05600c191300b004090351873dmr24821001wmq.31.1699268779697; Mon, 06 Nov 2023 03:06:19 -0800 (PST) Received: from m1x-phil.lan (176-131-220-199.abo.bbox.fr. [176.131.220.199]) by smtp.gmail.com with ESMTPSA id e22-20020a05600c109600b0040523bef620sm5449491wmd.0.2023.11.06.03.06.17 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:06:19 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Roman Bolshakov , Zhao Liu , Cameron Esfahani , Roman Bolshakov Subject: [PULL 23/60] target/i386/hvf: Use x86_cpu in simulate_[rdmsr|wrmsr]() Date: Mon, 6 Nov 2023 12:02:55 +0100 Message-ID: <20231106110336.358-24-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 We already have 'x86_cpu = X86_CPU(cpu)'. Use the variable instead of doing another QOM cast with X86_CPU(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Roman Bolshakov Tested-by: Roman Bolshakov Reviewed-by: Zhao Liu Message-Id: <20231009110239.66778-6-philmd@linaro.org> --- target/i386/hvf/x86_emu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c index ccda568478..af1f205ecf 100644 --- a/target/i386/hvf/x86_emu.c +++ b/target/i386/hvf/x86_emu.c @@ -676,7 +676,7 @@ void simulate_rdmsr(struct CPUState *cpu) val = rdtscp() + rvmcs(cpu->accel->fd, VMCS_TSC_OFFSET); break; case MSR_IA32_APICBASE: - val = cpu_get_apic_base(X86_CPU(cpu)->apic_state); + val = cpu_get_apic_base(x86_cpu->apic_state); break; case MSR_IA32_UCODE_REV: val = x86_cpu->ucode_rev; @@ -776,7 +776,7 @@ void simulate_wrmsr(struct CPUState *cpu) case MSR_IA32_TSC: break; case MSR_IA32_APICBASE: - cpu_set_apic_base(X86_CPU(cpu)->apic_state, data); + cpu_set_apic_base(x86_cpu->apic_state, data); break; case MSR_FSBASE: wvmcs(cpu->accel->fd, VMCS_GUEST_FS_BASE, data); From patchwork Mon Nov 6 11:02:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13446640 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E9CA91EB2B for ; Mon, 6 Nov 2023 11:06:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="Ieo7ztTi" Received: from mail-wm1-x32a.google.com (mail-wm1-x32a.google.com [IPv6:2a00:1450:4864:20::32a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 229291B2 for ; Mon, 6 Nov 2023 03:06:27 -0800 (PST) Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-40859c46447so27369395e9.1 for ; Mon, 06 Nov 2023 03:06:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699268786; x=1699873586; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3KIslD3tBGe6rvvH4379K4CtN4FVJCslZLzDLuVWSbo=; b=Ieo7ztTi3KWvsVeJAdtKoCSCd8C5DREIODWn0L0ot5lcdF0CtZIX7PSydM+UfI0TjZ cS+J22BptJlN+xOeGZg2HuOA7EgqoOBJRzRFuCmx3j1mvnbUAFEe3+nhtJwO4tRxKQ0f 5ObcY+DEXu9+j5Cwa1iFkphpdT8AuVgHm3LnkzKmz7lXMW40aT6jdv+Jz6FtYk65yQPo 1cbRP13O9C2XNz9HuxBZMgH3sXGaFUe6/i3vU14RUoS9adf0n/jPD1IkR6fhnrJCwUaO mMk31NUBmEczuwE73BjZSU4Z5cYndZHinYGrURwoKWaaqZjS82pQeuFmOjDNJgWkMQ2R EiUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699268786; x=1699873586; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3KIslD3tBGe6rvvH4379K4CtN4FVJCslZLzDLuVWSbo=; b=fcUTHaBOdXLkeNuveqX4G0cEoUC8eqUplr+UuXSb0uMMWJclUN8Z6oK60axChoXuos Ps8nie0PRZU7skmr5OYFKP8EgdOELnIk/b+JNUwjPXeA9Zc4ZG0lpmUvyt+xkStfR7Wr uwyTKrI6oySE3aaRpv53UIkNnGxnOTZhFpP9u4tUBMQwIhZYx0Of5s42zwgomtQoQEpu USKGGm1qphTOjoSGRp9cB4YN9933bsNWYFuPcX/xZT7Tb77uQyfxWigbeykQZ/8nujoA npgnL+9VTIMn0EgTwK6eYvoGykEVji/8lCStvfZ8JLepJadi9G1B+s0rbzCxiIaaTONR 3ujw== X-Gm-Message-State: AOJu0YyH1Y7GoxEjeYZPVMro1D/5eXPd8EJlj7z8bCUsTBrlXgjjjLVA 7I7tSXky8Ss/D7BfqEUPeJBhAA== X-Google-Smtp-Source: AGHT+IFqstTlySqqtM85ehr6LLy2+6l54CyDhFwQFN2W5FnsbrQ2ysa+hdHfl+FfvhmGvxPogIc2ZA== X-Received: by 2002:a05:600c:1c27:b0:405:1c14:9227 with SMTP id j39-20020a05600c1c2700b004051c149227mr21583067wms.33.1699268786451; Mon, 06 Nov 2023 03:06:26 -0800 (PST) Received: from m1x-phil.lan (176-131-220-199.abo.bbox.fr. [176.131.220.199]) by smtp.gmail.com with ESMTPSA id j19-20020a05600c1c1300b004060f0a0fd5sm11856347wms.13.2023.11.06.03.06.24 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:06:26 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Roman Bolshakov , Zhao Liu , Cameron Esfahani , Roman Bolshakov Subject: [PULL 24/60] target/i386/hvf: Use env_archcpu() in simulate_[rdmsr/wrmsr]() Date: Mon, 6 Nov 2023 12:02:56 +0100 Message-ID: <20231106110336.358-25-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 When CPUArchState* is available (here CPUX86State*), we can use the fast env_archcpu() macro to get ArchCPU* (here X86CPU*). The QOM cast X86_CPU() macro will be slower when building with --enable-qom-cast-debug. Pass CPUX86State* as argument to simulate_rdmsr / simulate_wrmsr instead of a CPUState* to avoid an extra cast. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Roman Bolshakov Tested-by: Roman Bolshakov Reviewed-by: Zhao Liu Message-Id: <20231009110239.66778-7-philmd@linaro.org> --- target/i386/hvf/x86_emu.h | 4 ++-- target/i386/hvf/hvf.c | 4 ++-- target/i386/hvf/x86_emu.c | 21 ++++++++++----------- 3 files changed, 14 insertions(+), 15 deletions(-) diff --git a/target/i386/hvf/x86_emu.h b/target/i386/hvf/x86_emu.h index 640da90b30..4b846ba80e 100644 --- a/target/i386/hvf/x86_emu.h +++ b/target/i386/hvf/x86_emu.h @@ -29,8 +29,8 @@ bool exec_instruction(CPUX86State *env, struct x86_decode *ins); void load_regs(struct CPUState *cpu); void store_regs(struct CPUState *cpu); -void simulate_rdmsr(struct CPUState *cpu); -void simulate_wrmsr(struct CPUState *cpu); +void simulate_rdmsr(CPUX86State *env); +void simulate_wrmsr(CPUX86State *env); target_ulong read_reg(CPUX86State *env, int reg, int size); void write_reg(CPUX86State *env, int reg, target_ulong val, int size); diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c index cb2cd0b02f..20b9ca3ef5 100644 --- a/target/i386/hvf/hvf.c +++ b/target/i386/hvf/hvf.c @@ -591,9 +591,9 @@ int hvf_vcpu_exec(CPUState *cpu) { load_regs(cpu); if (exit_reason == EXIT_REASON_RDMSR) { - simulate_rdmsr(cpu); + simulate_rdmsr(env); } else { - simulate_wrmsr(cpu); + simulate_wrmsr(env); } env->eip += ins_len; store_regs(cpu); diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c index af1f205ecf..b1f8a685d1 100644 --- a/target/i386/hvf/x86_emu.c +++ b/target/i386/hvf/x86_emu.c @@ -663,11 +663,10 @@ static void exec_lods(CPUX86State *env, struct x86_decode *decode) env->eip += decode->len; } -void simulate_rdmsr(struct CPUState *cpu) +void simulate_rdmsr(CPUX86State *env) { - X86CPU *x86_cpu = X86_CPU(cpu); - CPUX86State *env = &x86_cpu->env; - CPUState *cs = env_cpu(env); + X86CPU *x86_cpu = env_archcpu(env); + CPUState *cpu = env_cpu(env); uint32_t msr = ECX(env); uint64_t val = 0; @@ -746,8 +745,8 @@ void simulate_rdmsr(struct CPUState *cpu) val = env->mtrr_deftype; break; case MSR_CORE_THREAD_COUNT: - val = cs->nr_threads * cs->nr_cores; /* thread count, bits 15..0 */ - val |= ((uint32_t)cs->nr_cores << 16); /* core count, bits 31..16 */ + val = cpu->nr_threads * cpu->nr_cores; /* thread count, bits 15..0 */ + val |= ((uint32_t)cpu->nr_cores << 16); /* core count, bits 31..16 */ break; default: /* fprintf(stderr, "%s: unknown msr 0x%x\n", __func__, msr); */ @@ -761,14 +760,14 @@ void simulate_rdmsr(struct CPUState *cpu) static void exec_rdmsr(CPUX86State *env, struct x86_decode *decode) { - simulate_rdmsr(env_cpu(env)); + simulate_rdmsr(env); env->eip += decode->len; } -void simulate_wrmsr(struct CPUState *cpu) +void simulate_wrmsr(CPUX86State *env) { - X86CPU *x86_cpu = X86_CPU(cpu); - CPUX86State *env = &x86_cpu->env; + X86CPU *x86_cpu = env_archcpu(env); + CPUState *cpu = env_cpu(env); uint32_t msr = ECX(env); uint64_t data = ((uint64_t)EDX(env) << 32) | EAX(env); @@ -856,7 +855,7 @@ void simulate_wrmsr(struct CPUState *cpu) static void exec_wrmsr(CPUX86State *env, struct x86_decode *decode) { - simulate_wrmsr(env_cpu(env)); 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id iv12-20020a05600c548c00b0040641a9d49bsm11948176wmb.17.2023.11.06.03.06.31 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:06:32 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Zhao Liu , Cameron Esfahani , Roman Bolshakov Subject: [PULL 25/60] target/i386/hvf: Use CPUState typedef Date: Mon, 6 Nov 2023 12:02:57 +0100 Message-ID: <20231106110336.358-26-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Follow C style guidelines and use CPUState forward declaration from "qemu/typedefs.h". No functional changes. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Zhao Liu Message-Id: <20231020111136.44401-2-philmd@linaro.org> --- target/i386/hvf/x86_emu.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c index b1f8a685d1..cd7ef30126 100644 --- a/target/i386/hvf/x86_emu.c +++ b/target/i386/hvf/x86_emu.c @@ -45,7 +45,7 @@ #include "vmcs.h" #include "vmx.h" -void hvf_handle_io(struct CPUState *cpu, uint16_t port, void *data, +void hvf_handle_io(CPUState *cpu, uint16_t port, void *data, int direction, int size, uint32_t count); #define EXEC_2OP_FLAGS_CMD(env, decode, cmd, FLAGS_FUNC, save_res) \ @@ -1417,7 +1417,7 @@ static void init_cmd_handler() } } -void load_regs(struct CPUState *cpu) +void load_regs(CPUState *cpu) { X86CPU *x86_cpu = X86_CPU(cpu); CPUX86State *env = &x86_cpu->env; @@ -1440,7 +1440,7 @@ void load_regs(struct CPUState *cpu) env->eip = rreg(cpu->accel->fd, HV_X86_RIP); } -void store_regs(struct CPUState *cpu) +void store_regs(CPUState *cpu) { X86CPU *x86_cpu = X86_CPU(cpu); CPUX86State *env = &x86_cpu->env; From patchwork Mon Nov 6 11:02:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13446642 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4610A18636 for ; Mon, 6 Nov 2023 11:06:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="EtDRzNDf" Received: from mail-lj1-x236.google.com (mail-lj1-x236.google.com [IPv6:2a00:1450:4864:20::236]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 431A698 for ; Mon, 6 Nov 2023 03:06:41 -0800 (PST) Received: by mail-lj1-x236.google.com with SMTP id 38308e7fff4ca-2c5087d19a6so58551371fa.0 for ; Mon, 06 Nov 2023 03:06:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699268799; x=1699873599; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zvMSXcHtnsGDEEiq2Ygmmilt86JHxbxrpSYP17lWc2k=; b=EtDRzNDfVvqoH0pBylwAc790aFTUqTYALM68PtJI3zZ3g50p7m9toevhla4Zqnah0L ZB5LjhXZap0mCeDO2fJcgb6b4Z2Rf6ZMzgnSzz4FJoBrIyp3EuJIuhLINkn0sRV6/5YF tyOxHji6hjHOf4Oqrv6deUTyzwxKE81pbCfIkk/htQmh1HEbu3aoQVuB1w+MYpl0qIyf pp2SfWwqckFn8NrKOm2bjw7wDiLIZqxGFMnMLcy9L5MonJhVKzTbxE/PDOAmSyH/y44M R1YvQHcdNxb5FWFayOZZhm+79WYxlBZmHnjw15nQjwsllMaipw97X5pmIf4C1w+SYmjp dmfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699268799; x=1699873599; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zvMSXcHtnsGDEEiq2Ygmmilt86JHxbxrpSYP17lWc2k=; b=C6/k2F0WYd/jgBB6JDqPlLCuWigraXyKkV0ejoDpy7UwzT6sFIjLNlhosXDEuEHd+P TGPcCA5N8zswvCYODyxzW3XAvQilWH0LDxn45PFDkHpGI2fqtV0LxP7gmU3cyBro9zXR 6bRqqNXXU2jC/qZgYn8w/QBKbL49u1L0jRc9kvPShpmQeFiQjBqQMhBHtJF6hWVBZTDD 2XY8yUQlCv28N+mWeD6gossbvP8RvfFjey1jW5LXtLgwwfOoeOoyNKdg2i2Y1mJyhQXZ DQQqStrpImLI7Q2liHgz7qjIOp7mw0k+cGUloFFLv8dBViKco6LJLr7RWhKDG4JooZxS vKLw== X-Gm-Message-State: AOJu0YzFb+XJkaPh8RUEogAVoJ9EKlGjVF4teTl3xNeyAtmF1mmAL6AR qDCdbWuKRE5K4XBAQamP1rjQFA== X-Google-Smtp-Source: AGHT+IFk6N3D8WZ9WThiL89QlbWI0KZq0GY/jC5dBPn7GsRDiYKFS2TWfXN5PF6/U9Fqhbvy1HoMPQ== X-Received: by 2002:a05:651c:210e:b0:2b6:df71:cff1 with SMTP id a14-20020a05651c210e00b002b6df71cff1mr28309158ljq.52.1699268799607; Mon, 06 Nov 2023 03:06:39 -0800 (PST) Received: from m1x-phil.lan (176-131-220-199.abo.bbox.fr. [176.131.220.199]) by smtp.gmail.com with ESMTPSA id g20-20020a05600c4ed400b003fee8793911sm12017300wmq.44.2023.11.06.03.06.37 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:06:39 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Zhao Liu , Cameron Esfahani , Roman Bolshakov Subject: [PULL 26/60] target/i386/hvf: Rename 'CPUState *cpu' variable as 'cs' Date: Mon, 6 Nov 2023 12:02:58 +0100 Message-ID: <20231106110336.358-27-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Follow the naming used by other files in target/i386/. No functional changes. Suggested-by: Zhao Liu Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Zhao Liu Message-Id: <20231020111136.44401-3-philmd@linaro.org> --- target/i386/hvf/x86_emu.c | 92 +++++++++++++++++++-------------------- 1 file changed, 46 insertions(+), 46 deletions(-) diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c index cd7ef30126..5b82e84778 100644 --- a/target/i386/hvf/x86_emu.c +++ b/target/i386/hvf/x86_emu.c @@ -45,7 +45,7 @@ #include "vmcs.h" #include "vmx.h" -void hvf_handle_io(CPUState *cpu, uint16_t port, void *data, +void hvf_handle_io(CPUState *cs, uint16_t port, void *data, int direction, int size, uint32_t count); #define EXEC_2OP_FLAGS_CMD(env, decode, cmd, FLAGS_FUNC, save_res) \ @@ -666,13 +666,13 @@ static void exec_lods(CPUX86State *env, struct x86_decode *decode) void simulate_rdmsr(CPUX86State *env) { X86CPU *x86_cpu = env_archcpu(env); - CPUState *cpu = env_cpu(env); + CPUState *cs = env_cpu(env); uint32_t msr = ECX(env); uint64_t val = 0; switch (msr) { case MSR_IA32_TSC: - val = rdtscp() + rvmcs(cpu->accel->fd, VMCS_TSC_OFFSET); + val = rdtscp() + rvmcs(cs->accel->fd, VMCS_TSC_OFFSET); break; case MSR_IA32_APICBASE: val = cpu_get_apic_base(x86_cpu->apic_state); @@ -681,16 +681,16 @@ void simulate_rdmsr(CPUX86State *env) val = x86_cpu->ucode_rev; break; case MSR_EFER: - val = rvmcs(cpu->accel->fd, VMCS_GUEST_IA32_EFER); + val = rvmcs(cs->accel->fd, VMCS_GUEST_IA32_EFER); break; case MSR_FSBASE: - val = rvmcs(cpu->accel->fd, VMCS_GUEST_FS_BASE); + val = rvmcs(cs->accel->fd, VMCS_GUEST_FS_BASE); break; case MSR_GSBASE: - val = rvmcs(cpu->accel->fd, VMCS_GUEST_GS_BASE); + val = rvmcs(cs->accel->fd, VMCS_GUEST_GS_BASE); break; case MSR_KERNELGSBASE: - val = rvmcs(cpu->accel->fd, VMCS_HOST_FS_BASE); + val = rvmcs(cs->accel->fd, VMCS_HOST_FS_BASE); break; case MSR_STAR: abort(); @@ -745,8 +745,8 @@ void simulate_rdmsr(CPUX86State *env) val = env->mtrr_deftype; break; case MSR_CORE_THREAD_COUNT: - val = cpu->nr_threads * cpu->nr_cores; /* thread count, bits 15..0 */ - val |= ((uint32_t)cpu->nr_cores << 16); /* core count, bits 31..16 */ + val = cs->nr_threads * cs->nr_cores; /* thread count, bits 15..0 */ + val |= ((uint32_t)cs->nr_cores << 16); /* core count, bits 31..16 */ break; default: /* fprintf(stderr, "%s: unknown msr 0x%x\n", __func__, msr); */ @@ -767,7 +767,7 @@ static void exec_rdmsr(CPUX86State *env, struct x86_decode *decode) void simulate_wrmsr(CPUX86State *env) { X86CPU *x86_cpu = env_archcpu(env); - CPUState *cpu = env_cpu(env); + CPUState *cs = env_cpu(env); uint32_t msr = ECX(env); uint64_t data = ((uint64_t)EDX(env) << 32) | EAX(env); @@ -778,13 +778,13 @@ void simulate_wrmsr(CPUX86State *env) cpu_set_apic_base(x86_cpu->apic_state, data); break; case MSR_FSBASE: - wvmcs(cpu->accel->fd, VMCS_GUEST_FS_BASE, data); + wvmcs(cs->accel->fd, VMCS_GUEST_FS_BASE, data); break; case MSR_GSBASE: - wvmcs(cpu->accel->fd, VMCS_GUEST_GS_BASE, data); + wvmcs(cs->accel->fd, VMCS_GUEST_GS_BASE, data); break; case MSR_KERNELGSBASE: - wvmcs(cpu->accel->fd, VMCS_HOST_FS_BASE, data); + wvmcs(cs->accel->fd, VMCS_HOST_FS_BASE, data); break; case MSR_STAR: abort(); @@ -796,10 +796,10 @@ void simulate_wrmsr(CPUX86State *env) abort(); break; case MSR_EFER: - /*printf("new efer %llx\n", EFER(cpu));*/ - wvmcs(cpu->accel->fd, VMCS_GUEST_IA32_EFER, data); + /*printf("new efer %llx\n", EFER(cs));*/ + wvmcs(cs->accel->fd, VMCS_GUEST_IA32_EFER, data); if (data & MSR_EFER_NXE) { - hv_vcpu_invalidate_tlb(cpu->accel->fd); + hv_vcpu_invalidate_tlb(cs->accel->fd); } break; case MSR_MTRRphysBase(0): @@ -848,9 +848,9 @@ void simulate_wrmsr(CPUX86State *env) /* Related to support known hypervisor interface */ /* if (g_hypervisor_iface) - g_hypervisor_iface->wrmsr_handler(cpu, msr, data); + g_hypervisor_iface->wrmsr_handler(cs, msr, data); - printf("write msr %llx\n", RCX(cpu));*/ + printf("write msr %llx\n", RCX(cs));*/ } static void exec_wrmsr(CPUX86State *env, struct x86_decode *decode) @@ -1417,56 +1417,56 @@ static void init_cmd_handler() } } -void load_regs(CPUState *cpu) +void load_regs(CPUState *cs) { - X86CPU *x86_cpu = X86_CPU(cpu); + X86CPU *x86_cpu = X86_CPU(cs); CPUX86State *env = &x86_cpu->env; int i = 0; - RRX(env, R_EAX) = rreg(cpu->accel->fd, HV_X86_RAX); - RRX(env, R_EBX) = rreg(cpu->accel->fd, HV_X86_RBX); - RRX(env, R_ECX) = rreg(cpu->accel->fd, HV_X86_RCX); - RRX(env, R_EDX) = rreg(cpu->accel->fd, HV_X86_RDX); - RRX(env, R_ESI) = rreg(cpu->accel->fd, HV_X86_RSI); - RRX(env, R_EDI) = rreg(cpu->accel->fd, HV_X86_RDI); - RRX(env, R_ESP) = rreg(cpu->accel->fd, HV_X86_RSP); - RRX(env, R_EBP) = rreg(cpu->accel->fd, HV_X86_RBP); + RRX(env, R_EAX) = rreg(cs->accel->fd, HV_X86_RAX); + RRX(env, R_EBX) = rreg(cs->accel->fd, HV_X86_RBX); + RRX(env, R_ECX) = rreg(cs->accel->fd, HV_X86_RCX); + RRX(env, R_EDX) = rreg(cs->accel->fd, HV_X86_RDX); + RRX(env, R_ESI) = rreg(cs->accel->fd, HV_X86_RSI); + RRX(env, R_EDI) = rreg(cs->accel->fd, HV_X86_RDI); + RRX(env, R_ESP) = rreg(cs->accel->fd, HV_X86_RSP); + RRX(env, R_EBP) = rreg(cs->accel->fd, HV_X86_RBP); for (i = 8; i < 16; i++) { - RRX(env, i) = rreg(cpu->accel->fd, HV_X86_RAX + i); + RRX(env, i) = rreg(cs->accel->fd, HV_X86_RAX + i); } - env->eflags = rreg(cpu->accel->fd, HV_X86_RFLAGS); + env->eflags = rreg(cs->accel->fd, HV_X86_RFLAGS); rflags_to_lflags(env); - env->eip = rreg(cpu->accel->fd, HV_X86_RIP); + env->eip = rreg(cs->accel->fd, HV_X86_RIP); } -void store_regs(CPUState *cpu) +void store_regs(CPUState *cs) { - X86CPU *x86_cpu = X86_CPU(cpu); + X86CPU *x86_cpu = X86_CPU(cs); CPUX86State *env = &x86_cpu->env; int i = 0; - wreg(cpu->accel->fd, HV_X86_RAX, RAX(env)); - wreg(cpu->accel->fd, HV_X86_RBX, RBX(env)); - wreg(cpu->accel->fd, HV_X86_RCX, RCX(env)); - wreg(cpu->accel->fd, HV_X86_RDX, RDX(env)); - wreg(cpu->accel->fd, HV_X86_RSI, RSI(env)); - wreg(cpu->accel->fd, HV_X86_RDI, RDI(env)); - wreg(cpu->accel->fd, HV_X86_RBP, RBP(env)); - wreg(cpu->accel->fd, HV_X86_RSP, RSP(env)); + wreg(cs->accel->fd, HV_X86_RAX, RAX(env)); + wreg(cs->accel->fd, HV_X86_RBX, RBX(env)); + wreg(cs->accel->fd, HV_X86_RCX, RCX(env)); + wreg(cs->accel->fd, HV_X86_RDX, RDX(env)); + wreg(cs->accel->fd, HV_X86_RSI, RSI(env)); + wreg(cs->accel->fd, HV_X86_RDI, RDI(env)); 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id n3-20020a05600c4f8300b004064288597bsm11904145wmq.30.2023.11.06.03.06.44 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:06:45 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Zhao Liu , Cameron Esfahani , Roman Bolshakov Subject: [PULL 27/60] target/i386/hvf: Rename 'X86CPU *x86_cpu' variable as 'cpu' Date: Mon, 6 Nov 2023 12:02:59 +0100 Message-ID: <20231106110336.358-28-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Follow the naming used by other files in target/i386/. No functional changes. Suggested-by: Zhao Liu Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Zhao Liu Message-Id: <20231020111136.44401-4-philmd@linaro.org> --- target/i386/hvf/x86_emu.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c index 5b82e84778..3a3f0a50d0 100644 --- a/target/i386/hvf/x86_emu.c +++ b/target/i386/hvf/x86_emu.c @@ -665,7 +665,7 @@ static void exec_lods(CPUX86State *env, struct x86_decode *decode) void simulate_rdmsr(CPUX86State *env) { - X86CPU *x86_cpu = env_archcpu(env); + X86CPU *cpu = env_archcpu(env); CPUState *cs = env_cpu(env); uint32_t msr = ECX(env); uint64_t val = 0; @@ -675,10 +675,10 @@ void simulate_rdmsr(CPUX86State *env) val = rdtscp() + rvmcs(cs->accel->fd, VMCS_TSC_OFFSET); break; case MSR_IA32_APICBASE: - val = cpu_get_apic_base(x86_cpu->apic_state); + val = cpu_get_apic_base(cpu->apic_state); break; case MSR_IA32_UCODE_REV: - val = x86_cpu->ucode_rev; + val = cpu->ucode_rev; break; case MSR_EFER: val = rvmcs(cs->accel->fd, VMCS_GUEST_IA32_EFER); @@ -766,7 +766,7 @@ static void exec_rdmsr(CPUX86State *env, struct x86_decode *decode) void simulate_wrmsr(CPUX86State *env) { - X86CPU *x86_cpu = env_archcpu(env); + X86CPU *cpu = env_archcpu(env); CPUState *cs = env_cpu(env); uint32_t msr = ECX(env); uint64_t data = ((uint64_t)EDX(env) << 32) | EAX(env); @@ -775,7 +775,7 @@ void simulate_wrmsr(CPUX86State *env) case MSR_IA32_TSC: break; case MSR_IA32_APICBASE: - cpu_set_apic_base(x86_cpu->apic_state, data); + cpu_set_apic_base(cpu->apic_state, data); break; case MSR_FSBASE: wvmcs(cs->accel->fd, VMCS_GUEST_FS_BASE, data); @@ -1419,8 +1419,8 @@ static void init_cmd_handler() void load_regs(CPUState *cs) { - X86CPU *x86_cpu = X86_CPU(cs); - CPUX86State *env = &x86_cpu->env; + X86CPU *cpu = X86_CPU(cs); + CPUX86State *env = &cpu->env; int i = 0; RRX(env, R_EAX) = rreg(cs->accel->fd, HV_X86_RAX); @@ -1442,8 +1442,8 @@ void load_regs(CPUState *cs) void store_regs(CPUState *cs) { - X86CPU *x86_cpu = X86_CPU(cs); - CPUX86State *env = &x86_cpu->env; + X86CPU *cpu = X86_CPU(cs); + CPUX86State *env = &cpu->env; int i = 0; wreg(cs->accel->fd, HV_X86_RAX, RAX(env)); From patchwork Mon Nov 6 11:03:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13446644 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C25311A737 for ; Mon, 6 Nov 2023 11:06:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="bTpmU5ZL" Received: from mail-lj1-x236.google.com (mail-lj1-x236.google.com [IPv6:2a00:1450:4864:20::236]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 329D1D8 for ; Mon, 6 Nov 2023 03:06:54 -0800 (PST) Received: by mail-lj1-x236.google.com with SMTP id 38308e7fff4ca-2c50305c5c4so62262801fa.1 for ; Mon, 06 Nov 2023 03:06:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699268812; x=1699873612; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+6pej+XFgeNy8hwy7UMk7tmyBIA+j/BAJUFV7Aiq4os=; b=bTpmU5ZLc5ri5Q00b6T1J30V3JDJV2sLvqLDS120vyRgZ5/4lzOlm/tiFzU8Wxv7u6 +dVzAQ6kZ/wBEhSV8FWG/BUV0T9goeLvYkWqpon68Mrxy8k012UeZY/3pS4n2qbe7Fzd Y7h4h0Chm4Vg64Aw/V7ETaBUKwZfW4aWMFVOW/YcSZEqdrbghgzDUHbXdwoLB862iTUT KnndFYXJMma6JpVZGcZXM1p/x05CB/oxiciJCyEtXo0F3wa0jyEKeW2c9u7F3isVysBL eVoh4pzzmcAJdgVcjNgrY8RgzCpB84py51Ox7XsBnOndBzX6toNy12FvUfxcWIF0JLgb Zdqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699268812; x=1699873612; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+6pej+XFgeNy8hwy7UMk7tmyBIA+j/BAJUFV7Aiq4os=; b=HudCeijGqy2vvL8JK4yCiKXKU5NKa7Td4eGF/zKqWs5lP2KAZ6fzinYDFbpFILWhF9 6zUIPFvf5Gt/VW2oNkpdDYvgR4QE8cHXR6Y/cRfHDhxZ7AsO9mw1uwe92uTnA313E+5O 3p+LDcvL7lArC7lzaDUWOz0sQH9z+BesUm8HU/V78tNwvqbgRkNndbLujp7EACvb7E2t m7uUwK9mBDSp0EWMe9PZ50LnNyXMTpi4uFh/smW59hMN1X3oQuwiFtmNalOd7I3MnEKW v7HNoo5UxcTZ0+ArXlm+DIn3XdYYVSQCLCRfqA2KyornY1DgvxlsaIkNWRHWYSk4xfW2 /0yQ== X-Gm-Message-State: AOJu0YxWJCw7Ie6+n6OSfv2y//OlwfrSFmDi+mZU9NwxhgbBmhEltjOM 0MmGauFapLVH4WL9qka+aFPEKw== X-Google-Smtp-Source: AGHT+IH9cDYwLDc1MRsfDAEGSPwPoLCFIf+s8baeSOuvBOTKWXUgUmhGOWDpYJxS4pQKbqZtqaKfYw== X-Received: by 2002:a05:651c:200c:b0:2c5:2d7:412 with SMTP id s12-20020a05651c200c00b002c502d70412mr18916048ljo.19.1699268812592; Mon, 06 Nov 2023 03:06:52 -0800 (PST) Received: from m1x-phil.lan (176-131-220-199.abo.bbox.fr. [176.131.220.199]) by smtp.gmail.com with ESMTPSA id r16-20020a05600c459000b003fefaf299b6sm11914693wmo.38.2023.11.06.03.06.50 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:06:52 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Paolo Bonzini , Marcelo Tosatti Subject: [PULL 28/60] target/i386/kvm: Correct comment in kvm_cpu_realize() Date: Mon, 6 Nov 2023 12:03:00 +0100 Message-ID: <20231106110336.358-29-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20230918160257.30127-4-philmd@linaro.org> --- target/i386/kvm/kvm-cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/i386/kvm/kvm-cpu.c b/target/i386/kvm/kvm-cpu.c index 56c72f3c45..9c791b7b05 100644 --- a/target/i386/kvm/kvm-cpu.c +++ b/target/i386/kvm/kvm-cpu.c @@ -37,6 +37,7 @@ static bool kvm_cpu_realizefn(CPUState *cs, Error **errp) * -> cpu_exec_realizefn(): * -> accel_cpu_common_realize() * kvm_cpu_realizefn() -> host_cpu_realizefn() + * -> cpu_common_realizefn() * -> check/update ucode_rev, phys_bits, mwait */ if (cpu->max_features) { From patchwork Mon Nov 6 11:03:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13446645 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7233918053 for ; Mon, 6 Nov 2023 11:07:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="CSK+K7sw" Received: from mail-wr1-x436.google.com (mail-wr1-x436.google.com [IPv6:2a00:1450:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B6F8DCC for ; Mon, 6 Nov 2023 03:07:00 -0800 (PST) Received: by mail-wr1-x436.google.com with SMTP id ffacd0b85a97d-32da4ffd7e5so2578569f8f.0 for ; Mon, 06 Nov 2023 03:07:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699268819; x=1699873619; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=W+HrE2ba95t1ooYtGszc36ebWNEUF8WT6p6gpPtPmuY=; b=CSK+K7swZEwWSSxB+KJXD62WjY42VcBtBnV+/LTH2znGOyIsQQxXHW/bNVsNSSaIrM SMxSsCsfSOeEYlVlewbq9ivI+j3Dy6GMtcsKaUc5S7JApfDeTaSj2OT2zLxRRzGRBjHN 14Sd7TJqOCqgOTIuO6O9QyOyGM9SEKVbg3/KQ/qH3mw9yfEmQgAE4ha3maf6Tfl0Ym6g NEDtQmk9lsjMNPvsebHYprHvzWSnWPsYAfvyDXwQhMtUk2vP2sIdVBA04yB9X/jF9n2e mfqM+Ro1VSXHK4ksQY+/DYPS6hkJ4mF2plk0Zy9mrjj+8Bpuzd7Y+cfeB9YG7VDi/GnG G2og== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699268819; x=1699873619; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=W+HrE2ba95t1ooYtGszc36ebWNEUF8WT6p6gpPtPmuY=; b=aJplUpFfhMiL6OJmwhh302F5mS3AUyVupPmObOE6/Ek41zNbMP6eDpHJnPjKu57YhC wavSaMvuYxWiNGy2DD6oOFXB4OSaFgZWuGBp5c+zLDlbxxER/oDbfTeu0iYFk4FQ8dA7 51fu+Qgdw3l5JOQnq+rplfi+Ge6vk6BHfpmktm/Gc0xYdUY+JxIWQB2iZiAOGQgoWK6s Vp5X1zsDLz3mjcMPk81OSGzdyzPMe+Szk9KdhiJ2rQOO9b6NjalkOUJl9ZVnH8WAjSxr v6yAAxmhppSxiIznBP9CPoqblUvaaCrzk+60nkuQsXSc4ANjGBjRRL0BeQUux6pEcusp 53EA== X-Gm-Message-State: AOJu0YxE0Rq+R5Y+1wR5sWTk8KywONZG4BbycFTmeBsuV196XUyAh0dQ qfEGaCPBX9YN6XqcNlutLWl1GA== X-Google-Smtp-Source: AGHT+IEt4PrEy7npLJh89eCdwNzRVAyjkPfVkzj/Lltpi44y5ZAeM5YDAM8Cq8QFxZb/uU2kaiqCHg== X-Received: by 2002:a05:6000:12ca:b0:32f:76a0:a99b with SMTP id l10-20020a05600012ca00b0032f76a0a99bmr8610843wrx.19.1699268819099; Mon, 06 Nov 2023 03:06:59 -0800 (PST) Received: from m1x-phil.lan (176-131-220-199.abo.bbox.fr. [176.131.220.199]) by smtp.gmail.com with ESMTPSA id f4-20020a5d6644000000b0032da49e18fasm9178802wrw.23.2023.11.06.03.06.57 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:06:58 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Dongli Zhang , Joe Jin , =?utf-8?q?Daniel_P_=2E_Berrang=C3=A9?= , David Woodhouse , Juan Quintela , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 29/60] target/i386/monitor: synchronize cpu state for lapic info Date: Mon, 6 Nov 2023 12:03:01 +0100 Message-ID: <20231106110336.358-30-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Dongli Zhang While the default "info lapic" always synchronizes cpu state ... mon_get_cpu() -> mon_get_cpu_sync(mon, true) -> cpu_synchronize_state(cpu) -> ioctl KVM_GET_LAPIC (taking KVM as example) ... the cpu state is not synchronized when the apic-id is available as argument. The cpu state should be synchronized when apic-id is available. Otherwise the "info lapic " always returns stale data. Reference: https://lore.kernel.org/all/20211028155457.967291-19-berrange@redhat.com/ Cc: Joe Jin Signed-off-by: Dongli Zhang Reviewed-by: Daniel P. Berrangé Reviewed-by: David Woodhouse Message-ID: <20231030085336.2681386-1-armbru@redhat.com> Reviewed-by: Juan Quintela Message-ID: <20231026211938.162815-1-dongli.zhang@oracle.com> Signed-off-by: Philippe Mathieu-Daudé --- target/i386/monitor.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/i386/monitor.c b/target/i386/monitor.c index 6512846327..950ff9ccbc 100644 --- a/target/i386/monitor.c +++ b/target/i386/monitor.c @@ -28,6 +28,7 @@ #include "monitor/hmp-target.h" #include "monitor/hmp.h" #include "qapi/qmp/qdict.h" +#include "sysemu/hw_accel.h" #include "sysemu/kvm.h" #include "qapi/error.h" #include "qapi/qapi-commands-misc-target.h" @@ -654,7 +655,11 @@ void hmp_info_local_apic(Monitor *mon, const QDict *qdict) if (qdict_haskey(qdict, "apic-id")) { int id = qdict_get_try_int(qdict, "apic-id", 0); + cs = cpu_by_arch_id(id); + if (cs) { + cpu_synchronize_state(cs); + } } else { cs = mon_get_cpu(mon); } From patchwork Mon Nov 6 11:03:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13446646 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2BFC618644 for ; Mon, 6 Nov 2023 11:07:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="I+MH3LWD" Received: from mail-wm1-x335.google.com (mail-wm1-x335.google.com [IPv6:2a00:1450:4864:20::335]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C8FDA10F4 for ; Mon, 6 Nov 2023 03:07:07 -0800 (PST) Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-407da05f05aso30526955e9.3 for ; Mon, 06 Nov 2023 03:07:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699268826; x=1699873626; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GyckcOuF1Bcu5rrRcor+Uzyh2YOL0vEJEmdAm/ud3/A=; b=I+MH3LWDOPgqzZEkf89C2h6REEKSKe5oqO0k5PDkpmt8G3Nji9yOYoYFWzowNsc1+4 VX0fpbuBxn8yHx24fKVHIGm5TG9BTAU2AYUOEr3ewoR6oOjWJTuSWfAvDcooC8BKeNXJ EAHjLZ4+3ObxPaG/TmR618ZYapQU1CzrVFxlJqhtQgADiLxpItD0AAkPKaYUwHuGH0tS uXf2/wmb06xMMYpXLrKwcz9c1Zz1/BMVAr5/MWReJgUXmVHMSAMTtR7P9aIEmU7Lh/ec gTuAt2jfVq7sKGgKNhahPnIs3t5Er3419Ud/pEkwjS3nVpX83ndkMHMIEbIpUINQP3WR ZxlA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699268826; x=1699873626; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GyckcOuF1Bcu5rrRcor+Uzyh2YOL0vEJEmdAm/ud3/A=; b=cr/LmINDxC41Gq01Qy6e4vFPnM0JMBGSHs0UBZA+QiIR7R/ELEoZHIlxFM9A7AiXiS A8C9XYNXP4qNcFacYGrK7v2CgHNP4f4S7i10gIHQYsT9H4DymzJPZQs0YC3VKjAlM59d JVw7AR0xHcwxz8Xtd8vaYs6qH4IJnneoHsNNXjB0WUfVqe2GZpvi+e/Rt2x1onVOLtHd U0Ou5g61YM4UaZCY+nMhjkqKgberXxNiof0ZTeIopzfzy0JlW2dezapdAgYjt++WTDeH HHR8Dig5eB3J3PT/F+nUPMFPZUVEyVlSZpwZ1jxpWTk0jbvIzE7tbNzyNbrHuncHk+tF FmTA== X-Gm-Message-State: AOJu0YzEeemS7EyQZvvShYc15+5DaEbcJgbj65ufPe8AZM90y2Iau0Em QE93QraOiHqlM/7r0K7ryXdBfg== X-Google-Smtp-Source: AGHT+IFFKKaoUyusuMn43SnLhory9traUNVPbmAEOKUR6lhSW54LBkg8wsQBYrYSz3Gl8EhHfaGVqQ== X-Received: by 2002:a05:600c:4f02:b0:405:3885:490a with SMTP id l2-20020a05600c4f0200b004053885490amr23785982wmq.0.1699268825836; Mon, 06 Nov 2023 03:07:05 -0800 (PST) Received: from m1x-phil.lan (176-131-220-199.abo.bbox.fr. [176.131.220.199]) by smtp.gmail.com with ESMTPSA id k18-20020a5d6d52000000b0032da4f70756sm9120501wri.5.2023.11.06.03.07.03 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:07:05 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , qemu-stable@nongnu.org, Sergey Evlashev , Richard Henderson , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo Subject: [PULL 30/60] target/mips: Fix MSA BZ/BNZ opcodes displacement Date: Mon, 6 Nov 2023 12:03:02 +0100 Message-ID: <20231106110336.358-31-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The PC offset is *signed*. Cc: qemu-stable@nongnu.org Reported-by: Sergey Evlashev Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1624 Fixes: c7a9ef7517 ("target/mips: Introduce decode tree bindings for MSA ASE") Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20230914085807.12241-1-philmd@linaro.org> --- target/mips/tcg/msa.decode | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index 9575289195..4410e2a02e 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -31,8 +31,8 @@ @lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &r @ldst ...... sa:s10 ws:5 wd:5 .... df:2 &msa_i -@bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3 -@bz ...... ... df:2 wt:5 sa:16 &msa_bz +@bz_v ...... ... .. wt:5 sa:s16 &msa_bz df=3 +@bz ...... ... df:2 wt:5 sa:s16 &msa_bz @elm_df ...... .... ...... ws:5 wd:5 ...... &msa_elm_df df=%elm_df n=%elm_n @elm ...... .......... ws:5 wd:5 ...... &msa_elm @vec ...... ..... wt:5 ws:5 wd:5 ...... &msa_r df=0 From patchwork Mon Nov 6 11:03:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13446647 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6ED0618E05 for ; Mon, 6 Nov 2023 11:07:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="YYVh/pkZ" Received: from mail-wm1-x334.google.com (mail-wm1-x334.google.com [IPv6:2a00:1450:4864:20::334]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 12F38D4D for ; Mon, 6 Nov 2023 03:07:14 -0800 (PST) Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-40838915cecso32072305e9.2 for ; Mon, 06 Nov 2023 03:07:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699268832; x=1699873632; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ysTm3sVa8NXK5p6adWouAn7jMZtjrRCTYZ5tPCHuc7A=; b=YYVh/pkZQNYXP7k/N5UbLPmszCb88jopRJAdsACawZD6NxYrHkBo3Z/4YsKgaspEmc CTWP/MreBVH3AljkVvnM8iFhkt6KNkk+e3P1pRmQjUCCxRW8m+Cg6t6uslA21zg1hSYP lhfVtJhiCrT0qL1Api3mYUqjyFWaphaoFGcrbqTlkMPrW3NqG/EMKKylQVUJ36HKhm38 mWBdP09SckwQoBk0irSLH2Z4HovaWLRwsy/7aE0AyrHL7TSCOGQfwzSf1v72FfpSdas3 S6vq4oJB2tIZuOXczGRz0Iue46TheAvk3z4ZrfHmGBMuBgKUe5Pu/+I740FFNhT7LYBE trxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699268832; x=1699873632; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ysTm3sVa8NXK5p6adWouAn7jMZtjrRCTYZ5tPCHuc7A=; b=cNVXEtcSLp8Wse+FtH8726OsmpmCwosmGN7htUaNdUF8OgF3s+Hero4U+9fEwzhDJ5 EXwYbaCmxeiZ56APjhdzbJqhII1pgGCHx+m5v2jRineoMvBZRUwzMi6BPwvjbbFPsCmD jPaslRYcO3HtG1Lb11Is4UVh5rE9No39Hwph8DAGCPBnPB2E40EBV2KN3QgfuZWzsvPD Qj/1yWgPQtjfIiVOR7taAhA+cULgjhSI1m8SgbfPSQzuD4X7bskOMfvwrtiQwwwwRy9p XRFzoeBkXO5rKtiDdchs7eOYmMNCPBlUDU6jpLPmnxy0TuvWMXHlCcJPxu+GmG+gAds8 Jhbw== X-Gm-Message-State: AOJu0Yza7a8/ek4jUCFYPtq2CGhThVCx3hBeotr0y+NXbWPhaUXzZbHa jtS3DPLCLddPEB0aHLPupyTheg5MH3hYxOsjtIw= X-Google-Smtp-Source: AGHT+IGkZmXraGC+Dqk5EDM2vOTL7rIZmIj2iksC9goOWR5dfHU27l8hEGkXXJizaXpag9YQzn2U8A== X-Received: by 2002:a05:600c:4f55:b0:408:3707:b199 with SMTP id m21-20020a05600c4f5500b004083707b199mr21831254wmq.3.1699268832460; Mon, 06 Nov 2023 03:07:12 -0800 (PST) Received: from m1x-phil.lan (176-131-220-199.abo.bbox.fr. [176.131.220.199]) by smtp.gmail.com with ESMTPSA id jg2-20020a05600ca00200b004065daba6casm11958500wmb.46.2023.11.06.03.07.10 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:07:12 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , qemu-stable@nongnu.org, Richard Henderson , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo Subject: [PULL 31/60] target/mips: Fix TX79 LQ/SQ opcodes Date: Mon, 6 Nov 2023 12:03:03 +0100 Message-ID: <20231106110336.358-32-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The base register address offset is *signed*. Cc: qemu-stable@nongnu.org Fixes: aaaa82a9f9 ("target/mips/tx79: Introduce LQ opcode (Load Quadword)") Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20230914090447.12557-1-philmd@linaro.org> --- target/mips/tcg/tx79.decode | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/mips/tcg/tx79.decode b/target/mips/tcg/tx79.decode index 57d87a2076..578b8c54c0 100644 --- a/target/mips/tcg/tx79.decode +++ b/target/mips/tcg/tx79.decode @@ -24,7 +24,7 @@ @rs ...... rs:5 ..... .......... ...... &r sa=0 rt=0 rd=0 @rd ...... .......... rd:5 ..... ...... &r sa=0 rs=0 rt=0 -@ldst ...... base:5 rt:5 offset:16 &i +@ldst ...... base:5 rt:5 offset:s16 &i ########################################################################### From patchwork Mon Nov 6 11:03:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13446657 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5A2481A598 for ; Mon, 6 Nov 2023 11:07:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="HxkprFIC" Received: from mail-lj1-x231.google.com (mail-lj1-x231.google.com [IPv6:2a00:1450:4864:20::231]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C6253D73 for ; Mon, 6 Nov 2023 03:07:20 -0800 (PST) Received: by mail-lj1-x231.google.com with SMTP id 38308e7fff4ca-2c6b48cb2b6so61122941fa.2 for ; Mon, 06 Nov 2023 03:07:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699268839; x=1699873639; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=S8/5vIGDLKMGAXYMu1UZsIS0RjKQzcO4h+Duvu/oNU4=; b=HxkprFIC4OGDu5zmDRCgl4rUg3HUPT6iT7yscdI7ZLfbbZiJp5wA2m8x2b6m4siGZA GTF770ccxx0Prpc0G2oz8+4ITg0QKzhfR6ofBOBHQ/Pgzd1loHAaWob44K/SRmKiQw// oQMXVIyz6a++UmRuwVX2rxWHYgMIOP79z6Rah01ZSUqZF9djXappWbc0w6W2oZJgeVXY QSfzMUzbwuYLPWHSK9/Iq254yruTmYL5VTh7veHKSRDtnmAwx60lJ0tlOQkAzfOl63Zh pL7K02ME+jx7GJDGBP6CG1wCvIL/ISJnW/ZUEZP51741g3p006zgZbbusu9Qr7KZ98G4 Kdrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699268839; x=1699873639; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=S8/5vIGDLKMGAXYMu1UZsIS0RjKQzcO4h+Duvu/oNU4=; b=UYMwQXyOTZrWkHDTHRX5mDoQqet+d9sF7vn/SClni2ISmizFo59josBcqOVm281LoC LmVLTdShyaUFsarK2CAEv5MV+TuPLBfvKUWw00c+KUKyAL7zUKe3gryjG2ZRn5ZJDJQe OHQwZC3Eih843ot2Cr7SBVr7bILl33B9s7iZfz++w+HC+KyFB2b7Qx1jyvw6D+NgUjLv TQVusZpIEnpG9nLeeJZJCVJw5NH2ISqx1gjID1ubmXIAx/IxWa9c019Lj1qj9zS/xayK i0VboZEipBqjEzy14EKU4G438L8uH1CGGL3hu7E4y27+9UNt5XKf6IsGZ7D0RFIo5dYD Lu1g== X-Gm-Message-State: AOJu0Ywn7ylQlFTQgQvS04hijQlZScZiOcs3iJAiat7i3KxgKU//KEGG ysRDXrxKb6c3if18wkDXkYqKvQ== X-Google-Smtp-Source: AGHT+IGUmAjl7n06mFubnd+gEr0baz8hJiaRcQUniE2ytONQaxbr97H+8iARFxziBtFUQ6m1v/mnVw== X-Received: by 2002:a2e:940e:0:b0:2c6:e46e:9849 with SMTP id i14-20020a2e940e000000b002c6e46e9849mr10927288ljh.15.1699268838970; Mon, 06 Nov 2023 03:07:18 -0800 (PST) Received: from m1x-phil.lan (176-131-220-199.abo.bbox.fr. [176.131.220.199]) by smtp.gmail.com with ESMTPSA id v9-20020a05600c470900b003feea62440bsm11701095wmo.43.2023.11.06.03.07.17 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:07:18 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Michael Tokarev , Daniel Henrique Barboza , Paolo Bonzini , Nicholas Piggin , =?utf-8?q?C=C3=A9dric_Le_Goater?= Subject: [PULL 32/60] sysemu/kvm: Restrict kvmppc_get_radix_page_info() to ppc targets Date: Mon, 6 Nov 2023 12:03:04 +0100 Message-ID: <20231106110336.358-33-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 kvm_get_radix_page_info() is only defined for ppc targets (in target/ppc/kvm.c). The declaration is not useful in other targets, reduce its scope. Rename using the 'kvmppc_' prefix following other declarations from target/ppc/kvm_ppc.h. Suggested-by: Michael Tokarev Reviewed-by: Daniel Henrique Barboza Message-Id: <20231003070427.69621-2-philmd@linaro.org> Signed-off-by: Philippe Mathieu-Daudé --- include/sysemu/kvm.h | 1 - target/ppc/kvm.c | 4 ++-- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h index 80b69d88f6..d614878164 100644 --- a/include/sysemu/kvm.h +++ b/include/sysemu/kvm.h @@ -521,7 +521,6 @@ int kvm_set_one_reg(CPUState *cs, uint64_t id, void *source); * Returns: 0 on success, or a negative errno on failure. */ int kvm_get_one_reg(CPUState *cs, uint64_t id, void *target); -struct ppc_radix_page_info *kvm_get_radix_page_info(void); /* Notify resamplefd for EOI of specific interrupts. */ void kvm_resample_fd_notify(int gsi); diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index d0e2dcdc77..9b1abe2fc4 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -268,7 +268,7 @@ static void kvm_get_smmu_info(struct kvm_ppc_smmu_info *info, Error **errp) "KVM failed to provide the MMU features it supports"); } -struct ppc_radix_page_info *kvm_get_radix_page_info(void) +static struct ppc_radix_page_info *kvmppc_get_radix_page_info(void) { KVMState *s = KVM_STATE(current_accel()); struct ppc_radix_page_info *radix_page_info; @@ -2368,7 +2368,7 @@ static void kvmppc_host_cpu_class_init(ObjectClass *oc, void *data) } #if defined(TARGET_PPC64) - pcc->radix_page_info = kvm_get_radix_page_info(); + pcc->radix_page_info = kvmppc_get_radix_page_info(); if ((pcc->pvr & 0xffffff00) == CPU_POWERPC_POWER9_DD1) { /* From patchwork Mon Nov 6 11:03:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13446658 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5D4991A72A for ; Mon, 6 Nov 2023 11:07:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="OuV1/Wk3" Received: from mail-lj1-x233.google.com (mail-lj1-x233.google.com [IPv6:2a00:1450:4864:20::233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3FCCABD for ; Mon, 6 Nov 2023 03:07:27 -0800 (PST) Received: by mail-lj1-x233.google.com with SMTP id 38308e7fff4ca-2c509d5ab43so62477151fa.0 for ; Mon, 06 Nov 2023 03:07:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699268845; x=1699873645; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2OUN8qI3wvvK+6EjwaYybG9IZ1pKduK7zbEAWLMDuTw=; b=OuV1/Wk3p2CYejNS+Gmt2fBvHPaXuFEdMy3ENvZKuseLm9SyNXLphqn+KAOww7EgB3 kQrUyMLV7PixhbhbbOliMsTqMYLHOcH9FOIkZ5M4uissYodFsVdFoD8Mkcnu8wf+in+G pV85dQii9abuJ+x9BCNGFfEyJvxtN+5KVl8Q3Etp87oXyE1I3EuoqLNMm6FB6+OacD1l 177JvWzSBdJqiM8JaWGnge1WvxedXGLDyWf4KvLifPTWCNShDnhxF7+vqbHEgogpgL5R 6wGqljJ2rF3AvWZj9zFTfqm1b/XV40CFh4cghPgE3foVYY7RnNRs/o57lrI2YxaEozrL BdsA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699268845; x=1699873645; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2OUN8qI3wvvK+6EjwaYybG9IZ1pKduK7zbEAWLMDuTw=; b=VKsQJ9XdvYK5b4r+OicjoaBf8GNGeUWp3AVkHS+3RBklJ04SZYzi5TiyQTXjJ+QPzq Z7TZWsfISZQUWbNuzzNcSbabSq8eG9Ny4YexbgZNRBzp0/Sh5A7+le1hSMl5GaV+1G0J LYZKu0e1eRufbmNK5BEOgFqMHwHlvDX8MEo9LaOjOhy82ZHwzjj6kpoW7T6yhR9CiGnU R4lHavtHPvK0tiiviDY5Yab+SpgAfbC9jhWuUTpRSk95oK4Jygy37ZnEb5UxTmc1+2Om TeV2plCaEPfJas/+eRyoJxMQ8w+KpzhYebia696jHAI0oOJYypdNIem9GwPeBs2Yln5U x0zA== X-Gm-Message-State: AOJu0Yx8BlejoIU2ON6Kr0iG2Fu3q76fPmgQY/DQo7l6pLcBN54Y/rNP rOw0tiBz5rdGoLbYCwolQtnicA== X-Google-Smtp-Source: AGHT+IFLhhaF5dO3+8DYorxoIdQA7+GAd7X/cQ5bFHpXQKo5JyRHH2aTx5vdNP64N0ZZh22eyd9tMw== X-Received: by 2002:a2e:3816:0:b0:2c5:8a0:b502 with SMTP id f22-20020a2e3816000000b002c508a0b502mr21890109lja.48.1699268845464; Mon, 06 Nov 2023 03:07:25 -0800 (PST) Received: from m1x-phil.lan (176-131-220-199.abo.bbox.fr. [176.131.220.199]) by smtp.gmail.com with ESMTPSA id j8-20020a05600c1c0800b004063977eccesm11981849wms.42.2023.11.06.03.07.23 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:07:25 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Michael Tokarev , Nicholas Piggin , Daniel Henrique Barboza , =?utf-8?q?C=C3=A9dric_Le_G?= =?utf-8?q?oater?= Subject: [PULL 33/60] hw/ppc/e500: Restrict ppce500_init_mpic_kvm() to KVM Date: Mon, 6 Nov 2023 12:03:05 +0100 Message-ID: <20231106110336.358-34-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Inline and guard the single call to kvm_openpic_connect_vcpu() allows to remove kvm-stub.c. Reviewed-by: Michael Tokarev Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20231003070427.69621-3-philmd@linaro.org> --- hw/ppc/e500.c | 4 ++++ target/ppc/kvm-stub.c | 19 ------------------- target/ppc/meson.build | 2 +- 3 files changed, 5 insertions(+), 20 deletions(-) delete mode 100644 target/ppc/kvm-stub.c diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index e04114fb3c..384226296b 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -834,6 +834,7 @@ static DeviceState *ppce500_init_mpic_qemu(PPCE500MachineState *pms, static DeviceState *ppce500_init_mpic_kvm(const PPCE500MachineClass *pmc, IrqLines *irqs, Error **errp) { +#ifdef CONFIG_KVM DeviceState *dev; CPUState *cs; @@ -854,6 +855,9 @@ static DeviceState *ppce500_init_mpic_kvm(const PPCE500MachineClass *pmc, } return dev; +#else + g_assert_not_reached(); +#endif } static DeviceState *ppce500_init_mpic(PPCE500MachineState *pms, diff --git a/target/ppc/kvm-stub.c b/target/ppc/kvm-stub.c deleted file mode 100644 index b98e1d404f..0000000000 --- a/target/ppc/kvm-stub.c +++ /dev/null @@ -1,19 +0,0 @@ -/* - * QEMU KVM PPC specific function stubs - * - * Copyright Freescale Inc. 2013 - * - * Author: Alexander Graf - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - * - */ -#include "qemu/osdep.h" -#include "cpu.h" -#include "hw/ppc/openpic_kvm.h" - -int kvm_openpic_connect_vcpu(DeviceState *d, CPUState *cs) -{ - return -EINVAL; -} diff --git a/target/ppc/meson.build b/target/ppc/meson.build index 97ceb6e7c0..eab4e3e1b3 100644 --- a/target/ppc/meson.build +++ b/target/ppc/meson.build @@ -30,7 +30,7 @@ gen = [ ] ppc_ss.add(when: 'CONFIG_TCG', if_true: gen) -ppc_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: files('kvm-stub.c')) +ppc_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) ppc_ss.add(when: 'CONFIG_USER_ONLY', if_true: files('user_only_helper.c')) ppc_system_ss = ss.source_set() From patchwork Mon Nov 6 11:03:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13446659 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1730C1A737 for ; Mon, 6 Nov 2023 11:07:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="zvHmpphE" Received: from mail-wm1-x335.google.com (mail-wm1-x335.google.com [IPv6:2a00:1450:4864:20::335]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 70C7ED6B for ; Mon, 6 Nov 2023 03:07:33 -0800 (PST) Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-4079ed65582so32870765e9.1 for ; Mon, 06 Nov 2023 03:07:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699268852; x=1699873652; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Cb2SoP+Kcg9QwI4B3FcAYm9BYCwnPa3WzQeoNeejBGE=; b=zvHmpphETVF1bVI04pb8VaDcDZCtQq3zDUq2EkMzpSBxWIzfs/WsMTxi5Fyjd/euyw rLJypWa/XIb9r5bDZjlDYVtMKPNVKilyOCDgpVKNjGHMf7tv6jf6x6JzHzUbx/aLjQKu mjKqlLchCYeQ2/Ak6WKwjGEgFendwxfsA1uU3kixHAW+C/mC7tj1jnSGp+ISu35uzhmR VyYhLWH4Xmumtflf5jVFOUkM0RIP0FStwu4GokeeZOi++5ovtLwtFNzxhxC2kVn1szcz maaQBqdOsGRxMQRUAcF6z/slUjxRQ1Cp5zKfPR5eRGtKMVySixpgP1dwXbI6bPGSlhDB 604g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699268852; x=1699873652; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Cb2SoP+Kcg9QwI4B3FcAYm9BYCwnPa3WzQeoNeejBGE=; b=T+X9581+cRk5PT7a6YSVC8AQKeOdN7vonWkPd8tZhUhoQ1kCZIRLmj4N3hDDbnFhwi exMzgQDLOZjhMomwBj4xWuHZvpEI6eBi1SkqQSMMmVaI7vCf+xY08BjllioxmYoeL+AX DI3ZNVhRNsNSkzsStKt5ioUQz4TmlEsVTqXWiaN/on88Ld8eIk7FQT0drC8M03n3pORv QP32P+Kgrn2cliR8mMG1KljQT3SIgCu35OZ8r6VDSZhL2y8wxx5+atvCVb7fiK6NryZB /fCN1DXvNKSRQFkfuVqdTZV3W+MI0unfmT1uyVWhCgb1okOI7O4V20qIzPx1W2G3kC1W 70Lg== X-Gm-Message-State: AOJu0YzaAUtd3dCfrox5KWNmRGYnq3KWwAEV/XyaNAtermpejxTl8r8K WmsPKD48dq1wL3KSyFXH5jHBTQ== X-Google-Smtp-Source: AGHT+IGOwGb19To8VXCdR8ERpA0kEx5JDBtiDEBtx2l74K+wLoipriHx1wrJrWcABU//cghRcbbU9g== X-Received: by 2002:a05:600c:4fc6:b0:401:b652:b6cf with SMTP id o6-20020a05600c4fc600b00401b652b6cfmr23757960wmq.13.1699268851941; Mon, 06 Nov 2023 03:07:31 -0800 (PST) Received: from m1x-phil.lan (176-131-220-199.abo.bbox.fr. [176.131.220.199]) by smtp.gmail.com with ESMTPSA id f13-20020a05600c4e8d00b0040596352951sm11677086wmq.5.2023.11.06.03.07.30 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:07:31 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Michael Tokarev , Nicholas Piggin , Daniel Henrique Barboza , =?utf-8?q?C=C3=A9dric_Le_G?= =?utf-8?q?oater?= Subject: [PULL 34/60] target/ppc: Restrict KVM objects to system emulation Date: Mon, 6 Nov 2023 12:03:06 +0100 Message-ID: <20231106110336.358-35-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 CONFIG_KVM is always FALSE on user emulation, so 'kvm.c' won't be added to ppc_ss[] source set; direcly use the system specific ppc_system_ss[] source set. Reviewed-by: Michael Tokarev Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20231003070427.69621-4-philmd@linaro.org> --- target/ppc/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/ppc/meson.build b/target/ppc/meson.build index eab4e3e1b3..0b89f9b89f 100644 --- a/target/ppc/meson.build +++ b/target/ppc/meson.build @@ -30,7 +30,6 @@ gen = [ ] ppc_ss.add(when: 'CONFIG_TCG', if_true: gen) -ppc_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) ppc_ss.add(when: 'CONFIG_USER_ONLY', if_true: files('user_only_helper.c')) ppc_system_ss = ss.source_set() @@ -46,6 +45,7 @@ ppc_system_ss.add(when: 'CONFIG_TCG', if_true: files( ), if_false: files( 'tcg-stub.c', )) +ppc_system_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) ppc_system_ss.add(when: 'TARGET_PPC64', if_true: files( 'compat.c', From patchwork Mon Nov 6 11:03:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13446660 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B95121EB39 for ; Mon, 6 Nov 2023 11:07:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="BwTOngkf" Received: from mail-wm1-x334.google.com (mail-wm1-x334.google.com [IPv6:2a00:1450:4864:20::334]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 353E5123 for ; Mon, 6 Nov 2023 03:07:40 -0800 (PST) Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-408002b5b9fso32375715e9.3 for ; Mon, 06 Nov 2023 03:07:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699268858; x=1699873658; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/8FQLEYTqFB9Ro3y1RtUGoGmFmjKyGG2i99735loRZ8=; b=BwTOngkflAtW3hPshKdVksO7RjIqhbJRW/QDH5FtEziR7q1SKhNHqQNusFFhbToGfM Lt4RtSOvonispD027ST875cyLOa3l/dI21BaNfBEtpMfs9k88i88GtrH5FJl4kDCxtJM vwKYrejLqFHlB9D9xTffm+w/XKeC6eYjgpm9ZBdssPUc/jRoyIEjZsvpT9JwYtQZTqTW kgw9XOhV1LWaiVWyJ9R09XE50WW6Qng7QK0cOFgMEw9jpz2bJGhN1UAajJi8CL2g6ceW ad8GidRUkzi6jpAnMQAaVb9Tr406KaK/pbMImKyFw6sJTfvUP6I/AHyk37MaJJ30urkz pDBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699268858; x=1699873658; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/8FQLEYTqFB9Ro3y1RtUGoGmFmjKyGG2i99735loRZ8=; b=svLCA2vXW+l6MoL0Wt/1N5SB3778+sa4g3jqE916qfTvzCp7VJpwaDMnCQQkH1v/wG wqUTMav1qYZ4Ex7P3JHFqKyxGPvJRMcLrv3bahPbPvhGMBKg7MPboTTi/BpC1gKaJxYF qaQrBrHagpOlhDk1Zhp78E27iOPzhekdNcyr+ptyHKKNds0Nlq/S5x87d/94Xut3ADXB nbGPXQ4Teq2NMgX8eyqTtlgWwjpwwV78ITMACknwTBhhAoXV6LpKseyepjNGdhNjEZXq yQcuKMhbl4NvegHHwVFBBDKdtiDVIuicaWxcw1wNq5l99/+PELZU6zonFFl3ibKZICLB HYBw== X-Gm-Message-State: AOJu0YxVxI31Qhz9swDWRsCB72DN+HEhpd6FRTXBDU4J+Y/VnhVgyaQm Q6ys/AQ0mkwXa8U70kf9EavmX18T5wF88QvFqDU= X-Google-Smtp-Source: AGHT+IGSllHpaGQMqKbvX8OyPw5FMMgGznDw9vfBmKkgEXMDizlL7BCd/fkfmOdW9htoRowrrHTYDQ== X-Received: by 2002:a5d:6dae:0:b0:32f:7c01:5376 with SMTP id u14-20020a5d6dae000000b0032f7c015376mr22752718wrs.31.1699268858733; Mon, 06 Nov 2023 03:07:38 -0800 (PST) Received: from m1x-phil.lan (176-131-220-199.abo.bbox.fr. [176.131.220.199]) by smtp.gmail.com with ESMTPSA id z13-20020a5d4d0d000000b0031ad5fb5a0fsm9131295wrt.58.2023.11.06.03.07.36 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:07:38 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Kevin Wolf , Daniel Henrique Barboza , Nicholas Piggin , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Paolo Bonzini Subject: [PULL 35/60] target/ppc: Prohibit target specific KVM prototypes on user emulation Date: Mon, 6 Nov 2023 12:03:07 +0100 Message-ID: <20231106110336.358-36-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 None of these target-specific prototypes should be used by user emulation. Remove their declaration there, so we get a compile failure if ever used (instead of having to deal with linker and its possible optimizations, such dead code removal). Suggested-by: Kevin Wolf Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Daniel Henrique Barboza Message-Id: <20231003070427.69621-5-philmd@linaro.org> --- target/ppc/kvm_ppc.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/ppc/kvm_ppc.h b/target/ppc/kvm_ppc.h index 6a4dd9c560..1975fb5ee6 100644 --- a/target/ppc/kvm_ppc.h +++ b/target/ppc/kvm_ppc.h @@ -13,6 +13,10 @@ #include "exec/hwaddr.h" #include "cpu.h" +#ifdef CONFIG_USER_ONLY +#error Cannot include kvm_ppc.h from user emulation +#endif + #ifdef CONFIG_KVM uint32_t kvmppc_get_tbfreq(void); From patchwork Mon Nov 6 11:03:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13446661 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D8E711EB39 for ; Mon, 6 Nov 2023 11:07:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="z43JXbHH" Received: from mail-wm1-x32a.google.com (mail-wm1-x32a.google.com [IPv6:2a00:1450:4864:20::32a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A9F4D123 for ; Mon, 6 Nov 2023 03:07:46 -0800 (PST) Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-40891d38e3fso30632525e9.1 for ; Mon, 06 Nov 2023 03:07:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699268865; x=1699873665; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=95fjXxwoCEM5MPpLzleCUNmgt+EGYy9i69c6BsnNRfk=; b=z43JXbHHlKFbOubTUOoUCrRLBbX8i0hv8qPD+KqlgC1Cj2as9T79PKiAchSEv1q7Ib hInIIyPfDLyhlOHFHZVhQf8ayAw94IsVlrdlcvBOGcDCfPKAZ7PUaiGFDy6CK/7lhb/p 35p3h5ugMmIsp20avrotb9IyoRkM6l14dj1Ag/Tk6e+E2BquDe8MMnW6utP7jJIitBvp nORknrmIIH73JiDauubZPsikvclLDtABnvjsvW7FzUSCYb2kcIvO5w7HytZwgNgSZ3Rb EK7pCEk2wdsVHfa3uTStIRjzh6IWbRxLHCOvP34qgZQWtZcOnzeovu+0xtILhKN0PdQW k2cA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699268865; x=1699873665; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=95fjXxwoCEM5MPpLzleCUNmgt+EGYy9i69c6BsnNRfk=; b=DMXMiBe2IFgwDugW25MF/1UYdf1LMbNb38djEwwMuLDWoLR9QRGJEHNy8zh/HQkw7T LXE7xctbmXInBwMPz/C0dM/ubY9xDtrH3wXsYXTGEKXM1m8gQEmycB6he5nREp295ZC2 5qRqBEt/v8BReFQfc8nVVhcSCf6afjSKqdEl2Z7UMSrLARXI0rN0h4mgL+z0d5o6XfKN 0+5kOxP0jkLv4lAV6to0TXxwpqeeTeUR+AIc70LUnij9Z1psHih18oD2zgpFVbLMIRgo 0irFy1L/ap7KzUGLtR7XQh+OnaTmK8zJP61oTnR+TDried/VLeRtVlPWZ0cj2+q/LjLa /5JA== X-Gm-Message-State: AOJu0YzxX6b1u1cS7P12ljCKUDrAQZFFZLrv3S9igNjZDUSXWJu0Oj76 LYJAGatSdlLmCNbDUM3fs9bBboBw9/LoAXlkfQA= X-Google-Smtp-Source: AGHT+IFA2chfzU/RG3fUnF9L1zuwbrR/mZ3//aX7n36RLMNo0C4jCT70SUW9S7M0scEuKtQWCV9uyw== X-Received: by 2002:a05:600c:4c9a:b0:409:57ec:9d7e with SMTP id g26-20020a05600c4c9a00b0040957ec9d7emr13786805wmp.21.1699268865155; Mon, 06 Nov 2023 03:07:45 -0800 (PST) Received: from m1x-phil.lan (176-131-220-199.abo.bbox.fr. [176.131.220.199]) by smtp.gmail.com with ESMTPSA id f20-20020a05600c43d400b003fbe4cecc3bsm11518827wmn.16.2023.11.06.03.07.43 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:07:44 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Chris Wulff , Marek Vasut Subject: [PULL 36/60] target/nios2: Create IRQs *after* accelerator vCPU is realized Date: Mon, 6 Nov 2023 12:03:08 +0100 Message-ID: <20231106110336.358-37-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Architecture specific hardware doesn't have a particular dependency on the accelerator vCPU (created with cpu_exec_realizefn), and can be initialized *after* the vCPU is realized. Doing so allows further generic API simplification (in few commits). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20230918160257.30127-12-philmd@linaro.org> --- target/nios2/cpu.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 15e499f828..a27732bf2b 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -199,14 +199,6 @@ static void nios2_cpu_realizefn(DeviceState *dev, Error **errp) Nios2CPUClass *ncc = NIOS2_CPU_GET_CLASS(dev); Error *local_err = NULL; -#ifndef CONFIG_USER_ONLY - if (cpu->eic_present) { - qdev_init_gpio_in_named(DEVICE(cpu), eic_set_irq, "EIC", 1); - } else { - qdev_init_gpio_in_named(DEVICE(cpu), iic_set_irq, "IRQ", 32); - } -#endif - cpu_exec_realizefn(cs, &local_err); if (local_err != NULL) { error_propagate(errp, local_err); @@ -220,6 +212,14 @@ static void nios2_cpu_realizefn(DeviceState *dev, Error **errp) /* We have reserved storage for cpuid; might as well use it. */ cpu->env.ctrl[CR_CPUID] = cs->cpu_index; +#ifndef CONFIG_USER_ONLY + if (cpu->eic_present) { + qdev_init_gpio_in_named(DEVICE(cpu), eic_set_irq, "EIC", 1); + } else { + qdev_init_gpio_in_named(DEVICE(cpu), iic_set_irq, "IRQ", 32); + } +#endif + ncc->parent_realize(dev, errp); } From patchwork Mon Nov 6 11:03:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13446662 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 291641EB29 for ; Mon, 6 Nov 2023 11:07:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="K2k1mgOn" Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 59165C6 for ; Mon, 6 Nov 2023 03:07:53 -0800 (PST) Received: by mail-lf1-x12c.google.com with SMTP id 2adb3069b0e04-5094727fa67so5758741e87.3 for ; Mon, 06 Nov 2023 03:07:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699268871; x=1699873671; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pDLz44pMnS6BY17PlhPlXPTDOUKf2M5E2FKcksHeUks=; b=K2k1mgOnrFGOSkqX8vuZeNMUc+VoeJLQpSc+AsxYzi7DnLeAYTNtpuxf6f+f9zPMWc CfhHOOfQ3NfdefvnDFQbp1yKAsm38+3jnN3oX7Y5vIYDJ4sQSeMJX/yUoBnQNJqwc05f CNtTSO78vt834B8vnut/6DbQSbznJ/6qRSVDBId6IQfQlMlookYq6y9w2UVLccffixRf WJiToko16SOt9hFcflUpD073AdGm+rw4Et8fPC6LVo9ljQVoKSCCIcbTNnL2kyaXIFlt v+S8wZZ/MN5/MZZMdS6P6119xq8vAjJkCsacPUIDvL7kpRgKzeKW0nv78KnLL5B0eHdm i+HQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699268871; x=1699873671; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pDLz44pMnS6BY17PlhPlXPTDOUKf2M5E2FKcksHeUks=; b=ES96WkmLGRFMynLNeOLMf0gkCtY9H7gzF0V/B7WsNGV6NjNKD4UkDamRMZV7SN+qdb PXL/2J/bHLHA5o5gPFX9QPT5BfknJCatp19xkwKHkCehlkK84X9KPpUEtOu5U7Ypjima R9L9w9Bps+/JQbZ16C80rNsT2mfI+4yEEcYuPKwHuVR0ratWnY4aET1+1WVwgwu66Y4r olPU8pY0ak5KZ1vsWy3yx4x2jS4GjQi7s5NBf5bq5KLKLbqc/lD3gD2ks03BC0T3TTBo ezvDJ0BTTU/7nPrWALU9XbJjqvJzddgG3sDAkl22MFtRKDvypBj3vOVX4/Ln8fuPuvzd 9J/A== X-Gm-Message-State: AOJu0YwnU8NpnotAok/15SMqjVOi8E7nn9ZkkovlBm+djoggQeVO9xFl AIh2aUzOYJarxVDo/mFo5msYGA== X-Google-Smtp-Source: AGHT+IHcdyLqApBzrM1UIl1rL4HV5Kt/MnTQib7GE9Ti6YP9IhDYtQPkYZQNlydR2XL1DbF6EVXSWA== X-Received: by 2002:ac2:44ae:0:b0:503:38f2:6e1 with SMTP id c14-20020ac244ae000000b0050338f206e1mr18200122lfm.5.1699268871711; Mon, 06 Nov 2023 03:07:51 -0800 (PST) Received: from m1x-phil.lan (176-131-220-199.abo.bbox.fr. [176.131.220.199]) by smtp.gmail.com with ESMTPSA id k18-20020a5d6d52000000b0032da4f70756sm9122296wri.5.2023.11.06.03.07.49 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:07:51 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Gavin Shan Subject: [PULL 37/60] target/alpha: Tidy up alpha_cpu_class_by_name() Date: Mon, 6 Nov 2023 12:03:09 +0100 Message-ID: <20231106110336.358-38-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Gavin Shan Message-Id: <20230908112235.75914-2-philmd@linaro.org> --- target/alpha/cpu.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 51b7d8d1bf..fae2cb6ec7 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -142,13 +142,10 @@ static ObjectClass *alpha_cpu_class_by_name(const char *cpu_model) typename = g_strdup_printf(ALPHA_CPU_TYPE_NAME("%s"), cpu_model); oc = object_class_by_name(typename); g_free(typename); - if (oc != NULL && object_class_is_abstract(oc)) { - oc = NULL; - } /* TODO: remove match everything nonsense */ - /* Default to ev67; no reason not to emulate insns by default. */ - if (!oc) { + if (!oc || object_class_is_abstract(oc)) { + /* Default to ev67; no reason not to emulate insns by default. */ oc = object_class_by_name(ALPHA_CPU_TYPE_NAME("ev67")); } From patchwork Mon Nov 6 11:03:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13446663 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EFB6517754 for ; Mon, 6 Nov 2023 11:08:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="HIDP4jIR" Received: from mail-wr1-x42e.google.com (mail-wr1-x42e.google.com [IPv6:2a00:1450:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7324DB0 for ; Mon, 6 Nov 2023 03:08:01 -0800 (PST) Received: by mail-wr1-x42e.google.com with SMTP id ffacd0b85a97d-32f87b1c725so3054986f8f.3 for ; Mon, 06 Nov 2023 03:08:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699268880; x=1699873680; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KMjbC2xJWHxNTrhQC1HW/27kz6qe7U3LIUpfEfCgflY=; b=HIDP4jIRpU1/hcmWWmR4dZbaGRms5qyrf/6wx9v2M9kXLYYSG5pFjcv5qbsLqN55BW WQX4b3xqYi21ni8YffZZMOgInyhYHN3WxnqCwx8RRWmDC63/tH23JbJXc13TV9lHe2Le B5AFFA0juHhWZuL0oPu/xJ7XdsKRfmPRtVXhoisAsq0HWToPttOznDaUUVIcQ87Im6xz N0P8dXDeVx1FSnY8H2ZobK3F7M4ZDH9bfu9QhGiSAID8e1BAuJYLBq0EHmlyk1rhoMo6 7s0yvK0yF6iRLhOKV8Mz2b0p1KS/HMNBmk3kqdWxVvfWWftJqjbgcWpE5cqXMGg6ZbGo z9Bg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699268880; x=1699873680; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KMjbC2xJWHxNTrhQC1HW/27kz6qe7U3LIUpfEfCgflY=; b=hNYifSsUl2iuHL99KYVwx1aUM1wI97fozvyWNBaiYXOn52d79JUozU5K2bZnWE1UrK wZYLhV5w1ePAenX6f96VnVJCkuZtMveoRztqjqUsZssLMHYCkC0f9nqgJh5DMkPGJNiL tnQ6soF266dq0Jill/l4unV013hjHOGduf/pjLIBmf2DefGtNWWTdqst+/nQVRbS+iTc polv/wXZWscSeDbIB7DswYjtJCSbyLFChQxIHF7vadfhor8qljPrezCDBvnzD3JO0c8b uTsFRctM5j793z4fno05eu1qvEmG+x4Gd4HEFkDuUURoapYoTy7BLYny21x78lXekNAT OeGQ== X-Gm-Message-State: AOJu0Yx8I/oseVTqCQ6El6kD2Gv3QLclGbT0QkLCBz58NY0vw2zVh9m3 WkN6FNXn/LOnbn1KrKukxgZ/QQ== X-Google-Smtp-Source: AGHT+IH9X2GE3xs55/ZsOwgF8AvUm+DWjmmM+7ejsJtn9NBM/K//H0bsohOzSfHKuAoPE0hD1kKuBQ== X-Received: by 2002:a5d:47a9:0:b0:32f:96c6:8bb with SMTP id 9-20020a5d47a9000000b0032f96c608bbmr13753845wrb.7.1699268879845; Mon, 06 Nov 2023 03:07:59 -0800 (PST) Received: from m1x-phil.lan (176-131-220-199.abo.bbox.fr. [176.131.220.199]) by smtp.gmail.com with ESMTPSA id l4-20020a5d5604000000b0032f78feb826sm9106145wrv.104.2023.11.06.03.07.56 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:07:59 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Eduardo Habkost , Marcel Apfelbaum , Yanan Wang , Peter Maydell , Michael Rolnik , "Edgar E. Iglesias" , Brian Cain , Song Gao , Laurent Vivier , Stafford Horne , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Yoshinori Sato , Bastian Koppelmann , Max Filippov Subject: [PULL 38/60] hw/cpu: Call object_class_is_abstract() once in cpu_class_by_name() Date: Mon, 6 Nov 2023 12:03:10 +0100 Message-ID: <20231106110336.358-39-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Let CPUClass::class_by_name() handlers to return abstract classes, and filter them once in the public cpu_class_by_name() method. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20230908112235.75914-3-philmd@linaro.org> --- include/hw/core/cpu.h | 7 ++++--- hw/core/cpu-common.c | 14 +++++++++++--- target/alpha/cpu.c | 3 +-- target/arm/cpu.c | 3 +-- target/avr/cpu.c | 3 +-- target/cris/cpu.c | 3 +-- target/hexagon/cpu.c | 3 +-- target/loongarch/cpu.c | 3 +-- target/m68k/cpu.c | 3 +-- target/openrisc/cpu.c | 3 +-- target/riscv/cpu.c | 3 +-- target/rx/cpu.c | 6 +----- target/sh4/cpu.c | 3 --- target/tricore/cpu.c | 3 +-- target/xtensa/cpu.c | 3 +-- 15 files changed, 27 insertions(+), 36 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 6373aa4501..5d6f8dca43 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -102,7 +102,7 @@ struct SysemuCPUOps; /** * CPUClass: * @class_by_name: Callback to map -cpu command line model name to an - * instantiatable CPU type. + * instantiatable CPU type. * @parse_features: Callback to parse command line arguments. * @reset_dump_flags: #CPUDumpFlags to use for reset logging. * @has_work: Callback for checking if there is work to do. @@ -772,9 +772,10 @@ void cpu_reset(CPUState *cpu); * @typename: The CPU base type. * @cpu_model: The model string without any parameters. * - * Looks up a CPU #ObjectClass matching name @cpu_model. + * Looks up a concrete CPU #ObjectClass matching name @cpu_model. * - * Returns: A #CPUClass or %NULL if not matching class is found. + * Returns: A concrete #CPUClass or %NULL if no matching class is found + * or if the matching class is abstract. */ ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model); diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c index baa6d28b64..d4112b8919 100644 --- a/hw/core/cpu-common.c +++ b/hw/core/cpu-common.c @@ -146,10 +146,18 @@ static bool cpu_common_has_work(CPUState *cs) ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model) { - CPUClass *cc = CPU_CLASS(object_class_by_name(typename)); + ObjectClass *oc; + CPUClass *cc; - assert(cpu_model && cc->class_by_name); - return cc->class_by_name(cpu_model); + oc = object_class_by_name(typename); + cc = CPU_CLASS(oc); + assert(cc->class_by_name); + assert(cpu_model); + oc = cc->class_by_name(cpu_model); + if (oc == NULL || object_class_is_abstract(oc)) { + return NULL; + } + return oc; } static void cpu_common_parse_features(const char *typename, char *features, diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index fae2cb6ec7..39cf841b3e 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -126,8 +126,7 @@ static ObjectClass *alpha_cpu_class_by_name(const char *cpu_model) int i; oc = object_class_by_name(cpu_model); - if (oc != NULL && object_class_dynamic_cast(oc, TYPE_ALPHA_CPU) != NULL && - !object_class_is_abstract(oc)) { + if (oc != NULL && object_class_dynamic_cast(oc, TYPE_ALPHA_CPU) != NULL) { return oc; } diff --git a/target/arm/cpu.c b/target/arm/cpu.c index df6496b019..25e9d2ae7b 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2401,8 +2401,7 @@ static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) oc = object_class_by_name(typename); g_strfreev(cpuname); g_free(typename); - if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || - object_class_is_abstract(oc)) { + if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU)) { return NULL; } return oc; diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 14d8b9d1f0..44de1e18d1 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -157,8 +157,7 @@ static ObjectClass *avr_cpu_class_by_name(const char *cpu_model) ObjectClass *oc; oc = object_class_by_name(cpu_model); - if (object_class_dynamic_cast(oc, TYPE_AVR_CPU) == NULL || - object_class_is_abstract(oc)) { + if (object_class_dynamic_cast(oc, TYPE_AVR_CPU) == NULL) { oc = NULL; } return oc; diff --git a/target/cris/cpu.c b/target/cris/cpu.c index be4a44c218..675b73ac04 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -95,8 +95,7 @@ static ObjectClass *cris_cpu_class_by_name(const char *cpu_model) typename = g_strdup_printf(CRIS_CPU_TYPE_NAME("%s"), cpu_model); oc = object_class_by_name(typename); g_free(typename); - if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_CRIS_CPU) || - object_class_is_abstract(oc))) { + if (oc != NULL && !object_class_dynamic_cast(oc, TYPE_CRIS_CPU)) { oc = NULL; } return oc; diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 1adc11b713..9d1ffc3b4b 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -63,8 +63,7 @@ static ObjectClass *hexagon_cpu_class_by_name(const char *cpu_model) oc = object_class_by_name(typename); g_strfreev(cpuname); g_free(typename); - if (!oc || !object_class_dynamic_cast(oc, TYPE_HEXAGON_CPU) || - object_class_is_abstract(oc)) { + if (!oc || !object_class_dynamic_cast(oc, TYPE_HEXAGON_CPU)) { return NULL; } return oc; diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index ef1bf89dac..06d1b9bb95 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -648,8 +648,7 @@ static ObjectClass *loongarch_cpu_class_by_name(const char *cpu_model) } } - if (object_class_dynamic_cast(oc, TYPE_LOONGARCH_CPU) - && !object_class_is_abstract(oc)) { + if (object_class_dynamic_cast(oc, TYPE_LOONGARCH_CPU)) { return oc; } return NULL; diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 538d9473c2..11c7e0a790 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -111,8 +111,7 @@ static ObjectClass *m68k_cpu_class_by_name(const char *cpu_model) typename = g_strdup_printf(M68K_CPU_TYPE_NAME("%s"), cpu_model); oc = object_class_by_name(typename); g_free(typename); - if (oc != NULL && (object_class_dynamic_cast(oc, TYPE_M68K_CPU) == NULL || - object_class_is_abstract(oc))) { + if (oc != NULL && object_class_dynamic_cast(oc, TYPE_M68K_CPU) == NULL) { return NULL; } return oc; diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index f5a3d5273b..1173260017 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -164,8 +164,7 @@ static ObjectClass *openrisc_cpu_class_by_name(const char *cpu_model) typename = g_strdup_printf(OPENRISC_CPU_TYPE_NAME("%s"), cpu_model); oc = object_class_by_name(typename); g_free(typename); - if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_OPENRISC_CPU) || - object_class_is_abstract(oc))) { + if (oc != NULL && !object_class_dynamic_cast(oc, TYPE_OPENRISC_CPU)) { return NULL; } return oc; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ac4a6c7eec..63624e8b76 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -636,8 +636,7 @@ static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) oc = object_class_by_name(typename); g_strfreev(cpuname); g_free(typename); - if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) || - object_class_is_abstract(oc)) { + if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU)) { return NULL; } return oc; diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 4d0d3a0c8c..9cc9d9d15e 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -111,16 +111,12 @@ static ObjectClass *rx_cpu_class_by_name(const char *cpu_model) char *typename; oc = object_class_by_name(cpu_model); - if (oc != NULL && object_class_dynamic_cast(oc, TYPE_RX_CPU) != NULL && - !object_class_is_abstract(oc)) { + if (oc != NULL && object_class_dynamic_cast(oc, TYPE_RX_CPU) != NULL) { return oc; } typename = g_strdup_printf(RX_CPU_TYPE_NAME("%s"), cpu_model); oc = object_class_by_name(typename); g_free(typename); - if (oc != NULL && object_class_is_abstract(oc)) { - oc = NULL; - } return oc; } diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 788e41fea6..a8ec98b134 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -152,9 +152,6 @@ static ObjectClass *superh_cpu_class_by_name(const char *cpu_model) typename = g_strdup_printf(SUPERH_CPU_TYPE_NAME("%s"), s); oc = object_class_by_name(typename); - if (oc != NULL && object_class_is_abstract(oc)) { - oc = NULL; - } out: g_free(s); diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 5ca666ee12..034e01c189 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -132,8 +132,7 @@ static ObjectClass *tricore_cpu_class_by_name(const char *cpu_model) typename = g_strdup_printf(TRICORE_CPU_TYPE_NAME("%s"), cpu_model); oc = object_class_by_name(typename); g_free(typename); - if (!oc || !object_class_dynamic_cast(oc, TYPE_TRICORE_CPU) || - object_class_is_abstract(oc)) { + if (!oc || !object_class_dynamic_cast(oc, TYPE_TRICORE_CPU)) { return NULL; } return oc; diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index ea1dae7390..e20fe87bf2 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -141,8 +141,7 @@ static ObjectClass *xtensa_cpu_class_by_name(const char *cpu_model) typename = g_strdup_printf(XTENSA_CPU_TYPE_NAME("%s"), cpu_model); oc = object_class_by_name(typename); g_free(typename); - if (oc == NULL || !object_class_dynamic_cast(oc, TYPE_XTENSA_CPU) || - object_class_is_abstract(oc)) { + if (oc == NULL || !object_class_dynamic_cast(oc, TYPE_XTENSA_CPU)) { return NULL; } return oc; From patchwork Mon Nov 6 11:03:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13446664 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C7FCF1864A for ; Mon, 6 Nov 2023 11:08:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="MC1qL/c1" Received: from mail-lf1-x12b.google.com (mail-lf1-x12b.google.com [IPv6:2a00:1450:4864:20::12b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 345C8BB for ; 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id a1-20020a05600c348100b003fe1fe56202sm12104665wmq.33.2023.11.06.03.08.04 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:08:06 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Marcel Apfelbaum , Yanan Wang Subject: [PULL 39/60] exec/cpu: Have cpu_exec_realize() return a boolean Date: Mon, 6 Nov 2023 12:03:11 +0100 Message-ID: <20231106110336.358-40-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Following the example documented since commit e3fe3988d7 ("error: Document Error API usage rules"), have cpu_exec_realizefn() return a boolean indicating whether an error is set or not. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20230918160257.30127-22-philmd@linaro.org> --- include/hw/core/cpu.h | 2 +- cpu-target.c | 6 ++++-- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 5d6f8dca43..eb943efb8f 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -1152,7 +1152,7 @@ G_NORETURN void cpu_abort(CPUState *cpu, const char *fmt, ...) /* $(top_srcdir)/cpu.c */ void cpu_class_init_props(DeviceClass *dc); void cpu_exec_initfn(CPUState *cpu); -void cpu_exec_realizefn(CPUState *cpu, Error **errp); +bool cpu_exec_realizefn(CPUState *cpu, Error **errp); void cpu_exec_unrealizefn(CPUState *cpu); void cpu_exec_reset_hold(CPUState *cpu); diff --git a/cpu-target.c b/cpu-target.c index 79363ae370..f3e1ad8bcd 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -131,13 +131,13 @@ const VMStateDescription vmstate_cpu_common = { }; #endif -void cpu_exec_realizefn(CPUState *cpu, Error **errp) +bool cpu_exec_realizefn(CPUState *cpu, Error **errp) { /* cache the cpu class for the hotpath */ cpu->cc = CPU_GET_CLASS(cpu); if (!accel_cpu_common_realize(cpu, errp)) { - return; + return false; } /* Wait until cpu initialization complete before exposing cpu. */ @@ -159,6 +159,8 @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp) vmstate_register(NULL, cpu->cpu_index, cpu->cc->sysemu_ops->legacy_vmsd, cpu); } #endif /* CONFIG_USER_ONLY */ + + return true; } void cpu_exec_unrealizefn(CPUState *cpu) From patchwork Mon Nov 6 11:03:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13446665 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F403C182C1 for ; Mon, 6 Nov 2023 11:08:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="MuvGfNFA" Received: from mail-wr1-x42b.google.com (mail-wr1-x42b.google.com [IPv6:2a00:1450:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 08517A3 for ; Mon, 6 Nov 2023 03:08:15 -0800 (PST) Received: by mail-wr1-x42b.google.com with SMTP id ffacd0b85a97d-32fd7fc9f19so308058f8f.2 for ; Mon, 06 Nov 2023 03:08:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699268893; x=1699873693; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1c+BV5Tpk9NJdk/9uGPTtpoehyOljryZgDubWA0xkSQ=; b=MuvGfNFAM9MQGFCQS/5TsqG4N8yHvx90JnWeZNahhXuAn2uH1k9DOiIcJIfhlamMDe VaW2mB+dNj7est0QJoPY9TkwceBI4YQVx9KZhp6HZVtKryxDMnDP72n02ITufK8aKcLq Vl+DADaPUFW3/pRN4H9MfwZ+p0FpH8o9eCq+5sLeOqa+N/ZI8IKyhDlsdD7tsHixJwuu al0e94PH2wL7KP5GgoD/OnCkI2sl+Z2Iz+ZWFspyftc3R+OYH083DGjmFAD55Ii3WxO9 Dp2lFsidAuy5RNtPxzuDjNn4THV+yIaBgwcFG0xipi1SOBammULu8FryYNvJEypdhRgn L3Cw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699268893; x=1699873693; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1c+BV5Tpk9NJdk/9uGPTtpoehyOljryZgDubWA0xkSQ=; b=ph3Nzt1DvY3Yrg8tTqQNG/jF+ZBbqxaAwrBveBPGixdKePNZiPacqsgpUeyBM416bb 3ZWXh+rZniWvQ9BCoFAXq8znXsO4ILnQxKmlqeRuivKvChw25Xtbi53zcb7KlOMwEt1v pFrxnnokv8jlBM/u4gDpEPDPllu+/AKBiohCj/71NPrVSk7DfSB+24Ga04r07xbaCwQN 6bZuNtaoMiVNPBrlmtRKuiTC0GE7fsCwuYHAPBK8dbV7HThmUGQXBJvLT4Lip63Xi4fj aVpFw/G3grbjp0TMTY5Zs0BAT7/Q+Weih/dbwqaPuZ6uOOMXU5Offh9tmXkIV5o5rQzH HzOw== X-Gm-Message-State: AOJu0YylylXbgeo1ickU9ZM3q+tkVfhECyMWb6F7t6yuwWUiOkEvVU14 LQt3UDQPT8AgIrEL3sMMldSRLQ== X-Google-Smtp-Source: AGHT+IFUfEPgJeqeBUUqYn0HxWEHowevUtNbHp5ZBZ2R9PkQdeXdrg9oHvMCfdnh5DWjqHW4fF0gbg== X-Received: by 2002:a05:6000:1864:b0:32f:7c4d:8746 with SMTP id d4-20020a056000186400b0032f7c4d8746mr24071431wri.12.1699268893422; Mon, 06 Nov 2023 03:08:13 -0800 (PST) Received: from m1x-phil.lan (176-131-220-199.abo.bbox.fr. [176.131.220.199]) by smtp.gmail.com with ESMTPSA id h16-20020a05600004d000b0032dbf99bf4fsm9290025wri.89.2023.11.06.03.08.10 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:08:13 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Ani Sinha , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Marcel Apfelbaum , Yanan Wang , Laurent Vivier , David Hildenbrand , Thomas Huth , Ilya Leoshkevich Subject: [PULL 40/60] hw/cpu: Clean up global variable shadowing Date: Mon, 6 Nov 2023 12:03:12 +0100 Message-ID: <20231106110336.358-41-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Fix: hw/core/machine.c:1302:22: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] const CPUArchId *cpus = possible_cpus->cpus; ^ hw/core/numa.c:69:17: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] uint16List *cpus = NULL; ^ hw/acpi/aml-build.c:2005:20: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] CPUArchIdList *cpus = ms->possible_cpus; ^ hw/core/machine-smp.c:77:14: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] unsigned cpus = config->has_cpus ? config->cpus : 0; ^ include/hw/core/cpu.h:589:17: note: previous declaration is here extern CPUTailQ cpus; ^ Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Ani Sinha Message-Id: <20231010115048.11856-2-philmd@linaro.org> --- include/hw/core/cpu.h | 8 ++++---- cpu-common.c | 6 +++--- linux-user/main.c | 2 +- target/s390x/cpu_models.c | 2 +- 4 files changed, 9 insertions(+), 9 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index eb943efb8f..77893d7b81 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -586,13 +586,13 @@ static inline CPUArchState *cpu_env(CPUState *cpu) } typedef QTAILQ_HEAD(CPUTailQ, CPUState) CPUTailQ; -extern CPUTailQ cpus; +extern CPUTailQ cpus_queue; -#define first_cpu QTAILQ_FIRST_RCU(&cpus) +#define first_cpu QTAILQ_FIRST_RCU(&cpus_queue) #define CPU_NEXT(cpu) QTAILQ_NEXT_RCU(cpu, node) -#define CPU_FOREACH(cpu) QTAILQ_FOREACH_RCU(cpu, &cpus, node) +#define CPU_FOREACH(cpu) QTAILQ_FOREACH_RCU(cpu, &cpus_queue, node) #define CPU_FOREACH_SAFE(cpu, next_cpu) \ - QTAILQ_FOREACH_SAFE_RCU(cpu, &cpus, node, next_cpu) + QTAILQ_FOREACH_SAFE_RCU(cpu, &cpus_queue, node, next_cpu) extern __thread CPUState *current_cpu; diff --git a/cpu-common.c b/cpu-common.c index 45c745ecf6..c81fd72d16 100644 --- a/cpu-common.c +++ b/cpu-common.c @@ -73,7 +73,7 @@ static int cpu_get_free_index(void) return max_cpu_index; } -CPUTailQ cpus = QTAILQ_HEAD_INITIALIZER(cpus); +CPUTailQ cpus_queue = QTAILQ_HEAD_INITIALIZER(cpus_queue); static unsigned int cpu_list_generation_id; unsigned int cpu_list_generation_id_get(void) @@ -90,7 +90,7 @@ void cpu_list_add(CPUState *cpu) } else { assert(!cpu_index_auto_assigned); } - QTAILQ_INSERT_TAIL_RCU(&cpus, cpu, node); + QTAILQ_INSERT_TAIL_RCU(&cpus_queue, cpu, node); cpu_list_generation_id++; } @@ -102,7 +102,7 @@ void cpu_list_remove(CPUState *cpu) return; } - QTAILQ_REMOVE_RCU(&cpus, cpu, node); + QTAILQ_REMOVE_RCU(&cpus_queue, cpu, node); cpu->cpu_index = UNASSIGNED_CPU_INDEX; cpu_list_generation_id++; } diff --git a/linux-user/main.c b/linux-user/main.c index 0c23584a96..0cdaf30d34 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -156,7 +156,7 @@ void fork_end(int child) Discard information about the parent threads. */ CPU_FOREACH_SAFE(cpu, next_cpu) { if (cpu != thread_cpu) { - QTAILQ_REMOVE_RCU(&cpus, cpu, node); + QTAILQ_REMOVE_RCU(&cpus_queue, cpu, node); } } qemu_init_cpu_list(); diff --git a/target/s390x/cpu_models.c b/target/s390x/cpu_models.c index 4dead48650..5c455d00c0 100644 --- a/target/s390x/cpu_models.c +++ b/target/s390x/cpu_models.c @@ -757,7 +757,7 @@ void s390_set_qemu_cpu_model(uint16_t type, uint8_t gen, uint8_t ec_ga, const S390CPUDef *def = s390_find_cpu_def(type, gen, ec_ga, NULL); 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id j19-20020a05600c1c1300b004060f0a0fd5sm11862251wms.13.2023.11.06.03.08.18 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:08:20 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Ani Sinha Subject: [PULL 41/60] hw/loader: Clean up global variable shadowing in rom_add_file() Date: Mon, 6 Nov 2023 12:03:13 +0100 Message-ID: <20231106110336.358-42-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Fix: hw/core/loader.c:1073:27: error: declaration shadows a variable in the global scope [-Werror,-Wshadow] bool option_rom, MemoryRegion *mr, ^ include/sysemu/sysemu.h:57:22: note: previous declaration is here extern QEMUOptionRom option_rom[MAX_OPTION_ROMS]; ^ Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Ani Sinha Message-Id: <20231010115048.11856-3-philmd@linaro.org> --- include/hw/loader.h | 2 +- hw/core/loader.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/include/hw/loader.h b/include/hw/loader.h index c4c14170ea..8685e27334 100644 --- a/include/hw/loader.h +++ b/include/hw/loader.h @@ -272,7 +272,7 @@ void pstrcpy_targphys(const char *name, ssize_t rom_add_file(const char *file, const char *fw_dir, hwaddr addr, int32_t bootindex, - bool option_rom, MemoryRegion *mr, AddressSpace *as); + bool has_option_rom, MemoryRegion *mr, AddressSpace *as); MemoryRegion *rom_add_blob(const char *name, const void *blob, size_t len, size_t max_len, hwaddr addr, const char *fw_file_name, diff --git a/hw/core/loader.c b/hw/core/loader.c index 4dd5a71fb7..7f0cbfb214 100644 --- a/hw/core/loader.c +++ b/hw/core/loader.c @@ -1070,7 +1070,7 @@ static void *rom_set_mr(Rom *rom, Object *owner, const char *name, bool ro) ssize_t rom_add_file(const char *file, const char *fw_dir, hwaddr addr, int32_t bootindex, - bool option_rom, MemoryRegion *mr, + bool has_option_rom, MemoryRegion *mr, AddressSpace *as) { MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); @@ -1139,7 +1139,7 @@ ssize_t rom_add_file(const char *file, const char *fw_dir, basename); snprintf(devpath, sizeof(devpath), "/rom@%s", fw_file_name); - if ((!option_rom || mc->option_rom_has_mr) && mc->rom_file_has_mr) { + if ((!has_option_rom || mc->option_rom_has_mr) && mc->rom_file_has_mr) { data = rom_set_mr(rom, OBJECT(fw_cfg), devpath, true); } else { data = rom->data; From patchwork Mon Nov 6 11:03:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13446667 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4467C182DF for ; Mon, 6 Nov 2023 11:08:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="MfJs3QM8" Received: from mail-wm1-x332.google.com (mail-wm1-x332.google.com [IPv6:2a00:1450:4864:20::332]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 31B3798 for ; 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id m1-20020a056000180100b0031980783d78sm9136370wrh.54.2023.11.06.03.08.24 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:08:26 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Bernhard Beschow , Markus Armbruster , Richard Henderson , =?utf-8?q?Herv=C3=A9_Pous?= =?utf-8?q?sineau?= Subject: [PULL 42/60] hw/isa/i82378: Propagate error if PC_SPEAKER device creation failed Date: Mon, 6 Nov 2023 12:03:14 +0100 Message-ID: <20231106110336.358-43-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 In commit 40f8214fcd ("hw/audio/pcspk: Inline pcspk_init()") we neglected to give a change to the caller to handle failed device creation cleanly. Respect the caller API contract and propagate the error if creating the PC_SPEAKER device ever failed. This avoid yet another bad API use to be taken as example and copy / pasted all over the code base. Reported-by: Bernhard Beschow Suggested-by: Markus Armbruster Reviewed-by: Richard Henderson Reviewed-by: Bernhard Beschow Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20231020171509.87839-5-philmd@linaro.org> --- hw/isa/i82378.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/isa/i82378.c b/hw/isa/i82378.c index 79ffbb52a0..203b92c264 100644 --- a/hw/isa/i82378.c +++ b/hw/isa/i82378.c @@ -105,7 +105,9 @@ static void i82378_realize(PCIDevice *pci, Error **errp) /* speaker */ pcspk = isa_new(TYPE_PC_SPEAKER); object_property_set_link(OBJECT(pcspk), "pit", OBJECT(pit), &error_fatal); - isa_realize_and_unref(pcspk, isabus, &error_fatal); + if (!isa_realize_and_unref(pcspk, isabus, errp)) { + return; + } /* 2 82C37 (dma) */ isa_create_simple(isabus, "i82374"); From patchwork Mon Nov 6 11:03:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13446668 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2F53718C07 for ; Mon, 6 Nov 2023 11:08:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="OisbtFhg" Received: from mail-lf1-x12a.google.com (mail-lf1-x12a.google.com [IPv6:2a00:1450:4864:20::12a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 377F6B0 for ; Mon, 6 Nov 2023 03:08:35 -0800 (PST) Received: by mail-lf1-x12a.google.com with SMTP id 2adb3069b0e04-50939d39d0fso5615044e87.1 for ; Mon, 06 Nov 2023 03:08:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699268913; x=1699873713; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pKMRzxqRYnKl/hVlIV0E2OCjWVD0Ib40S0FzpaLqDMw=; b=OisbtFhgpMccEZi6GLYef7ecz1L3U/ERrOrIJJbeMlq06wL3dvDnSvnlencODy0+px Fhea6at7yz3YOefwp6ErKRQ0Oon7g3q12h04liCdt4hdMisV6U+z6tG1mxtH6qQGoB8j K3TL1A5IYCX8wvdMiU844ZjbhYMuEC/XYO24+DeYGf302f2ax3qWs7MUoc8iNoanfElu lYSo3gF0PN+Qzr6IuNypMR7bJQho9feiKE+n/JhLehz7gBshX0uBGJ9HcDTNCCSVR55n jWq/vBTx9B2l0FUmWYs7tv+A8ZDCnra7xo26b8akheyQJdBClq0PNBoPLAs+aFELVKzd 25jA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699268913; x=1699873713; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pKMRzxqRYnKl/hVlIV0E2OCjWVD0Ib40S0FzpaLqDMw=; b=gy4SUjjGSeHfaTyVnQHidDiKHmjN/2og+bow/4knw243Q1GobSLaeuJupGJpCIjyHm QduUxGtnw6NWq3vgXLoTZxZ4Hh1Kt7RPFKWhgMck2+ogTdapn5N9+SyFlyV1t3TNrFTX jq2Skzy1ZK1A1J899P8HGJ+Et5EdPxpNgBcoLWGNEzqFkJaiFuvFqt0+wn0xckQkDuHd GV9hn51GtT0Uyag2ArQUWDIas0BQ4NVKGQBFMgvfpEO2lzDD1LsDIAYkgA19heaNa3v8 5Olm89gLn/oSHFTU6aDdE9qa968WE50fIW0i6R0/C0Ob/Ii/QvmW/JnkSyVR+yUdEZGX U3sw== X-Gm-Message-State: AOJu0Yz2R1I6igw51djbxxNV41KO3Bfchlzv8OArrAHUdVFrofg87rxw wZIhKWYBDPAbSRfn2ofA9ObJ4g== X-Google-Smtp-Source: AGHT+IGMI9IHWBGUOo6/TSzJ7f5lWu5csZyUwrcaXQuq2CyxKG8+98G9h0M8RSeKlrf4DHh1XI1+uQ== X-Received: by 2002:ac2:5e6d:0:b0:504:4165:54ab with SMTP id a13-20020ac25e6d000000b00504416554abmr19292506lfr.56.1699268913486; Mon, 06 Nov 2023 03:08:33 -0800 (PST) Received: from m1x-phil.lan (176-131-220-199.abo.bbox.fr. [176.131.220.199]) by smtp.gmail.com with ESMTPSA id k8-20020a05600c1c8800b004081a011c0esm11883242wms.12.2023.11.06.03.08.31 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:08:33 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Zhao Liu , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Yanan Wang , Xiaoyao Li , Babu Moger , Yongwei Ma , "Michael S . Tsirkin" , Marcel Apfelbaum Subject: [PULL 43/60] hw/i386: Fix comment style in topology.h Date: Mon, 6 Nov 2023 12:03:15 +0100 Message-ID: <20231106110336.358-44-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Zhao Liu For function comments in this file, keep the comment style consistent with other files in the directory. Signed-off-by: Zhao Liu Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Yanan Wang Reviewed-by: Xiaoyao Li Reviewed-by: Babu Moger Tested-by: Babu Moger Tested-by: Yongwei Ma Acked-by: Michael S. Tsirkin Message-ID: <20231024090323.1859210-2-zhao1.liu@linux.intel.com> Signed-off-by: Philippe Mathieu-Daudé --- include/hw/i386/topology.h | 33 +++++++++++++++++---------------- 1 file changed, 17 insertions(+), 16 deletions(-) diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h index 380cb27ded..d4eeb7ab82 100644 --- a/include/hw/i386/topology.h +++ b/include/hw/i386/topology.h @@ -24,7 +24,8 @@ #ifndef HW_I386_TOPOLOGY_H #define HW_I386_TOPOLOGY_H -/* This file implements the APIC-ID-based CPU topology enumeration logic, +/* + * This file implements the APIC-ID-based CPU topology enumeration logic, * documented at the following document: * Intel® 64 Architecture Processor Topology Enumeration * http://software.intel.com/en-us/articles/intel-64-architecture-processor-topology-enumeration/ @@ -41,7 +42,8 @@ #include "qemu/bitops.h" -/* APIC IDs can be 32-bit, but beware: APIC IDs > 255 require x2APIC support +/* + * APIC IDs can be 32-bit, but beware: APIC IDs > 255 require x2APIC support */ typedef uint32_t apic_id_t; @@ -58,8 +60,7 @@ typedef struct X86CPUTopoInfo { unsigned threads_per_core; } X86CPUTopoInfo; -/* Return the bit width needed for 'count' IDs - */ +/* Return the bit width needed for 'count' IDs */ static unsigned apicid_bitwidth_for_count(unsigned count) { g_assert(count >= 1); @@ -67,15 +68,13 @@ static unsigned apicid_bitwidth_for_count(unsigned count) return count ? 32 - clz32(count) : 0; } -/* Bit width of the SMT_ID (thread ID) field on the APIC ID - */ +/* Bit width of the SMT_ID (thread ID) field on the APIC ID */ static inline unsigned apicid_smt_width(X86CPUTopoInfo *topo_info) { return apicid_bitwidth_for_count(topo_info->threads_per_core); } -/* Bit width of the Core_ID field - */ +/* Bit width of the Core_ID field */ static inline unsigned apicid_core_width(X86CPUTopoInfo *topo_info) { return apicid_bitwidth_for_count(topo_info->cores_per_die); @@ -87,8 +86,7 @@ static inline unsigned apicid_die_width(X86CPUTopoInfo *topo_info) return apicid_bitwidth_for_count(topo_info->dies_per_pkg); } -/* Bit offset of the Core_ID field - */ +/* Bit offset of the Core_ID field */ static inline unsigned apicid_core_offset(X86CPUTopoInfo *topo_info) { return apicid_smt_width(topo_info); @@ -100,14 +98,14 @@ static inline unsigned apicid_die_offset(X86CPUTopoInfo *topo_info) return apicid_core_offset(topo_info) + apicid_core_width(topo_info); } -/* Bit offset of the Pkg_ID (socket ID) field - */ +/* Bit offset of the Pkg_ID (socket ID) field */ static inline unsigned apicid_pkg_offset(X86CPUTopoInfo *topo_info) { return apicid_die_offset(topo_info) + apicid_die_width(topo_info); } -/* Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID +/* + * Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID * * The caller must make sure core_id < nr_cores and smt_id < nr_threads. */ @@ -120,7 +118,8 @@ static inline apic_id_t x86_apicid_from_topo_ids(X86CPUTopoInfo *topo_info, topo_ids->smt_id; } -/* Calculate thread/core/package IDs for a specific topology, +/* + * Calculate thread/core/package IDs for a specific topology, * based on (contiguous) CPU index */ static inline void x86_topo_ids_from_idx(X86CPUTopoInfo *topo_info, @@ -137,7 +136,8 @@ static inline void x86_topo_ids_from_idx(X86CPUTopoInfo *topo_info, topo_ids->smt_id = cpu_index % nr_threads; } -/* Calculate thread/core/package IDs for a specific topology, +/* + * Calculate thread/core/package IDs for a specific topology, * based on APIC ID */ static inline void x86_topo_ids_from_apicid(apic_id_t apicid, @@ -155,7 +155,8 @@ static inline void x86_topo_ids_from_apicid(apic_id_t apicid, topo_ids->pkg_id = apicid >> apicid_pkg_offset(topo_info); } -/* Make APIC ID for the CPU 'cpu_index' +/* + * Make APIC ID for the CPU 'cpu_index' * * 'cpu_index' is a sequential, contiguous ID for the CPU. */ From patchwork Mon Nov 6 11:03:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13446669 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5576C1A591 for ; Mon, 6 Nov 2023 11:08:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id u7-20020a05600c138700b0040836519dd9sm11912962wmf.25.2023.11.06.03.08.38 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:08:40 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Zhao Liu , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Babu Moger , Yongwei Ma , "Michael S . Tsirkin" , Thomas Huth , Marcel Apfelbaum Subject: [PULL 44/60] tests/unit: Rename test-x86-cpuid.c to test-x86-topo.c Date: Mon, 6 Nov 2023 12:03:16 +0100 Message-ID: <20231106110336.358-45-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Zhao Liu The tests in this file actually test the APIC ID combinations. Rename to test-x86-topo.c to make its name more in line with its actual content. Signed-off-by: Zhao Liu Reviewed-by: Philippe Mathieu-Daudé Tested-by: Babu Moger Tested-by: Yongwei Ma Acked-by: Michael S. Tsirkin Reviewed-by: Thomas Huth Message-ID: <20231024090323.1859210-3-zhao1.liu@linux.intel.com> Signed-off-by: Philippe Mathieu-Daudé --- MAINTAINERS | 2 +- tests/unit/{test-x86-cpuid.c => test-x86-topo.c} | 2 +- tests/unit/meson.build | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) rename tests/unit/{test-x86-cpuid.c => test-x86-topo.c} (99%) diff --git a/MAINTAINERS b/MAINTAINERS index 8e8a7d5be5..126cddd285 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1772,7 +1772,7 @@ F: include/hw/southbridge/ich9.h F: include/hw/southbridge/piix.h F: hw/isa/apm.c F: include/hw/isa/apm.h -F: tests/unit/test-x86-cpuid.c +F: tests/unit/test-x86-topo.c F: tests/qtest/test-x86-cpuid-compat.c PC Chipset diff --git a/tests/unit/test-x86-cpuid.c b/tests/unit/test-x86-topo.c similarity index 99% rename from tests/unit/test-x86-cpuid.c rename to tests/unit/test-x86-topo.c index bfabc0403a..2b104f86d7 100644 --- a/tests/unit/test-x86-cpuid.c +++ b/tests/unit/test-x86-topo.c @@ -1,5 +1,5 @@ /* - * Test code for x86 CPUID and Topology functions + * Test code for x86 APIC ID and Topology functions * * Copyright (c) 2012 Red Hat Inc. * diff --git a/tests/unit/meson.build b/tests/unit/meson.build index f33ae64b8d..0dbe32ba9b 100644 --- a/tests/unit/meson.build +++ b/tests/unit/meson.build @@ -21,8 +21,8 @@ tests = { 'test-opts-visitor': [testqapi], 'test-visitor-serialization': [testqapi], 'test-bitmap': [], - # all code tested by test-x86-cpuid is inside topology.h - 'test-x86-cpuid': [], + # all code tested by test-x86-topo is inside topology.h + 'test-x86-topo': [], 'test-cutils': [], 'test-div128': [], 'test-shift128': [], From patchwork Mon Nov 6 11:03:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13446670 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AD35E171D7 for ; Mon, 6 Nov 2023 11:08:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="NQkBWiDI" Received: from mail-wr1-x42b.google.com (mail-wr1-x42b.google.com [IPv6:2a00:1450:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EB2DF98 for ; Mon, 6 Nov 2023 03:08:48 -0800 (PST) Received: by mail-wr1-x42b.google.com with SMTP id ffacd0b85a97d-32fbf271346so1513829f8f.1 for ; Mon, 06 Nov 2023 03:08:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699268927; x=1699873727; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0yFelocR66jYXowauowrhR0mUeB3U99cidSOqtYw+Cg=; b=NQkBWiDIgicR1gWykWuId+4C8SxhjMrGR4qCpB7TKKogEbNsS+2WWbZc4AWUw/aRjC E0/7Z2a6GaGTJxhb5weYsz2VNlksbyDLSt/My6UL5GF8EJdXTKezUQ06PojJMC2N+ZWW Vjlfe8EufcXSUzO2Bups1tFG9U4X5ncHunwsaiiqozzn9+GbkN5Oe11u7Ywkllb8q68j A/tiqe6WAkLL2PflUj/5QfWtRB7XwYu7ZXb37IQ08PbuzAvpBcnDbNtSD4+Z5OSx6/2f 67NGQDDSlxq3vXhoWzoj9lLYdvBtEsMXyp8VfwzgFnESgX+Z2qMFfgbsEsG/mI4PNIeb xE5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699268927; x=1699873727; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0yFelocR66jYXowauowrhR0mUeB3U99cidSOqtYw+Cg=; b=biDt5vuqboG91cQEOLbVt95EBk6ph0NJrfAS1Y4EDJfdRDScJmkxdfhALydZLU9BWT 7ykzc9JRoJlJDUPaw1u0jqA+RyQ2UYrUlrKpQcjLlFWYXK++fvBGcoMLOPsC40xzrwZl pc9EtAZ9q2dPSBVKXiyl7+NJJQ0oj8YR1k9/Dx10VugREiF0256xB4Ph0HG3xMmP/Nn1 Z3hXSWHeksCYNSqdCUdvY5WcuhcyOdW1qIao9O4+DCefoYBVUZiF9FlEY+XvqvJ6uTRh bIzxCDIpBHjUGUWVhDNIl520aVzSieDTZnLLUydM/Jzwh7Tdr3wmvaZYGC7+QiZoHX2x CnJQ== X-Gm-Message-State: AOJu0YyC8RSHbaaHsF0t8SAIZcoFjG9+DM3aaErlNiVkUZdrnAJ5rVvr inhX1lwxVaGOHmsAh6rFFexlxw== X-Google-Smtp-Source: AGHT+IGgL0F1g9v6gQaqWqalE046qIpD1vXiY6eu81D5A7cfp1tnEC2cOxrnm8DtADlNcX3GEcp3bw== X-Received: by 2002:a5d:6c6f:0:b0:32f:8085:7411 with SMTP id r15-20020a5d6c6f000000b0032f80857411mr21345810wrz.24.1699268927044; Mon, 06 Nov 2023 03:08:47 -0800 (PST) Received: from m1x-phil.lan (176-131-220-199.abo.bbox.fr. [176.131.220.199]) by smtp.gmail.com with ESMTPSA id g8-20020a5d4888000000b0032f7cc56509sm1544640wrq.98.2023.11.06.03.08.44 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:08:46 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Zhuocheng Ding , Zhao Liu , Babu Moger , Yongwei Ma , "Michael S . Tsirkin" , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Paolo Bonzini , Richard Henderson Subject: [PULL 45/60] system/cpus: Fix CPUState.nr_cores' calculation Date: Mon, 6 Nov 2023 12:03:17 +0100 Message-ID: <20231106110336.358-46-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Zhuocheng Ding From CPUState.nr_cores' comment, it represents "number of cores within this CPU package". After 003f230e37d7 ("machine: Tweak the order of topology members in struct CpuTopology"), the meaning of smp.cores changed to "the number of cores in one die", but this commit missed to change CPUState.nr_cores' calculation, so that CPUState.nr_cores became wrong and now it misses to consider numbers of clusters and dies. At present, only i386 is using CPUState.nr_cores. But as for i386, which supports die level, the uses of CPUState.nr_cores are very confusing: Early uses are based on the meaning of "cores per package" (before die is introduced into i386), and later uses are based on "cores per die" (after die's introduction). This difference is due to that commit a94e1428991f ("target/i386: Add CPUID.1F generation support for multi-dies PCMachine") misunderstood that CPUState.nr_cores means "cores per die" when calculated CPUID.1FH.01H:EBX. After that, the changes in i386 all followed this wrong understanding. With the influence of 003f230e37d7 and a94e1428991f, for i386 currently the result of CPUState.nr_cores is "cores per die", thus the original uses of CPUState.cores based on the meaning of "cores per package" are wrong when multiple dies exist: 1. In cpu_x86_cpuid() of target/i386/cpu.c, CPUID.01H:EBX[bits 23:16] is incorrect because it expects "cpus per package" but now the result is "cpus per die". 2. In cpu_x86_cpuid() of target/i386/cpu.c, for all leaves of CPUID.04H: EAX[bits 31:26] is incorrect because they expect "cpus per package" but now the result is "cpus per die". The error not only impacts the EAX calculation in cache_info_passthrough case, but also impacts other cases of setting cache topology for Intel CPU according to cpu topology (specifically, the incoming parameter "num_cores" expects "cores per package" in encode_cache_cpuid4()). 3. In cpu_x86_cpuid() of target/i386/cpu.c, CPUID.0BH.01H:EBX[bits 15:00] is incorrect because the EBX of 0BH.01H (core level) expects "cpus per package", which may be different with 1FH.01H (The reason is 1FH can support more levels. For QEMU, 1FH also supports die, 1FH.01H:EBX[bits 15:00] expects "cpus per die"). 4. In cpu_x86_cpuid() of target/i386/cpu.c, when CPUID.80000001H is calculated, here "cpus per package" is expected to be checked, but in fact, now it checks "cpus per die". Though "cpus per die" also works for this code logic, this isn't consistent with AMD's APM. 5. In cpu_x86_cpuid() of target/i386/cpu.c, CPUID.80000008H:ECX expects "cpus per package" but it obtains "cpus per die". 6. In simulate_rdmsr() of target/i386/hvf/x86_emu.c, in kvm_rdmsr_core_thread_count() of target/i386/kvm/kvm.c, and in helper_rdmsr() of target/i386/tcg/sysemu/misc_helper.c, MSR_CORE_THREAD_COUNT expects "cpus per package" and "cores per package", but in these functions, it obtains "cpus per die" and "cores per die". On the other hand, these uses are correct now (they are added in/after a94e1428991f): 1. In cpu_x86_cpuid() of target/i386/cpu.c, topo_info.cores_per_die meets the actual meaning of CPUState.nr_cores ("cores per die"). 2. In cpu_x86_cpuid() of target/i386/cpu.c, vcpus_per_socket (in CPUID. 04H's calculation) considers number of dies, so it's correct. 3. In cpu_x86_cpuid() of target/i386/cpu.c, CPUID.1FH.01H:EBX[bits 15:00] needs "cpus per die" and it gets the correct result, and CPUID.1FH.02H:EBX[bits 15:00] gets correct "cpus per package". When CPUState.nr_cores is correctly changed to "cores per package" again , the above errors will be fixed without extra work, but the "currently" correct cases will go wrong and need special handling to pass correct "cpus/cores per die" they want. Fix CPUState.nr_cores' calculation to fit the original meaning "cores per package", as well as changing calculation of topo_info.cores_per_die, vcpus_per_socket and CPUID.1FH. Fixes: a94e1428991f ("target/i386: Add CPUID.1F generation support for multi-dies PCMachine") Fixes: 003f230e37d7 ("machine: Tweak the order of topology members in struct CpuTopology") Signed-off-by: Zhuocheng Ding Co-developed-by: Zhao Liu Signed-off-by: Zhao Liu Tested-by: Babu Moger Tested-by: Yongwei Ma Acked-by: Michael S. Tsirkin Message-ID: <20231024090323.1859210-4-zhao1.liu@linux.intel.com> Signed-off-by: Philippe Mathieu-Daudé --- system/cpus.c | 2 +- target/i386/cpu.c | 9 ++++----- 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/system/cpus.c b/system/cpus.c index 952f15868c..a444a747f0 100644 --- a/system/cpus.c +++ b/system/cpus.c @@ -631,7 +631,7 @@ void qemu_init_vcpu(CPUState *cpu) { MachineState *ms = MACHINE(qdev_get_machine()); - cpu->nr_cores = ms->smp.cores; + cpu->nr_cores = machine_topo_get_cores_per_socket(ms); cpu->nr_threads = ms->smp.threads; cpu->stopped = true; cpu->random_seed = qemu_guest_random_seed_thread_part1(); diff --git a/target/i386/cpu.c b/target/i386/cpu.c index fc8484cb5e..358d9c0a65 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6019,7 +6019,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, X86CPUTopoInfo topo_info; topo_info.dies_per_pkg = env->nr_dies; - topo_info.cores_per_die = cs->nr_cores; + topo_info.cores_per_die = cs->nr_cores / env->nr_dies; topo_info.threads_per_core = cs->nr_threads; /* Calculate & apply limits for different index ranges */ @@ -6095,8 +6095,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, */ if (*eax & 31) { int host_vcpus_per_cache = 1 + ((*eax & 0x3FFC000) >> 14); - int vcpus_per_socket = env->nr_dies * cs->nr_cores * - cs->nr_threads; + int vcpus_per_socket = cs->nr_cores * cs->nr_threads; if (cs->nr_cores > 1) { *eax &= ~0xFC000000; *eax |= (pow2ceil(cs->nr_cores) - 1) << 26; @@ -6273,12 +6272,12 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, break; case 1: *eax = apicid_die_offset(&topo_info); - *ebx = cs->nr_cores * cs->nr_threads; + *ebx = topo_info.cores_per_die * topo_info.threads_per_core; *ecx |= CPUID_TOPOLOGY_LEVEL_CORE; break; case 2: *eax = apicid_pkg_offset(&topo_info); - *ebx = env->nr_dies * cs->nr_cores * cs->nr_threads; + *ebx = cs->nr_cores * cs->nr_threads; *ecx |= CPUID_TOPOLOGY_LEVEL_DIE; break; default: From patchwork Mon Nov 6 11:03:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13446671 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9240718AE4 for ; Mon, 6 Nov 2023 11:08:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="CkQ8+o90" Received: from mail-lj1-x233.google.com (mail-lj1-x233.google.com [IPv6:2a00:1450:4864:20::233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 63944BE for ; Mon, 6 Nov 2023 03:08:55 -0800 (PST) Received: by mail-lj1-x233.google.com with SMTP id 38308e7fff4ca-2c6ed1b9a1cso58270251fa.3 for ; Mon, 06 Nov 2023 03:08:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699268933; x=1699873733; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GYvSXfF+xbSSjVZB+VdYev9ZdU+Lgrd51drrmwgB968=; b=CkQ8+o90NA2u6JPpvKczDywY7M8BOWYlaSBORGMurJ+6MmTCZhU1OuftboX5QmrcQq xdzdu0AxOS4W2l7h8D6sHWj43YNGLlYUQdFgx4ZYf8es/ppkRNeYoQhIzh8Esyrw9Pqs /SzWW3Ya08Ne4UXlR0atk9ckrBem9RrfLd8ljgcdhlUwrHtjf2XcdYkt/GuswMrujN5J ufflOzaTd3nqIBmRc5HcT/ItsaWz9h4ZHcrEXB3Uiigm53YxcugoXL2Y+WrUBzCo9xW/ SKRFdNYD/DuSY1Fz6Nygo763HxQ+LXpXgJEN7CsP5ioGVBquiYyFHWZ9zk8LNlxO6GTB glew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699268933; x=1699873733; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GYvSXfF+xbSSjVZB+VdYev9ZdU+Lgrd51drrmwgB968=; b=PAdTctFTWQhzOZgmODDHacX4ds1I3YRXd0hoyc4VHJk6z8mzahRpmaaAEDq2QwQrko +7FT32nKrEwZgTdzsD3A9YxZdcSBe5AFptV9+mRJ0dgkUZLubOCg/fa/wbyOnbMB54qI z843GeoabzdbkXCQV0Wyv9mwUrJ6zjtX6cD/CJaYwrUaO9rMYGDAIU7rV5TBVYQ6bZec 34jDjyHgI6N0L8Z3X1h7PS1r2KPLAl41k2kTlSjVnG90mz+R28ZVJCtPgjDpljkMdSZj o5mkiu59ZZvCiOH033MI/pPD5eOKt60vT+h1dOnOW5uD48Sij2M9iopFj6hl5HXjeras 0UDg== X-Gm-Message-State: AOJu0YxA97a0R4HAkBew9e/vAPyqnPBTnlPvA3gQkUWph5Tjg73SGpRI pwpjv0ii4W6SugtSM/WpL0Zryw== X-Google-Smtp-Source: AGHT+IF/xZcrKq/LJLj9ohahw7rIxBUK2ed8EiXaUmWnZkVh+fy3szTtE+BCuI465Mb1P6JS3uEWwQ== X-Received: by 2002:a2e:7a17:0:b0:2c2:a337:5ea with SMTP id v23-20020a2e7a17000000b002c2a33705eamr22917103ljc.27.1699268933639; Mon, 06 Nov 2023 03:08:53 -0800 (PST) Received: from m1x-phil.lan (176-131-220-199.abo.bbox.fr. [176.131.220.199]) by smtp.gmail.com with ESMTPSA id h15-20020a5d688f000000b0032f9688ea48sm9121553wru.10.2023.11.06.03.08.51 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:08:53 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Zhao Liu , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Babu Moger , Yongwei Ma , "Michael S . Tsirkin" , Eduardo Habkost , Marcel Apfelbaum , Yanan Wang Subject: [PULL 46/60] hw/cpu: Update the comments of nr_cores and nr_dies Date: Mon, 6 Nov 2023 12:03:18 +0100 Message-ID: <20231106110336.358-47-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Zhao Liu In the nr_threads' comment, specify it represents the number of threads in the "core" to avoid confusion. Also add comment for nr_dies in CPUX86State. Signed-off-by: Zhao Liu Reviewed-by: Philippe Mathieu-Daudé Tested-by: Babu Moger Tested-by: Yongwei Ma Acked-by: Michael S. Tsirkin Message-ID: <20231024090323.1859210-5-zhao1.liu@linux.intel.com> Signed-off-by: Philippe Mathieu-Daudé --- include/hw/core/cpu.h | 2 +- target/i386/cpu.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 77893d7b81..c0c8320413 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -408,7 +408,7 @@ struct qemu_work_item; * See TranslationBlock::TCG CF_CLUSTER_MASK. * @tcg_cflags: Pre-computed cflags for this cpu. * @nr_cores: Number of cores within this CPU package. - * @nr_threads: Number of threads within this CPU. + * @nr_threads: Number of threads within this CPU core. * @running: #true if CPU is currently running (lockless). * @has_waiter: #true if a CPU is currently waiting for the cpu_exec_end; * valid under cpu_list_lock. diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 6c6b066986..b60a417074 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1882,6 +1882,7 @@ typedef struct CPUArchState { TPRAccess tpr_access_type; + /* Number of dies within this CPU package. */ unsigned nr_dies; } CPUX86State; From patchwork Mon Nov 6 11:03:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13446672 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 08D3218E05 for ; Mon, 6 Nov 2023 11:09:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="Qyd27gcY" Received: from mail-wr1-x436.google.com (mail-wr1-x436.google.com [IPv6:2a00:1450:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C4DD4FA for ; Mon, 6 Nov 2023 03:09:01 -0800 (PST) Received: by mail-wr1-x436.google.com with SMTP id ffacd0b85a97d-32d849cc152so3001768f8f.1 for ; Mon, 06 Nov 2023 03:09:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699268940; x=1699873740; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=l0/vWnFHt+cyNHMvzu2dssx7xYyn6IEpyeIo7MQjzWQ=; b=Qyd27gcYpUAX33VuD3V60EEg/WXc1kq2QYg5IXwR+c3PfBhsU7glBHDKlepNdhJSf5 sVAR02LIRRvMd8eX247VxwFXjpaYUfiU+QBqZ8YVQs1OrNxV45n/JJvCcBVe+KCwSWjW i1rqy0EIYq+4n0FuB03lJVY4qc+sEJH3ftifVZKEwM+FepjRBenX22qQ4PwDHnw6D2b6 u1FNKcVZnuX/bYk2kLBcUylV8mRNLvDaDECsfx56rMfPtxPt9NqHUVj8yckPspjh/OxP k2IqMsMsBhnDqhn/ksScJX3fXxctlNy+NUAfbY4U2wnM655XKzYiaBrT2F7MXCIyA+OV K0Qw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699268940; x=1699873740; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=l0/vWnFHt+cyNHMvzu2dssx7xYyn6IEpyeIo7MQjzWQ=; b=PecpfpG6X4R4NH4tsSzFIyzN/h+EstzDNxPsgo0E+hqhydqoMBIAm9pN9eLllM8m8A fD0exSMxlFHPtbmDz7pLUk0CYoZeA7Vpi7hHp0MDP926LdpvQQaeTU5gXiOEtM14Rcop VVV1v3RRkqr73s+mwt5wX20b/SP2rB/4tw3aArWczpT05f2xTHLYJD5cnSjpUsSzTRQL ecek0W/q1cJYN+zZqR//2ymuFouylQdb0CSiDhhikIj2kw+PLGRjuXt81XOzIKPbtnD6 Z1HQpyLsDM93GZdXQPESPYqYacQFLeL75uHP6JjPPjKH7rlL3mPfNM+c3DXwSwuXX4V9 UZUA== X-Gm-Message-State: AOJu0YymW5pGaELUN+9cSJKj3B/boRnN1iTlDsttu3czzWkqXp8FzZOd Mmz1k+OHXJjOCAkSshxxaz8q1g== X-Google-Smtp-Source: AGHT+IFsbitm3bJThRshzHVNkwv0m7bE7yeAZoRxHUIurMBc1Abgxn0QnxImhW8tuDAE+j3RuaAyCQ== X-Received: by 2002:a05:6000:1361:b0:32d:9b80:e2c6 with SMTP id q1-20020a056000136100b0032d9b80e2c6mr22417154wrz.26.1699268940275; Mon, 06 Nov 2023 03:09:00 -0800 (PST) Received: from m1x-phil.lan (176-131-220-199.abo.bbox.fr. [176.131.220.199]) by smtp.gmail.com with ESMTPSA id z18-20020adfec92000000b0032da8fb0d05sm9132494wrn.110.2023.11.06.03.08.58 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:08:59 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Fiona Ebner , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , simon.rowe@nutanix.com, John Snow Subject: [PULL 47/60] hw/ide: reset: cancel async DMA operation before resetting state Date: Mon, 6 Nov 2023 12:03:19 +0100 Message-ID: <20231106110336.358-48-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Fiona Ebner If there is a pending DMA operation during ide_bus_reset(), the fact that the IDEState is already reset before the operation is canceled can be problematic. In particular, ide_dma_cb() might be called and then use the reset IDEState which contains the signature after the reset. When used to construct the IO operation this leads to ide_get_sector() returning 0 and nsector being 1. This is particularly bad, because a write command will thus destroy the first sector which often contains a partition table or similar. Traces showing the unsolicited write happening with IDEState 0x5595af6949d0 being used after reset: > ahci_port_write ahci(0x5595af6923f0)[0]: port write [reg:PxSCTL] @ 0x2c: 0x00000300 > ahci_reset_port ahci(0x5595af6923f0)[0]: reset port > ide_reset IDEstate 0x5595af6949d0 > ide_reset IDEstate 0x5595af694da8 > ide_bus_reset_aio aio_cancel > dma_aio_cancel dbs=0x7f64600089a0 > dma_blk_cb dbs=0x7f64600089a0 ret=0 > dma_complete dbs=0x7f64600089a0 ret=0 cb=0x5595acd40b30 > ahci_populate_sglist ahci(0x5595af6923f0)[0] > ahci_dma_prepare_buf ahci(0x5595af6923f0)[0]: prepare buf limit=512 prepared=512 > ide_dma_cb IDEState 0x5595af6949d0; sector_num=0 n=1 cmd=DMA WRITE > dma_blk_io dbs=0x7f6420802010 bs=0x5595ae2c6c30 offset=0 to_dev=1 > dma_blk_cb dbs=0x7f6420802010 ret=0 > (gdb) p *qiov > $11 = {iov = 0x7f647c76d840, niov = 1, {{nalloc = 1, local_iov = {iov_base = 0x0, > iov_len = 512}}, {__pad = "\001\000\000\000\000\000\000\000\000\000\000", > size = 512}}} > (gdb) bt > #0 blk_aio_pwritev (blk=0x5595ae2c6c30, offset=0, qiov=0x7f6420802070, flags=0, > cb=0x5595ace6f0b0 , opaque=0x7f6420802010) > at ../block/block-backend.c:1682 > #1 0x00005595ace6f185 in dma_blk_cb (opaque=0x7f6420802010, ret=) > at ../softmmu/dma-helpers.c:179 > #2 0x00005595ace6f778 in dma_blk_io (ctx=0x5595ae0609f0, > sg=sg@entry=0x5595af694d00, offset=offset@entry=0, align=align@entry=512, > io_func=io_func@entry=0x5595ace6ee30 , > io_func_opaque=io_func_opaque@entry=0x5595ae2c6c30, > cb=0x5595acd40b30 , opaque=0x5595af6949d0, > dir=DMA_DIRECTION_TO_DEVICE) at ../softmmu/dma-helpers.c:244 > #3 0x00005595ace6f90a in dma_blk_write (blk=0x5595ae2c6c30, > sg=sg@entry=0x5595af694d00, offset=offset@entry=0, align=align@entry=512, > cb=cb@entry=0x5595acd40b30 , opaque=opaque@entry=0x5595af6949d0) > at ../softmmu/dma-helpers.c:280 > #4 0x00005595acd40e18 in ide_dma_cb (opaque=0x5595af6949d0, ret=) > at ../hw/ide/core.c:953 > #5 0x00005595ace6f319 in dma_complete (ret=0, dbs=0x7f64600089a0) > at ../softmmu/dma-helpers.c:107 > #6 dma_blk_cb (opaque=0x7f64600089a0, ret=0) at ../softmmu/dma-helpers.c:127 > #7 0x00005595ad12227d in blk_aio_complete (acb=0x7f6460005b10) > at ../block/block-backend.c:1527 > #8 blk_aio_complete (acb=0x7f6460005b10) at ../block/block-backend.c:1524 > #9 blk_aio_write_entry (opaque=0x7f6460005b10) at ../block/block-backend.c:1594 > #10 0x00005595ad258cfb in coroutine_trampoline (i0=, > i1=) at ../util/coroutine-ucontext.c:177 Signed-off-by: Fiona Ebner Reviewed-by: Philippe Mathieu-Daudé Tested-by: simon.rowe@nutanix.com Message-ID: <20230906130922.142845-1-f.ebner@proxmox.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/ide/core.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/hw/ide/core.c b/hw/ide/core.c index b5e0dcd29b..63ba665f3d 100644 --- a/hw/ide/core.c +++ b/hw/ide/core.c @@ -2515,19 +2515,19 @@ static void ide_dummy_transfer_stop(IDEState *s) void ide_bus_reset(IDEBus *bus) { - bus->unit = 0; - bus->cmd = 0; - ide_reset(&bus->ifs[0]); - ide_reset(&bus->ifs[1]); - ide_clear_hob(bus); - - /* pending async DMA */ + /* pending async DMA - needs the IDEState before it is reset */ if (bus->dma->aiocb) { trace_ide_bus_reset_aio(); blk_aio_cancel(bus->dma->aiocb); bus->dma->aiocb = NULL; } + bus->unit = 0; + bus->cmd = 0; + ide_reset(&bus->ifs[0]); + ide_reset(&bus->ifs[1]); + ide_clear_hob(bus); + /* reset dma provider too */ if (bus->dma->ops->reset) { bus->dma->ops->reset(bus->dma); From patchwork Mon Nov 6 11:03:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13446673 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 59B461A596 for ; Mon, 6 Nov 2023 11:09:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id j19-20020a05600c191300b004090ca6d785sm11949457wmq.2.2023.11.06.03.09.04 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:09:06 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Fiona Ebner , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , John Snow , Thomas Huth , Laurent Vivier , Paolo Bonzini Subject: [PULL 48/60] tests/qtest: ahci-test: add test exposing reset issue with pending callback Date: Mon, 6 Nov 2023 12:03:20 +0100 Message-ID: <20231106110336.358-49-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Fiona Ebner Before commit "hw/ide: reset: cancel async DMA operation before resetting state", this test would fail, because a reset with a pending write operation would lead to an unsolicited write to the first sector of the disk. The test writes a pattern to the beginning of the disk and verifies that it is still intact after a reset with a pending operation. It also checks that the pending operation actually completes correctly. Signed-off-by: Fiona Ebner Message-ID: <20230906130922.142845-2-f.ebner@proxmox.com> Signed-off-by: Philippe Mathieu-Daudé --- tests/qtest/ahci-test.c | 86 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 85 insertions(+), 1 deletion(-) diff --git a/tests/qtest/ahci-test.c b/tests/qtest/ahci-test.c index eea8b5f77b..5a1923f721 100644 --- a/tests/qtest/ahci-test.c +++ b/tests/qtest/ahci-test.c @@ -1424,6 +1424,89 @@ static void test_reset(void) ahci_shutdown(ahci); } +static void test_reset_pending_callback(void) +{ + AHCIQState *ahci; + AHCICommand *cmd; + uint8_t port; + uint64_t ptr1; + uint64_t ptr2; + + int bufsize = 4 * 1024; + int speed = bufsize + (bufsize / 2); + int offset1 = 0; + int offset2 = bufsize / AHCI_SECTOR_SIZE; + + g_autofree unsigned char *tx1 = g_malloc(bufsize); + g_autofree unsigned char *tx2 = g_malloc(bufsize); + g_autofree unsigned char *rx1 = g_malloc0(bufsize); + g_autofree unsigned char *rx2 = g_malloc0(bufsize); + + /* Uses throttling to make test independent of specific environment. */ + ahci = ahci_boot_and_enable("-drive if=none,id=drive0,file=%s," + "cache=writeback,format=%s," + "throttling.bps-write=%d " + "-M q35 " + "-device ide-hd,drive=drive0 ", + tmp_path, imgfmt, speed); + + port = ahci_port_select(ahci); + ahci_port_clear(ahci, port); + + ptr1 = ahci_alloc(ahci, bufsize); + ptr2 = ahci_alloc(ahci, bufsize); + + g_assert(ptr1 && ptr2); + + /* Need two different patterns. */ + do { + generate_pattern(tx1, bufsize, AHCI_SECTOR_SIZE); + generate_pattern(tx2, bufsize, AHCI_SECTOR_SIZE); + } while (memcmp(tx1, tx2, bufsize) == 0); + + qtest_bufwrite(ahci->parent->qts, ptr1, tx1, bufsize); + qtest_bufwrite(ahci->parent->qts, ptr2, tx2, bufsize); + + /* Write to beginning of disk to check it wasn't overwritten later. */ + ahci_guest_io(ahci, port, CMD_WRITE_DMA_EXT, ptr1, bufsize, offset1); + + /* Issue asynchronously to get a pending callback during reset. */ + cmd = ahci_command_create(CMD_WRITE_DMA_EXT); + ahci_command_adjust(cmd, offset2, ptr2, bufsize, 0); + ahci_command_commit(ahci, cmd, port); + ahci_command_issue_async(ahci, cmd); + + ahci_set(ahci, AHCI_GHC, AHCI_GHC_HR); + + ahci_command_free(cmd); + + /* Wait for throttled write to finish. */ + sleep(1); + + /* Start again. */ + ahci_clean_mem(ahci); + ahci_pci_enable(ahci); + ahci_hba_enable(ahci); + port = ahci_port_select(ahci); + ahci_port_clear(ahci, port); + + /* Read and verify. */ + ahci_guest_io(ahci, port, CMD_READ_DMA_EXT, ptr1, bufsize, offset1); + qtest_bufread(ahci->parent->qts, ptr1, rx1, bufsize); + g_assert_cmphex(memcmp(tx1, rx1, bufsize), ==, 0); + + ahci_guest_io(ahci, port, CMD_READ_DMA_EXT, ptr2, bufsize, offset2); + qtest_bufread(ahci->parent->qts, ptr2, rx2, bufsize); + g_assert_cmphex(memcmp(tx2, rx2, bufsize), ==, 0); + + ahci_free(ahci, ptr1); + ahci_free(ahci, ptr2); + + ahci_clean_mem(ahci); + + ahci_shutdown(ahci); +} + static void test_ncq_simple(void) { AHCIQState *ahci; @@ -1945,7 +2028,8 @@ int main(int argc, char **argv) qtest_add_func("/ahci/migrate/dma/halted", test_migrate_halted_dma); qtest_add_func("/ahci/max", test_max); - qtest_add_func("/ahci/reset", test_reset); + qtest_add_func("/ahci/reset/simple", test_reset); + qtest_add_func("/ahci/reset/pending_callback", test_reset_pending_callback); qtest_add_func("/ahci/io/ncq/simple", test_ncq_simple); qtest_add_func("/ahci/migrate/ncq/simple", test_migrate_ncq); From patchwork Mon Nov 6 11:03:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13446674 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 495C21A708 for ; Mon, 6 Nov 2023 11:09:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="TH8UyjV/" Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 095BBDB for ; Mon, 6 Nov 2023 03:09:15 -0800 (PST) Received: by mail-wr1-x42a.google.com with SMTP id ffacd0b85a97d-32db188e254so2655319f8f.0 for ; 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id j17-20020a056000125100b0032db4e660d9sm9181558wrx.56.2023.11.06.03.09.11 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:09:12 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Titus Rwantare , Hao Wu , Corey Minyard , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 49/60] hw/i2c: pmbus add support for block receive Date: Mon, 6 Nov 2023 12:03:21 +0100 Message-ID: <20231106110336.358-50-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Titus Rwantare PMBus devices can send and receive variable length data using the block read and write format, with the first byte in the payload denoting the length. This is mostly used for strings and on-device logs. Devices can respond to a block read with an empty string. Reviewed-by: Hao Wu Acked-by: Corey Minyard Signed-off-by: Titus Rwantare Message-ID: <20231023-staging-pmbus-v3-v4-1-07a8cb7cd20a@google.com> Signed-off-by: Philippe Mathieu-Daudé --- include/hw/i2c/pmbus_device.h | 7 +++++++ hw/i2c/pmbus_device.c | 30 +++++++++++++++++++++++++++++- 2 files changed, 36 insertions(+), 1 deletion(-) diff --git a/include/hw/i2c/pmbus_device.h b/include/hw/i2c/pmbus_device.h index 93f5d57c9d..7dc00cc4d9 100644 --- a/include/hw/i2c/pmbus_device.h +++ b/include/hw/i2c/pmbus_device.h @@ -501,6 +501,13 @@ void pmbus_send64(PMBusDevice *state, uint64_t data); */ void pmbus_send_string(PMBusDevice *state, const char *data); +/** + * @brief Receive data sent with Block Write. + * @param dest - memory with enough capacity to receive the write + * @param len - the capacity of dest + */ +uint8_t pmbus_receive_block(PMBusDevice *pmdev, uint8_t *dest, size_t len); + /** * @brief Receive data over PMBus * These methods help track how much data is being received over PMBus diff --git a/hw/i2c/pmbus_device.c b/hw/i2c/pmbus_device.c index cef51663d0..ea15490720 100644 --- a/hw/i2c/pmbus_device.c +++ b/hw/i2c/pmbus_device.c @@ -102,7 +102,6 @@ void pmbus_send_string(PMBusDevice *pmdev, const char *data) } size_t len = strlen(data); - g_assert(len > 0); g_assert(len + pmdev->out_buf_len < SMBUS_DATA_MAX_LEN); pmdev->out_buf[len + pmdev->out_buf_len] = len; @@ -112,6 +111,35 @@ void pmbus_send_string(PMBusDevice *pmdev, const char *data) pmdev->out_buf_len += len + 1; } +uint8_t pmbus_receive_block(PMBusDevice *pmdev, uint8_t *dest, size_t len) +{ + /* dest may contain data from previous writes */ + memset(dest, 0, len); + + /* Exclude command code from return value */ + pmdev->in_buf++; + pmdev->in_buf_len--; + + /* The byte after the command code denotes the length */ + uint8_t sent_len = pmdev->in_buf[0]; + + if (sent_len != pmdev->in_buf_len - 1) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: length mismatch. Expected %d bytes, got %d bytes\n", + __func__, sent_len, pmdev->in_buf_len - 1); + } + + /* exclude length byte */ + pmdev->in_buf++; + pmdev->in_buf_len--; + + if (pmdev->in_buf_len < len) { + len = pmdev->in_buf_len; + } + memcpy(dest, pmdev->in_buf, len); + return len; +} + static uint64_t pmbus_receive_uint(PMBusDevice *pmdev) { From patchwork Mon Nov 6 11:03:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13446675 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 18F5F1BDCC for ; Mon, 6 Nov 2023 11:09:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="OOe5vG9a" Received: from mail-wm1-x333.google.com (mail-wm1-x333.google.com [IPv6:2a00:1450:4864:20::333]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9FAF7FA for ; Mon, 6 Nov 2023 03:09:21 -0800 (PST) Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-40837ebba42so27346555e9.0 for ; Mon, 06 Nov 2023 03:09:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699268960; x=1699873760; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=X3TRJ7mvtWFdvHNvT+G6kpqIlBzXe7wSn3LOLdu3gVg=; b=OOe5vG9a6beO9wl2CTEWZvgsrja2Y2Fee/67KVeV3+8BholjyGgrMdjN3tT6JTOgQY CHLsIWpQzvWMnWuOr8bPfcqzsmIXFukAiIcKpmPOCkhTQHxC4Pf4FtZbWtC6Gsj2KElz ROKmE/JoGDmBIb7tWKPAXZLE/hdGsgMFBAiwmyFZcNYo7Lgi5xX/TZ3RFMpWIZF3O1OZ ks6sPp+aL8bk9v3JkfjMu3ATN6Yo7+BZqf/YFfuBAUlrzwPtcogi2X71FVw3frULq0RQ VmjqeOrnwX09H3VWzQLbdxs1FwRKgGfmrNtVse/ZdCrVQpj6n0qad3n3eTUghDttUjl8 1R2Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699268960; x=1699873760; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=X3TRJ7mvtWFdvHNvT+G6kpqIlBzXe7wSn3LOLdu3gVg=; b=KFNs+2rluSERaTVktprhKCyxllMv5QtO6mc7muvvFD0EM67aGdWwPE3tf8hmPHhczb P8+NMhKP0FbvAOFqx54/kxX7ex4q1SzduFE7e4as+zRtWuiWmaxcvbHRon4zRyGOP5KT /f1bOBsa0+5Ejb/cG58PhZVzjykBGX3zuxQng403P0kXfY2JybMlI29YWfZmqTsHhQBI ntQhXA63sMv9AlqdYh2U8TCRw3wSaU1g+2cCJZRWBH3j4DipZgUJK2J673rpvXUrv/WU 7/vy/x6zHvSacMezHrxoGa08NR9Kta2swKFBkClBJyXqWgSZj4GzM2o68+RvW4UVDeAj /3Pg== X-Gm-Message-State: AOJu0YxQ990ubCNLtBdKU37FrocJk+Z5TScfUtmfCh1uGcLjzHdBtlwg 7ohfDPAFGOcwShpdbNwoG4TeDw== X-Google-Smtp-Source: AGHT+IF/QapXB/IOwC+mPuY/wRqr3XPsG7/5YWOQ5O+CSJmVp0xQfesuPuHXWRl4QaqtoFcKAg5Pqg== X-Received: by 2002:a05:600c:46c8:b0:3ff:233f:2cfb with SMTP id q8-20020a05600c46c800b003ff233f2cfbmr23090503wmo.23.1699268960044; Mon, 06 Nov 2023 03:09:20 -0800 (PST) Received: from m1x-phil.lan (176-131-220-199.abo.bbox.fr. [176.131.220.199]) by smtp.gmail.com with ESMTPSA id t14-20020a05600c198e00b00405d9a950a2sm11977070wmq.28.2023.11.06.03.09.18 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:09:19 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Titus Rwantare , Hao Wu , Corey Minyard , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 50/60] hw/i2c: pmbus: add vout mode bitfields Date: Mon, 6 Nov 2023 12:03:22 +0100 Message-ID: <20231106110336.358-51-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Titus Rwantare The VOUT_MODE command is described in the PMBus Specification, Part II, Ver 1.3 Section 8.3 VOUT_MODE has a three bit mode and 4 bit parameter, the three bit mode determines whether voltages are formatted as uint16, uint16, VID, and Direct modes. VID and Direct modes use the remaining 5 bits to scale the voltage readings. Reviewed-by: Hao Wu Acked-by: Corey Minyard Signed-off-by: Titus Rwantare Message-ID: <20231023-staging-pmbus-v3-v4-2-07a8cb7cd20a@google.com> Signed-off-by: Philippe Mathieu-Daudé --- include/hw/i2c/pmbus_device.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/hw/i2c/pmbus_device.h b/include/hw/i2c/pmbus_device.h index 7dc00cc4d9..2e95164aa1 100644 --- a/include/hw/i2c/pmbus_device.h +++ b/include/hw/i2c/pmbus_device.h @@ -444,6 +444,14 @@ typedef struct PMBusCoefficients { int32_t R; /* exponent */ } PMBusCoefficients; +/** + * VOUT_Mode bit fields + */ +typedef struct PMBusVoutMode { + uint8_t mode:3; + int8_t exp:5; +} PMBusVoutMode; + /** * Convert sensor values to direct mode format * From patchwork Mon Nov 6 11:03:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13446676 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B065D199B3 for ; Mon, 6 Nov 2023 11:09:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="CAU5PsWJ" Received: from mail-wm1-x32a.google.com (mail-wm1-x32a.google.com [IPv6:2a00:1450:4864:20::32a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 10DF9CC for ; Mon, 6 Nov 2023 03:09:28 -0800 (PST) Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-40842752c6eso33386795e9.1 for ; Mon, 06 Nov 2023 03:09:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699268966; x=1699873766; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SjHtz+lPcIw6M6S7bcDq7sYVmI6jCo0hvfjVBU4M5Y0=; b=CAU5PsWJRg1LWpCDjcp2g3JiR3mbXOGiyOf3WCmO16BCrHa2pU5a3WTOe5CYIUQo69 T2OfAjcn+FqOi4Up317xAp0ycpXnFsHKy2KwL65Ky1nKdDiUfrv/O6hh020kNiUqELq+ dlsT0kLgcc5yD65FT/Ou7OFmX7PkxlTvCil7zi34cN97YcnQY+Fj3hL8AEEP+3XXF9uu 5s5okkww2EjLtv7ZB4Idh3GR79IZe9pdisAoMwqB0PRtrKRgoX+BUT+yEetg9l+ekO9d zfoE3ehZcJdY7wL5R4aFzCYfQbMB1gC5neDEJz1BIUGXJHWgOd61Od977O8O6o/At5NQ r3Zw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699268966; x=1699873766; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SjHtz+lPcIw6M6S7bcDq7sYVmI6jCo0hvfjVBU4M5Y0=; b=wbxXvM7cTieWxN1UObtwCk0FsaBkP9/3Y1L2bUH6CSNAISL9vTPwdGMZRqFRCGS2kr ilduqHLdf5hfICoMYgA7MwEX4uHULYjUl4d9zGGHmmTHTvTaEng+fjz3KVf7nE/Y8UW/ CaW83p3NQFroF8amEa9KVk1EfC2HmbxFHefjfWYjKkc/VmToDqXAVvo1HpOwniXkXa62 VV2IDxP/oyT6SKlIk8TewM/JkvzLb0IgUUza7kW+CV1N0GqKlpKAi/ZMoGZl8YnCnK1d AHso3rrDc/AtFDtJfMMThQUQfuqHhYjazgocNHptfjC0hcF6ZXnDV/Hgr0r+xtNMmBh2 C2UQ== X-Gm-Message-State: AOJu0Yyb+WtGFJP9XjzZ5E6u8GvheW70HQzH+AkaQMntSSfCmYYhoEMh EDjMFqvRCT4nJEntevuACD8ha4lGF5b8U/22wgg= X-Google-Smtp-Source: AGHT+IG8Q4coZ+Ea54w4wY9DsUFuNEg759Mh+b6Z9wAr9dd+6s8Zg0s9ng5tqvrG8ylEYsTfJNq9ow== X-Received: by 2002:a05:600c:4693:b0:409:5a92:472f with SMTP id p19-20020a05600c469300b004095a92472fmr11071290wmo.6.1699268966532; Mon, 06 Nov 2023 03:09:26 -0800 (PST) Received: from m1x-phil.lan (176-131-220-199.abo.bbox.fr. [176.131.220.199]) by smtp.gmail.com with ESMTPSA id j6-20020adfea46000000b0032fc609c118sm6076145wrn.66.2023.11.06.03.09.24 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:09:26 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Titus Rwantare , Stephen Longfield , Corey Minyard , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 51/60] hw/i2c: pmbus: add fan support Date: Mon, 6 Nov 2023 12:03:23 +0100 Message-ID: <20231106110336.358-52-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Titus Rwantare PMBus devices may integrate fans whose operation is configurable over PMBus. This commit allows the driver to read and write the fan control registers but does not model the operation of fans. Reviewed-by: Stephen Longfield Acked-by: Corey Minyard Signed-off-by: Titus Rwantare Message-ID: <20231023-staging-pmbus-v3-v4-3-07a8cb7cd20a@google.com> Signed-off-by: Philippe Mathieu-Daudé --- include/hw/i2c/pmbus_device.h | 1 + hw/i2c/pmbus_device.c | 176 ++++++++++++++++++++++++++++++++++ 2 files changed, 177 insertions(+) diff --git a/include/hw/i2c/pmbus_device.h b/include/hw/i2c/pmbus_device.h index 2e95164aa1..ad431bdc7c 100644 --- a/include/hw/i2c/pmbus_device.h +++ b/include/hw/i2c/pmbus_device.h @@ -258,6 +258,7 @@ OBJECT_DECLARE_TYPE(PMBusDevice, PMBusDeviceClass, #define PB_HAS_TEMP2 BIT_ULL(41) #define PB_HAS_TEMP3 BIT_ULL(42) #define PB_HAS_TEMP_RATING BIT_ULL(43) +#define PB_HAS_FAN BIT_ULL(44) #define PB_HAS_MFR_INFO BIT_ULL(50) #define PB_HAS_STATUS_MFR_SPECIFIC BIT_ULL(51) diff --git a/hw/i2c/pmbus_device.c b/hw/i2c/pmbus_device.c index ea15490720..c1d8c93056 100644 --- a/hw/i2c/pmbus_device.c +++ b/hw/i2c/pmbus_device.c @@ -500,6 +500,54 @@ static uint8_t pmbus_receive_byte(SMBusDevice *smd) } break; + case PMBUS_FAN_CONFIG_1_2: /* R/W byte */ + if (pmdev->pages[index].page_flags & PB_HAS_FAN) { + pmbus_send8(pmdev, pmdev->pages[index].fan_config_1_2); + } else { + goto passthough; + } + break; + + case PMBUS_FAN_COMMAND_1: /* R/W word */ + if (pmdev->pages[index].page_flags & PB_HAS_FAN) { + pmbus_send16(pmdev, pmdev->pages[index].fan_command_1); + } else { + goto passthough; + } + break; + + case PMBUS_FAN_COMMAND_2: /* R/W word */ + if (pmdev->pages[index].page_flags & PB_HAS_FAN) { + pmbus_send16(pmdev, pmdev->pages[index].fan_command_2); + } else { + goto passthough; + } + break; + + case PMBUS_FAN_CONFIG_3_4: /* R/W byte */ + if (pmdev->pages[index].page_flags & PB_HAS_FAN) { + pmbus_send8(pmdev, pmdev->pages[index].fan_config_3_4); + } else { + goto passthough; + } + break; + + case PMBUS_FAN_COMMAND_3: /* R/W word */ + if (pmdev->pages[index].page_flags & PB_HAS_FAN) { + pmbus_send16(pmdev, pmdev->pages[index].fan_command_3); + } else { + goto passthough; + } + break; + + case PMBUS_FAN_COMMAND_4: /* R/W word */ + if (pmdev->pages[index].page_flags & PB_HAS_FAN) { + pmbus_send16(pmdev, pmdev->pages[index].fan_command_4); + } else { + goto passthough; + } + break; + case PMBUS_VOUT_OV_FAULT_LIMIT: /* R/W word */ if (pmdev->pages[index].page_flags & PB_HAS_VOUT) { pmbus_send16(pmdev, pmdev->pages[index].vout_ov_fault_limit); @@ -810,6 +858,22 @@ static uint8_t pmbus_receive_byte(SMBusDevice *smd) pmbus_send8(pmdev, pmdev->pages[index].status_mfr_specific); break; + case PMBUS_STATUS_FANS_1_2: /* R/W byte */ + if (pmdev->pages[index].page_flags & PB_HAS_FAN) { + pmbus_send8(pmdev, pmdev->pages[index].status_fans_1_2); + } else { + goto passthough; + } + break; + + case PMBUS_STATUS_FANS_3_4: /* R/W byte */ + if (pmdev->pages[index].page_flags & PB_HAS_FAN) { + pmbus_send8(pmdev, pmdev->pages[index].status_fans_3_4); + } else { + goto passthough; + } + break; + case PMBUS_READ_EIN: /* Read-Only block 5 bytes */ if (pmdev->pages[index].page_flags & PB_HAS_EIN) { pmbus_send(pmdev, pmdev->pages[index].read_ein, 5); @@ -882,6 +946,54 @@ static uint8_t pmbus_receive_byte(SMBusDevice *smd) } break; + case PMBUS_READ_FAN_SPEED_1: /* Read-Only word */ + if (pmdev->pages[index].page_flags & PB_HAS_FAN) { + pmbus_send16(pmdev, pmdev->pages[index].read_fan_speed_1); + } else { + goto passthough; + } + break; + + case PMBUS_READ_FAN_SPEED_2: /* Read-Only word */ + if (pmdev->pages[index].page_flags & PB_HAS_FAN) { + pmbus_send16(pmdev, pmdev->pages[index].read_fan_speed_2); + } else { + goto passthough; + } + break; + + case PMBUS_READ_FAN_SPEED_3: /* Read-Only word */ + if (pmdev->pages[index].page_flags & PB_HAS_FAN) { + pmbus_send16(pmdev, pmdev->pages[index].read_fan_speed_3); + } else { + goto passthough; + } + break; + + case PMBUS_READ_FAN_SPEED_4: /* Read-Only word */ + if (pmdev->pages[index].page_flags & PB_HAS_FAN) { + pmbus_send16(pmdev, pmdev->pages[index].read_fan_speed_4); + } else { + goto passthough; + } + break; + + case PMBUS_READ_DUTY_CYCLE: /* Read-Only word */ + if (pmdev->pages[index].page_flags & PB_HAS_FAN) { + pmbus_send16(pmdev, pmdev->pages[index].read_duty_cycle); + } else { + goto passthough; + } + break; + + case PMBUS_READ_FREQUENCY: /* Read-Only word */ + if (pmdev->pages[index].page_flags & PB_HAS_FAN) { + pmbus_send16(pmdev, pmdev->pages[index].read_frequency); + } else { + goto passthough; + } + break; + case PMBUS_READ_POUT: /* Read-Only word */ if (pmdev->pages[index].page_flags & PB_HAS_POUT) { pmbus_send16(pmdev, pmdev->pages[index].read_pout); @@ -1305,6 +1417,54 @@ static int pmbus_write_data(SMBusDevice *smd, uint8_t *buf, uint8_t len) } break; + case PMBUS_FAN_CONFIG_1_2: /* R/W byte */ + if (pmdev->pages[index].page_flags & PB_HAS_FAN) { + pmdev->pages[index].fan_config_1_2 = pmbus_receive8(pmdev); + } else { + goto passthrough; + } + break; + + case PMBUS_FAN_COMMAND_1: /* R/W word */ + if (pmdev->pages[index].page_flags & PB_HAS_FAN) { + pmdev->pages[index].fan_command_1 = pmbus_receive16(pmdev); + } else { + goto passthrough; + } + break; + + case PMBUS_FAN_COMMAND_2: /* R/W word */ + if (pmdev->pages[index].page_flags & PB_HAS_FAN) { + pmdev->pages[index].fan_command_2 = pmbus_receive16(pmdev); + } else { + goto passthrough; + } + break; + + case PMBUS_FAN_CONFIG_3_4: /* R/W byte */ + if (pmdev->pages[index].page_flags & PB_HAS_FAN) { + pmdev->pages[index].fan_config_3_4 = pmbus_receive8(pmdev); + } else { + goto passthrough; + } + break; + + case PMBUS_FAN_COMMAND_3: /* R/W word */ + if (pmdev->pages[index].page_flags & PB_HAS_FAN) { + pmdev->pages[index].fan_command_3 = pmbus_receive16(pmdev); + } else { + goto passthrough; + } + break; + + case PMBUS_FAN_COMMAND_4: /* R/W word */ + if (pmdev->pages[index].page_flags & PB_HAS_FAN) { + pmdev->pages[index].fan_command_4 = pmbus_receive16(pmdev); + } else { + goto passthrough; + } + break; + case PMBUS_VOUT_OV_FAULT_LIMIT: /* R/W word */ if (pmdev->pages[index].page_flags & PB_HAS_VOUT) { pmdev->pages[index].vout_ov_fault_limit = pmbus_receive16(pmdev); @@ -1610,6 +1770,22 @@ static int pmbus_write_data(SMBusDevice *smd, uint8_t *buf, uint8_t len) pmdev->pages[index].status_mfr_specific = pmbus_receive8(pmdev); break; + case PMBUS_STATUS_FANS_1_2: /* R/W byte */ + if (pmdev->pages[index].page_flags & PB_HAS_FAN) { + pmbus_send8(pmdev, pmdev->pages[index].status_fans_1_2); + } else { + goto passthrough; + } + break; + + case PMBUS_STATUS_FANS_3_4: /* R/W byte */ + if (pmdev->pages[index].page_flags & PB_HAS_FAN) { + pmbus_send8(pmdev, pmdev->pages[index].status_fans_3_4); + } else { + goto passthrough; + } + break; + case PMBUS_PAGE_PLUS_READ: /* Block Read-only */ case PMBUS_CAPABILITY: /* Read-Only byte */ case PMBUS_COEFFICIENTS: /* Read-only block 5 bytes */ From patchwork Mon Nov 6 11:03:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13446677 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8D3821A5A4 for ; Mon, 6 Nov 2023 11:09:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="W3apIab0" Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [IPv6:2a00:1450:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 99590BB for ; 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id y8-20020a5d4708000000b0032d2f09d991sm9141944wrq.33.2023.11.06.03.09.31 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:09:32 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Titus Rwantare , Benjamin Streb , Corey Minyard , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 52/60] hw/i2c: pmbus: add VCAP register Date: Mon, 6 Nov 2023 12:03:24 +0100 Message-ID: <20231106110336.358-53-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Titus Rwantare VCAP is a register for devices with energy storage capacitors. Reviewed-by: Benjamin Streb Acked-by: Corey Minyard Signed-off-by: Titus Rwantare Message-ID: <20231023-staging-pmbus-v3-v4-4-07a8cb7cd20a@google.com> Signed-off-by: Philippe Mathieu-Daudé --- include/hw/i2c/pmbus_device.h | 1 + hw/i2c/pmbus_device.c | 8 ++++++++ 2 files changed, 9 insertions(+) diff --git a/include/hw/i2c/pmbus_device.h b/include/hw/i2c/pmbus_device.h index ad431bdc7c..f195c11384 100644 --- a/include/hw/i2c/pmbus_device.h +++ b/include/hw/i2c/pmbus_device.h @@ -243,6 +243,7 @@ OBJECT_DECLARE_TYPE(PMBusDevice, PMBusDeviceClass, #define PB_HAS_VIN_RATING BIT_ULL(13) #define PB_HAS_VOUT_RATING BIT_ULL(14) #define PB_HAS_VOUT_MODE BIT_ULL(15) +#define PB_HAS_VCAP BIT_ULL(16) #define PB_HAS_IOUT BIT_ULL(21) #define PB_HAS_IIN BIT_ULL(22) #define PB_HAS_IOUT_RATING BIT_ULL(23) diff --git a/hw/i2c/pmbus_device.c b/hw/i2c/pmbus_device.c index c1d8c93056..3bce39e84e 100644 --- a/hw/i2c/pmbus_device.c +++ b/hw/i2c/pmbus_device.c @@ -906,6 +906,14 @@ static uint8_t pmbus_receive_byte(SMBusDevice *smd) } break; + case PMBUS_READ_VCAP: /* Read-Only word */ + if (pmdev->pages[index].page_flags & PB_HAS_VCAP) { + pmbus_send16(pmdev, pmdev->pages[index].read_vcap); + } else { + goto passthough; + } + break; + case PMBUS_READ_VOUT: /* Read-Only word */ if (pmdev->pages[index].page_flags & PB_HAS_VOUT) { pmbus_send16(pmdev, pmdev->pages[index].read_vout); From patchwork Mon Nov 6 11:03:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13446678 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 36C721A71D for ; Mon, 6 Nov 2023 11:09:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="s32bxmwS" Received: from mail-lj1-x22b.google.com (mail-lj1-x22b.google.com [IPv6:2a00:1450:4864:20::22b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 81CA398 for ; Mon, 6 Nov 2023 03:09:41 -0800 (PST) Received: by mail-lj1-x22b.google.com with SMTP id 38308e7fff4ca-2c6ef6c1ec2so52813641fa.2 for ; Mon, 06 Nov 2023 03:09:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699268980; x=1699873780; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=iac5EYIzrukJRvlyPwy92lw3bSASiGn2WGuusjle2eY=; b=s32bxmwSxoYxfVA2bkchUQIgjX04xg8ge1hW1eCSIbn6lv3GIbNtYt/0W7ncdrsqig MCKYp5TF7Z62b+WzW5Tm7QqHNjybAQWpQp6sabBfZvwO1suupc8flxUminjJpvsii/zM XdzyQqyTzJrPKSfq/b7t5GEXFAKuJtzqrcZ01vFvJVXbiujTzWRB7+JRPA73IqzO8WTM x2B0RK0+QTd6CPiJ2fXmW7+1Q56GMgGxwds1XSE+juzjwOqOHHyaDeNmKeaLMF8qtpYG D/mv5DFS5NQ+UGLz2D0iOVclupT1N++2Z4bbti8kjqC9ttIPpJKHY2wDGcPl5iObtF07 zkEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699268980; x=1699873780; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=iac5EYIzrukJRvlyPwy92lw3bSASiGn2WGuusjle2eY=; b=lnkyhBYTID72+lbM1pQNL/deCpigiRcMBgxOADKz8fVg0avUPJFwxOFT4m4q57nPXt MvF2h9j/ctaaGlCmRJwZ9AmRRNZEUiqlHSbEA0Q4HVC4Sc++FWt9V+OF9R135GhnDqjN TlY7v3Bgv60Bf/yrqyCvBz/NFTByewqHsMVYAdrOl+QKNwxLscydUfCSGJRSWk1WZTXS mcaB86fNRoAzMyE4ZQ6NVsrQCMTp6pIs84dYcr+t+Mf1MoPwh5DAKUKoVVuFgit3p+C6 Hng257YpT2IAn+F1xX8pJ9O94V7v/aD/pvQKcctQGocBhrwYPidCJ+PU9QvBbko0Izvi 71cA== X-Gm-Message-State: AOJu0YyyP1Km/6Ael8KhGFxAj8TiVFyYG9VPmG4RYozusp+kS1fa+X5N jaeh/xuxITxGMAGmOn/pO+JaMA== X-Google-Smtp-Source: AGHT+IGtnXRrMjhzzRV0caLFucBfgjOr7PtrWkTJeCvHRsyO/ZH9DcpMWWGhJ2druMFWhmrbO+CNOw== X-Received: by 2002:a05:651c:11d3:b0:2bc:b75e:b88 with SMTP id z19-20020a05651c11d300b002bcb75e0b88mr23964902ljo.18.1699268979795; Mon, 06 Nov 2023 03:09:39 -0800 (PST) Received: from m1x-phil.lan (176-131-220-199.abo.bbox.fr. [176.131.220.199]) by smtp.gmail.com with ESMTPSA id ew3-20020a05600c808300b004054dcbf92asm11515737wmb.20.2023.11.06.03.09.37 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:09:39 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Titus Rwantare , Hao Wu , Corey Minyard , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , Peter Maydell , Tyrone Ting Subject: [PULL 53/60] hw/sensor: add ADM1266 device model Date: Mon, 6 Nov 2023 12:03:25 +0100 Message-ID: <20231106110336.358-54-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Titus Rwantare The ADM1266 is a cascadable super sequencer with margin control and fault recording. This commit adds basic support for its PMBus commands and models the identification registers that can be modified in a firmware update. Reviewed-by: Hao Wu Acked-by: Corey Minyard Signed-off-by: Titus Rwantare [PMD: Cover file in MAINTAINERS] Message-ID: <20231023-staging-pmbus-v3-v4-5-07a8cb7cd20a@google.com> Signed-off-by: Philippe Mathieu-Daudé --- MAINTAINERS | 1 + hw/sensor/adm1266.c | 254 ++++++++++++++++++++++++++++++++++++++++++ hw/arm/Kconfig | 1 + hw/sensor/Kconfig | 5 + hw/sensor/meson.build | 1 + 5 files changed, 262 insertions(+) create mode 100644 hw/sensor/adm1266.c diff --git a/MAINTAINERS b/MAINTAINERS index 126cddd285..e6a2f57442 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -859,6 +859,7 @@ M: Hao Wu L: qemu-arm@nongnu.org S: Supported F: hw/*/npcm* +F: hw/sensor/adm1266.c F: include/hw/*/npcm* F: tests/qtest/npcm* F: pc-bios/npcm7xx_bootrom.bin diff --git a/hw/sensor/adm1266.c b/hw/sensor/adm1266.c new file mode 100644 index 0000000000..5ae4f82ba1 --- /dev/null +++ b/hw/sensor/adm1266.c @@ -0,0 +1,254 @@ +/* + * Analog Devices ADM1266 Cascadable Super Sequencer with Margin Control and + * Fault Recording with PMBus + * + * https://www.analog.com/media/en/technical-documentation/data-sheets/adm1266.pdf + * + * Copyright 2023 Google LLC + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hw/i2c/pmbus_device.h" +#include "hw/irq.h" +#include "migration/vmstate.h" +#include "qapi/error.h" +#include "qapi/visitor.h" +#include "qemu/log.h" +#include "qemu/module.h" + +#define TYPE_ADM1266 "adm1266" +OBJECT_DECLARE_SIMPLE_TYPE(ADM1266State, ADM1266) + +#define ADM1266_BLACKBOX_CONFIG 0xD3 +#define ADM1266_PDIO_CONFIG 0xD4 +#define ADM1266_READ_STATE 0xD9 +#define ADM1266_READ_BLACKBOX 0xDE +#define ADM1266_SET_RTC 0xDF +#define ADM1266_GPIO_SYNC_CONFIGURATION 0xE1 +#define ADM1266_BLACKBOX_INFORMATION 0xE6 +#define ADM1266_PDIO_STATUS 0xE9 +#define ADM1266_GPIO_STATUS 0xEA + +/* Defaults */ +#define ADM1266_OPERATION_DEFAULT 0x80 +#define ADM1266_CAPABILITY_DEFAULT 0xA0 +#define ADM1266_CAPABILITY_NO_PEC 0x20 +#define ADM1266_PMBUS_REVISION_DEFAULT 0x22 +#define ADM1266_MFR_ID_DEFAULT "ADI" +#define ADM1266_MFR_ID_DEFAULT_LEN 32 +#define ADM1266_MFR_MODEL_DEFAULT "ADM1266-A1" +#define ADM1266_MFR_MODEL_DEFAULT_LEN 32 +#define ADM1266_MFR_REVISION_DEFAULT "25" +#define ADM1266_MFR_REVISION_DEFAULT_LEN 8 + +#define ADM1266_NUM_PAGES 17 +/** + * PAGE Index + * Page 0 VH1. + * Page 1 VH2. + * Page 2 VH3. + * Page 3 VH4. + * Page 4 VP1. + * Page 5 VP2. + * Page 6 VP3. + * Page 7 VP4. + * Page 8 VP5. + * Page 9 VP6. + * Page 10 VP7. + * Page 11 VP8. + * Page 12 VP9. + * Page 13 VP10. + * Page 14 VP11. + * Page 15 VP12. + * Page 16 VP13. + */ +typedef struct ADM1266State { + PMBusDevice parent; + + char mfr_id[32]; + char mfr_model[32]; + char mfr_rev[8]; +} ADM1266State; + +static const uint8_t adm1266_ic_device_id[] = {0x03, 0x41, 0x12, 0x66}; +static const uint8_t adm1266_ic_device_rev[] = {0x08, 0x01, 0x08, 0x07, 0x0, + 0x0, 0x07, 0x41, 0x30}; + +static void adm1266_exit_reset(Object *obj) +{ + ADM1266State *s = ADM1266(obj); + PMBusDevice *pmdev = PMBUS_DEVICE(obj); + + pmdev->page = 0; + pmdev->capability = ADM1266_CAPABILITY_NO_PEC; + + for (int i = 0; i < ADM1266_NUM_PAGES; i++) { + pmdev->pages[i].operation = ADM1266_OPERATION_DEFAULT; + pmdev->pages[i].revision = ADM1266_PMBUS_REVISION_DEFAULT; + pmdev->pages[i].vout_mode = 0; + pmdev->pages[i].read_vout = pmbus_data2linear_mode(12, 0); + pmdev->pages[i].vout_margin_high = pmbus_data2linear_mode(15, 0); + pmdev->pages[i].vout_margin_low = pmbus_data2linear_mode(3, 0); + pmdev->pages[i].vout_ov_fault_limit = pmbus_data2linear_mode(16, 0); + pmdev->pages[i].revision = ADM1266_PMBUS_REVISION_DEFAULT; + } + + strncpy(s->mfr_id, ADM1266_MFR_ID_DEFAULT, 4); + strncpy(s->mfr_model, ADM1266_MFR_MODEL_DEFAULT, 11); + strncpy(s->mfr_rev, ADM1266_MFR_REVISION_DEFAULT, 3); +} + +static uint8_t adm1266_read_byte(PMBusDevice *pmdev) +{ + ADM1266State *s = ADM1266(pmdev); + + switch (pmdev->code) { + case PMBUS_MFR_ID: /* R/W block */ + pmbus_send_string(pmdev, s->mfr_id); + break; + + case PMBUS_MFR_MODEL: /* R/W block */ + pmbus_send_string(pmdev, s->mfr_model); + break; + + case PMBUS_MFR_REVISION: /* R/W block */ + pmbus_send_string(pmdev, s->mfr_rev); + break; + + case PMBUS_IC_DEVICE_ID: + pmbus_send(pmdev, adm1266_ic_device_id, sizeof(adm1266_ic_device_id)); + break; + + case PMBUS_IC_DEVICE_REV: + pmbus_send(pmdev, adm1266_ic_device_rev, sizeof(adm1266_ic_device_rev)); + break; + + default: + qemu_log_mask(LOG_UNIMP, + "%s: reading from unimplemented register: 0x%02x\n", + __func__, pmdev->code); + return 0xFF; + } + + return 0; +} + +static int adm1266_write_data(PMBusDevice *pmdev, const uint8_t *buf, + uint8_t len) +{ + ADM1266State *s = ADM1266(pmdev); + + switch (pmdev->code) { + case PMBUS_MFR_ID: /* R/W block */ + pmbus_receive_block(pmdev, (uint8_t *)s->mfr_id, sizeof(s->mfr_id)); + break; + + case PMBUS_MFR_MODEL: /* R/W block */ + pmbus_receive_block(pmdev, (uint8_t *)s->mfr_model, + sizeof(s->mfr_model)); + break; + + case PMBUS_MFR_REVISION: /* R/W block*/ + pmbus_receive_block(pmdev, (uint8_t *)s->mfr_rev, sizeof(s->mfr_rev)); + break; + + case ADM1266_SET_RTC: /* do nothing */ + break; + + default: + qemu_log_mask(LOG_UNIMP, + "%s: writing to unimplemented register: 0x%02x\n", + __func__, pmdev->code); + break; + } + return 0; +} + +static void adm1266_get(Object *obj, Visitor *v, const char *name, void *opaque, + Error **errp) +{ + uint16_t value; + PMBusDevice *pmdev = PMBUS_DEVICE(obj); + PMBusVoutMode *mode = (PMBusVoutMode *)&pmdev->pages[0].vout_mode; + + if (strcmp(name, "vout") == 0) { + value = pmbus_linear_mode2data(*(uint16_t *)opaque, mode->exp); + } else { + value = *(uint16_t *)opaque; + } + + visit_type_uint16(v, name, &value, errp); +} + +static void adm1266_set(Object *obj, Visitor *v, const char *name, void *opaque, + Error **errp) +{ + uint16_t *internal = opaque; + uint16_t value; + PMBusDevice *pmdev = PMBUS_DEVICE(obj); + PMBusVoutMode *mode = (PMBusVoutMode *)&pmdev->pages[0].vout_mode; + + if (!visit_type_uint16(v, name, &value, errp)) { + return; + } + + *internal = pmbus_data2linear_mode(value, mode->exp); + pmbus_check_limits(pmdev); +} + +static const VMStateDescription vmstate_adm1266 = { + .name = "ADM1266", + .version_id = 0, + .minimum_version_id = 0, + .fields = (VMStateField[]){ + VMSTATE_PMBUS_DEVICE(parent, ADM1266State), + VMSTATE_END_OF_LIST() + } +}; + +static void adm1266_init(Object *obj) +{ + PMBusDevice *pmdev = PMBUS_DEVICE(obj); + uint64_t flags = PB_HAS_VOUT_MODE | PB_HAS_VOUT | PB_HAS_VOUT_MARGIN | + PB_HAS_VOUT_RATING | PB_HAS_STATUS_MFR_SPECIFIC; + + for (int i = 0; i < ADM1266_NUM_PAGES; i++) { + pmbus_page_config(pmdev, i, flags); + + object_property_add(obj, "vout[*]", "uint16", + adm1266_get, + adm1266_set, NULL, &pmdev->pages[i].read_vout); + } +} + +static void adm1266_class_init(ObjectClass *klass, void *data) +{ + ResettableClass *rc = RESETTABLE_CLASS(klass); + DeviceClass *dc = DEVICE_CLASS(klass); + PMBusDeviceClass *k = PMBUS_DEVICE_CLASS(klass); + + dc->desc = "Analog Devices ADM1266 Hot Swap controller"; + dc->vmsd = &vmstate_adm1266; + k->write_data = adm1266_write_data; + k->receive_byte = adm1266_read_byte; + k->device_num_pages = 17; + + rc->phases.exit = adm1266_exit_reset; +} + +static const TypeInfo adm1266_info = { + .name = TYPE_ADM1266, + .parent = TYPE_PMBUS_DEVICE, + .instance_size = sizeof(ADM1266State), + .instance_init = adm1266_init, + .class_init = adm1266_class_init, +}; + +static void adm1266_register_types(void) +{ + type_register_static(&adm1266_info); +} + +type_init(adm1266_register_types) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index e35007ed41..0f22aee24b 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -489,6 +489,7 @@ config NPCM7XX default y depends on TCG && ARM select A9MPCORE + select ADM1266 select ADM1272 select ARM_GIC select SMBUS diff --git a/hw/sensor/Kconfig b/hw/sensor/Kconfig index e03bd09b50..bc6331b4ab 100644 --- a/hw/sensor/Kconfig +++ b/hw/sensor/Kconfig @@ -22,6 +22,11 @@ config ADM1272 bool depends on I2C +config ADM1266 + bool + depends on PMBUS + default y if PMBUS + config MAX34451 bool depends on I2C diff --git a/hw/sensor/meson.build b/hw/sensor/meson.build index 30e20e27b8..420fdc3359 100644 --- a/hw/sensor/meson.build +++ b/hw/sensor/meson.build @@ -2,6 +2,7 @@ system_ss.add(when: 'CONFIG_TMP105', if_true: files('tmp105.c')) system_ss.add(when: 'CONFIG_TMP421', if_true: files('tmp421.c')) system_ss.add(when: 'CONFIG_DPS310', if_true: files('dps310.c')) system_ss.add(when: 'CONFIG_EMC141X', if_true: files('emc141x.c')) +system_ss.add(when: 'CONFIG_ADM1266', if_true: files('adm1266.c')) system_ss.add(when: 'CONFIG_ADM1272', if_true: files('adm1272.c')) system_ss.add(when: 'CONFIG_MAX34451', if_true: files('max34451.c')) system_ss.add(when: 'CONFIG_LSM303DLHC_MAG', if_true: files('lsm303dlhc_mag.c')) From patchwork Mon Nov 6 11:03:26 2023 Content-Type: text/plain; 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id l4-20020adfa384000000b0032d2489a399sm9245951wrb.49.2023.11.06.03.09.44 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:09:46 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Titus Rwantare , Hao Wu , Corey Minyard , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Tyrone Ting , Thomas Huth , Laurent Vivier , Paolo Bonzini Subject: [PULL 54/60] tests/qtest: add tests for ADM1266 Date: Mon, 6 Nov 2023 12:03:26 +0100 Message-ID: <20231106110336.358-55-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Titus Rwantare The ADM1266 can have string fields written by the driver, so it's worth specifically testing. Reviewed-by: Hao Wu Acked-by: Corey Minyard Signed-off-by: Titus Rwantare [PMD: Cover file in MAINTAINERS] Message-ID: <20231023-staging-pmbus-v3-v4-6-07a8cb7cd20a@google.com> Signed-off-by: Philippe Mathieu-Daudé --- MAINTAINERS | 1 + tests/qtest/adm1266-test.c | 122 +++++++++++++++++++++++++++++++++++++ tests/qtest/meson.build | 1 + 3 files changed, 124 insertions(+) create mode 100644 tests/qtest/adm1266-test.c diff --git a/MAINTAINERS b/MAINTAINERS index e6a2f57442..c01c2e6ec0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -862,6 +862,7 @@ F: hw/*/npcm* F: hw/sensor/adm1266.c F: include/hw/*/npcm* F: tests/qtest/npcm* +F: tests/qtest/adm1266-test.c F: pc-bios/npcm7xx_bootrom.bin F: roms/vbootrom F: docs/system/arm/nuvoton.rst diff --git a/tests/qtest/adm1266-test.c b/tests/qtest/adm1266-test.c new file mode 100644 index 0000000000..6c312c499f --- /dev/null +++ b/tests/qtest/adm1266-test.c @@ -0,0 +1,122 @@ +/* + * Analog Devices ADM1266 Cascadable Super Sequencer with Margin Control and + * Fault Recording with PMBus + * + * Copyright 2022 Google LLC + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include +#include "hw/i2c/pmbus_device.h" +#include "libqtest-single.h" +#include "libqos/qgraph.h" +#include "libqos/i2c.h" +#include "qapi/qmp/qdict.h" +#include "qapi/qmp/qnum.h" +#include "qemu/bitops.h" + +#define TEST_ID "adm1266-test" +#define TEST_ADDR (0x12) + +#define ADM1266_BLACKBOX_CONFIG 0xD3 +#define ADM1266_PDIO_CONFIG 0xD4 +#define ADM1266_READ_STATE 0xD9 +#define ADM1266_READ_BLACKBOX 0xDE +#define ADM1266_SET_RTC 0xDF +#define ADM1266_GPIO_SYNC_CONFIGURATION 0xE1 +#define ADM1266_BLACKBOX_INFORMATION 0xE6 +#define ADM1266_PDIO_STATUS 0xE9 +#define ADM1266_GPIO_STATUS 0xEA + +/* Defaults */ +#define ADM1266_OPERATION_DEFAULT 0x80 +#define ADM1266_CAPABILITY_DEFAULT 0xA0 +#define ADM1266_CAPABILITY_NO_PEC 0x20 +#define ADM1266_PMBUS_REVISION_DEFAULT 0x22 +#define ADM1266_MFR_ID_DEFAULT "ADI" +#define ADM1266_MFR_ID_DEFAULT_LEN 32 +#define ADM1266_MFR_MODEL_DEFAULT "ADM1266-A1" +#define ADM1266_MFR_MODEL_DEFAULT_LEN 32 +#define ADM1266_MFR_REVISION_DEFAULT "25" +#define ADM1266_MFR_REVISION_DEFAULT_LEN 8 +#define TEST_STRING_A "a sample" +#define TEST_STRING_B "b sample" +#define TEST_STRING_C "rev c" + +static void compare_string(QI2CDevice *i2cdev, uint8_t reg, + const char *test_str) +{ + uint8_t len = i2c_get8(i2cdev, reg); + char i2c_str[SMBUS_DATA_MAX_LEN] = {0}; + + i2c_read_block(i2cdev, reg, (uint8_t *)i2c_str, len); + g_assert_cmpstr(i2c_str, ==, test_str); +} + +static void write_and_compare_string(QI2CDevice *i2cdev, uint8_t reg, + const char *test_str, uint8_t len) +{ + char buf[SMBUS_DATA_MAX_LEN] = {0}; + buf[0] = len; + strncpy(buf + 1, test_str, len); + i2c_write_block(i2cdev, reg, (uint8_t *)buf, len + 1); + compare_string(i2cdev, reg, test_str); +} + +static void test_defaults(void *obj, void *data, QGuestAllocator *alloc) +{ + uint16_t i2c_value; + QI2CDevice *i2cdev = (QI2CDevice *)obj; + + i2c_value = i2c_get8(i2cdev, PMBUS_OPERATION); + g_assert_cmphex(i2c_value, ==, ADM1266_OPERATION_DEFAULT); + + i2c_value = i2c_get8(i2cdev, PMBUS_REVISION); + g_assert_cmphex(i2c_value, ==, ADM1266_PMBUS_REVISION_DEFAULT); + + compare_string(i2cdev, PMBUS_MFR_ID, ADM1266_MFR_ID_DEFAULT); + compare_string(i2cdev, PMBUS_MFR_MODEL, ADM1266_MFR_MODEL_DEFAULT); + compare_string(i2cdev, PMBUS_MFR_REVISION, ADM1266_MFR_REVISION_DEFAULT); +} + +/* test r/w registers */ +static void test_rw_regs(void *obj, void *data, QGuestAllocator *alloc) +{ + QI2CDevice *i2cdev = (QI2CDevice *)obj; + + /* empty strings */ + i2c_set8(i2cdev, PMBUS_MFR_ID, 0); + compare_string(i2cdev, PMBUS_MFR_ID, ""); + + i2c_set8(i2cdev, PMBUS_MFR_MODEL, 0); + compare_string(i2cdev, PMBUS_MFR_MODEL, ""); + + i2c_set8(i2cdev, PMBUS_MFR_REVISION, 0); + compare_string(i2cdev, PMBUS_MFR_REVISION, ""); + + /* test strings */ + write_and_compare_string(i2cdev, PMBUS_MFR_ID, TEST_STRING_A, + sizeof(TEST_STRING_A)); + write_and_compare_string(i2cdev, PMBUS_MFR_ID, TEST_STRING_B, + sizeof(TEST_STRING_B)); + write_and_compare_string(i2cdev, PMBUS_MFR_ID, TEST_STRING_C, + sizeof(TEST_STRING_C)); +} + +static void adm1266_register_nodes(void) +{ + QOSGraphEdgeOptions opts = { + .extra_device_opts = "id=" TEST_ID ",address=0x12" + }; + add_qi2c_address(&opts, &(QI2CAddress) { TEST_ADDR }); + + qos_node_create_driver("adm1266", i2c_device_create); + qos_node_consumes("adm1266", "i2c-bus", &opts); + + qos_add_test("test_defaults", "adm1266", test_defaults, NULL); + qos_add_test("test_rw_regs", "adm1266", test_rw_regs, NULL); +} + +libqos_init(adm1266_register_nodes); diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index c9945e69b1..47dabf91d0 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -241,6 +241,7 @@ qos_test_ss = ss.source_set() qos_test_ss.add( 'ac97-test.c', 'adm1272-test.c', + 'adm1266-test.c', 'ds1338-test.c', 'e1000-test.c', 'eepro100-test.c', From patchwork Mon Nov 6 11:03:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13446680 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9A0731805F for ; Mon, 6 Nov 2023 11:09:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id f18-20020a5d58f2000000b0032da4c98ab2sm9102932wrd.35.2023.11.06.03.09.51 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:09:52 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Titus Rwantare , Patrick Venture , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 55/60] hw/i2c: pmbus: immediately clear faults on request Date: Mon, 6 Nov 2023 12:03:27 +0100 Message-ID: <20231106110336.358-56-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Titus Rwantare The probing process of the generic pmbus driver generates faults to determine if functions are available. These faults were not always cleared resulting in probe failures. Reviewed-by: Patrick Venture Signed-off-by: Titus Rwantare Message-ID: <20231023-staging-pmbus-v3-v4-7-07a8cb7cd20a@google.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/i2c/pmbus_device.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/hw/i2c/pmbus_device.c b/hw/i2c/pmbus_device.c index 3bce39e84e..481e158380 100644 --- a/hw/i2c/pmbus_device.c +++ b/hw/i2c/pmbus_device.c @@ -1244,6 +1244,11 @@ static int pmbus_write_data(SMBusDevice *smd, uint8_t *buf, uint8_t len) pmdev->in_buf = buf; pmdev->code = buf[0]; /* PMBus command code */ + + if (pmdev->code == PMBUS_CLEAR_FAULTS) { + pmbus_clear_faults(pmdev); + } + if (len == 1) { /* Single length writes are command codes only */ return 0; } From patchwork Mon Nov 6 11:03:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13446681 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5BCAA1EB36 for ; Mon, 6 Nov 2023 11:10:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="MMtJICmw" Received: from mail-lj1-x22e.google.com (mail-lj1-x22e.google.com [IPv6:2a00:1450:4864:20::22e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 44437A3 for ; Mon, 6 Nov 2023 03:10:01 -0800 (PST) Received: by mail-lj1-x22e.google.com with SMTP id 38308e7fff4ca-2c6efcef4eeso52292941fa.1 for ; Mon, 06 Nov 2023 03:10:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699268999; x=1699873799; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MGUqOvUDBSiuVjcJL6HNGd3FosLBI9RMurHd3wgpnc0=; b=MMtJICmw8xZsbWMl95HK0UcTLUBTOMOKhw9r9EwYdG1y5PvVKXwg0Hb4acJYG3/Xza xXkxXG1BWeC/V+GvA5Df0ZE7BR8kKQ8v/iGi+HudFnpZEuxNQspAWKbsaS2kUNOxISiZ mY4ATkzBVETelURQuBDZvjsQZw0OjdcOhwgQ9vUPM84ggBHs0bFTrKDZcMlzS7n4Xw49 P1h9dzAOA6N/l3nUxWK1C3AWK/TYba7fTwZ1m0fIqbkeDOTy8rRsS4+WS6wgI4T++0xD ijJQHCJJa1PXBx2090j21prbJsPvYSV3/XOHF6NxelSWL/5Vjp/jrjjdPfo9nd+qbQva XuDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699268999; x=1699873799; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MGUqOvUDBSiuVjcJL6HNGd3FosLBI9RMurHd3wgpnc0=; b=T1ZDbZNnYE/MvevPnK2ntSmTt1mjYtAh6QhbVxjXYNfMtiifa64xOXsSwJ73MiY9qK VZaK378cdi8oewYk3yKSEU9VTNQ73mLOWAr1R4BPz8DZuu2vnHHR+ymB/hbCyScEtyBt m06BTscPA8/OImuRmx7iO80eHwwGv6JHz1d1Fp9ZPKBfbo/vT2ROPkN/EkBIuKe4SJ+t f6C/DHADUgS/+cKAerm71TJpFwVpUE5PAzbDSVoXnuE2JGCEIF7QjVSvPuj8WqJ2CoUH JeseNEK2y2kYaYAo4Oep7mnZ979xigxM9xqLXxFzbOShXL3XGOV/VHHiNJBlSIpcFk1g SbaA== X-Gm-Message-State: AOJu0Yz0sN7Yu/JXbn6VGXSHahEnjtOcmwPmQDAE/NFYXGXwGxzkCGHb NPJROsnm7XEE0b7l7EXozTrXkA== X-Google-Smtp-Source: AGHT+IFzu+WNTNvikEhT3RfrTXgUYqfUsIePLUoFbNzyRmjcJbd74z4iaBvydg4KqQIGnFcZE2qYAg== X-Received: by 2002:a2e:8719:0:b0:2c5:1075:5ec9 with SMTP id m25-20020a2e8719000000b002c510755ec9mr21956567lji.13.1699268999654; Mon, 06 Nov 2023 03:09:59 -0800 (PST) Received: from m1x-phil.lan (176-131-220-199.abo.bbox.fr. [176.131.220.199]) by smtp.gmail.com with ESMTPSA id f13-20020a05600c4e8d00b0040596352951sm11684422wmq.5.2023.11.06.03.09.57 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:09:59 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Titus Rwantare , Hao Wu , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Thomas Huth , Laurent Vivier , Paolo Bonzini Subject: [PULL 56/60] hw/i2c: pmbus: reset page register for out of range reads Date: Mon, 6 Nov 2023 12:03:28 +0100 Message-ID: <20231106110336.358-57-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Titus Rwantare The linux pmbus driver scans all possible pages and does not reset the current page after the scan, making all future page reads fail as out of range on devices with a single page. This change resets out of range pages immediately on write. Also added a qtest for simultaneous writes to all pages. Reviewed-by: Hao Wu Signed-off-by: Titus Rwantare Message-ID: <20231023-staging-pmbus-v3-v4-8-07a8cb7cd20a@google.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/i2c/pmbus_device.c | 18 +++++++++--------- tests/qtest/max34451-test.c | 24 ++++++++++++++++++++++++ 2 files changed, 33 insertions(+), 9 deletions(-) diff --git a/hw/i2c/pmbus_device.c b/hw/i2c/pmbus_device.c index 481e158380..1b978e588f 100644 --- a/hw/i2c/pmbus_device.c +++ b/hw/i2c/pmbus_device.c @@ -1255,6 +1255,15 @@ static int pmbus_write_data(SMBusDevice *smd, uint8_t *buf, uint8_t len) if (pmdev->code == PMBUS_PAGE) { pmdev->page = pmbus_receive8(pmdev); + + if (pmdev->page > pmdev->num_pages - 1 && pmdev->page != PB_ALL_PAGES) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: page %u is out of range\n", + __func__, pmdev->page); + pmdev->page = 0; /* undefined behaviour - reset to page 0 */ + pmbus_cml_error(pmdev); + return PMBUS_ERR_BYTE; + } return 0; } @@ -1268,15 +1277,6 @@ static int pmbus_write_data(SMBusDevice *smd, uint8_t *buf, uint8_t len) return 0; } - if (pmdev->page > pmdev->num_pages - 1) { - qemu_log_mask(LOG_GUEST_ERROR, - "%s: page %u is out of range\n", - __func__, pmdev->page); - pmdev->page = 0; /* undefined behaviour - reset to page 0 */ - pmbus_cml_error(pmdev); - return PMBUS_ERR_BYTE; - } - index = pmdev->page; switch (pmdev->code) { diff --git a/tests/qtest/max34451-test.c b/tests/qtest/max34451-test.c index 0c98d0764c..dbf6ddc829 100644 --- a/tests/qtest/max34451-test.c +++ b/tests/qtest/max34451-test.c @@ -18,6 +18,7 @@ #define TEST_ID "max34451-test" #define TEST_ADDR (0x4e) +#define MAX34451_MFR_MODE 0xD1 #define MAX34451_MFR_VOUT_PEAK 0xD4 #define MAX34451_MFR_IOUT_PEAK 0xD5 #define MAX34451_MFR_TEMPERATURE_PEAK 0xD6 @@ -315,6 +316,28 @@ static void test_ot_faults(void *obj, void *data, QGuestAllocator *alloc) } } +#define RAND_ON_OFF_CONFIG 0x12 +#define RAND_MFR_MODE 0x3456 + +/* test writes to all pages */ +static void test_all_pages(void *obj, void *data, QGuestAllocator *alloc) +{ + uint16_t i2c_value; + QI2CDevice *i2cdev = (QI2CDevice *)obj; + + i2c_set8(i2cdev, PMBUS_PAGE, PB_ALL_PAGES); + i2c_set8(i2cdev, PMBUS_ON_OFF_CONFIG, RAND_ON_OFF_CONFIG); + max34451_i2c_set16(i2cdev, MAX34451_MFR_MODE, RAND_MFR_MODE); + + for (int i = 0; i < MAX34451_NUM_TEMP_DEVICES + MAX34451_NUM_PWR_DEVICES; + i++) { + i2c_value = i2c_get8(i2cdev, PMBUS_ON_OFF_CONFIG); + g_assert_cmphex(i2c_value, ==, RAND_ON_OFF_CONFIG); + i2c_value = max34451_i2c_get16(i2cdev, MAX34451_MFR_MODE); + g_assert_cmphex(i2c_value, ==, RAND_MFR_MODE); + } +} + static void max34451_register_nodes(void) { QOSGraphEdgeOptions opts = { @@ -332,5 +355,6 @@ static void max34451_register_nodes(void) qos_add_test("test_ro_regs", "max34451", test_ro_regs, NULL); qos_add_test("test_ov_faults", "max34451", test_ov_faults, NULL); qos_add_test("test_ot_faults", "max34451", test_ot_faults, NULL); + qos_add_test("test_all_pages", "max34451", test_all_pages, NULL); } libqos_init(max34451_register_nodes); From patchwork Mon Nov 6 11:03:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13446682 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5DE061EB29 for ; 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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id l9-20020adfe589000000b0032f7d7ec4adsm9119404wrm.92.2023.11.06.03.10.04 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:10:05 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Thomas Huth , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Yoshinori Sato Subject: [PULL 57/60] MAINTAINERS: Add include/hw/timer/tmu012.h to the SH4 R2D section Date: Mon, 6 Nov 2023 12:03:29 +0100 Message-ID: <20231106110336.358-58-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Thomas Huth tmu012.h is the header that belongs to hw/timer/sh_timer.c, so we should list it in the same section as sh_timer.c. Signed-off-by: Thomas Huth Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Yoshinori Sato Message-ID: <20231026080011.156325-1-thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index c01c2e6ec0..3014e768f7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1617,6 +1617,7 @@ F: hw/intc/sh_intc.c F: hw/pci-host/sh_pci.c F: hw/timer/sh_timer.c F: include/hw/sh4/sh_intc.h +F: include/hw/timer/tmu012.h Shix R: Yoshinori Sato From patchwork Mon Nov 6 11:03:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13446683 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5BFC318C07 for ; Mon, 6 Nov 2023 11:10:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="Z7bIyyF2" Received: from mail-wr1-x435.google.com (mail-wr1-x435.google.com [IPv6:2a00:1450:4864:20::435]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D38C0CC for ; Mon, 6 Nov 2023 03:10:13 -0800 (PST) Received: by mail-wr1-x435.google.com with SMTP id ffacd0b85a97d-32d895584f1so2598451f8f.1 for ; Mon, 06 Nov 2023 03:10:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699269012; x=1699873812; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cyEPFd8qKgVauKHH+mzQW+99WSkPGmQyoZYgi3VA9Vc=; b=Z7bIyyF2oS+al0C0npkdYuv5lL3BiSEtFNek7DQPLKejCQJhUTWHDIP0wWurpA7xXh MdAtbuMueUhx2S+A9PITajCEtRxlO3AbWZC8L4MuWte10D/TuBc0RML2HSlow2ytuuio EdEfAQCMv91sUaRf1KgS1sMBcsmq2t0KZfkRRnkegpgRMrwg48sA7TKVQwjJ0KJUVBHd tzdZ+04+v6WJyh8pCz04vdWDMoPiFLl1I/NxqHciTSLXOj9Kv/o6AVi1oLzyE8Ja7Yvy ZeuRVpXoJGSNF/Y+7UvasrIlmqtoPx1v1rBvSR2oadSDCZIY/+7WUvHdV83vYyzdVmkY 9VCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699269012; x=1699873812; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cyEPFd8qKgVauKHH+mzQW+99WSkPGmQyoZYgi3VA9Vc=; b=aHz08eQ96USPTe+D1HXIcuQJK/NLPb/TCMCeFx0qs754Qrur/hzAj2PGHp8xtK465m zo3hLbxmorbrQbUG26R9lulNXsEU/sFD9dExIqk8OdoFmtWoNw2Z1F6KXeOajoz0zBsZ CmV06GpLxPD+saLd4CtpxB2bIe9GBCQ0dyLQGHMnJaaUgBdPjgQdp8WbXTMxL7H+iIsU E2aYh9x84E5ShnATUDAtFhQdnR6qRZljUWJPtpJcz2ORUyHy0kOlOGEJoBbTlRoJR4u1 onXkdkU4k/nSuOLq7gs2cVmlIQlO1K9snFXlOolKox3rvGBJIa0Cdal9PLGk5zjXQFa4 ZWFA== X-Gm-Message-State: AOJu0YzT/U3mpkju+VKk1MFidMpgbZEmyJWTRXu6TA7wfD0H9kFO02AE cux2aDlXdNohWy++GZIB4vBb5A== X-Google-Smtp-Source: AGHT+IEMIDW7hBBkWZ0URkD2CfnnnPG/ExOR7Okjzu2uwpb1mtEO/NwWscUpM9JIRDLHPNQlRwIx/g== X-Received: by 2002:a05:6000:1842:b0:32f:7b2e:2dd with SMTP id c2-20020a056000184200b0032f7b2e02ddmr23663996wri.45.1699269012416; Mon, 06 Nov 2023 03:10:12 -0800 (PST) Received: from m1x-phil.lan (176-131-220-199.abo.bbox.fr. [176.131.220.199]) by smtp.gmail.com with ESMTPSA id j5-20020adfe505000000b0031fd849e797sm8761303wrm.105.2023.11.06.03.10.10 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:10:12 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Thomas Huth , Vikram Garhwal , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Pavel Pisa Subject: [PULL 58/60] MAINTAINERS: Add the CAN documentation file to the CAN section Date: Mon, 6 Nov 2023 12:03:30 +0100 Message-ID: <20231106110336.358-59-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Thomas Huth Add can.rst to the corresponding section in MAINTAINERS, so that the maintainers get CC:-ed on corresponding patches. Signed-off-by: Thomas Huth Reviewed-by: Vikram Garhwal Reviewed-by: Philippe Mathieu-Daudé Acked-by: Pavel Pisa Message-ID: <20231027060931.242491-1-thuth@redhat.com> [PMD: Fixed typo in subject] Signed-off-by: Philippe Mathieu-Daudé --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 3014e768f7..c57868c94c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2588,6 +2588,7 @@ W: https://canbus.pages.fel.cvut.cz/ F: net/can/* F: hw/net/can/* F: include/net/can_*.h +F: docs/system/devices/can.rst OpenPIC interrupt controller M: Mark Cave-Ayland From patchwork Mon Nov 6 11:03:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13446684 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 999BB199A7 for ; Mon, 6 Nov 2023 11:10:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="DJtXwULa" Received: from mail-wm1-x334.google.com (mail-wm1-x334.google.com [IPv6:2a00:1450:4864:20::334]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0E4E6D70 for ; Mon, 6 Nov 2023 03:10:19 -0800 (PST) Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-40839807e82so26144695e9.0 for ; Mon, 06 Nov 2023 03:10:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699269018; x=1699873818; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RacUCXaZM0ryRlMszwI6IYYuk8+9tjRt89OkiSY3LIw=; b=DJtXwULaVfLvNnHd7c2dUMhI0PeZ6VPAmZymGaBihCEm2vBizGRralknfw9Zqm3hDl a4mWzVgWgw2+iIctfhFbnIiK8gP7vAWY2ifAPCvWTZJ17J7wqFIamCrbCL/JIuC73aTP eiGAq/NixRg0fcR5ite9uswFQuNPONUngMZTn7YhpXqXmO9p2ZqcMDb60IrLSekrb1a9 HDOoIgjloNSjkqqV7vBU3f/OxWg2hOKBs89vAAhvwj5DzJQF20IPpbDM9GSJ2l4CXtTK h+5mWHd7f7/B0fijwgUx3qROIVqJAbTwSUgHzH95/sbrT2MZ+LRaXdQxy1rJlqS/LYSs VA3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699269018; x=1699873818; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RacUCXaZM0ryRlMszwI6IYYuk8+9tjRt89OkiSY3LIw=; b=SL7BK8cSgZiTepiSxIOnBlRsGfMrjXapufCecwtO8mt53lSYGKHL6coFbVqnmC33sG WVmbrq7hEbha1Bf9nG1DF21kppMa0MbwDfCZfqMMDSipElk6VKTxZJXvIZqm20iFCz4c 44MZqbSFC2+ecz6fBoAIz0YIwWNWcVsjRIx1vwsJSsCd6Z722a1HB8Rw1bGVXVJbAmuD PBYJH1Ik6wQ95uX5TkkwhSsBE7ArG6HqRon4yawztEpLNcHm62kq54wKmFBxidzxcHlC utgzt+QxSBJfy1N8PENUGWgO0hYnXN/0/waIBM3gYgH7KDEjWVmA4mOq6gKey21TCfpR x8OA== X-Gm-Message-State: AOJu0YzSpH9Y52/FnACx/wDaj5yK/Feb+8rsatNojozmceLuRE2MZWMJ yLEhLUK8OMVJO+T7aEbqmTHqzw== X-Google-Smtp-Source: AGHT+IHCLWJGvQCJQCgk0pcjJbrXFUVevq6ZIuy44lY2uK/9jLH2wD0CdVyKAn01kc68xmugzJzUNg== X-Received: by 2002:a05:600c:4e12:b0:406:51a0:17ea with SMTP id b18-20020a05600c4e1200b0040651a017eamr11538636wmq.10.1699269018513; Mon, 06 Nov 2023 03:10:18 -0800 (PST) Received: from m1x-phil.lan (176-131-220-199.abo.bbox.fr. [176.131.220.199]) by smtp.gmail.com with ESMTPSA id c12-20020a05600c0a4c00b0040775501256sm12046304wmq.16.2023.11.06.03.10.17 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:10:18 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , =?utf-8?q?Phil?= =?utf-8?q?ippe_Mathieu-Daud=C3=A9?= Subject: [PULL 59/60] MAINTAINERS: update libvirt devel mailing list address Date: Mon, 6 Nov 2023 12:03:31 +0100 Message-ID: <20231106110336.358-60-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Daniel P. Berrangé Effective immediately, the libvirt project has moved its list off libvir-list@redhat.com, to devel@lists.libvirt.org Signed-off-by: Daniel P. Berrangé Message-ID: <20231027095643.2842382-1-berrange@redhat.com> Signed-off-by: Philippe Mathieu-Daudé --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index c57868c94c..3582e2a71a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4049,7 +4049,7 @@ F: gitdm.config F: contrib/gitdm/* Incompatible changes -R: libvir-list@redhat.com +R: devel@lists.libvirt.org F: docs/about/deprecated.rst Build System From patchwork Mon Nov 6 11:03:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13446685 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 810621A708 for ; Mon, 6 Nov 2023 11:10:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="n8l9ZI/O" Received: from mail-lf1-x12a.google.com (mail-lf1-x12a.google.com [IPv6:2a00:1450:4864:20::12a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 95BFA10DD for ; Mon, 6 Nov 2023 03:10:26 -0800 (PST) Received: by mail-lf1-x12a.google.com with SMTP id 2adb3069b0e04-509109104e2so5579183e87.3 for ; Mon, 06 Nov 2023 03:10:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1699269025; x=1699873825; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xBR3Oh8zClbS1YQ62m6eKxWZ4Ons8qsU0E4Liv4Rvg0=; b=n8l9ZI/O3VCPjKKwhlguMHar3XNfCp7tyCNywAL0BlErgA6BQ44f+TrfMzJpGvrmay GhSMjsLWYt2kRYr/gx9yPXI3XsANxJlpn0mynrB4nd3xTRMEb51jYZxLN4elHi8YPYAl dMsMC7qS+HFUkbyxjpIKMcLbNX61pndH1OcawcZBzxOXwPHzveEsjknwlp6jllT/2a3Q MbsMnN+X4P8y5XyUc67pcDhpMzzyIhk8FMr9eMvwuygcngZM53aKryBF5+1xRxQcphag CQSL8lrrKspVptWaDoU3Qe6kV8LlOzYVtLUwyYTslxu9pHz+uzOY6TQq0X0eGx/4Ylt9 8BEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699269025; x=1699873825; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xBR3Oh8zClbS1YQ62m6eKxWZ4Ons8qsU0E4Liv4Rvg0=; b=jYGeXkpH5XMq2l5B/lUKKMo8VZipXo6Aw2dtM/4AWXQbLv8ZUGQf3SNceNFH/UvAZG xZrQ77s80Uf8FdnIVHWeAu3fYiLA2HOJeHdqZ4RXdIGBUHC9wjBJlkrnUP/zCUPbW+mF 3qLlkRC5ADNiZW4u++z7zysvW1RN6c5jRohdIPr58TTmFV6sOrz9JcyrxNX70S+MpcJB EvSMqvU1cgYw29YFCGSQxovl2hrUFSr7OgVOu0wY27rxd3aw5T726S/KIHQAuF5nShiv yar2OLNz/hwsJ+0JnVeePBKMwYsEY4qFpUpX9ionUXIcVH6WmmUeWiWRJhyCbE2s045W ZCrQ== X-Gm-Message-State: AOJu0Yx7ft7/V9rHilitNEfFzmtkPt+IkBVqGO2BBVHxFumx0b0tvCkt PjjCXBeadn1/orzCI3V5p1NBtw== X-Google-Smtp-Source: AGHT+IFMIKgYKaG2x26tSZ+5foWBGqKNS7CQHWd9OLbklpXVybTTE5AVAduGsFeWircKlsRiiuVWlA== X-Received: by 2002:a05:6512:318f:b0:509:45ed:1083 with SMTP id i15-20020a056512318f00b0050945ed1083mr12662290lfe.40.1699269024745; Mon, 06 Nov 2023 03:10:24 -0800 (PST) Received: from m1x-phil.lan (176-131-220-199.abo.bbox.fr. [176.131.220.199]) by smtp.gmail.com with ESMTPSA id bh7-20020a05600c3d0700b00401b242e2e6sm11965729wmb.47.2023.11.06.03.10.23 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:10:24 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, Adrian Wowk , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Gerd Hoffmann Subject: [PULL 60/60] ui/sdl2: use correct key names in win title on mac Date: Mon, 6 Nov 2023 12:03:32 +0100 Message-ID: <20231106110336.358-61-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Adrian Wowk Previously, when using the SDL2 UI on MacOS, the title bar uses incorrect key names (such as Ctrl and Alt instead of the standard MacOS key symbols like ⌃ and ⌥). This commit changes sdl_update_caption in ui/sdl2.c to use the correct symbols when compiling for MacOS (CONFIG_DARWIN is defined). Unfortunately, standard Mac keyboards do not include a "Right-Ctrl" key, so in the case that the SDL grab mode is set to HOT_KEY_MOD_RCTRL, the default text is still used. Signed-off-by: Adrian Wowk Acked-by: Marc-André Lureau Tested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20231030024119.28342-1-dev@adrianwowk.com> Signed-off-by: Philippe Mathieu-Daudé --- ui/sdl2.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/ui/sdl2.c b/ui/sdl2.c index fbfdb64e90..4971963f00 100644 --- a/ui/sdl2.c +++ b/ui/sdl2.c @@ -172,11 +172,19 @@ static void sdl_update_caption(struct sdl2_console *scon) status = " [Stopped]"; } else if (gui_grab) { if (alt_grab) { +#ifdef CONFIG_DARWIN + status = " - Press ⌃⌥⇧G to exit grab"; +#else status = " - Press Ctrl-Alt-Shift-G to exit grab"; +#endif } else if (ctrl_grab) { status = " - Press Right-Ctrl-G to exit grab"; } else { +#ifdef CONFIG_DARWIN + status = " - Press ⌃⌥G to exit grab"; +#else status = " - Press Ctrl-Alt-G to exit grab"; +#endif } }