From patchwork Tue Nov 7 00:14:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13447613 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 14B68C4332F for ; Tue, 7 Nov 2023 00:15:16 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 36D4910E483; Tue, 7 Nov 2023 00:15:13 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8D2EB10E48B; Tue, 7 Nov 2023 00:15:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1699316110; x=1730852110; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=CesbfyjL4I7PK4dqIP+5yt8TLL9yr35zx0S2rfjlcIU=; b=HE81X+ipYqBiKjsQE5JDbf6p7ypyrEiv6yPN3OhgwS75QznTq8OeBdUO om/TNNsdkDw2ZJ8DWo0nRbyZVNhQxzwxax7OJs8sb5KTXjmWyd5GzrD6J 7sBWHZ3pj0blMZMs1fFG181TkwQVg7oJAP+cE6C2HgkZkk40ryksdiQ5E j32jbQXCsdRIyqcQgRs2oYUve5NP8iGOpHn78+2QSZo+0G13zMPVIvP2u +LuVhv6meqXJFIRdhHgHYRDadYz63G3SJ3SBrwqQi+BgWBQT5cW2sJYov L7KkUzgEUvgZ9iNTF5RnaB0bHa0To7+rxJ5vbpSVKmmA1SCCqFsvO3RmM g==; X-IronPort-AV: E=McAfee;i="6600,9927,10886"; a="369596194" X-IronPort-AV: E=Sophos;i="6.03,282,1694761200"; d="scan'208";a="369596194" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Nov 2023 16:15:10 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10886"; a="853177980" X-IronPort-AV: E=Sophos;i="6.03,282,1694761200"; d="scan'208";a="853177980" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Nov 2023 16:15:07 -0800 From: Imre Deak To: intel-gfx@lists.freedesktop.org Date: Tue, 7 Nov 2023 02:14:58 +0200 Message-Id: <20231107001505.3370108-1-imre.deak@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231030155843.2251023-10-imre.deak@intel.com> References: <20231030155843.2251023-10-imre.deak@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v5 09/30] drm/dp: Add helpers to calculate the link BW overhead X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org, Maxime Ripard Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add helpers drivers can use to calculate the BW allocation overhead - due to SSC, FEC, DSC and data alignment on symbol cycles - and the channel coding efficiency - due to the 8b/10b, 128b/132b encoding. On 128b/132b links the FEC overhead is part of the coding efficiency, so not accounted for in the BW allocation overhead. The drivers can use these functions to calculate a ratio, controlling the stream symbol insertion rate of the source device in each SST TU or MST MTP frame. Drivers can calculate this m/n = (pixel_data_rate * drm_dp_bw_overhead()) / (link_data_rate * drm_dp_bw_channel_coding_efficiency()) ratio for a given link and pixel stream and with that the slots_per_mtp = CEIL(64 * m / n) allocated slots per MTP for the stream in a link frame and with that the pbn = slots_per_mtp * drm_mst_get_pbn_divider() allocated PBNs for the stream on the MST link path. Take drm_dp_bw_overhead() into use in drm_dp_calc_pbn_mode(), for drivers calculating the PBN value directly. v2: - Add dockbook description to drm_dp_bw_channel_coding_efficiency(). (LKP). - Clarify the way m/n ratio is calculated in the commit log. v3: - Fix compile breakage for !CONFIG_BACKLIGHT_CLASS_DEVICE. (LKP) - Account for FEC_PM overhead (+ 0.0015625 %), add comment with the formula to calculate the total FEC overhead. (Ville) v4: - Rename DRM_DP_OVERHEAD_SSC to DRM_DP_OVERHEAD_SSC_REF_CLK. (Ville) v5: - Clarify in the commit log what MTP means. - Simplify the commit log's formula to calculate PBN. Cc: Lyude Paul Cc: Ville Syrjälä Cc: kernel test robot Cc: dri-devel@lists.freedesktop.org Reviewed-by: Stanislav Lisovskiy (v2) Acked-by: Maxime Ripard Signed-off-by: Imre Deak Reviewed-by: Lyude Paul --- drivers/gpu/drm/display/drm_dp_helper.c | 132 ++++++++++++++++++ drivers/gpu/drm/display/drm_dp_mst_topology.c | 23 ++- include/drm/display/drm_dp_helper.h | 11 ++ 3 files changed, 160 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c index e5d7970a9ddd0..72ba9ae89f862 100644 --- a/drivers/gpu/drm/display/drm_dp_helper.c +++ b/drivers/gpu/drm/display/drm_dp_helper.c @@ -3900,3 +3900,135 @@ int drm_panel_dp_aux_backlight(struct drm_panel *panel, struct drm_dp_aux *aux) EXPORT_SYMBOL(drm_panel_dp_aux_backlight); #endif + +/* See DP Standard v2.1 2.6.4.4.1.1, 2.8.4.4, 2.8.7 */ +static int drm_dp_link_symbol_cycles(int lane_count, int pixels, int bpp_x16, + int symbol_size, bool is_mst) +{ + int cycles = DIV_ROUND_UP(pixels * bpp_x16, 16 * symbol_size * lane_count); + int align = is_mst ? 4 / lane_count : 1; + + return ALIGN(cycles, align); +} + +static int drm_dp_link_dsc_symbol_cycles(int lane_count, int pixels, int slice_count, + int bpp_x16, int symbol_size, bool is_mst) +{ + int slice_pixels = DIV_ROUND_UP(pixels, slice_count); + int slice_data_cycles = drm_dp_link_symbol_cycles(lane_count, slice_pixels, + bpp_x16, symbol_size, is_mst); + int slice_eoc_cycles = is_mst ? 4 / lane_count : 1; + + return slice_count * (slice_data_cycles + slice_eoc_cycles); +} + +/** + * drm_dp_bw_overhead - Calculate the BW overhead of a DP link stream + * @lane_count: DP link lane count + * @hactive: pixel count of the active period in one scanline of the stream + * @dsc_slice_count: DSC slice count if @flags/DRM_DP_LINK_BW_OVERHEAD_DSC is set + * @bpp_x16: bits per pixel in .4 binary fixed point + * @flags: DRM_DP_OVERHEAD_x flags + * + * Calculate the BW allocation overhead of a DP link stream, depending + * on the link's + * - @lane_count + * - SST/MST mode (@flags / %DRM_DP_OVERHEAD_MST) + * - symbol size (@flags / %DRM_DP_OVERHEAD_UHBR) + * - FEC mode (@flags / %DRM_DP_OVERHEAD_FEC) + * - SSC/REF_CLK mode (@flags / %DRM_DP_OVERHEAD_SSC_REF_CLK) + * as well as the stream's + * - @hactive timing + * - @bpp_x16 color depth + * - compression mode (@flags / %DRM_DP_OVERHEAD_DSC). + * Note that this overhead doesn't account for the 8b/10b, 128b/132b + * channel coding efficiency, for that see + * @drm_dp_link_bw_channel_coding_efficiency(). + * + * Returns the overhead as 100% + overhead% in 1ppm units. + */ +int drm_dp_bw_overhead(int lane_count, int hactive, + int dsc_slice_count, + int bpp_x16, unsigned long flags) +{ + int symbol_size = flags & DRM_DP_BW_OVERHEAD_UHBR ? 32 : 8; + bool is_mst = flags & DRM_DP_BW_OVERHEAD_MST; + u32 overhead = 1000000; + int symbol_cycles; + + /* + * DP Standard v2.1 2.6.4.1 + * SSC downspread and ref clock variation margin: + * 5300ppm + 300ppm ~ 0.6% + */ + if (flags & DRM_DP_BW_OVERHEAD_SSC_REF_CLK) + overhead += 6000; + + /* + * DP Standard v2.1 2.6.4.1.1, 3.5.1.5.4: + * FEC symbol insertions for 8b/10b channel coding: + * After each 250 data symbols on 2-4 lanes: + * 250 LL + 5 FEC_PARITY_PH + 1 CD_ADJ (256 byte FEC block) + * After each 2 x 250 data symbols on 1 lane: + * 2 * 250 LL + 11 FEC_PARITY_PH + 1 CD_ADJ (512 byte FEC block) + * After 256 (2-4 lanes) or 128 (1 lane) FEC blocks: + * 256 * 256 bytes + 1 FEC_PM + * or + * 128 * 512 bytes + 1 FEC_PM + * (256 * 6 + 1) / (256 * 250) = 2.4015625 % + */ + if (flags & DRM_DP_BW_OVERHEAD_FEC) + overhead += 24016; + + /* + * DP Standard v2.1 2.7.9, 5.9.7 + * The FEC overhead for UHBR is accounted for in its 96.71% channel + * coding efficiency. + */ + WARN_ON((flags & DRM_DP_BW_OVERHEAD_UHBR) && + (flags & DRM_DP_BW_OVERHEAD_FEC)); + + if (flags & DRM_DP_BW_OVERHEAD_DSC) + symbol_cycles = drm_dp_link_dsc_symbol_cycles(lane_count, hactive, + dsc_slice_count, + bpp_x16, symbol_size, + is_mst); + else + symbol_cycles = drm_dp_link_symbol_cycles(lane_count, hactive, + bpp_x16, symbol_size, + is_mst); + + return DIV_ROUND_UP_ULL(mul_u32_u32(symbol_cycles * symbol_size * lane_count, + overhead * 16), + hactive * bpp_x16); +} +EXPORT_SYMBOL(drm_dp_bw_overhead); + +/** + * drm_dp_bw_channel_coding_efficiency - Get a DP link's channel coding efficiency + * @is_uhbr: Whether the link has a 128b/132b channel coding + * + * Return the channel coding efficiency of the given DP link type, which is + * either 8b/10b or 128b/132b (aka UHBR). The corresponding overhead includes + * the 8b -> 10b, 128b -> 132b pixel data to link symbol conversion overhead + * and for 128b/132b any link or PHY level control symbol insertion overhead + * (LLCP, FEC, PHY sync, see DP Standard v2.1 3.5.2.18). For 8b/10b the + * corresponding FEC overhead is BW allocation specific, included in the value + * returned by drm_dp_bw_overhead(). + * + * Returns the efficiency in the 100%/coding-overhead% ratio in + * 1ppm units. + */ +int drm_dp_bw_channel_coding_efficiency(bool is_uhbr) +{ + if (is_uhbr) + return 967100; + else + /* + * Note that on 8b/10b MST the efficiency is only + * 78.75% due to the 1 out of 64 MTPH packet overhead, + * not accounted for here. + */ + return 800000; +} +EXPORT_SYMBOL(drm_dp_bw_channel_coding_efficiency); diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c index cc0a8fe84d290..4d72c9a32026e 100644 --- a/drivers/gpu/drm/display/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c @@ -4726,17 +4726,28 @@ EXPORT_SYMBOL(drm_dp_check_act_status); int drm_dp_calc_pbn_mode(int clock, int bpp) { /* - * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006 * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on * common multiplier to render an integer PBN for all link rate/lane * counts combinations * calculate - * peak_kbps *= (1006/1000) - * peak_kbps *= (64/54) - * peak_kbps *= 8 convert to bytes + * peak_kbps = clock * bpp / 16 + * peak_kbps *= SSC overhead / 1000000 + * peak_kbps /= 8 convert to Kbytes + * peak_kBps *= (64/54) / 1000 convert to PBN */ - return DIV_ROUND_UP_ULL(mul_u32_u32(clock * bpp, 64 * 1006 >> 4), - 1000 * 8 * 54 * 1000); + /* + * TODO: Use the actual link and mode parameters to calculate + * the overhead. For now it's assumed that these are + * 4 link lanes, 4096 hactive pixels, which don't add any + * significant data padding overhead and that there is no DSC + * or FEC overhead. + */ + int overhead = drm_dp_bw_overhead(4, 4096, 0, bpp, + DRM_DP_BW_OVERHEAD_MST | + DRM_DP_BW_OVERHEAD_SSC_REF_CLK); + + return DIV64_U64_ROUND_UP(mul_u32_u32(clock * bpp, 64 * overhead >> 4), + 1000000ULL * 8 * 54 * 1000); } EXPORT_SYMBOL(drm_dp_calc_pbn_mode); diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h index da94932f4262b..caee29d28463c 100644 --- a/include/drm/display/drm_dp_helper.h +++ b/include/drm/display/drm_dp_helper.h @@ -788,4 +788,15 @@ bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZ const u8 port_cap[4], u8 color_spc); int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc); +#define DRM_DP_BW_OVERHEAD_MST BIT(0) +#define DRM_DP_BW_OVERHEAD_UHBR BIT(1) +#define DRM_DP_BW_OVERHEAD_SSC_REF_CLK BIT(2) +#define DRM_DP_BW_OVERHEAD_FEC BIT(3) +#define DRM_DP_BW_OVERHEAD_DSC BIT(4) + +int drm_dp_bw_overhead(int lane_count, int hactive, + int dsc_slice_count, + int bpp_x16, unsigned long flags); +int drm_dp_bw_channel_coding_efficiency(bool is_uhbr); + #endif /* _DRM_DP_HELPER_H_ */ From patchwork Tue Nov 7 00:14:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13447614 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 58573C4167B for ; Tue, 7 Nov 2023 00:15:17 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BC74710E485; Tue, 7 Nov 2023 00:15:13 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id D2AF210E483 for ; Tue, 7 Nov 2023 00:15:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1699316111; x=1730852111; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=w44LXLN+IIGqLyhV/zKcpHWWWCrcvR7Mfk+g56GHGTo=; b=DaN442/8eW0cZ0CFVagYgTqztLp6rUBtSbr3Y89ywW8B7hi0pwN7A5vB p7s1rwY0vR31FSi1a9NXWqDrvHT9QMcTCiypC35NwO+/zbQnycsyAwTTi nWcd2t9H2YEnNgTRK9zdEwh4BDdqIgg4CnlIp2zTt56weUpOei8DYs4lh hz+CO0kaMeEsNGXIAIpPXC6gF2sjk0JSzTHpEgLFS+nLkO82bmyaQRCsI wittIZMyBanLVhWLcD8vOeynOW9aAX741pb1zFAaepmYj1Kmqu487Deqm ydtZlTmqNyB55xXiuSP2JUd3nQzeGLCs656QQ035IDyku7MvTNGK2reN4 g==; X-IronPort-AV: E=McAfee;i="6600,9927,10886"; a="369596198" X-IronPort-AV: E=Sophos;i="6.03,282,1694761200"; d="scan'208";a="369596198" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Nov 2023 16:15:11 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10886"; a="853177985" X-IronPort-AV: E=Sophos;i="6.03,282,1694761200"; d="scan'208";a="853177985" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Nov 2023 16:15:10 -0800 From: Imre Deak To: intel-gfx@lists.freedesktop.org Date: Tue, 7 Nov 2023 02:14:59 +0200 Message-Id: <20231107001505.3370108-2-imre.deak@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231030155843.2251023-14-imre.deak@intel.com> References: <20231030155843.2251023-14-imre.deak@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v5 13/30] drm/i915/dp_mst: Account for FEC and DSC overhead during BW allocation X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Atm, the BW allocated for an MST stream doesn't take into account the DSC control symbol (EOC) and data alignment overhead on the local (first downstream) MST link (reflected by the data M/N/TU values) and - besides the above overheads - the FEC symbol overhead on 8b/10b remote (after a downstream branch device) MST links. In addition the FEC overhead used on the local link is a fixed amount, which only applies to certain modes, but not enough for all modes; add a code comment clarifying this. Fix the above by calculating the data M/N values with the total BW overhead (not including the SSC overhead, since this isn't enabled by the source device) and using this the PBN and TU values for the local link and PBN for remote links (including SSC, since this is mandatory for links after downstream branch devices). For now keep the current fixed FEC overhead as a minimum, since this is what bspec requires for audio functionality. Calculate the effective link BW in a clearer way, applying the channel coding efficiency based on the coding type. The calculation was correct for 8b/10b, but not for 128b/132b links; this patch leaves the behavior for this unchanged, leaving the fix for a follow-up. v2: - Fix TU size programmed to the HW, making it match the payload size programmed to the payload table. v3: - Add code comment about the connection between the payload's size in the payload table and the corresponding PBN value. (Ville) - Add WARN_ON(remote_m_n.tu < dp_m_n.tu). (Ville) - Add code comment about factors not accounted for by the BW calculation in intel_dp_mst_mode_valid_ctx() (and compute config). (Ville) - Simplify calculation of PBN to remote_m_n.tu * mst_state->pbn_div. Cc: Ville Syrjälä Reviewed-by: Stanislav Lisovskiy (v1) Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 124 ++++++++++++++++---- 1 file changed, 99 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 1f6fbab7d4ada..9d6b76d1a52a7 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -67,6 +67,63 @@ static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int bpp return 0; } +static int intel_dp_mst_bw_overhead(const struct intel_crtc_state *crtc_state, + const struct intel_connector *connector, + bool ssc, bool dsc, int bpp) +{ + const struct drm_display_mode *adjusted_mode = + &crtc_state->hw.adjusted_mode; + unsigned long flags = DRM_DP_BW_OVERHEAD_MST; + int dsc_slice_count = 0; + int overhead; + + flags |= intel_dp_is_uhbr(crtc_state) ? DRM_DP_BW_OVERHEAD_UHBR : 0; + flags |= ssc ? DRM_DP_BW_OVERHEAD_SSC_REF_CLK : 0; + flags |= crtc_state->fec_enable ? DRM_DP_BW_OVERHEAD_FEC : 0; + + if (dsc) { + flags |= DRM_DP_BW_OVERHEAD_DSC; + /* TODO: add support for bigjoiner */ + dsc_slice_count = intel_dp_dsc_get_slice_count(connector, + adjusted_mode->clock, + adjusted_mode->hdisplay, + false); + } + + overhead = drm_dp_bw_overhead(crtc_state->lane_count, + adjusted_mode->hdisplay, + dsc_slice_count, + to_bpp_x16(bpp), + flags); + + /* + * TODO: clarify whether a minimum required by the fixed FEC overhead + * in the bspec audio programming sequence is required here. + */ + return max(overhead, intel_dp_bw_fec_overhead(crtc_state->fec_enable)); +} + +static void intel_dp_mst_compute_m_n(const struct intel_crtc_state *crtc_state, + const struct intel_connector *connector, + bool ssc, bool dsc, + int bpp, + struct intel_link_m_n *m_n) +{ + const struct drm_display_mode *adjusted_mode = + &crtc_state->hw.adjusted_mode; + int overhead = intel_dp_mst_bw_overhead(crtc_state, + connector, + ssc, dsc, bpp); + + intel_link_compute_m_n(bpp, crtc_state->lane_count, + adjusted_mode->crtc_clock, + crtc_state->port_clock, + overhead, + m_n); + + m_n->tu = DIV_ROUND_UP_ULL(mul_u32_u32(m_n->data_m, 64), m_n->data_n); +} + static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state, int max_bpp, @@ -107,14 +164,40 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder, crtc_state->lane_count); for (bpp = max_bpp; bpp >= min_bpp; bpp -= step) { + struct intel_link_m_n remote_m_n; + int link_bpp; + drm_dbg_kms(&i915->drm, "Trying bpp %d\n", bpp); ret = intel_dp_mst_check_constraints(i915, bpp, adjusted_mode, crtc_state, dsc); if (ret) continue; - crtc_state->pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock, - bpp << 4); + link_bpp = dsc ? bpp : + intel_dp_output_bpp(crtc_state->output_format, bpp); + + intel_dp_mst_compute_m_n(crtc_state, connector, false, dsc, link_bpp, + &crtc_state->dp_m_n); + intel_dp_mst_compute_m_n(crtc_state, connector, true, dsc, link_bpp, + &remote_m_n); + + /* + * The TU size programmed to the HW determines which slots in + * an MTP frame are used for this stream, which needs to match + * the payload size programmed to the first downstream branch + * device's payload table. + * + * Note that atm the payload's PBN value DRM core sends via + * the ALLOCATE_PAYLOAD side-band message matches the payload + * size (which it calculates from the PBN value) it programs + * to the first branch device's payload table. The allocation + * in the payload table could be reduced though (to + * crtc_state->dp_m_n.tu), provided that the driver doesn't + * enable SSC on the corresponding link. + */ + drm_WARN_ON(&i915->drm, remote_m_n.tu < crtc_state->dp_m_n.tu); + crtc_state->dp_m_n.tu = remote_m_n.tu; + crtc_state->pbn = remote_m_n.tu * mst_state->pbn_div; slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst_mgr, connector->port, @@ -123,6 +206,8 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder, return slots; if (slots >= 0) { + drm_WARN_ON(&i915->drm, slots != remote_m_n.tu); + ret = drm_dp_mst_atomic_check(state); /* * If we got slots >= 0 and we can fit those based on check @@ -156,10 +241,7 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder, struct drm_connector_state *conn_state, struct link_config_limits *limits) { - const struct drm_display_mode *adjusted_mode = - &crtc_state->hw.adjusted_mode; int slots = -EINVAL; - int link_bpp; /* * FIXME: allocate the BW according to link_bpp, which in the case of @@ -174,16 +256,6 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder, if (slots < 0) return slots; - link_bpp = intel_dp_output_bpp(crtc_state->output_format, crtc_state->pipe_bpp); - - intel_link_compute_m_n(link_bpp, - crtc_state->lane_count, - adjusted_mode->crtc_clock, - crtc_state->port_clock, - intel_dp_bw_fec_overhead(crtc_state->fec_enable), - &crtc_state->dp_m_n); - crtc_state->dp_m_n.tu = slots; - return 0; } @@ -195,8 +267,6 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder, struct intel_connector *connector = to_intel_connector(conn_state->connector); struct drm_i915_private *i915 = to_i915(connector->base.dev); - const struct drm_display_mode *adjusted_mode = - &crtc_state->hw.adjusted_mode; int slots = -EINVAL; int i, num_bpc; u8 dsc_bpc[3] = {}; @@ -271,14 +341,6 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder, return slots; } - intel_link_compute_m_n(crtc_state->dsc.compressed_bpp, - crtc_state->lane_count, - adjusted_mode->crtc_clock, - crtc_state->port_clock, - intel_dp_bw_fec_overhead(crtc_state->fec_enable), - &crtc_state->dp_m_n); - crtc_state->dp_m_n.tu = slots; - return 0; } static int intel_dp_mst_update_slots(struct intel_encoder *encoder, @@ -987,6 +1049,18 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector, if (ret) return ret; + /* + * TODO: + * - Also check if compression would allow for the mode + * - Calculate the overhead using drm_dp_bw_overhead() / + * drm_dp_bw_channel_coding_efficiency(), similarly to the + * compute config code, as drm_dp_calc_pbn_mode() doesn't + * account with all the overheads. + * - Check here and during compute config the BW reported by + * DFP_Link_Available_Payload_Bandwidth_Number (or the + * corresponding link capabilities of the sink) in case the + * stream is uncompressed for it by the last branch device. + */ if (mode_rate > max_rate || mode->clock > max_dotclk || drm_dp_calc_pbn_mode(mode->clock, min_bpp << 4) > port->full_pbn) { *status = MODE_CLOCK_HIGH; From patchwork Tue Nov 7 00:15:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13447615 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CF144C4167D for ; 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X-IronPort-AV: E=McAfee;i="6600,9927,10886"; a="369596200" X-IronPort-AV: E=Sophos;i="6.03,282,1694761200"; d="scan'208";a="369596200" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Nov 2023 16:15:12 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10886"; a="853177991" X-IronPort-AV: E=Sophos;i="6.03,282,1694761200"; d="scan'208";a="853177991" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Nov 2023 16:15:11 -0800 From: Imre Deak To: intel-gfx@lists.freedesktop.org Date: Tue, 7 Nov 2023 02:15:00 +0200 Message-Id: <20231107001505.3370108-3-imre.deak@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231030155843.2251023-16-imre.deak@intel.com> References: <20231030155843.2251023-16-imre.deak@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v5 15/30] drm/i915/dp_mst: Program the DSC PPS SDP for each stream X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Atm the DSC PPS SDP is programmed only if the first stream is compressed and then it's programmed only for the first stream. This left all other compressed streams blank. Program the SDP for all streams. v2: - Rebase on upstream include "intel_vdsc.h" change. Reviewed-by: Stanislav Lisovskiy Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_ddi.c | 12 +++++++----- drivers/gpu/drm/i915/display/intel_dp_mst.c | 1 + 2 files changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index c75fd00e360ac..87fa7f7369254 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -2505,7 +2505,8 @@ static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state, /* 6.o Configure and enable FEC if needed */ intel_ddi_enable_fec(encoder, crtc_state); - intel_dsc_dp_pps_write(encoder, crtc_state); + if (!is_mst) + intel_dsc_dp_pps_write(encoder, crtc_state); } static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, @@ -2643,7 +2644,8 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, /* 7.l Configure and enable FEC if needed */ intel_ddi_enable_fec(encoder, crtc_state); - intel_dsc_dp_pps_write(encoder, crtc_state); + if (!is_mst) + intel_dsc_dp_pps_write(encoder, crtc_state); } static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, @@ -2705,10 +2707,10 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, intel_ddi_enable_fec(encoder, crtc_state); - if (!is_mst) + if (!is_mst) { intel_ddi_enable_transcoder_clock(encoder, crtc_state); - - intel_dsc_dp_pps_write(encoder, crtc_state); + intel_dsc_dp_pps_write(encoder, crtc_state); + } } static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index c9faac174aa2c..5efc3cea73e52 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -860,6 +860,7 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state, if (DISPLAY_VER(dev_priv) < 12 || !first_mst_stream) intel_ddi_enable_transcoder_clock(encoder, pipe_config); + intel_dsc_dp_pps_write(&dig_port->base, pipe_config); intel_ddi_set_dp_msa(pipe_config, conn_state); } From patchwork Tue Nov 7 00:15:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13447616 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D62ABC4332F for ; Tue, 7 Nov 2023 00:15:19 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2628810E489; Tue, 7 Nov 2023 00:15:18 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4853F10E489 for ; Tue, 7 Nov 2023 00:15:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1699316114; x=1730852114; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=rTvim+IxdgIwYSmho5PE+TOCtXtydvZPzNkI2rGHceQ=; b=LHbq6kX7DG1id4bb8DItdxkg60XV8AHISTQDaYb3KCx/VWbNfMdVDCqu CnjcEIioW+MpPtR/I3AfdYc02RCMSwrd291wFKj5p8g8jJy45JUhZw+pj 00iY6/xZGs+QDQ8mszKSAl3RYUlGXPUyH1/gMzV+1zgVNiFTlq547C60K dgMh8QGUG+9JlfDHKyeATOsiwmcQzPIwzpnDPZGLLd3CgozVLMGK/JnuH SEXgD1yrN7seYEMUGywzVXJ6S4SEDOgQIw+4zQuD0io9lp5wKkaMdCl9t 6ljGgyX+wUFpTJkHMrOE+t75ldOdj6KRO8c3oWnlltkWPSH/qNbbOmin6 w==; X-IronPort-AV: E=McAfee;i="6600,9927,10886"; a="369596203" X-IronPort-AV: E=Sophos;i="6.03,282,1694761200"; d="scan'208";a="369596203" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Nov 2023 16:15:14 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10886"; a="853177998" X-IronPort-AV: E=Sophos;i="6.03,282,1694761200"; d="scan'208";a="853177998" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Nov 2023 16:15:13 -0800 From: Imre Deak To: intel-gfx@lists.freedesktop.org Date: Tue, 7 Nov 2023 02:15:01 +0200 Message-Id: <20231107001505.3370108-4-imre.deak@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231030155843.2251023-22-imre.deak@intel.com> References: <20231030155843.2251023-22-imre.deak@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v5 21/30] drm/i915/dp_mst: Handle the Synaptics HBlank expansion quirk X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The Synaptics MST hubs expose some sink EDID modes with a reduced HBLANK period, presumedly to save BW, which the hub expands before forwarding the stream to the sink. In particular a 4k mode with a standard CVT HBLANK period is exposed with either a CVT reduced blank RBv1,v2 (80, 160 pixel) or a non-CVT 56 pixel HBLANK period. The DP standard describes the above HBLANK expansion functionality, but it requires enabling this explicitly, whereas these hubs apply the expansion transparently. In some TBT docks with such a Synaptics hub (DELL WD22TB4) the above modes will work okay until DSC decompression is enabled in the hub for the given sink, but after this the same mode will not work reliably in decompressed mode. In another TBT dock (Thinkpad 40B0) the above modes will not work in uncompressed/18bpp mode (regardless of whether DSC decompression was enabled before or not). As a workaround force enable DSC for such modes. Apply the WA when the HBLANK period is 300ns or below, matching the above tested modes with a 533.25MHz dotclock and maximum 160 HBLANK pixels. OTOH DSC for these modes will only work above a certain compressed bpp threshold which depends on the link rate, so apply this limit as well in the workaround. On platforms, pipe/port configurations where DSC is not supported, for instance on ICL where DSC/MST is still work-in-progress, limit the minimum link bpp to 24. Apply the workaround only for Synaptics hubs which support the HBLANK expansion. v2: - Apply the WA whenever the HBLANK period is 300ns or below. v3: - Clarify in the commit log the failure modes of the different docks. - Handle platforms/pipe/port configurations without DSC support. Reviewed-by: Stanislav Lisovskiy (v1) Signed-off-by: Imre Deak --- .../drm/i915/display/intel_display_types.h | 2 + drivers/gpu/drm/i915/display/intel_dp_mst.c | 133 +++++++++++++++++- 2 files changed, 131 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 047fe3f8905ac..6c2f18ef543e4 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -624,6 +624,8 @@ struct intel_connector { struct drm_dp_aux *dsc_decompression_aux; u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]; u8 fec_capability; + + u8 dsc_hblank_expansion_quirk:1; } dp; /* Work struct to schedule a uevent on link train failure */ diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 4d0827a3cd9b1..4f066a868b9a2 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -378,8 +378,91 @@ intel_dp_mst_dsc_source_support(const struct intel_crtc_state *crtc_state) return DISPLAY_VER(i915) >= 12 && intel_dsc_source_support(crtc_state); } +static int mode_hblank_period_ns(const struct drm_display_mode *mode) +{ + return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(mode->htotal - mode->hdisplay, + NSEC_PER_SEC / 1000), + mode->crtc_clock); +} + +static bool +hblank_expansion_quirk_needs_dsc(const struct intel_connector *connector, + const struct intel_crtc_state *crtc_state) +{ + const struct drm_display_mode *adjusted_mode = + &crtc_state->hw.adjusted_mode; + + if (!connector->dp.dsc_hblank_expansion_quirk) + return false; + + if (mode_hblank_period_ns(adjusted_mode) > 300) + return false; + + return true; +} + +static bool +adjust_limits_for_dsc_hblank_expansion_quirk(const struct intel_connector *connector, + const struct intel_crtc_state *crtc_state, + struct link_config_limits *limits, + bool dsc) +{ + struct drm_i915_private *i915 = to_i915(connector->base.dev); + const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + int min_bpp_x16 = limits->link.min_bpp_x16; + + if (!hblank_expansion_quirk_needs_dsc(connector, crtc_state)) + return true; + + if (!dsc) { + if (intel_dp_mst_dsc_source_support(crtc_state)) { + drm_dbg_kms(&i915->drm, + "[CRTC:%d:%s][CONNECTOR:%d:%s] DSC needed by hblank expansion quirk\n", + crtc->base.base.id, crtc->base.name, + connector->base.base.id, connector->base.name); + return false; + } + + drm_dbg_kms(&i915->drm, + "[CRTC:%d:%s][CONNECTOR:%d:%s] Increasing link min bpp to 24 due to hblank expansion quirk\n", + crtc->base.base.id, crtc->base.name, + connector->base.base.id, connector->base.name); + + if (limits->link.max_bpp_x16 < to_bpp_x16(24)) + return false; + + limits->link.min_bpp_x16 = to_bpp_x16(24); + + return true; + } + + drm_WARN_ON(&i915->drm, limits->min_rate != limits->max_rate); + + if (limits->max_rate < 540000) + min_bpp_x16 = to_bpp_x16(13); + else if (limits->max_rate < 810000) + min_bpp_x16 = to_bpp_x16(10); + + if (limits->link.min_bpp_x16 >= min_bpp_x16) + return true; + + drm_dbg_kms(&i915->drm, + "[CRTC:%d:%s][CONNECTOR:%d:%s] Increasing link min bpp to " BPP_X16_FMT " in DSC mode due to hblank expansion quirk\n", + crtc->base.base.id, crtc->base.name, + connector->base.base.id, connector->base.name, + BPP_X16_ARGS(min_bpp_x16)); + + if (limits->link.max_bpp_x16 < min_bpp_x16) + return false; + + limits->link.min_bpp_x16 = min_bpp_x16; + + return true; +} + static bool intel_dp_mst_compute_config_limits(struct intel_dp *intel_dp, + const struct intel_connector *connector, struct intel_crtc_state *crtc_state, bool dsc, struct link_config_limits *limits) @@ -407,10 +490,16 @@ intel_dp_mst_compute_config_limits(struct intel_dp *intel_dp, intel_dp_adjust_compliance_config(intel_dp, crtc_state, limits); - return intel_dp_compute_config_link_bpp_limits(intel_dp, - crtc_state, - dsc, - limits); + if (!intel_dp_compute_config_link_bpp_limits(intel_dp, + crtc_state, + dsc, + limits)) + return false; + + return adjust_limits_for_dsc_hblank_expansion_quirk(connector, + crtc_state, + limits, + dsc); } static int intel_dp_mst_compute_config(struct intel_encoder *encoder, @@ -420,6 +509,8 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder, struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); struct intel_dp *intel_dp = &intel_mst->primary->dp; + const struct intel_connector *connector = + to_intel_connector(conn_state->connector); const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; struct link_config_limits limits; @@ -435,6 +526,7 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder, dsc_needed = intel_dp->force_dsc_en || !intel_dp_mst_compute_config_limits(intel_dp, + connector, pipe_config, false, &limits); @@ -460,6 +552,7 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder, return -EINVAL; if (!intel_dp_mst_compute_config_limits(intel_dp, + connector, pipe_config, true, &limits)) @@ -1236,6 +1329,36 @@ intel_dp_mst_read_decompression_port_dsc_caps(struct intel_dp *intel_dp, intel_dp_get_dsc_sink_cap(dpcd_caps[DP_DPCD_REV], connector); } +static bool detect_dsc_hblank_expansion_quirk(const struct intel_connector *connector) +{ + struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct drm_dp_desc desc; + u8 dpcd[DP_RECEIVER_CAP_SIZE]; + + if (!connector->dp.dsc_decompression_aux) + return false; + + if (drm_dp_read_desc(connector->dp.dsc_decompression_aux, + &desc, true) < 0) + return false; + + if (!drm_dp_has_quirk(&desc, + DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC)) + return false; + + if (drm_dp_read_dpcd_caps(connector->dp.dsc_decompression_aux, dpcd) < 0) + return false; + + if (!(dpcd[DP_RECEIVE_PORT_0_CAP_0] & DP_HBLANK_EXPANSION_CAPABLE)) + return false; + + drm_dbg_kms(&i915->drm, + "[CONNECTOR:%d:%s] DSC HBLANK expansion quirk detected\n", + connector->base.base.id, connector->base.name); + + return true; +} + static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port, const char *pathprop) @@ -1265,6 +1388,8 @@ static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topolo */ intel_connector->dp.dsc_decompression_aux = &intel_dp->aux; intel_dp_mst_read_decompression_port_dsc_caps(intel_dp, intel_connector); + intel_connector->dp.dsc_hblank_expansion_quirk = + detect_dsc_hblank_expansion_quirk(intel_connector); connector = &intel_connector->base; ret = drm_connector_init(dev, connector, &intel_dp_mst_connector_funcs, From patchwork Tue Nov 7 00:15:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13447617 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1A31DC4167B for ; Tue, 7 Nov 2023 00:15:21 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 89AE210E494; Tue, 7 Nov 2023 00:15:18 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7DA0D10E488 for ; Tue, 7 Nov 2023 00:15:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1699316115; x=1730852115; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=v2N8JtUmFUqURiJzbPz8vL/gshWqziovh6zz8G52+Sk=; b=gcd9xaOpdM9obVmb8s0Tqplc+bxgwcCpIdu94X2kqRFpJwHJ3qRUv3Ea bfWHh7NsH/uFVM6NFAXvQJ8IDspCcai++HZj226sCA3sUzeKLlBQ6E1pp sGq3V2G7R3KK5RuTgf7KCv+3V31gyLULXqbyOvzWu1cS26RGr7W7+SVOB 358umU5JOdtdvFhxD1tYHjgeBAwBm4Z99Um4J8bZYhA50QzDTaYGDw44K 2D8MgELniWpj9iQ3pZCj1kkWXWVsV2My98ZDojRgs6LKe1hHbzIqxedLY fIrYjw8OHB7nJJBZ68D9rjsF6+M9TESwiWYBft9wqLmc7sVzQHLI5/SFC A==; X-IronPort-AV: E=McAfee;i="6600,9927,10886"; a="369596205" X-IronPort-AV: E=Sophos;i="6.03,282,1694761200"; d="scan'208";a="369596205" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Nov 2023 16:15:15 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10886"; a="853178004" X-IronPort-AV: E=Sophos;i="6.03,282,1694761200"; d="scan'208";a="853178004" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Nov 2023 16:15:14 -0800 From: Imre Deak To: intel-gfx@lists.freedesktop.org Date: Tue, 7 Nov 2023 02:15:02 +0200 Message-Id: <20231107001505.3370108-5-imre.deak@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231030155843.2251023-23-imre.deak@intel.com> References: <20231030155843.2251023-23-imre.deak@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v5 22/30] drm/i915/dp_mst: Enable decompression in the sink from the MST encoder hooks X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Enable/disable the DSC decompression in the sink/branch from the MST encoder hooks. This prepares for an upcoming patch toggling DSC for each stream as needed, but for now keeps the current behavior, as DSC is only enabled for the first MST stream. v2: - Rebased on latest drm-tip. Reviewed-by: Stanislav Lisovskiy Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_ddi.c | 12 ++++++++---- drivers/gpu/drm/i915/display/intel_dp_mst.c | 15 ++++++++++++++- 2 files changed, 22 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 1abf74af6c5ce..cc2a38fc22d0d 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -2538,7 +2538,9 @@ static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state, intel_dp_set_power(intel_dp, DP_SET_POWER_D0); intel_dp_configure_protocol_converter(intel_dp, crtc_state); - intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true); + if (!is_mst) + intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true); + /* * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit * in the FEC_CONFIGURATION register to 1 before initiating link @@ -2689,7 +2691,8 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, intel_dp_set_power(intel_dp, DP_SET_POWER_D0); intel_dp_configure_protocol_converter(intel_dp, crtc_state); - intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true); + if (!is_mst) + intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true); /* * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit * in the FEC_CONFIGURATION register to 1 before initiating link @@ -2769,8 +2772,9 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, if (!is_mst) intel_dp_set_power(intel_dp, DP_SET_POWER_D0); intel_dp_configure_protocol_converter(intel_dp, crtc_state); - intel_dp_sink_set_decompression_state(intel_dp, crtc_state, - true); + if (!is_mst) + intel_dp_sink_set_decompression_state(intel_dp, crtc_state, + true); intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); intel_dp_start_link_train(intel_dp, crtc_state); if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) && diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 4f066a868b9a2..eab69f57655d9 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -776,6 +776,13 @@ static void intel_mst_disable_dp(struct intel_atomic_state *state, intel_hdcp_disable(intel_mst->connector); intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state); + + if (intel_dp->active_mst_links == 1) /* last stream ? */ + /* + * TODO: disable decompression for all streams/in any MST ports, not + * only in the first downstream branch device. + */ + intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state, false); } static void intel_mst_post_disable_dp(struct intel_atomic_state *state, @@ -932,9 +939,15 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state, drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port, true); - if (first_mst_stream) + if (first_mst_stream) { + /* + * TODO: enable decompression for all streams/in any MST ports, not + * only in the first downstream branch device. + */ + intel_dp_sink_set_decompression_state(intel_dp, pipe_config, true); dig_port->base.pre_enable(state, &dig_port->base, pipe_config, NULL); + } intel_dp->active_mst_links++; From patchwork Tue Nov 7 00:15:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13447620 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 76B62C0032E for ; Tue, 7 Nov 2023 00:15:24 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E349B10E497; Tue, 7 Nov 2023 00:15:23 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id C880610E489 for ; Tue, 7 Nov 2023 00:15:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1699316116; x=1730852116; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fbKa4Lx+qHLkrSKT89PQ8l8sJyzh+em64oPtZS1GBmM=; b=lNw9QuIr/EhfN9fRIkDHpad1Daoi+awukn2PvcpdTwtF+NZni1kwWZZu PZ1uWqUdwcB1UZJ/X3kt7/FAdEEgJC2psAEReA3nxosvqNKedYL4wycJ4 rQrqdB1RAP9V+vi8m3g93zBb+ZI8jypR4OUxWbjjHzPQ96Jz/m7/qV8YN Xj7dMh1q/jsz9dqT93ywh4zO4F1QWqA9IWalN2IhrRZLpy2LIFOqySzon /LQWUAAqcd3ob4g0vvw82XMKD5Wcpb8z4yzucGMtvy0g4+md9ymja4lv3 VVoowVelarEnnNwOV4Uxk8GLOyoAHwyqR7W2So0H3dU8PBC6GCioyNRh4 g==; X-IronPort-AV: E=McAfee;i="6600,9927,10886"; a="369596207" X-IronPort-AV: E=Sophos;i="6.03,282,1694761200"; d="scan'208";a="369596207" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Nov 2023 16:15:16 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10886"; a="853178008" X-IronPort-AV: E=Sophos;i="6.03,282,1694761200"; d="scan'208";a="853178008" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Nov 2023 16:15:15 -0800 From: Imre Deak To: intel-gfx@lists.freedesktop.org Date: Tue, 7 Nov 2023 02:15:03 +0200 Message-Id: <20231107001505.3370108-6-imre.deak@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231030155843.2251023-26-imre.deak@intel.com> References: <20231030155843.2251023-26-imre.deak@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v5 25/30] drm/i915/dp_mst: Enable MST DSC decompression for all streams X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Enable DSC decompression for all streams. In particular atm if a sink is connected to a last branch device that is downstream of the first branch device connected to the source, decompression is not enabled for it. Similarly it's not enabled if the sink supports this with the last branch device passing through the compressed stream to it. Enable DSC in the above cases as well. Since last branch devices may handle the decompression for multiple ports, toggling DSC needs to be refcounted, add this using the DSC AUX device as a reference. v2: - Fix refcounting, setting/clearing connector->dp.dsc_decompression_enabled always as needed. (Stan) - Make the refcounting more uniform for the SST vs. MST case. - Add state checks for connector->dp.dsc_decompression_enabled and connector crtc. - Sanitize connector DSC decompression state during HW setup. - s/use_count/ref_count/ v3: - Remove stale TODO: comment to set the actual decompression_aux. Cc: Stanislav Lisovskiy Signed-off-by: Imre Deak Reviewed-by: Stanislav Lisovskiy --- .../drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_dp.c | 72 ++++++++++++++++++- drivers/gpu/drm/i915/display/intel_dp_mst.c | 24 ++----- .../drm/i915/display/intel_modeset_setup.c | 6 ++ 4 files changed, 82 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 6c2f18ef543e4..0a5508c90e8bc 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -626,6 +626,7 @@ struct intel_connector { u8 fec_capability; u8 dsc_hblank_expansion_quirk:1; + u8 dsc_decompression_enabled:1; } dp; /* Work struct to schedule a uevent on link train failure */ diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index bea0c03b94835..3fee371529f17 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1403,6 +1403,7 @@ static bool intel_dp_supports_dsc(const struct intel_connector *connector, return false; return intel_dsc_source_support(crtc_state) && + connector->dp.dsc_decompression_aux && drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd); } @@ -2986,6 +2987,65 @@ intel_dp_sink_set_dsc_passthrough(const struct intel_connector *connector, str_enable_disable(enable)); } +static int intel_dp_dsc_aux_ref_count(struct intel_atomic_state *state, + const struct intel_connector *connector, + bool for_get_ref) +{ + struct drm_i915_private *i915 = to_i915(state->base.dev); + struct drm_connector *_connector_iter; + struct drm_connector_state *old_conn_state; + struct drm_connector_state *new_conn_state; + int ref_count = 0; + int i; + + /* + * On SST the decompression AUX device won't be shared, each connector + * uses for this its own AUX targeting the sink device. + */ + if (!connector->mst_port) + return connector->dp.dsc_decompression_enabled ? 1 : 0; + + for_each_oldnew_connector_in_state(&state->base, _connector_iter, + old_conn_state, new_conn_state, i) { + const struct intel_connector * + connector_iter = to_intel_connector(_connector_iter); + + if (connector_iter->mst_port != connector->mst_port) + continue; + + if (!connector_iter->dp.dsc_decompression_enabled) + continue; + + drm_WARN_ON(&i915->drm, + (for_get_ref && !new_conn_state->crtc) || + (!for_get_ref && !old_conn_state->crtc)); + + if (connector_iter->dp.dsc_decompression_aux == + connector->dp.dsc_decompression_aux) + ref_count++; + } + + return ref_count; +} + +static bool intel_dp_dsc_aux_get_ref(struct intel_atomic_state *state, + struct intel_connector *connector) +{ + bool ret = intel_dp_dsc_aux_ref_count(state, connector, true) == 0; + + connector->dp.dsc_decompression_enabled = true; + + return ret; +} + +static bool intel_dp_dsc_aux_put_ref(struct intel_atomic_state *state, + struct intel_connector *connector) +{ + connector->dp.dsc_decompression_enabled = false; + + return intel_dp_dsc_aux_ref_count(state, connector, false) == 0; +} + /** * intel_dp_sink_enable_decompression - Enable DSC decompression in sink/last branch device * @state: atomic state @@ -3009,7 +3069,11 @@ void intel_dp_sink_enable_decompression(struct intel_atomic_state *state, return; if (drm_WARN_ON(&i915->drm, - !connector->dp.dsc_decompression_aux)) + !connector->dp.dsc_decompression_aux || + connector->dp.dsc_decompression_enabled)) + return; + + if (!intel_dp_dsc_aux_get_ref(state, connector)) return; intel_dp_sink_set_dsc_passthrough(connector, true); @@ -3036,7 +3100,11 @@ void intel_dp_sink_disable_decompression(struct intel_atomic_state *state, return; if (drm_WARN_ON(&i915->drm, - !connector->dp.dsc_decompression_aux)) + !connector->dp.dsc_decompression_aux || + !connector->dp.dsc_decompression_enabled)) + return; + + if (!intel_dp_dsc_aux_put_ref(state, connector)) return; intel_dp_sink_set_dsc_decompression(connector, false); diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index bc992e77ffc7a..b3d952bbb3cf0 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -777,12 +777,7 @@ static void intel_mst_disable_dp(struct intel_atomic_state *state, intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state); - if (intel_dp->active_mst_links == 1) /* last stream ? */ - /* - * TODO: disable decompression for all streams/in any MST ports, not - * only in the first downstream branch device. - */ - intel_dp_sink_disable_decompression(state, connector, old_crtc_state); + intel_dp_sink_disable_decompression(state, connector, old_crtc_state); } static void intel_mst_post_disable_dp(struct intel_atomic_state *state, @@ -939,15 +934,11 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state, drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port, true); - if (first_mst_stream) { - /* - * TODO: enable decompression for all streams/in any MST ports, not - * only in the first downstream branch device. - */ - intel_dp_sink_enable_decompression(state, connector, pipe_config); + intel_dp_sink_enable_decompression(state, connector, pipe_config); + + if (first_mst_stream) dig_port->base.pre_enable(state, &dig_port->base, pipe_config, NULL); - } intel_dp->active_mst_links++; @@ -1394,12 +1385,7 @@ static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topolo intel_connector->port = port; drm_dp_mst_get_port_malloc(port); - /* - * TODO: set the AUX for the actual MST port decompressing the stream. - * At the moment the driver only supports enabling this globally in the - * first downstream MST branch, via intel_dp's (root port) AUX. - */ - intel_connector->dp.dsc_decompression_aux = &intel_dp->aux; + intel_connector->dp.dsc_decompression_aux = drm_dp_mst_dsc_aux_for_port(port); intel_dp_mst_read_decompression_port_dsc_caps(intel_dp, intel_connector); intel_connector->dp.dsc_hblank_expansion_quirk = detect_dsc_hblank_expansion_quirk(intel_connector); diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c index b8f43efb0ab5a..94eece7f63be3 100644 --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c @@ -318,6 +318,12 @@ static void intel_modeset_update_connector_atomic_state(struct drm_i915_private const struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); + if (crtc_state->dsc.compression_enable) { + drm_WARN_ON(&i915->drm, !connector->dp.dsc_decompression_aux); + connector->dp.dsc_decompression_enabled = true; + } else { + connector->dp.dsc_decompression_enabled = false; + } conn_state->max_bpc = (crtc_state->pipe_bpp ?: 24) / 3; } } From patchwork Tue Nov 7 00:15:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13447618 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 29FDAC4167D for ; Tue, 7 Nov 2023 00:15:22 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 112F510E48E; Tue, 7 Nov 2023 00:15:20 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3E5BD10E48E for ; Tue, 7 Nov 2023 00:15:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1699316118; x=1730852118; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+cBlnwRlJOnT0Bjd0o96H2tEfQnFHAvTFDUIqluHBQo=; b=lccmc2CcSxH8/jO5ADw6leeED/YK6ye2E4Sd+j7UGEgGjCx4ADu327KX 3Ah8Ci8SpgiDkn3pymkmhUiCnuVhDVSz9FMqqssxjKrYGg4p+5Fk6VWC7 oLC7iCLxYPwqSu2QaamKO44g867c1FlwzrVIid/Yy115Xtu/PhbKFUiGj NrG9XXfw8wj3oJrNAb6SI83+O5jL7Evxo4r+ALy0K82IWlHrkviIu2900 iSg78M3qGVZLUcD/Mz8ofjx0YIUuflEG6+YGAxHc+ZUxgb7CspOPOuRZ+ pWhiszF7EsQLaRy4w3aw80Gc6GJ3CQIFpmZeIcA6eTTpUnmkpq4XbJ340 A==; X-IronPort-AV: E=McAfee;i="6600,9927,10886"; a="369596209" X-IronPort-AV: E=Sophos;i="6.03,282,1694761200"; d="scan'208";a="369596209" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Nov 2023 16:15:18 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10886"; a="853178013" X-IronPort-AV: E=Sophos;i="6.03,282,1694761200"; d="scan'208";a="853178013" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Nov 2023 16:15:16 -0800 From: Imre Deak To: intel-gfx@lists.freedesktop.org Date: Tue, 7 Nov 2023 02:15:04 +0200 Message-Id: <20231107001505.3370108-7-imre.deak@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231030155843.2251023-27-imre.deak@intel.com> References: <20231030155843.2251023-27-imre.deak@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v5 26/30] drm/i915: Factor out function to clear pipe update flags X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Factor out a helper to clear the pipe update flags, used by a follow-up patch to modeset an MST topology. v2: - Move the intel_crtc_needs_modeset() check to the callers. (Ville) v3 (Ville): - Rename clear_pipe_update_flags_on_modeset_crtc() to intel_crtc_flag_modeset(). - Also set crtc_state->uapi.mode_changed in the function. - Leave out the unrelated change to use intel_modeset_pipes_in_mask_early(). Cc: Ville Syrjälä Reviewed-by: Stanislav Lisovskiy (v1) Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_display.c | 49 +++++++++----------- 1 file changed, 23 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 3c7ef2cc3b8b1..afa5613fd847c 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -5542,6 +5542,16 @@ int intel_modeset_pipes_in_mask_early(struct intel_atomic_state *state, return 0; } +static void +intel_crtc_flag_modeset(struct intel_crtc_state *crtc_state) +{ + crtc_state->uapi.mode_changed = true; + + crtc_state->update_pipe = false; + crtc_state->update_m_n = false; + crtc_state->update_lrr = false; +} + /** * intel_modeset_all_pipes_late - force a full modeset on all pipes * @state: intel atomic state @@ -5575,9 +5585,8 @@ int intel_modeset_all_pipes_late(struct intel_atomic_state *state, if (ret) return ret; - crtc_state->update_pipe = false; - crtc_state->update_m_n = false; - crtc_state->update_lrr = false; + intel_crtc_flag_modeset(crtc_state); + crtc_state->update_planes |= crtc_state->active_planes; crtc_state->async_flip_planes = 0; crtc_state->do_async_flip = false; @@ -5690,17 +5699,17 @@ static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_sta else new_crtc_state->uapi.mode_changed = false; - if (intel_crtc_needs_modeset(new_crtc_state) || - intel_compare_link_m_n(&old_crtc_state->dp_m_n, + if (intel_compare_link_m_n(&old_crtc_state->dp_m_n, &new_crtc_state->dp_m_n)) new_crtc_state->update_m_n = false; - if (intel_crtc_needs_modeset(new_crtc_state) || - (old_crtc_state->hw.adjusted_mode.crtc_vtotal == new_crtc_state->hw.adjusted_mode.crtc_vtotal && + if ((old_crtc_state->hw.adjusted_mode.crtc_vtotal == new_crtc_state->hw.adjusted_mode.crtc_vtotal && old_crtc_state->hw.adjusted_mode.crtc_vblank_end == new_crtc_state->hw.adjusted_mode.crtc_vblank_end)) new_crtc_state->update_lrr = false; - if (!intel_crtc_needs_modeset(new_crtc_state)) + if (intel_crtc_needs_modeset(new_crtc_state)) + intel_crtc_flag_modeset(new_crtc_state); + else new_crtc_state->update_pipe = true; } @@ -6475,12 +6484,8 @@ int intel_atomic_check(struct drm_device *dev, if (intel_dp_mst_is_slave_trans(new_crtc_state)) { enum transcoder master = new_crtc_state->mst_master_transcoder; - if (intel_cpu_transcoders_need_modeset(state, BIT(master))) { - new_crtc_state->uapi.mode_changed = true; - new_crtc_state->update_pipe = false; - new_crtc_state->update_m_n = false; - new_crtc_state->update_lrr = false; - } + if (intel_cpu_transcoders_need_modeset(state, BIT(master))) + intel_crtc_flag_modeset(new_crtc_state); } if (is_trans_port_sync_mode(new_crtc_state)) { @@ -6489,21 +6494,13 @@ int intel_atomic_check(struct drm_device *dev, if (new_crtc_state->master_transcoder != INVALID_TRANSCODER) trans |= BIT(new_crtc_state->master_transcoder); - if (intel_cpu_transcoders_need_modeset(state, trans)) { - new_crtc_state->uapi.mode_changed = true; - new_crtc_state->update_pipe = false; - new_crtc_state->update_m_n = false; - new_crtc_state->update_lrr = false; - } + if (intel_cpu_transcoders_need_modeset(state, trans)) + intel_crtc_flag_modeset(new_crtc_state); } if (new_crtc_state->bigjoiner_pipes) { - if (intel_pipes_need_modeset(state, new_crtc_state->bigjoiner_pipes)) { - new_crtc_state->uapi.mode_changed = true; - new_crtc_state->update_pipe = false; - new_crtc_state->update_m_n = false; - new_crtc_state->update_lrr = false; - } + if (intel_pipes_need_modeset(state, new_crtc_state->bigjoiner_pipes)) + intel_crtc_flag_modeset(new_crtc_state); } } From patchwork Tue Nov 7 00:15:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13447619 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AAAE4C4332F for ; Tue, 7 Nov 2023 00:15:23 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 02D6C10E498; Tue, 7 Nov 2023 00:15:23 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id BE16F10E495 for ; Tue, 7 Nov 2023 00:15:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1699316119; x=1730852119; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2BDpAsFGoje3LCRlhV2JLKe+7LVI0zGpMOIB3rYYIwE=; b=QPm9hzm9Oa+hJrZ8HMrAevGr0rZ9CABD4b1TR932xc9yL7ZYaPTQCw17 /8h3LY5qxN9OU7PvApUJ/cT6iGsJmki/yNXPIeFzdCiQNzGMKyFhKM1qO EyEbbhsiUl24DTXmlACWqkVkZYciDZm7tEccejFhvsZxy1YIXJ6DeRiuC DnGYRGTz5aRS+LFNqxKi42vCJHo0tOuvfZvOEeb+OWQHFdyGnU23K46x5 mwzkY+vOUj1v0yeCs+jX9F2O+3WNmXYi/cCYuWpS6hzJVdJv60Qew0gCM XRA+ovw1LiW87F7s0GKAw33KExqz/6CWWGxMInMgVJeniiAMr88yUAgRa g==; X-IronPort-AV: E=McAfee;i="6600,9927,10886"; a="369596213" X-IronPort-AV: E=Sophos;i="6.03,282,1694761200"; d="scan'208";a="369596213" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Nov 2023 16:15:19 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10886"; a="853178020" X-IronPort-AV: E=Sophos;i="6.03,282,1694761200"; d="scan'208";a="853178020" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Nov 2023 16:15:17 -0800 From: Imre Deak To: intel-gfx@lists.freedesktop.org Date: Tue, 7 Nov 2023 02:15:05 +0200 Message-Id: <20231107001505.3370108-8-imre.deak@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231030155843.2251023-28-imre.deak@intel.com> References: <20231030155843.2251023-28-imre.deak@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v5 27/30] drm/i915/dp_mst: Force modeset CRTC if DSC toggling requires it X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Enabling / disabling DSC decompression in the branch device downstream of the source may reset the whole branch device. To avoid this while the streams are still active, force a modeset on all CRTC/ports connected to this branch device. v2: - Check the CRTC state for each connector in the topology, instead of the CRTC being checked for a modeset requirement. (Ville) - Add DocBook for the new function. v3: - Rebased on a change not to use intel_modeset_pipes_in_mask_early(). Cc: Ville Syrjälä Reviewed-by: Stanislav Lisovskiy (v1) Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_display.c | 3 + drivers/gpu/drm/i915/display/intel_dp_mst.c | 88 ++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_dp_mst.h | 2 + 3 files changed, 93 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index afa5613fd847c..c4cb0e2273a00 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -6481,6 +6481,9 @@ int intel_atomic_check(struct drm_device *dev, if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(new_crtc_state)) continue; + if (intel_dp_mst_crtc_needs_modeset(state, crtc)) + intel_crtc_flag_modeset(new_crtc_state); + if (intel_dp_mst_is_slave_trans(new_crtc_state)) { enum transcoder master = new_crtc_state->mst_master_transcoder; diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index b3d952bbb3cf0..079986b09f8bf 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -1628,3 +1628,91 @@ int intel_dp_mst_add_topology_state_for_crtc(struct intel_atomic_state *state, return 0; } + +static struct intel_connector * +get_connector_in_state_for_crtc(struct intel_atomic_state *state, + const struct intel_crtc *crtc) +{ + struct drm_connector_state *old_conn_state; + struct drm_connector_state *new_conn_state; + struct drm_connector *_connector; + int i; + + for_each_oldnew_connector_in_state(&state->base, _connector, + old_conn_state, new_conn_state, i) { + struct intel_connector *connector = + to_intel_connector(_connector); + + if (old_conn_state->crtc == &crtc->base || + new_conn_state->crtc == &crtc->base) + return connector; + } + + return NULL; +} + +/** + * intel_dp_mst_crtc_needs_modeset - check if changes in topology need to modeset the given CRTC + * @state: atomic state + * @crtc: CRTC for which to check the modeset requirement + * + * Check if any change in a MST topology requires a forced modeset on @crtc in + * this topology. One such change is enabling/disabling the DSC decompression + * state in the first branch device's UFP DPCD as required by one CRTC, while + * the other @crtc in the same topology is still active, requiring a full modeset + * on @crtc. + */ +bool intel_dp_mst_crtc_needs_modeset(struct intel_atomic_state *state, + struct intel_crtc *crtc) +{ + const struct intel_connector *crtc_connector; + const struct drm_connector_state *conn_state; + const struct drm_connector *_connector; + int i; + + if (!intel_crtc_has_type(intel_atomic_get_new_crtc_state(state, crtc), + INTEL_OUTPUT_DP_MST)) + return false; + + crtc_connector = get_connector_in_state_for_crtc(state, crtc); + + if (!crtc_connector) + /* None of the connectors in the topology needs modeset */ + return false; + + for_each_new_connector_in_state(&state->base, _connector, conn_state, i) { + const struct intel_connector *connector = + to_intel_connector(_connector); + const struct intel_crtc_state *new_crtc_state; + const struct intel_crtc_state *old_crtc_state; + struct intel_crtc *crtc_iter; + + if (connector->mst_port != crtc_connector->mst_port || + !conn_state->crtc) + continue; + + crtc_iter = to_intel_crtc(conn_state->crtc); + + new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc_iter); + old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc_iter); + + if (!intel_crtc_needs_modeset(new_crtc_state)) + continue; + + if (old_crtc_state->dsc.compression_enable == + new_crtc_state->dsc.compression_enable) + continue; + /* + * Toggling the decompression flag because of this stream in + * the first downstream branch device's UFP DPCD may reset the + * whole branch device. To avoid the reset while other streams + * are also active modeset the whole MST topology in this + * case. + */ + if (connector->dp.dsc_decompression_aux == + &connector->mst_port->aux) + return true; + } + + return false; +} diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.h b/drivers/gpu/drm/i915/display/intel_dp_mst.h index f1815bb722672..fc5e85776a858 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.h +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.h @@ -22,5 +22,7 @@ bool intel_dp_mst_is_slave_trans(const struct intel_crtc_state *crtc_state); bool intel_dp_mst_source_support(struct intel_dp *intel_dp); int intel_dp_mst_add_topology_state_for_crtc(struct intel_atomic_state *state, struct intel_crtc *crtc); +bool intel_dp_mst_crtc_needs_modeset(struct intel_atomic_state *state, + struct intel_crtc *crtc); #endif /* __INTEL_DP_MST_H__ */