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envelope-from=chalap1@us.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Tue, 07 Nov 2023 11:16:20 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Chalapathi V This part of the patchset creates a common pervasive chiplet model where it houses the common units of a chiplets. The chiplet control unit is common across chiplets and this commit implements the pervasive chiplet model with chiplet control registers. Signed-off-by: Chalapathi V --- hw/ppc/meson.build | 1 + hw/ppc/pnv_pervasive.c | 213 +++++++++++++++++++++++++++++++++++++++++ include/hw/ppc/pnv_pervasive.h | 39 ++++++++ include/hw/ppc/pnv_xscom.h | 3 + 4 files changed, 256 insertions(+) create mode 100644 hw/ppc/pnv_pervasive.c create mode 100644 include/hw/ppc/pnv_pervasive.h diff --git a/hw/ppc/meson.build b/hw/ppc/meson.build index 7c2c524..c80d2f6 100644 --- a/hw/ppc/meson.build +++ b/hw/ppc/meson.build @@ -50,6 +50,7 @@ ppc_ss.add(when: 'CONFIG_POWERNV', if_true: files( 'pnv_bmc.c', 'pnv_homer.c', 'pnv_pnor.c', + 'pnv_pervasive.c', )) # PowerPC 4xx boards ppc_ss.add(when: 'CONFIG_PPC405', if_true: files( diff --git a/hw/ppc/pnv_pervasive.c b/hw/ppc/pnv_pervasive.c new file mode 100644 index 0000000..40f60b5 --- /dev/null +++ b/hw/ppc/pnv_pervasive.c @@ -0,0 +1,213 @@ +/* + * QEMU PowerPC pervasive common chiplet model + * + * Copyright (c) 2023, IBM Corporation. + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * This code is licensed under the GPL version 2 or later. See the + * COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "hw/qdev-properties.h" +#include "hw/ppc/pnv.h" +#include "hw/ppc/pnv_xscom.h" +#include "hw/ppc/pnv_pervasive.h" +#include "hw/ppc/fdt.h" +#include + +#define CPLT_CONF0 0x08 +#define CPLT_CONF0_OR 0x18 +#define CPLT_CONF0_CLEAR 0x28 +#define CPLT_CONF1 0x09 +#define CPLT_CONF1_OR 0x19 +#define CPLT_CONF1_CLEAR 0x29 +#define CPLT_STAT0 0x100 +#define CPLT_MASK0 0x101 +#define CPLT_PROTECT_MODE 0x3FE +#define CPLT_ATOMIC_CLOCK 0x3FF + +static uint64_t pnv_chiplet_ctrl_read(void *opaque, hwaddr addr, + unsigned size) +{ + PnvPervChiplet *perv_chiplet = PNV_PERVCHIPLET(opaque); + int reg = addr >> 3; + uint64_t val = ~0ull; + /* CPLT_CTRL0 to CPLT_CTRL5 */ + for (int i = 0; i <= 5; i++) { + if (reg == i) { + val = perv_chiplet->control_regs.cplt_ctrl[i]; + return val; + } else if ((reg == (i + 0x10)) || (reg == (i + 0x20))) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Write only register, ignoring " + "xscom read at 0x%" PRIx64 "\n", + __func__, (unsigned long)reg); + return val; + } + } + + switch (reg) { + case CPLT_CONF0: + val = perv_chiplet->control_regs.cplt_cfg0; + break; + case CPLT_CONF0_OR: + case CPLT_CONF0_CLEAR: + qemu_log_mask(LOG_GUEST_ERROR, "%s: Write only register, ignoring " + "xscom read at 0x%" PRIx64 "\n", + __func__, (unsigned long)reg); + break; + case CPLT_CONF1: + val = perv_chiplet->control_regs.cplt_cfg1; + break; + case CPLT_CONF1_OR: + case CPLT_CONF1_CLEAR: + qemu_log_mask(LOG_GUEST_ERROR, "%s: Write only register, ignoring " + "xscom read at 0x%" PRIx64 "\n", + __func__, (unsigned long)reg); + break; + case CPLT_STAT0: + val = perv_chiplet->control_regs.cplt_stat0; + break; + case CPLT_MASK0: + val = perv_chiplet->control_regs.cplt_mask0; + break; + case CPLT_PROTECT_MODE: + val = perv_chiplet->control_regs.ctrl_protect_mode; + break; + case CPLT_ATOMIC_CLOCK: + val = perv_chiplet->control_regs.ctrl_atomic_lock; + break; + default: + qemu_log_mask(LOG_UNIMP, "%s: Chiplet_control_regs: Invalid xscom " + "read at 0x%" PRIx64 "\n", __func__, (unsigned long)reg); + } + return val; +} + +static void pnv_chiplet_ctrl_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) +{ + PnvPervChiplet *perv_chiplet = PNV_PERVCHIPLET(opaque); + int reg = addr >> 3; + /* CPLT_CTRL0 to CPLT_CTRL5 */ + for (int i = 0; i <= 5; i++) { + if (reg == i) { + perv_chiplet->control_regs.cplt_ctrl[i] = val; + return; + } else if (reg == (i + 0x10)) { + perv_chiplet->control_regs.cplt_ctrl[i] |= val; + return; + } else if (reg == (i + 0x20)) { + perv_chiplet->control_regs.cplt_ctrl[i] &= ~val; + return; + } + } + + switch (reg) { + case CPLT_CONF0: + perv_chiplet->control_regs.cplt_cfg0 = val; + break; + case CPLT_CONF0_OR: + perv_chiplet->control_regs.cplt_cfg0 |= val; + break; + case CPLT_CONF0_CLEAR: + perv_chiplet->control_regs.cplt_cfg0 &= ~val; + break; + case CPLT_CONF1: + perv_chiplet->control_regs.cplt_cfg1 = val; + break; + case CPLT_CONF1_OR: + perv_chiplet->control_regs.cplt_cfg1 |= val; + break; + case CPLT_CONF1_CLEAR: + perv_chiplet->control_regs.cplt_cfg1 &= ~val; + break; + case CPLT_STAT0: + perv_chiplet->control_regs.cplt_stat0 = val; + break; + case CPLT_MASK0: + perv_chiplet->control_regs.cplt_mask0 = val; + break; + case CPLT_PROTECT_MODE: + perv_chiplet->control_regs.ctrl_protect_mode = val; + break; + case CPLT_ATOMIC_CLOCK: + perv_chiplet->control_regs.ctrl_atomic_lock = val; + break; + default: + qemu_log_mask(LOG_UNIMP, "%s: Chiplet_control_regs: Invalid xscom " + "write at 0x%" PRIx64 "\n", + __func__, (unsigned long)reg); + } + return; +} + +static const MemoryRegionOps pnv_perv_chiplet_control_xscom_ops = { + .read = pnv_chiplet_ctrl_read, + .write = pnv_chiplet_ctrl_write, + .valid.min_access_size = 8, + .valid.max_access_size = 8, + .impl.min_access_size = 8, + .impl.max_access_size = 8, + .endianness = DEVICE_BIG_ENDIAN, +}; + +static void pnv_perv_chiplet_realize(DeviceState *dev, Error **errp) +{ + PnvPervChiplet *perv_chiplet = PNV_PERVCHIPLET(dev); + + /* Chiplet control scoms */ + pnv_xscom_region_init(&perv_chiplet->xscom_perv_ctrl_regs, + OBJECT(perv_chiplet), + &pnv_perv_chiplet_control_xscom_ops, + perv_chiplet, "xscom-chiplet-control-regs", + PNV10_XSCOM_CTRL_CHIPLET_SIZE); +} + +void pnv_perv_dt(uint32_t base_addr, void *fdt, + int offset) +{ + g_autofree char *name = NULL; + int perv_chiplet_offset; + + const char compat[] = "ibm,power10-perv-chiplet"; + uint32_t reg[] = { + base_addr, + cpu_to_be32(PNV10_XSCOM_CTRL_CHIPLET_SIZE) + }; + name = g_strdup_printf("perv_chiplet@%x", base_addr); + perv_chiplet_offset = fdt_add_subnode(fdt, offset, name); + _FDT(perv_chiplet_offset); + + _FDT(fdt_setprop(fdt, perv_chiplet_offset, "reg", reg, sizeof(reg))); + _FDT(fdt_setprop(fdt, perv_chiplet_offset, "compatible", + compat, sizeof(compat))); +} + +static void pnv_perv_chiplet_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->desc = "PowerNV perv chiplet"; + dc->realize = pnv_perv_chiplet_realize; +} + +static const TypeInfo pnv_perv_chiplet_info = { + .name = TYPE_PNV_PERV_CHIPLET, + .parent = TYPE_DEVICE, + .instance_size = sizeof(PnvPervChiplet), + .class_init = pnv_perv_chiplet_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_PNV_XSCOM_INTERFACE }, + { } + } +}; + +static void pnv_perv_chiplet_register_types(void) +{ + type_register_static(&pnv_perv_chiplet_info); +} + +type_init(pnv_perv_chiplet_register_types); diff --git a/include/hw/ppc/pnv_pervasive.h b/include/hw/ppc/pnv_pervasive.h new file mode 100644 index 0000000..61be4cf --- /dev/null +++ b/include/hw/ppc/pnv_pervasive.h @@ -0,0 +1,39 @@ +/* + * QEMU PowerPC pervasive common chiplet model + * + * Copyright (c) 2023, IBM Corporation. + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * This code is licensed under the GPL version 2 or later. See the + * COPYING file in the top-level directory. + */ + +#ifndef PPC_PNV_PERVASIVE_H +#define PPC_PNV_PERVASIVE_H + +#define TYPE_PNV_PERV_CHIPLET "pnv-pervasive-chiplet" +#define PNV_PERVCHIPLET(obj) OBJECT_CHECK(PnvPervChiplet, (obj), TYPE_PNV_PERV_CHIPLET) + +typedef struct ControlRegs { + + uint64_t cplt_ctrl[6]; + uint64_t cplt_cfg0; + uint64_t cplt_cfg1; + uint64_t cplt_stat0; + uint64_t cplt_mask0; + uint64_t ctrl_protect_mode; + uint64_t ctrl_atomic_lock; +} ControlRegs; + +typedef struct PnvPervChiplet { + + DeviceState parent; + struct PnvChip *chip; + MemoryRegion xscom_perv_ctrl_regs; + ControlRegs control_regs; + +} PnvPervChiplet; + +void pnv_perv_dt(uint32_t base, void *fdt, int offset); +#endif /*PPC_PNV_PERVASIVE_H */ diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h index 35b1961..87bbee8 100644 --- a/include/hw/ppc/pnv_xscom.h +++ b/include/hw/ppc/pnv_xscom.h @@ -164,6 +164,9 @@ struct PnvXScomInterfaceClass { #define PNV10_XSCOM_XIVE2_BASE 0x2010800 #define PNV10_XSCOM_XIVE2_SIZE 0x400 +#define PNV10_XSCOM_NEST1_CTRL_CHIPLET_BASE 0x3000000 +#define PNV10_XSCOM_CTRL_CHIPLET_SIZE 0x400 + #define PNV10_XSCOM_PEC_NEST_BASE 0x3011800 /* index goes downwards ... */ #define PNV10_XSCOM_PEC_NEST_SIZE 0x100 From patchwork Tue Nov 7 07:41:26 2023 Content-Type: text/plain; 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Tue, 7 Nov 2023 07:41:32 +0000 (GMT) Received: from smtpav06.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id BC3D158043; Tue, 7 Nov 2023 07:41:32 +0000 (GMT) Received: from gfwr516.rchland.ibm.com (unknown [9.10.239.105]) by smtpav06.dal12v.mail.ibm.com (Postfix) with ESMTPS; Tue, 7 Nov 2023 07:41:32 +0000 (GMT) Received: by gfwr516.rchland.ibm.com (Postfix, from userid 607334) id 431CC220040; Tue, 7 Nov 2023 01:41:32 -0600 (CST) From: Chalapathi V To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, fbarrat@linux.ibm.com, npiggin@gmail.com, clg@kaod.org, calebs@us.ibm.com, chalapathi.v@ibm.com, saif.abrar@linux.vnet.ibm.com, Chalapathi V Subject: [PATCH v4 2/3] hw/ppc: Add nest1 chiplet model Date: Tue, 7 Nov 2023 01:41:26 -0600 Message-Id: <20231107074127.31821-3-chalap1@gfwr516.rchland.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20231107074127.31821-1-chalap1@gfwr516.rchland.ibm.com> References: <20231107074127.31821-1-chalap1@gfwr516.rchland.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: m1BaXaJQwFJECaDOW4ARNaBkbPSY0HH1 X-Proofpoint-ORIG-GUID: JNzXzCnhTZz8_mSOKTxEanDmtsuRjdB- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-06_15,2023-11-02_03,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 mlxlogscore=999 bulkscore=0 impostorscore=0 lowpriorityscore=0 phishscore=0 mlxscore=0 priorityscore=1501 malwarescore=0 adultscore=0 clxscore=1034 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2310240000 definitions=main-2311070062 Received-SPF: pass client-ip=148.163.158.5; envelope-from=chalap1@us.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Tue, 07 Nov 2023 11:16:20 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Chalapathi V The nest1 chiplet handle the high speed i/o traffic over PCIe and others. The nest1 chiplet consists of PowerBus Fabric controller, nest Memory Management Unit, chiplet control unit and more. This commit creates a nest1 chiplet model and initialize and realize the pervasive chiplet model where chiplet control registers are implemented. Signed-off-by: Chalapathi V --- hw/ppc/meson.build | 1 + hw/ppc/pnv_nest1_chiplet.c | 94 +++++++++++++++++++++++++++++++++++++++ include/hw/ppc/pnv_nest_chiplet.h | 41 +++++++++++++++++ 3 files changed, 136 insertions(+) create mode 100644 hw/ppc/pnv_nest1_chiplet.c create mode 100644 include/hw/ppc/pnv_nest_chiplet.h diff --git a/hw/ppc/meson.build b/hw/ppc/meson.build index c80d2f6..4e45e5c 100644 --- a/hw/ppc/meson.build +++ b/hw/ppc/meson.build @@ -51,6 +51,7 @@ ppc_ss.add(when: 'CONFIG_POWERNV', if_true: files( 'pnv_homer.c', 'pnv_pnor.c', 'pnv_pervasive.c', + 'pnv_nest1_chiplet.c', )) # PowerPC 4xx boards ppc_ss.add(when: 'CONFIG_PPC405', if_true: files( diff --git a/hw/ppc/pnv_nest1_chiplet.c b/hw/ppc/pnv_nest1_chiplet.c new file mode 100644 index 0000000..e078076 --- /dev/null +++ b/hw/ppc/pnv_nest1_chiplet.c @@ -0,0 +1,94 @@ +/* + * QEMU PowerPC nest1 chiplet model + * + * Copyright (c) 2023, IBM Corporation. + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * This code is licensed under the GPL version 2 or later. See the + * COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "hw/qdev-properties.h" +#include "hw/ppc/pnv.h" +#include "hw/ppc/pnv_xscom.h" +#include "hw/ppc/pnv_nest_chiplet.h" +#include "hw/ppc/pnv_pervasive.h" +#include "hw/ppc/fdt.h" +#include + +/* + * The nest1 chiplet contains chiplet control unit, + * PowerBus/RaceTrack/Bridge logic, nest Memory Management Unit(nMMU) + * and more. + */ + +static void pnv_nest1_chiplet_realize(DeviceState *dev, Error **errp) +{ + PnvNest1Chiplet *nest1_chiplet = PNV_NEST1CHIPLET(dev); + + object_initialize_child(OBJECT(nest1_chiplet), "perv_chiplet", + &nest1_chiplet->perv_chiplet, + TYPE_PNV_PERV_CHIPLET); + + if (!qdev_realize(DEVICE(&nest1_chiplet->perv_chiplet), NULL, errp)) { + return; + } +} + +static int pnv_nest1_chiplet_dt_xscom(PnvXScomInterface *dev, void *fdt, + int offset) +{ + g_autofree char *name = NULL; + int nest1_chiplet_offset; + const char compat[] = "ibm,power10-nest1-chiplet"; + + name = g_strdup_printf("nest1_chiplet@%x", + PNV10_XSCOM_NEST1_CTRL_CHIPLET_BASE); + nest1_chiplet_offset = fdt_add_subnode(fdt, offset, name); + _FDT(nest1_chiplet_offset); + + _FDT(fdt_setprop(fdt, nest1_chiplet_offset, "compatible", + compat, sizeof(compat))); + return 0; +} + +static void pnv_nest1_dt_populate(void *fdt) +{ + + uint32_t nest1_base = cpu_to_be32(PNV10_XSCOM_NEST1_CTRL_CHIPLET_BASE); + pnv_perv_dt(nest1_base, fdt, 0); +} + +static void pnv_nest1_chiplet_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + PnvNest1Class *nest1_class = PNV_NEST1CHIPLET_CLASS(klass); + PnvXScomInterfaceClass *xscomc = PNV_XSCOM_INTERFACE_CLASS(klass); + + xscomc->dt_xscom = pnv_nest1_chiplet_dt_xscom; + + dc->desc = "PowerNV nest1 chiplet"; + dc->realize = pnv_nest1_chiplet_realize; + nest1_class->nest1_dt_populate = pnv_nest1_dt_populate; +} + +static const TypeInfo pnv_nest1_chiplet_info = { + .name = TYPE_PNV_NEST1_CHIPLET, + .parent = TYPE_DEVICE, + .instance_size = sizeof(PnvNest1Chiplet), + .class_init = pnv_nest1_chiplet_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_PNV_XSCOM_INTERFACE }, + { } + } +}; + +static void pnv_nest1_chiplet_register_types(void) +{ + type_register_static(&pnv_nest1_chiplet_info); +} + +type_init(pnv_nest1_chiplet_register_types); diff --git a/include/hw/ppc/pnv_nest_chiplet.h b/include/hw/ppc/pnv_nest_chiplet.h new file mode 100644 index 0000000..12525d3 --- /dev/null +++ b/include/hw/ppc/pnv_nest_chiplet.h @@ -0,0 +1,41 @@ +/* + * QEMU PowerPC nest chiplet model + * + * Copyright (c) 2023, IBM Corporation. + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * This code is licensed under the GPL version 2 or later. See the + * COPYING file in the top-level directory. + * + */ + +#ifndef PPC_PNV_NEST1_CHIPLET_H +#define PPC_PNV_NEST1_CHIPLET_H + +#include "hw/ppc/pnv_pervasive.h" + +#define TYPE_PNV_NEST1_CHIPLET "pnv-nest1-chiplet" +typedef struct PnvNest1Class PnvNest1Class; +typedef struct PnvNest1Chiplet PnvNest1Chiplet; +DECLARE_OBJ_CHECKERS(PnvNest1Chiplet, PnvNest1Class, + PNV_NEST1CHIPLET, TYPE_PNV_NEST1_CHIPLET) + +typedef struct PnvNest1Chiplet { + DeviceState parent; + + struct PnvChip *chip; + + /* common pervasive chiplet unit */ + PnvPervChiplet perv_chiplet; +} PnvNest1Chiplet; + +struct PnvNest1Class { + DeviceClass parent_class; + + DeviceRealize parent_realize; + + void (*nest1_dt_populate)(void *fdt); +}; + +#endif /*PPC_PNV_NEST1_CHIPLET_H */ From patchwork Tue Nov 7 07:41:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chalapathi V X-Patchwork-Id: 13449108 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D3AC5C41535 for ; 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Tue, 7 Nov 2023 01:41:32 -0600 (CST) From: Chalapathi V To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, fbarrat@linux.ibm.com, npiggin@gmail.com, clg@kaod.org, calebs@us.ibm.com, chalapathi.v@ibm.com, saif.abrar@linux.vnet.ibm.com, Chalapathi V Subject: [PATCH v4 3/3] hw/ppc: Nest1 chiplet wiring Date: Tue, 7 Nov 2023 01:41:27 -0600 Message-Id: <20231107074127.31821-4-chalap1@gfwr516.rchland.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20231107074127.31821-1-chalap1@gfwr516.rchland.ibm.com> References: <20231107074127.31821-1-chalap1@gfwr516.rchland.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: B1JaVuTRIogQJ2klZ4OZSShgf-lFzlCg X-Proofpoint-ORIG-GUID: TnCjVkpcXZAK6akRaViQNELVdZtI44xd X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-06_15,2023-11-02_03,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 spamscore=0 mlxscore=0 priorityscore=1501 phishscore=0 adultscore=0 suspectscore=0 clxscore=1034 mlxlogscore=843 malwarescore=0 impostorscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2310240000 definitions=main-2311070062 Received-SPF: pass client-ip=148.163.158.5; envelope-from=chalap1@us.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Tue, 07 Nov 2023 11:16:20 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Chalapathi V This part of the patchset connects the nest1 chiplet model to p10 chip. Signed-off-by: Chalapathi V --- hw/ppc/pnv.c | 14 ++++++++++++++ include/hw/ppc/pnv_chip.h | 2 ++ 2 files changed, 16 insertions(+) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index c0e34ff..2b93cdd 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -351,6 +351,8 @@ static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) static const char compat[] = "ibm,power10-xscom\0ibm,xscom"; int i; + Pnv10Chip *chip10 = PNV10_CHIP(chip); + pnv_dt_xscom(chip, fdt, 0, cpu_to_be64(PNV10_XSCOM_BASE(chip)), cpu_to_be64(PNV10_XSCOM_SIZE), @@ -366,6 +368,9 @@ static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); } + /* Populate nest1_chiplet device tree */ + PNV_NEST1CHIPLET_GET_CLASS(&chip10->nest1_chiplet)->nest1_dt_populate(fdt); + pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); } @@ -1649,6 +1654,8 @@ static void pnv_chip_power10_instance_init(Object *obj) object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC); object_initialize_child(obj, "sbe", &chip10->sbe, TYPE_PNV10_SBE); object_initialize_child(obj, "homer", &chip10->homer, TYPE_PNV10_HOMER); + object_initialize_child(obj, "nest1_chiplet", &chip10->nest1_chiplet, + TYPE_PNV_NEST1_CHIPLET); chip->num_pecs = pcc->num_pecs; @@ -1813,6 +1820,13 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) memory_region_add_subregion(get_system_memory(), PNV10_HOMER_BASE(chip), &chip10->homer.regs); + /* nest1 chiplet control regs */ + if (!qdev_realize(DEVICE(&chip10->nest1_chiplet), NULL, errp)) { + return; + } + pnv_xscom_add_subregion(chip, PNV10_XSCOM_NEST1_CTRL_CHIPLET_BASE, + &chip10->nest1_chiplet.perv_chiplet.xscom_perv_ctrl_regs); + /* PHBs */ pnv_chip_power10_phb_realize(chip, &local_err); if (local_err) { diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h index 53e1d92..4bcb925 100644 --- a/include/hw/ppc/pnv_chip.h +++ b/include/hw/ppc/pnv_chip.h @@ -4,6 +4,7 @@ #include "hw/pci-host/pnv_phb4.h" #include "hw/ppc/pnv_core.h" #include "hw/ppc/pnv_homer.h" +#include "hw/ppc/pnv_nest_chiplet.h" #include "hw/ppc/pnv_lpc.h" #include "hw/ppc/pnv_occ.h" #include "hw/ppc/pnv_psi.h" @@ -109,6 +110,7 @@ struct Pnv10Chip { PnvOCC occ; PnvSBE sbe; PnvHomer homer; + PnvNest1Chiplet nest1_chiplet; uint32_t nr_quads; PnvQuad *quads;