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Thu, 14 Feb 2019 01:54:01 +0000 From: Anson Huang To: "robh+dt@kernel.org" , "mark.rutland@arm.com" , "shawnguo@kernel.org" , "s.hauer@pengutronix.de" , "kernel@pengutronix.de" , "festevam@gmail.com" , "mturquette@baylibre.com" , "sboyd@kernel.org" , Aisheng Dong , Daniel Baluta , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "linux-clk@vger.kernel.org" , "viresh.kumar@linaro.org" Subject: [PATCH V4 1/2] arm64: dts: freescale: imx8qxp: add cpu opp table Thread-Topic: [PATCH V4 1/2] arm64: dts: freescale: imx8qxp: add cpu opp table Thread-Index: AQHUxAgoEGMMDf+QVUa0wIDEs6tvwg== Date: Thu, 14 Feb 2019 01:54:01 +0000 Message-ID: <1550108915-574-1-git-send-email-Anson.Huang@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.7.4 x-clientproxiedby: HK2PR02CA0163.apcprd02.prod.outlook.com (2603:1096:201:1f::23) To DB3PR0402MB3916.eurprd04.prod.outlook.com (2603:10a6:8:10::18) authentication-results: spf=none (sender IP is ) smtp.mailfrom=anson.huang@nxp.com; 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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dl-linux-imx Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add i.MX8QXP CPU opp table to support cpufreq. Signed-off-by: Anson Huang --- No change since V3. --- arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi index 4021f25..593e2db 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -34,6 +34,10 @@ reg = <0x0 0x0>; enable-method = "psci"; next-level-cache = <&A35_L2>; + clocks = <&clk IMX_A35_CLK>; + clock-latency = <61036>; + #cooling-cells = <2>; + operating-points-v2 = <&a35_0_opp_table>; }; A35_1: cpu@1 { @@ -42,6 +46,7 @@ reg = <0x0 0x1>; enable-method = "psci"; next-level-cache = <&A35_L2>; + operating-points-v2 = <&a35_0_opp_table>; }; A35_2: cpu@2 { @@ -50,6 +55,7 @@ reg = <0x0 0x2>; enable-method = "psci"; next-level-cache = <&A35_L2>; + operating-points-v2 = <&a35_0_opp_table>; }; A35_3: cpu@3 { @@ -58,6 +64,7 @@ reg = <0x0 0x3>; enable-method = "psci"; next-level-cache = <&A35_L2>; + operating-points-v2 = <&a35_0_opp_table>; }; A35_L2: l2-cache0 { @@ -65,6 +72,24 @@ }; }; + a35_0_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <150000>; + }; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <150000>; + opp-suspend; + }; + }; + gic: interrupt-controller@51a00000 { compatible = "arm,gic-v3"; reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ From patchwork Thu Feb 14 01:54:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anson Huang X-Patchwork-Id: 10811601 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1048F13BF for ; Thu, 14 Feb 2019 01:54:21 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EF12C28682 for ; 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bh=hHkYAJ4t/SYAqFMpMYi9fxYycrMV51Pn/LP5JnRobNs=; b=rJwFqxdB81iPZ2hhBT0EwrgGJX8k8yY3BfqdqHRyjRRoPAM5KMG3MW+ISDwAgUov98v6pJo+8hBjpU8s6wGdBylesmakNwiBmq0BM59nTyVAv8+0EUXvJdAb1B8BkbNbOwg/PLD8jgct4I84wANt7wj+KDjKVnsQCn4xAxYgF2w= Received: from DB3PR0402MB3916.eurprd04.prod.outlook.com (52.134.72.18) by DB3PR0402MB3850.eurprd04.prod.outlook.com (52.134.65.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1601.22; Thu, 14 Feb 2019 01:54:08 +0000 Received: from DB3PR0402MB3916.eurprd04.prod.outlook.com ([fe80::14e8:6d2e:fe21:4fd5]) by DB3PR0402MB3916.eurprd04.prod.outlook.com ([fe80::14e8:6d2e:fe21:4fd5%3]) with mapi id 15.20.1601.023; Thu, 14 Feb 2019 01:54:08 +0000 From: Anson Huang To: "robh+dt@kernel.org" , "mark.rutland@arm.com" , "shawnguo@kernel.org" , "s.hauer@pengutronix.de" , "kernel@pengutronix.de" , "festevam@gmail.com" , "mturquette@baylibre.com" , "sboyd@kernel.org" , Aisheng Dong , Daniel Baluta , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "linux-clk@vger.kernel.org" , "viresh.kumar@linaro.org" Subject: [PATCH V4 2/2] clk: imx: scu: add cpu frequency scaling support Thread-Topic: [PATCH V4 2/2] clk: imx: scu: add cpu frequency scaling support Thread-Index: AQHUxAgs8uuWj5mH40eZScOWTh4APw== Date: Thu, 14 Feb 2019 01:54:08 +0000 Message-ID: <1550108915-574-2-git-send-email-Anson.Huang@nxp.com> References: <1550108915-574-1-git-send-email-Anson.Huang@nxp.com> In-Reply-To: <1550108915-574-1-git-send-email-Anson.Huang@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.7.4 x-clientproxiedby: HK2PR02CA0163.apcprd02.prod.outlook.com (2603:1096:201:1f::23) To DB3PR0402MB3916.eurprd04.prod.outlook.com (2603:10a6:8:10::18) authentication-results: spf=none (sender IP is ) smtp.mailfrom=anson.huang@nxp.com; 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This patch adds i.MX system controller CPU frequency scaling support, it reuses cpufreq-dt driver and implement the CPU frequency scaling inside SCU clock driver. Signed-off-by: Anson Huang Acked-by: Stephen Boyd --- Changes since V3: - use different clk ops for CPU clock to avoid runtime check in clk_set_rate; - use rsrc_id to determine whether it is CPU frequency change and also to get cluster ID for SMC call. --- drivers/clk/imx/clk-scu.c | 35 ++++++++++++++++++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-scu.c b/drivers/clk/imx/clk-scu.c index 7ccf7ed..c234a6e 100644 --- a/drivers/clk/imx/clk-scu.c +++ b/drivers/clk/imx/clk-scu.c @@ -4,12 +4,17 @@ * Dong Aisheng */ +#include +#include #include #include #include #include "clk-scu.h" +#define IMX_SIP_CPUFREQ 0xC2000001 +#define IMX_SIP_SET_CPUFREQ 0x00 + static struct imx_sc_ipc *ccm_ipc_handle; /* @@ -145,6 +150,23 @@ static long clk_scu_round_rate(struct clk_hw *hw, unsigned long rate, return rate; } +static int clk_scu_atf_set_cpu_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_scu *clk = to_clk_scu(hw); + struct arm_smccc_res res; + unsigned long cluster_id; + + if (clk->rsrc_id == IMX_SC_R_A35) + cluster_id = 0; + + /* CPU frequency scaling can ONLY be done by ARM-Trusted-Firmware */ + arm_smccc_smc(IMX_SIP_CPUFREQ, IMX_SIP_SET_CPUFREQ, + cluster_id, rate, 0, 0, 0, 0, &res); + + return 0; +} + /* * clk_scu_set_rate - Set rate for a SCU clock * @hw: clock to change rate for @@ -232,6 +254,14 @@ static const struct clk_ops clk_scu_ops = { .unprepare = clk_scu_unprepare, }; +static const struct clk_ops clk_scu_cpu_ops = { + .recalc_rate = clk_scu_recalc_rate, + .round_rate = clk_scu_round_rate, + .set_rate = clk_scu_atf_set_cpu_rate, + .prepare = clk_scu_prepare, + .unprepare = clk_scu_unprepare, +}; + struct clk_hw *imx_clk_scu(const char *name, u32 rsrc_id, u8 clk_type) { struct clk_init_data init; @@ -247,7 +277,10 @@ struct clk_hw *imx_clk_scu(const char *name, u32 rsrc_id, u8 clk_type) clk->clk_type = clk_type; init.name = name; - init.ops = &clk_scu_ops; + if (rsrc_id == IMX_SC_R_A35) + init.ops = &clk_scu_cpu_ops; + else + init.ops = &clk_scu_ops; init.num_parents = 0; /* * Note on MX8, the clocks are tightly coupled with power domain