From patchwork Thu Nov 9 19:13:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Quinlan X-Patchwork-Id: 13451652 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BFF95C4332F for ; Thu, 9 Nov 2023 19:14:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234659AbjKITOI (ORCPT ); Thu, 9 Nov 2023 14:14:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37700 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230185AbjKITOI (ORCPT ); Thu, 9 Nov 2023 14:14:08 -0500 Received: from mail-pl1-x636.google.com (mail-pl1-x636.google.com [IPv6:2607:f8b0:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1D1FA3C13 for ; Thu, 9 Nov 2023 11:14:06 -0800 (PST) Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-1cc58219376so11195345ad.1 for ; Thu, 09 Nov 2023 11:14:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1699557245; x=1700162045; darn=vger.kernel.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=cj3ECyT0kKgX9OMN3LVQVHviwSNFY7MUvWn4Mo5E0xo=; b=d0FJLKJnFN5cfBwkNrhCgVq+sJRGSYr3WbAQHfmFU7gG011wWUA/vuBrb6lsfbaQXA k3IMlXTKARr4HktCzJk7IeVH97V42zhQKLedcZWRMiDwPqbsX6ps+IL/kF+lqA1p7xnc rBNheoUQkkfnAEyTP7JlLrJtBLLLMBtOXDb+Q= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699557245; x=1700162045; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=cj3ECyT0kKgX9OMN3LVQVHviwSNFY7MUvWn4Mo5E0xo=; b=qKMhL4fv0udk8qAFIXQ8kdaQPAZbq4Fn35VI//uS1mI6bq6TrzF8hS/wu0Crka1hv+ Axm+onsA2O9it9maRT5baA+Pjj4a7v61hb99NqNRFnxb+sM7M73GKT81t5ynrVbq3E62 kXpDDCuRsBcEKs0F1zbWmPdsE4tP0V94HQJ6HhrwYULQKKbltoQoNuv84wsAXtj+3+W3 p4T7POrsXP/8ATWFl+pPgLgZ54skDOmZ+6aoV0w6RX0Z+EnoqVIeI15Cn1btocJ52wWH AxRO0DQIY/MM6ZvE/OdCw2fyT/sWrfT/k8jL3c63P+CGnzwhXsgb/FufYjJYHnND9+8I DOWQ== X-Gm-Message-State: AOJu0Yy2ai9CJH8TB95a0OfOL4s/e5nOOaC8wMV0AkB6BE/OgxaaJpRA OxCQDh3x6ybQXN4ivGMNg1yFSEzVveWAbxeS7gI+P4fEHi9iVUwy+Q8WsjTF2Zf2NDBgfsruEqW eNyFsDXQg4pTurfFrodE44npPjZ8JdUrTMvHQ3dwy8VxK9sC5WAM1Sm3ViQSU/Q8YSBnXtzC3bE RsG1RKPi0H3JPC X-Google-Smtp-Source: AGHT+IEeKu000QUnOY8ufASRQnlK20TPw6yuERVkwYldxGsl22CFd1ano6SoYr6eisX00tuZkdW9tw== X-Received: by 2002:a17:90b:4c91:b0:27f:df1e:199e with SMTP id my17-20020a17090b4c9100b0027fdf1e199emr3039866pjb.28.1699557245028; Thu, 09 Nov 2023 11:14:05 -0800 (PST) Received: from stbsrv-and-01.and.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id pj9-20020a17090b4f4900b00282ecb631a9sm124069pjb.25.2023.11.09.11.14.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Nov 2023 11:14:04 -0800 (PST) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , Phil Elwell , bcm-kernel-feedback-list@broadcom.com, james.quinlan@broadcom.com Cc: Jim Quinlan , Florian Fainelli , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE), linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v7 1/3] dt-bindings: PCI: brcmstb: Add property "brcm,clkreq-mode" Date: Thu, 9 Nov 2023 14:13:52 -0500 Message-Id: <20231109191355.27738-2-james.quinlan@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231109191355.27738-1-james.quinlan@broadcom.com> References: <20231109191355.27738-1-james.quinlan@broadcom.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The Broadcom STB/CM PCIe HW -- a core that is also used by RPi SOCs -- requires the driver to deliberately place the RC HW one of three CLKREQ# modes. The "brcm,clkreq-mode" property allows the user to override the default setting. If this property is omitted, the default mode shall be "default". Signed-off-by: Jim Quinlan --- .../bindings/pci/brcm,stb-pcie.yaml | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml index 7e15aae7d69e..992b35e915a5 100644 --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml @@ -64,6 +64,27 @@ properties: aspm-no-l0s: true + brcm,clkreq-mode: + description: A string that determines the operating + clkreq mode of the PCIe RC HW WRT controlling the refclk signal. + There are three different modes -- + "safe", which drives the + refclk signal unconditionally and will work for all devices but does + not provide any power savings; + "no-l1ss" -- which provides Clock Power Management, L0s, and + L1, but cannot provide L1 substate (L1SS) power + savings. If the downstream device connected to the RC is + L1SS capable AND the OS enables L1SS, all PCIe traffic + may abruptly halt, potentially hanging the system; + "default" -- which provides L0s, L1, and L1SS, but not + compliant to provide Clock Power Management; + specifically, may not be able to meet the Tclron max + timing of 400ns as specified in "Dynamic Clock Control", + section 3.2.5.2.2 of the PCIe spec. This situation is + atypical and should happen only with older devices. + $ref: /schemas/types.yaml#/definitions/string + enum: [ safe, no-l1ss, default ] + brcm,scb-sizes: description: u64 giving the 64bit PCIe memory viewport size of a memory controller. There may be up to From patchwork Thu Nov 9 19:13:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Quinlan X-Patchwork-Id: 13451653 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B70CDC4332F for ; Thu, 9 Nov 2023 19:14:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234750AbjKITOQ (ORCPT ); Thu, 9 Nov 2023 14:14:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37830 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234766AbjKITOL (ORCPT ); Thu, 9 Nov 2023 14:14:11 -0500 Received: from mail-pg1-x535.google.com (mail-pg1-x535.google.com [IPv6:2607:f8b0:4864:20::535]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B71D23C1D for ; Thu, 9 Nov 2023 11:14:09 -0800 (PST) Received: by mail-pg1-x535.google.com with SMTP id 41be03b00d2f7-5bd099e3d3cso944499a12.1 for ; Thu, 09 Nov 2023 11:14:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1699557248; x=1700162048; darn=vger.kernel.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=DAybglcYL9refhWhesRdogos54dvF4427E0+TxEAlZg=; b=hz863U84kzCW1tRXSF5w4RVwSRRgkE/Qkcn1TeQZRjKr4wvpcZQdQ3yCkTdfGPZJVn pnucaEYNLTs2LI7p9CfYu7bDDyq5wEOVc2hQnEqnoGzQdFHcF1ZhKZwugN3I7aacZPGZ d+ih+a7Z3juJ/H+QY/TUgA1OUxY01k/yA1He0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699557248; x=1700162048; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=DAybglcYL9refhWhesRdogos54dvF4427E0+TxEAlZg=; b=kHybnCF6QCFufv0pHXOoDR8u9+Z1WWt2ed4opB7AY2hdPXC0UUrSOmVHaZt38RgswQ WCULfgzfCwG8lSjTyLtzKZLBYNiGp1i39sq9ZZLvSz/V6RYeGc1m1L3zHcTUCROeTMBC wdXp7m92rCArJ/Yh7zKkZ5/1fWZjxuCfYUcuXMYDRIHo2vGSbUVehwpmLkOt+l8llQGu DlpmXTD/5Uk7UolLctBifk5bzu/8OcxtfrMm23v0pzWgQdkYTPB8UF3Kwd+8xmbgvhz7 8wMQYPMaI+BQGqqBJYUBc6eCE0ZI0EnGxSASx4wUsGwNVfvrW+UsjwH+q5JP0okIjs4r 5/qg== X-Gm-Message-State: AOJu0YyqCiy+vSgO2aiQ9kBuF1kvw+3CQ5J5vG4YeemfCSb0cRX3GlU6 4cWBeQehnigjMubzjqoE8aUqX666MHW4kjj7c/Kv3sYsIpX6s5L+6Ku8XjFxoYvf4eiDoTjpUzw K/bXa3d5/Epf/ujqmCjUskFhlIXxAwlMwp6EKwF485Si7VlpIzgxYtcYmGZKeL6ahz/fqgJbJGO xOdVbkDD0XQEwJ X-Google-Smtp-Source: AGHT+IFbDMN3XcDP+WCQ+MCqwQDFoK+t2VBXmAyPT88GE+vPDmT6ZyG5Ec6Dx8qq3L5NTlqh6duAFg== X-Received: by 2002:a17:90a:eb0a:b0:280:509:30c6 with SMTP id j10-20020a17090aeb0a00b00280050930c6mr2484093pjz.46.1699557248151; Thu, 09 Nov 2023 11:14:08 -0800 (PST) Received: from stbsrv-and-01.and.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id pj9-20020a17090b4f4900b00282ecb631a9sm124069pjb.25.2023.11.09.11.14.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Nov 2023 11:14:07 -0800 (PST) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , Phil Elwell , bcm-kernel-feedback-list@broadcom.com, james.quinlan@broadcom.com Cc: Jim Quinlan , Florian Fainelli , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v7 2/3] PCI: brcmstb: Configure HW CLKREQ# mode appropriate for downstream device Date: Thu, 9 Nov 2023 14:13:53 -0500 Message-Id: <20231109191355.27738-3-james.quinlan@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231109191355.27738-1-james.quinlan@broadcom.com> References: <20231109191355.27738-1-james.quinlan@broadcom.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The Broadcom STB/CM PCIe HW core, which is also used in RPi SOCs, must be deliberately set by the PCIe RC HW into one of three mutually exclusive modes: "safe" -- No CLKREQ# expected or required, refclk is always provided. This mode should work for all devices but is not be capable of any refclk power savings. "no-l1ss" -- CLKREQ# is expected to be driven by the downstream device for CPM and ASPM L0s and L1. Provides Clock Power Management, L0s, and L1, but cannot provide L1 substate (L1SS) power savings. If the downstream device connected to the RC is L1SS capable AND the OS enables L1SS, all PCIe traffic may abruptly halt, potentially hanging the system. "default" -- Bidirectional CLKREQ# between the RC and downstream device. Provides ASPM L0s, L1, and L1SS, but not compliant to provide Clock Power Management; specifically, may not be able to meet the Tclron max timing of 400ns as specified in "Dynamic Clock Control", section 3.2.5.2.2 of the PCIe spec. This situation is atypical and should happen only with older devices. Previously, this driver always set the mode to "no-l1ss", as almost all STB/CM boards operate in this mode. But now there is interest in activating L1SS power savings from STB/CM customers, which requires "aspm" mode. In addition, a bug was filed for RPi4 CM platform because most devices did not work in "no-l1ss" mode. Note that the mode is specified by the DT property "brcm,clkreq-mode". If this property is omitted, then "default" mode is chosen. Link: https://bugzilla.kernel.org/show_bug.cgi?id=217276 Signed-off-by: Jim Quinlan --- drivers/pci/controller/pcie-brcmstb.c | 65 ++++++++++++++++++++++----- 1 file changed, 55 insertions(+), 10 deletions(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c index f9dd6622fe10..f45c5d0168d3 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -121,9 +121,12 @@ #define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2 +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_L1SS_ENABLE_MASK 0x200000 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000 #define PCIE_BMIPS_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x00800000 - +#define PCIE_CLKREQ_MASK \ + (PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK | \ + PCIE_MISC_HARD_PCIE_HARD_DEBUG_L1SS_ENABLE_MASK) #define PCIE_INTR2_CPU_BASE 0x4300 #define PCIE_MSI_INTR2_BASE 0x4500 @@ -1028,13 +1031,61 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) return 0; } +static void brcm_config_clkreq(struct brcm_pcie *pcie) +{ + static const char err_msg[] = "invalid 'brcm,clkreq-mode' DT string\n"; + const char *mode = "default"; + u32 clkreq_cntl; + int ret; + + ret = of_property_read_string(pcie->np, "brcm,clkreq-mode", &mode); + if (ret && ret != -EINVAL) { + dev_err(pcie->dev, err_msg); + mode = "safe"; + } + + /* Start out assuming safe mode (both mode bits cleared) */ + clkreq_cntl = readl(pcie->base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); + clkreq_cntl &= ~PCIE_CLKREQ_MASK; + + if (strcmp(mode, "no-l1ss") == 0) { + /* + * "no-l1ss" -- Provides Clock Power Management, L0s, and + * L1, but cannot provide L1 substate (L1SS) power + * savings. If the downstream device connected to the RC is + * L1SS capable AND the OS enables L1SS, all PCIe traffic + * may abruptly halt, potentially hanging the system. + */ + clkreq_cntl |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK; + } else if (strcmp(mode, "default") == 0) { + /* + * "default" -- Provides L0s, L1, and L1SS, but not + * compliant to provide Clock Power Management; + * specifically, may not be able to meet the Tclron max + * timing of 400ns as specified in "Dynamic Clock Control", + * section 3.2.5.2.2 of the PCIe spec. This situation is + * atypical and should happen only with older devices. + */ + clkreq_cntl |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_L1SS_ENABLE_MASK; + } else { + /* + * "safe" -- No power savings; refclk is driven by RC + * unconditionally. + */ + if (strcmp(mode, "safe") != 0) + dev_err(pcie->dev, err_msg); + mode = "safe"; + } + writel(clkreq_cntl, pcie->base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); + dev_info(pcie->dev, "clkreq-mode set to %s\n", mode); +} + static int brcm_pcie_start_link(struct brcm_pcie *pcie) { struct device *dev = pcie->dev; void __iomem *base = pcie->base; u16 nlw, cls, lnksta; bool ssc_good = false; - u32 tmp; int ret, i; /* Unassert the fundamental reset */ @@ -1059,6 +1110,8 @@ static int brcm_pcie_start_link(struct brcm_pcie *pcie) return -ENODEV; } + brcm_config_clkreq(pcie); + if (pcie->gen) brcm_pcie_set_gen(pcie, pcie->gen); @@ -1077,14 +1130,6 @@ static int brcm_pcie_start_link(struct brcm_pcie *pcie) pci_speed_string(pcie_link_speed[cls]), nlw, ssc_good ? "(SSC)" : "(!SSC)"); - /* - * Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1 - * is enabled => setting the CLKREQ_DEBUG_ENABLE field to 1. - */ - tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); - tmp |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK; - writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); - return 0; } From patchwork Thu Nov 9 19:13:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Quinlan X-Patchwork-Id: 13451654 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F3F9CC4332F for ; Thu, 9 Nov 2023 19:14:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234809AbjKITOV (ORCPT ); Thu, 9 Nov 2023 14:14:21 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37792 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234808AbjKITOT (ORCPT ); Thu, 9 Nov 2023 14:14:19 -0500 Received: from mail-pj1-x1035.google.com (mail-pj1-x1035.google.com [IPv6:2607:f8b0:4864:20::1035]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C8DE03C19 for ; Thu, 9 Nov 2023 11:14:12 -0800 (PST) Received: by mail-pj1-x1035.google.com with SMTP id 98e67ed59e1d1-28037d046b0so1055259a91.3 for ; Thu, 09 Nov 2023 11:14:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1699557251; x=1700162051; darn=vger.kernel.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=kMhkIiEUKQw3C/Si5kBml1FUuKIlgD/xSCHTIzP3dAs=; b=J8AnOdfphQdRuuxHP5Ywz2+E0BoLHtnj59h8P1d3BuV3NL83tAP2DATCsgw1+nMST2 qRd1euDDdSDp9QpIPtTdvxrbCaQAlkslgwi8Kacv3gzVTFWX1eZky1CW2X/FqVrkjrr0 1nyFhgcvIfdt+JY0TUIC4Aw0ahyQMb0dSinaM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699557251; x=1700162051; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=kMhkIiEUKQw3C/Si5kBml1FUuKIlgD/xSCHTIzP3dAs=; b=gvoh+r06s2J6+7B7RLO88LNcTApoB7simG6p0OjoLQq2vg8rGCL61bwbhN+BFRbmTA csov6auRBN411EeswEOZ14rwOM6k0zap6hTBLZcG68gsjXfts2/IoDOBU7hg/gyD6ACA b4cyj7Qwd0lfqwUN+14yfityne0IJOlcAp7ZPz9+KaXLgph3DH/vlxlFhhbgbux3ME36 QcdirCXvvsZ2wnT1EiiUDxfMRQFFLKS1FBM3CFuXVWI86tpU/GKNJ38PLg+hfFPC+R9l AbZDCr13YOOQwHOFZzqgJHXiNQ6+wcWLtRscs26WCLAsIMM1fHI6Z46fqB1zKkTD7IF0 ApmQ== X-Gm-Message-State: AOJu0Yz5HIuFSQqmXxfKKKf3fs51erApt75qQ1z/Dd8dPYyVktMz0JPw +N7T2qZWVXZzoP2NsntpNsSgwTSTphF0Wi/cYt53HrA14Ga0db2FdMFNVOlahirqgiR+NXpZRyT tAMbDBaNmCEpuwJfavYO3/mBIPGO8GpFwd21GssWu79pEwbVqL5tg/qp/pACdvI75kMLfawDbuj 7A75rIzyeHaF45 X-Google-Smtp-Source: AGHT+IGr9VprmPbSO0Bq6pzvM7OCgl/VP1LuUfAbpUcm/xZIOExx4XrMUzb881hGGMqiWsezzj6W9w== X-Received: by 2002:a17:90a:d913:b0:280:3a0c:bf73 with SMTP id c19-20020a17090ad91300b002803a0cbf73mr2678933pjv.26.1699557251275; Thu, 09 Nov 2023 11:14:11 -0800 (PST) Received: from stbsrv-and-01.and.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id pj9-20020a17090b4f4900b00282ecb631a9sm124069pjb.25.2023.11.09.11.14.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Nov 2023 11:14:10 -0800 (PST) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , Phil Elwell , bcm-kernel-feedback-list@broadcom.com, james.quinlan@broadcom.com Cc: Florian Fainelli , Jim Quinlan , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v7 3/3] PCI: brcmstb: Set higher value for internal bus timeout Date: Thu, 9 Nov 2023 14:13:54 -0500 Message-Id: <20231109191355.27738-4-james.quinlan@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231109191355.27738-1-james.quinlan@broadcom.com> References: <20231109191355.27738-1-james.quinlan@broadcom.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org During long periods of the PCIe RC HW being in an L1SS sleep state, there may be a timeout on an internal bus access, even though there may not be any PCIe access involved. Such a timeout will cause a subsequent CPU abort. Signed-off-by: Jim Quinlan --- drivers/pci/controller/pcie-brcmstb.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c index f45c5d0168d3..f82a3e1a843a 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -1031,6 +1031,21 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) return 0; } +/* + * This extends the timeout period for an access to an internal bus. This + * access timeout may occur during L1SS sleep periods, even without the + * presence of a PCIe access. + */ +static void brcm_extend_rbus_timeout(struct brcm_pcie *pcie) +{ + /* TIMEOUT register is two registers before RGR1_SW_INIT_1 */ + const unsigned int REG_OFFSET = PCIE_RGR1_SW_INIT_1(pcie) - 8; + u32 timeout_us = 4000000; /* 4 seconds, our setting for L1SS */ + + /* Each unit in timeout register is 1/216,000,000 seconds */ + writel(216 * timeout_us, pcie->base + REG_OFFSET); +} + static void brcm_config_clkreq(struct brcm_pcie *pcie) { static const char err_msg[] = "invalid 'brcm,clkreq-mode' DT string\n"; @@ -1067,6 +1082,7 @@ static void brcm_config_clkreq(struct brcm_pcie *pcie) * atypical and should happen only with older devices. */ clkreq_cntl |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_L1SS_ENABLE_MASK; + brcm_extend_rbus_timeout(pcie); } else { /* * "safe" -- No power savings; refclk is driven by RC