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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: G6hrnA7HPG8TEinXNjqpa889QhOk483vPGC4PgrqdZz3i3R1Tdq1g6oBxeV1oSvIHWEh14d6EmM0ukqAFsWWv4JOGb5e8fS9dC08Ev4y8WjxhBz3sMk9LRC9qt79ddDfR1C5RV9JeiuSkYueh4SPRSv2W2X2IED8/gZnWnbBlvkhGJEoIEdBav/T3gvckk/30FdDSVaEos7R6YjB0Kd5SeQxkCaNbbaNc36uLPsG34Uk+TF2j3RUCeq6qiGmKS53kdkjUtVUy2RUlI0AC89oNWuN/XMah7c4tc8OX+j2qK5lIKZ0enoGvcC6Vzmx3HEPalNV5kcWozzKGiU1ZPJDcEYyvL/Z2Cx8XKARV9n8HWXbCuE4t6v6excU/RA/QRUJPqyD6SSJdCEoAsgNWKKGLpmFG/N2/KFFXV0+bqkbXsZP+O20QZbbMwOG90bGac9UcaPXeVSSFNungKDQ9AJzMCA2L/FzZkwZ051yK3WSlrJuEqGMvTzZYyaZOXNgCrvvWxZKEAp3ElIEnUBnFjQY+0VvDhtTU+HduoJSJEerhIlb33QuoW0C1LQdwUZJjBGAstno03lw8kupnfu/+xIA+GhjP5CFw1nfjNabhcL42KpzAdr5DMqFnC5UJMCBnS5TA+V1j+/WUMDc4zHWGvwVQOH5loMspsWb5x5l4+wGmgSTQMtjsQf7CNFYUIcfB+Vyk1ZbsbsMHplqaDTQ2xgOy23L+4lp2iW+BE51/qw2c3bWbjt3bWHBvpQ9VMt/FKeJChc1mqm0YxqiI6I488flOhgWbAqG0D5DLJp3K1RSl7jysWubG1PG/K8y1lhkhBxTtnCgUuKnrPEvus8x1LkZGAl/ZRnPKERNFrigV25HZBP1YhVKOTx13cblBhgEkMLUk2WurrnMKTc/lrtgUScej8qXi08JqDj5LVUXfF+NsEg7+NjzScYyDm0CW3pmpWRuxHjjEW6/tOsKV1bLxJUwWxCUGPjFyiEaOG03Hath41rKMO6dJ5NTQD4oDVvHLOXVu0pXiujaIKqUclhMqdlzU6GngMk/8p43xSZkag0Ra7EKpL1jms6VBLh9HNm3GGp7p7K2Ky6hVXbKyS/byD5ZJYTno0b5Zi084fvFr5XpGv7dAg1r4EkFGoOHwDnLvZ88Lg+Ui6yXiVzE2dGuFGRmD4/vR0XrvVjG7v4Uh1Ykf3X6Pz3fI3EUmkMkkAo9d8LkZbPP7DX6Zwf4ufO/DXVI3bmNe7++kwK9BKTqphZ5Sr0oDa3WN+hgjyxwhiGJvSyI7CF9HBGM+t5ZAja5mjcS0VKxG6Z0ipV0huCRuW6R3pEOpy/3vQFwVmYRgRn5yLyBHXRf+pdANz/cG0+R/3hE0CGw6GmbCszvu6d9eLCx5h/Lb03SqzjW66Wh9Lq7cNpEF1HBvebg2ZpSxIzF46xHFdRja/cgtOzNgPCZtZlr/9S7AhFd6tQR+/ge0PPqLfaBhktCkDkokMtp7erNjnPMCjDJbaeeZbblOXShX0SeJ6SRYwF+sxS3v2m1uFYN0B5+UjBptiumDgO7fbu1cgLsE3dbZhAK4ZQRET3adAbDuwg= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 32a6b557-af37-4f0c-6a95-08dbe5293046 X-MS-Exchange-CrossTenant-AuthSource: AM6PR04MB4838.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Nov 2023 15:48:47.1413 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: zgNmV/Ior5IihPDOW+k719p6NVfPSyw85qMNn2gCWBz4qscpojioDQ8qSKrPXPqzyEAkFb5qLY00NL6IPoWkiA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9PR04MB8113 The eDMAv4 channel mux has a limitation where certain requests must use even channels, while others must use odd numbers. Add two flags (ARGS_EVEN_CH and ARGS_ODD_CH) to reflect this limitation. The device tree source (dts) files need to be updated accordingly. This issue was identified by the following commit: commit a725990557e7 ("arm64: dts: imx93: Fix the dmas entries order") Reverting channel orders triggered this problem. Fixes: 72f5801a4e2b ("dmaengine: fsl-edma: integrate v3 support") Signed-off-by: Frank Li --- drivers/dma/fsl-edma-main.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/dma/fsl-edma-main.c b/drivers/dma/fsl-edma-main.c index 4635e16d7705e..3ee08f390f810 100644 --- a/drivers/dma/fsl-edma-main.c +++ b/drivers/dma/fsl-edma-main.c @@ -24,6 +24,8 @@ #define ARGS_RX BIT(0) #define ARGS_REMOTE BIT(1) #define ARGS_MULTI_FIFO BIT(2) +#define ARGS_EVEN_CH BIT(3) +#define ARGS_ODD_CH BIT(4) static void fsl_edma_synchronize(struct dma_chan *chan) { @@ -157,6 +159,12 @@ static struct dma_chan *fsl_edma3_xlate(struct of_phandle_args *dma_spec, fsl_chan->is_remote = dma_spec->args[2] & ARGS_REMOTE; fsl_chan->is_multi_fifo = dma_spec->args[2] & ARGS_MULTI_FIFO; + if ((dma_spec->args[2] & ARGS_EVEN_CH) && (i & 0x1)) + continue; + + if ((dma_spec->args[2] & ARGS_ODD_CH) && !(i & 0x1)) + continue; + if (!b_chmux && i == dma_spec->args[0]) { chan = dma_get_slave_channel(chan); chan->device->privatecnt++; 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This addition aims to eliminate hardcoded values in dts files, promoting maintainability and consistency. DTS header file not support BIT() macro yet. Directly use 2^n number. Signed-off-by: Frank Li Reviewed-by: Rob Herring --- include/dt-bindings/dma/fsl-edma.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 include/dt-bindings/dma/fsl-edma.h diff --git a/include/dt-bindings/dma/fsl-edma.h b/include/dt-bindings/dma/fsl-edma.h new file mode 100644 index 0000000000000..fd11478cfe9cc --- /dev/null +++ b/include/dt-bindings/dma/fsl-edma.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ + +#ifndef _FSL_EDMA_DT_BINDING_H_ +#define _FSL_EDMA_DT_BINDING_H_ + +/* Receive Channel */ +#define FSL_EDMA_RX 0x1 + +/* iMX8 audio remote DMA */ +#define FSL_EDMA_REMOTE 0x2 + +/* FIFO is continue memory region */ +#define FSL_EDMA_MULTI_FIFO 0x4 + +/* Channel need stick to even channel */ +#define FSL_EDMA_EVEN_CH 0x8 + +/* Channel need stick to odd channel */ +#define FSL_EDMA_ODD_CH 0x10 + +#endif From patchwork Tue Nov 14 15:48:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 13455556 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 55F6A41771; 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Renaming ARGS* to FSL_EDMA*, ensuring no functional changes. Signed-off-by: Frank Li --- drivers/dma/fsl-edma-main.c | 17 ++++++----------- 1 file changed, 6 insertions(+), 11 deletions(-) diff --git a/drivers/dma/fsl-edma-main.c b/drivers/dma/fsl-edma-main.c index 3ee08f390f810..f53b0ec17bcbc 100644 --- a/drivers/dma/fsl-edma-main.c +++ b/drivers/dma/fsl-edma-main.c @@ -9,6 +9,7 @@ * Vybrid and Layerscape SoCs. */ +#include #include #include #include @@ -21,12 +22,6 @@ #include "fsl-edma-common.h" -#define ARGS_RX BIT(0) -#define ARGS_REMOTE BIT(1) -#define ARGS_MULTI_FIFO BIT(2) -#define ARGS_EVEN_CH BIT(3) -#define ARGS_ODD_CH BIT(4) - static void fsl_edma_synchronize(struct dma_chan *chan) { struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); @@ -155,14 +150,14 @@ static struct dma_chan *fsl_edma3_xlate(struct of_phandle_args *dma_spec, i = fsl_chan - fsl_edma->chans; fsl_chan->priority = dma_spec->args[1]; - fsl_chan->is_rxchan = dma_spec->args[2] & ARGS_RX; - fsl_chan->is_remote = dma_spec->args[2] & ARGS_REMOTE; - fsl_chan->is_multi_fifo = dma_spec->args[2] & ARGS_MULTI_FIFO; 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Received: from AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) by AM9PR04MB8113.eurprd04.prod.outlook.com (2603:10a6:20b:3b5::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7002.17; Tue, 14 Nov 2023 15:48:59 +0000 Received: from AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::bc7:1dcd:684d:4494]) by AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::bc7:1dcd:684d:4494%4]) with mapi id 15.20.7002.015; Tue, 14 Nov 2023 15:48:59 +0000 From: Frank Li To: krzysztof.kozlowski@linaro.org, shawnguo@kernel.org, festevam@denx.de Cc: Frank.li@nxp.com, devicetree@vger.kernel.org, dmaengine@vger.kernel.org, imx@lists.linux.dev, joy.zou@nxp.com, krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org, peng.fan@nxp.com, robh+dt@kernel.org, shenwei.wang@nxp.com, vkoul@kernel.org Subject: [PATCH 4/4] arm64: dts: imx93: Fix EDMA transfer failure Date: Tue, 14 Nov 2023 10:48:24 -0500 Message-Id: <20231114154824.3617255-5-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231114154824.3617255-1-Frank.Li@nxp.com> References: <20231114154824.3617255-1-Frank.Li@nxp.com> X-ClientProxiedBy: BY5PR13CA0010.namprd13.prod.outlook.com (2603:10b6:a03:180::23) To AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM6PR04MB4838:EE_|AM9PR04MB8113:EE_ X-MS-Office365-Filtering-Correlation-Id: f261359b-e079-4001-9f4e-08dbe5293755 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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The previous eDMA driver did not account for these restrictions, and it worked due to the order in dts matching the requirements. The commit below reverts the rx/tx channel, triggering this issue. Adds channel requirements to the dts to instruct the driver to allocate odd or even channels, ensuring it is not dependent on the order of rx/tx in dts. Fixes: a725990557e7 ("arm64: dts: imx93: Fix the dmas entries order") Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx93.dtsi | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi index ceccf47664407..6f06ebdcb2513 100644 --- a/arch/arm64/boot/dts/freescale/imx93.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -670,7 +671,8 @@ lpuart3: serial@42570000 { interrupts = ; clocks = <&clk IMX93_CLK_LPUART3_GATE>; clock-names = "ipg"; - dmas = <&edma2 18 0 1>, <&edma2 17 0 0>; + dmas = <&edma2 18 0 (FSL_EDMA_RX | FSL_EDMA_ODD_CH)>, + <&edma2 17 0 FSL_EDMA_EVEN_CH>; dma-names = "rx", "tx"; status = "disabled"; }; @@ -681,7 +683,8 @@ lpuart4: serial@42580000 { interrupts = ; clocks = <&clk IMX93_CLK_LPUART4_GATE>; clock-names = "ipg"; - dmas = <&edma2 20 0 1>, <&edma2 19 0 0>; + dmas = <&edma2 20 0 (FSL_EDMA_RX | FSL_EDMA_ODD_CH)>, + <&edma2 19 0 FSL_EDMA_EVEN_CH>; dma-names = "rx", "tx"; status = "disabled"; }; @@ -692,7 +695,8 @@ lpuart5: serial@42590000 { interrupts = ; clocks = <&clk IMX93_CLK_LPUART5_GATE>; clock-names = "ipg"; - dmas = <&edma2 22 0 1>, <&edma2 21 0 0>; + dmas = <&edma2 22 0 (FSL_EDMA_RX | FSL_EDMA_ODD_CH)>, + <&edma2 21 0 FSL_EDMA_EVEN_CH>; dma-names = "rx", "tx"; status = "disabled"; }; @@ -703,7 +707,8 @@ lpuart6: serial@425a0000 { interrupts = ; clocks = <&clk IMX93_CLK_LPUART6_GATE>; clock-names = "ipg"; - dmas = <&edma2 24 0 1>, <&edma2 23 0 0>; + dmas = <&edma2 24 0 (FSL_EDMA_RX | FSL_EDMA_ODD_CH)>, + <&edma2 23 0 FSL_EDMA_EVEN_CH>; dma-names = "rx", "tx"; status = "disabled"; };