From patchwork Fri Oct 27 14:39:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13455617 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1qwO04-0007BE-VB for mharc-qemu-devel@gnu.org; Fri, 27 Oct 2023 10:39:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qwO03-0007B4-RU for qemu-devel@nongnu.org; Fri, 27 Oct 2023 10:39:47 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qwO02-00086T-05 for qemu-devel@nongnu.org; Fri, 27 Oct 2023 10:39:47 -0400 Received: by mail-wr1-x431.google.com with SMTP id ffacd0b85a97d-32d9d8284abso1389249f8f.3 for ; Fri, 27 Oct 2023 07:39:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698417584; x=1699022384; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=3xRTp/BRadA7ZN58Un+Px0Mehec0HXObngq8aZKQDU8=; b=PzJAnLdvntFYHU6zE5HHnu12yQ5+52PKFrqYuWVC5/4xCKZ6L96BclGNk7XIajPc76 MXmSc8HkDktgMMzY/yXChEVbO1UHD5yi5lh9cb9A+Xlx3vUMIDTs6RapU7BUJLinFTRV nPs/Ov2zrI18V2oxY7Dp5YHr1jgMtnCTVl/hlhTSbGvsrrh2jX8H6HXVBetI0Ojo6Rbw MpV4Ph0dSrkbJDIVnsyUQJKNVFGGRPtW80lIR3SRmxH4R+HxMrfccXNtA+IKT1bOQx35 LNtbfE28rbxmXU4n5TBLRP+HsMXmxrMiAFurmIQQb70lb865rqtgcSUu4aAMjglI0lyh ET4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698417584; x=1699022384; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3xRTp/BRadA7ZN58Un+Px0Mehec0HXObngq8aZKQDU8=; b=bvzT9+sFDK9YccfdMQxfGEr/ywJjr4HzrMLFWwNv93cEarLUsw4YupTK04jCvuMFwb H6GFhyMmdaQrezMdycGLnSxG0vVV4Ra+TDfSy+xDlrkbICOKv31LIdqUhTi5XtiNiK/A 5IODmW7qw16TD4UrlXxLLE8PG0GIFuWVMGMrgbs8oA4e0wAbED1o1+nOKUmQ5X63a8+O XyoFvKGw0UzPlzfRoUu8HudJClWmyTcKmsr7UbMIfd+T0ToPxNeMJT7of8uNKYEZlCeK +ryl+qakAC2IUJV6DZXfbpCj9dzDfCIxnMJmM1IPA6Lo7iUjmdwmFZmPRnzogbKCGeow 7rag== X-Gm-Message-State: AOJu0Yxj14RWCC+uGjjSwbaMgwnnxJQlvVadQ3PWzFuvLR+IEzr+cxuf Y7323svlOUgi3FPTheRIhboItVBstEpTNZcLwbQ= X-Google-Smtp-Source: AGHT+IHTBqEud57WhQd9jidMP4tHr02SII/43v60BJPrHE1lgxGwbE1mfXICHZkqcFnc4tcgCJenyg== X-Received: by 2002:a5d:5381:0:b0:32d:939d:c7cf with SMTP id d1-20020a5d5381000000b0032d939dc7cfmr1868786wrv.52.1698417584170; Fri, 27 Oct 2023 07:39:44 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e2-20020a5d5002000000b0031c6581d55esm1874123wrt.91.2023.10.27.07.39.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Oct 2023 07:39:43 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/41] target/arm: Correct minor errors in Cortex-A710 definition Date: Fri, 27 Oct 2023 15:39:02 +0100 Message-Id: <20231027143942.3413881-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231027143942.3413881-1-peter.maydell@linaro.org> References: <20231027143942.3413881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Oct 2023 14:39:48 -0000 Correct a couple of minor errors in the Cortex-A710 definition: * ID_AA64DFR0_EL1.DebugVer is 9 (indicating Armv8.4 debug architecture) * ID_AA64ISAR1_EL1.APA is 5 (indicating more PAuth support) * there is an IMPDEF CPUCFR_EL1, like that on the Neoverse-N1 Fixes: e3d45c0a89576 ("target/arm: Implement cortex-a710") Signed-off-by: Peter Maydell Tested-by: Marcin Juszkiewicz Reviewed-by: Alex Bennée Message-id: 20230915185453.1871167-2-peter.maydell@linaro.org --- target/arm/tcg/cpu64.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index d978aa5f7ad..e2bcac48549 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -840,6 +840,13 @@ static const ARMCPRegInfo cortex_a710_cp_reginfo[] = { { .name = "CPUPFR_EL3", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 6, .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + /* + * Report CPUCFR_EL1.SCU as 1, as we do not implement the DSU + * (and in particular its system registers). + */ + { .name = "CPUCFR_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 0, + .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 4 }, /* * Stub RAMINDEX, as we don't actually implement caches, BTB, @@ -909,12 +916,12 @@ static void aarch64_a710_initfn(Object *obj) cpu->isar.id_aa64pfr0 = 0x1201111120111112ull; /* GIC filled in later */ cpu->isar.id_aa64pfr1 = 0x0000000000000221ull; cpu->isar.id_aa64zfr0 = 0x0000110100110021ull; /* with Crypto */ - cpu->isar.id_aa64dfr0 = 0x000011f010305611ull; + cpu->isar.id_aa64dfr0 = 0x000011f010305619ull; cpu->isar.id_aa64dfr1 = 0; cpu->id_aa64afr0 = 0; cpu->id_aa64afr1 = 0; cpu->isar.id_aa64isar0 = 0x0221111110212120ull; /* with Crypto */ - cpu->isar.id_aa64isar1 = 0x0010111101211032ull; + cpu->isar.id_aa64isar1 = 0x0010111101211052ull; cpu->isar.id_aa64mmfr0 = 0x0000022200101122ull; cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull; cpu->isar.id_aa64mmfr2 = 0x1221011110101011ull; From patchwork Fri Oct 27 14:39:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13455623 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1qwO0A-0007EB-3o for mharc-qemu-devel@gnu.org; Fri, 27 Oct 2023 10:39:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qwO06-0007Bn-Ed for qemu-devel@nongnu.org; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e2-20020a5d5002000000b0031c6581d55esm1874123wrt.91.2023.10.27.07.39.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Oct 2023 07:39:44 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/41] target/arm: Implement Neoverse N2 CPU model Date: Fri, 27 Oct 2023 15:39:03 +0100 Message-Id: <20231027143942.3413881-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231027143942.3413881-1-peter.maydell@linaro.org> References: <20231027143942.3413881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::135; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x135.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Oct 2023 14:39:50 -0000 Implement a model of the Neoverse N2 CPU. This is an Armv9.0-A processor very similar to the Cortex-A710. The differences are: * no FEAT_EVT * FEAT_DGH (data gathering hint) * FEAT_NV (not yet implemented in QEMU) * Statistical Profiling Extension (not implemented in QEMU) * 48 bit physical address range, not 40 * CTR_EL0.DIC = 1 (no explicit icache cleaning needed) * PMCR_EL0.N = 6 (always 6 PMU counters, not 20) Because it has 48-bit physical address support, we can use this CPU in the sbsa-ref board as well as the virt board. Signed-off-by: Peter Maydell Tested-by: Marcin Juszkiewicz Reviewed-by: Alex Bennée Message-id: 20230915185453.1871167-3-peter.maydell@linaro.org --- docs/system/arm/virt.rst | 1 + hw/arm/sbsa-ref.c | 1 + hw/arm/virt.c | 1 + target/arm/tcg/cpu64.c | 103 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 106 insertions(+) diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst index e1697ac8f48..7c4c80180c6 100644 --- a/docs/system/arm/virt.rst +++ b/docs/system/arm/virt.rst @@ -63,6 +63,7 @@ Supported guest CPU types: - ``host`` (with KVM only) - ``neoverse-n1`` (64-bit) - ``neoverse-v1`` (64-bit) +- ``neoverse-n2`` (64-bit) - ``max`` (same as ``host`` for KVM; best possible emulation with TCG) Note that the default is ``cortex-a15``, so for an AArch64 guest you must diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index e8a82618f0a..bce44690e5e 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -149,6 +149,7 @@ static const char * const valid_cpus[] = { ARM_CPU_TYPE_NAME("cortex-a72"), ARM_CPU_TYPE_NAME("neoverse-n1"), ARM_CPU_TYPE_NAME("neoverse-v1"), + ARM_CPU_TYPE_NAME("neoverse-n2"), ARM_CPU_TYPE_NAME("max"), }; diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 529f1c089c0..92085d2d8fb 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -215,6 +215,7 @@ static const char *valid_cpus[] = { ARM_CPU_TYPE_NAME("a64fx"), ARM_CPU_TYPE_NAME("neoverse-n1"), ARM_CPU_TYPE_NAME("neoverse-v1"), + ARM_CPU_TYPE_NAME("neoverse-n2"), #endif ARM_CPU_TYPE_NAME("cortex-a53"), ARM_CPU_TYPE_NAME("cortex-a57"), diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index e2bcac48549..a9a8c0a0592 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -963,6 +963,108 @@ static void aarch64_a710_initfn(Object *obj) aarch64_add_sve_properties(obj); } +/* Extra IMPDEF regs in the N2 beyond those in the A710 */ +static const ARMCPRegInfo neoverse_n2_cp_reginfo[] = { + { .name = "CPURNDBR_EL3", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 3, .opc2 = 0, + .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "CPURNDPEID_EL3", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 3, .opc2 = 1, + .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, +}; + +static void aarch64_neoverse_n2_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + + cpu->dtb_compatible = "arm,neoverse-n2"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + + /* Ordered by Section B.5: AArch64 ID registers */ + cpu->midr = 0x410FD493; /* r0p3 */ + cpu->revidr = 0; + cpu->isar.id_pfr0 = 0x21110131; + cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */ + cpu->isar.id_dfr0 = 0x16011099; + cpu->id_afr0 = 0; + cpu->isar.id_mmfr0 = 0x10201105; + cpu->isar.id_mmfr1 = 0x40000000; + cpu->isar.id_mmfr2 = 0x01260000; + cpu->isar.id_mmfr3 = 0x02122211; + cpu->isar.id_isar0 = 0x02101110; + cpu->isar.id_isar1 = 0x13112111; + cpu->isar.id_isar2 = 0x21232042; + cpu->isar.id_isar3 = 0x01112131; + cpu->isar.id_isar4 = 0x00010142; + cpu->isar.id_isar5 = 0x11011121; /* with Crypto */ + cpu->isar.id_mmfr4 = 0x01021110; + cpu->isar.id_isar6 = 0x01111111; + cpu->isar.mvfr0 = 0x10110222; + cpu->isar.mvfr1 = 0x13211111; + cpu->isar.mvfr2 = 0x00000043; + cpu->isar.id_pfr2 = 0x00000011; + cpu->isar.id_aa64pfr0 = 0x1201111120111112ull; /* GIC filled in later */ + cpu->isar.id_aa64pfr1 = 0x0000000000000221ull; + cpu->isar.id_aa64zfr0 = 0x0000110100110021ull; /* with Crypto */ + cpu->isar.id_aa64dfr0 = 0x000011f210305619ull; + cpu->isar.id_aa64dfr1 = 0; + cpu->id_aa64afr0 = 0; + cpu->id_aa64afr1 = 0; + cpu->isar.id_aa64isar0 = 0x0221111110212120ull; /* with Crypto */ + cpu->isar.id_aa64isar1 = 0x0011111101211052ull; + cpu->isar.id_aa64mmfr0 = 0x0000022200101125ull; + cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull; + cpu->isar.id_aa64mmfr2 = 0x1221011112101011ull; + cpu->clidr = 0x0000001482000023ull; + cpu->gm_blocksize = 4; + cpu->ctr = 0x00000004b444c004ull; + cpu->dcz_blocksize = 4; + /* TODO FEAT_MPAM: mpamidr_el1 = 0x0000_0001_001e_01ff */ + + /* Section B.7.2: PMCR_EL0 */ + cpu->isar.reset_pmcr_el0 = 0x3000; /* with 6 counters */ + + /* Section B.8.9: ICH_VTR_EL2 */ + cpu->gic_num_lrs = 4; + cpu->gic_vpribits = 5; + cpu->gic_vprebits = 5; + cpu->gic_pribits = 5; + + /* Section 14: Scalable Vector Extensions support */ + cpu->sve_vq.supported = 1 << 0; /* 128bit */ + + /* + * The Neoverse N2 TRM does not list CCSIDR values. The layout of + * the caches are in text in Table 7-1, Table 8-1, and Table 9-1. + * + * L1: 4-way set associative 64-byte line size, total 64K. + * L2: 8-way set associative 64 byte line size, total either 512K or 1024K. + */ + cpu->ccsidr[0] = make_ccsidr64(4, 64, 64 * KiB); /* L1 dcache */ + cpu->ccsidr[1] = cpu->ccsidr[0]; /* L1 icache */ + cpu->ccsidr[2] = make_ccsidr64(8, 64, 512 * KiB); /* L2 cache */ + + /* FIXME: Not documented -- copied from neoverse-v1 */ + cpu->reset_sctlr = 0x30c50838; + + /* + * The Neoverse N2 has all of the Cortex-A710 IMPDEF registers, + * and a few more RNG related ones. + */ + define_arm_cp_regs(cpu, cortex_a710_cp_reginfo); + define_arm_cp_regs(cpu, neoverse_n2_cp_reginfo); + + aarch64_add_pauth_properties(obj); + aarch64_add_sve_properties(obj); +} + /* * -cpu max: a CPU with as many features enabled as our emulation supports. * The version of '-cpu max' for qemu-system-arm is defined in cpu32.c; @@ -1165,6 +1267,7 @@ static const ARMCPUInfo aarch64_cpus[] = { { .name = "a64fx", .initfn = aarch64_a64fx_initfn }, { .name = "neoverse-n1", .initfn = aarch64_neoverse_n1_initfn }, { .name = "neoverse-v1", .initfn = aarch64_neoverse_v1_initfn }, + { .name = "neoverse-n2", .initfn = aarch64_neoverse_n2_initfn }, }; static void aarch64_cpu_register_types(void) From patchwork Fri Oct 27 14:39:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13455630 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1qwO0F-0007ID-4w for mharc-qemu-devel@gnu.org; Fri, 27 Oct 2023 10:39:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qwO0B-0007FR-CE for qemu-devel@nongnu.org; Fri, 27 Oct 2023 10:39:55 -0400 Received: from mail-lj1-x230.google.com ([2a00:1450:4864:20::230]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qwO06-00087B-6q for qemu-devel@nongnu.org; Fri, 27 Oct 2023 10:39:55 -0400 Received: by mail-lj1-x230.google.com with SMTP id 38308e7fff4ca-2c5087d19a6so30502021fa.0 for ; Fri, 27 Oct 2023 07:39:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698417586; x=1699022386; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=ulfdcFLrZf0yu0McYAZ/Hmd9QAnC/yaQGAKgjQxTyBc=; b=nmjz+bmQt6myxFQCvtHCfvYtdmZ9hUpM9WYaMnvN90fZRH1iOtsy4gUetxvcMsXEHG x8s66kq9iq18bkcrR6moEektn7Vccb0McbS4Ws2+pJa5HHBkwDp5VJIYZ1PNB6haeZe8 mjAmVYNJs2/8Hnosz2Jq+zOOwRgiE+Rf1u4Jx4gdlQ2N+6F4cm0JJPZmsDvRECx8mnIa GfMdYQ+KBGdK/Dxclxu2d0DOuH25G5usozZrZeI6Bka58BnQzKiw/mSwBOqnmhoQHUSR TyzrkHVSLvy+qcd9RYtnbM47sg1ecJoLxlmGQmKYR1wAjJAitTcC2RwUQ5dXNXkq6hTZ VLVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698417586; x=1699022386; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ulfdcFLrZf0yu0McYAZ/Hmd9QAnC/yaQGAKgjQxTyBc=; b=KUZR2oWT/PxVcta3nIKi4hIsVu+gM3a0CZ0M8o25tTHc3StXX21oLSVsAztal4NphA Bfzr4JWzIXYtNwCouOLxF5AQmxg/Ntgnu0Q7Pcr3VzQjwv8U1PaLSZYB452BN8TAz8or 72/Mp7i++uC8mN7hR9dA4VMx7ldYZoOqoMhEBavXg8CGPfz+fqhB7L6hkfno18kPIPde Dg1+LJNQR4NXYoRYQt+vNDhpsLVArZMqhEAtFGIfdl/RKIiazyn98OxoiIoPiGYtVJAe QKgxLURX4CbHmWRo1gTyLnDJ+fHWd3VrDCA3vTzxCokgpqvWf5r+fPVbI66CNLWFFchL /Dyw== X-Gm-Message-State: AOJu0Yy8XFEo/cAbNZjbabCzbwvJXV4hFfDiLlhqhQak8vC0+nDP+ad7 wv6DWGWAXTyZThoGmXEw1h/F8Qb1go+udjRBkjQ= X-Google-Smtp-Source: AGHT+IEoSEobZXgfGR8/o752+UDSZqhS08HrcHjAm136EWk88zaUG6D4KleiSfFiW9exsCcE8htjwg== X-Received: by 2002:a2e:8798:0:b0:2c5:be8:68b1 with SMTP id n24-20020a2e8798000000b002c50be868b1mr2758635lji.9.1698417585550; Fri, 27 Oct 2023 07:39:45 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e2-20020a5d5002000000b0031c6581d55esm1874123wrt.91.2023.10.27.07.39.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Oct 2023 07:39:45 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/41] target/arm: Move feature test functions to their own header Date: Fri, 27 Oct 2023 15:39:04 +0100 Message-Id: <20231027143942.3413881-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231027143942.3413881-1-peter.maydell@linaro.org> References: <20231027143942.3413881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::230; envelope-from=peter.maydell@linaro.org; helo=mail-lj1-x230.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Oct 2023 14:39:55 -0000 The feature test functions isar_feature_*() now take up nearly a thousand lines in target/arm/cpu.h. This header file is included by a lot of source files, most of which don't need these functions. Move the feature test functions to their own header file. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20231024163510.2972081-2-peter.maydell@linaro.org --- bsd-user/arm/target_arch.h | 1 + linux-user/aarch64/target_prctl.h | 2 + target/arm/cpu-features.h | 994 ++++++++++++++++++++++++++++++ target/arm/cpu.h | 971 ----------------------------- target/arm/internals.h | 1 + target/arm/tcg/translate.h | 2 +- hw/arm/armv7m.c | 1 + hw/intc/armv7m_nvic.c | 1 + linux-user/aarch64/cpu_loop.c | 1 + linux-user/aarch64/signal.c | 1 + linux-user/arm/signal.c | 1 + linux-user/elfload.c | 4 + linux-user/mmap.c | 4 + target/arm/arch_dump.c | 1 + target/arm/cpu.c | 1 + target/arm/cpu64.c | 1 + target/arm/debug_helper.c | 1 + target/arm/gdbstub.c | 1 + target/arm/helper.c | 1 + target/arm/kvm64.c | 1 + target/arm/machine.c | 1 + target/arm/ptw.c | 1 + target/arm/tcg/cpu64.c | 1 + target/arm/tcg/hflags.c | 1 + target/arm/tcg/m_helper.c | 1 + target/arm/tcg/op_helper.c | 1 + target/arm/tcg/pauth_helper.c | 1 + target/arm/tcg/tlb_helper.c | 1 + target/arm/vfp_helper.c | 1 + 29 files changed, 1028 insertions(+), 972 deletions(-) create mode 100644 target/arm/cpu-features.h diff --git a/bsd-user/arm/target_arch.h b/bsd-user/arm/target_arch.h index 561934bbd25..d80cb85c647 100644 --- a/bsd-user/arm/target_arch.h +++ b/bsd-user/arm/target_arch.h @@ -21,6 +21,7 @@ #define TARGET_ARCH_H #include "qemu.h" +#include "target/arm/cpu-features.h" void target_cpu_set_tls(CPUARMState *env, target_ulong newtls); target_ulong target_cpu_get_tls(CPUARMState *env); diff --git a/linux-user/aarch64/target_prctl.h b/linux-user/aarch64/target_prctl.h index 907c3141466..5067e7d7310 100644 --- a/linux-user/aarch64/target_prctl.h +++ b/linux-user/aarch64/target_prctl.h @@ -6,6 +6,8 @@ #ifndef AARCH64_TARGET_PRCTL_H #define AARCH64_TARGET_PRCTL_H +#include "target/arm/cpu-features.h" + static abi_long do_prctl_sve_get_vl(CPUArchState *env) { ARMCPU *cpu = env_archcpu(env); diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h new file mode 100644 index 00000000000..bfc9bfafe70 --- /dev/null +++ b/target/arm/cpu-features.h @@ -0,0 +1,994 @@ +/* + * QEMU Arm CPU -- feature test functions + * + * Copyright (c) 2023 Linaro Ltd + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#ifndef TARGET_ARM_FEATURES_H +#define TARGET_ARM_FEATURES_H + +/* + * Naming convention for isar_feature functions: + * Functions which test 32-bit ID registers should have _aa32_ in + * their name. Functions which test 64-bit ID registers should have + * _aa64_ in their name. These must only be used in code where we + * know for certain that the CPU has AArch32 or AArch64 respectively + * or where the correct answer for a CPU which doesn't implement that + * CPU state is "false" (eg when generating A32 or A64 code, if adding + * system registers that are specific to that CPU state, for "should + * we let this system register bit be set" tests where the 32-bit + * flavour of the register doesn't have the bit, and so on). + * Functions which simply ask "does this feature exist at all" have + * _any_ in their name, and always return the logical OR of the _aa64_ + * and the _aa32_ function. + */ + +/* + * 32-bit feature tests via id registers. + */ +static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0; +} + +static inline bool isar_feature_aa32_arm_div(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1; +} + +static inline bool isar_feature_aa32_lob(const ARMISARegisters *id) +{ + /* (M-profile) low-overhead loops and branch future */ + return FIELD_EX32(id->id_isar0, ID_ISAR0, CMPBRANCH) >= 3; +} + +static inline bool isar_feature_aa32_jazelle(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0; +} + +static inline bool isar_feature_aa32_aes(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0; +} + +static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1; +} + +static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA1) != 0; +} + +static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA2) != 0; +} + +static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_isar5, ID_ISAR5, CRC32) != 0; +} + +static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_isar5, ID_ISAR5, RDM) != 0; +} + +static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) != 0; +} + +static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) != 0; +} + +static inline bool isar_feature_aa32_dp(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0; +} + +static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0; +} + +static inline bool isar_feature_aa32_sb(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0; +} + +static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0; +} + +static inline bool isar_feature_aa32_bf16(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_isar6, ID_ISAR6, BF16) != 0; +} + +static inline bool isar_feature_aa32_i8mm(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_isar6, ID_ISAR6, I8MM) != 0; +} + +static inline bool isar_feature_aa32_ras(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_pfr0, ID_PFR0, RAS) != 0; +} + +static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) != 0; +} + +static inline bool isar_feature_aa32_m_sec_state(const ARMISARegisters *id) +{ + /* + * Return true if M-profile state handling insns + * (VSCCLRM, CLRM, FPCTX access insns) are implemented + */ + return FIELD_EX32(id->id_pfr1, ID_PFR1, SECURITY) >= 3; +} + +static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) +{ + /* Sadly this is encoded differently for A-profile and M-profile */ + if (isar_feature_aa32_mprofile(id)) { + return FIELD_EX32(id->mvfr1, MVFR1, FP16) > 0; + } else { + return FIELD_EX32(id->mvfr1, MVFR1, FPHP) >= 3; + } +} + +static inline bool isar_feature_aa32_mve(const ARMISARegisters *id) +{ + /* + * Return true if MVE is supported (either integer or floating point). + * We must check for M-profile as the MVFR1 field means something + * else for A-profile. + */ + return isar_feature_aa32_mprofile(id) && + FIELD_EX32(id->mvfr1, MVFR1, MVE) > 0; +} + +static inline bool isar_feature_aa32_mve_fp(const ARMISARegisters *id) +{ + /* + * Return true if MVE is supported (either integer or floating point). + * We must check for M-profile as the MVFR1 field means something + * else for A-profile. + */ + return isar_feature_aa32_mprofile(id) && + FIELD_EX32(id->mvfr1, MVFR1, MVE) >= 2; +} + +static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id) +{ + /* + * Return true if either VFP or SIMD is implemented. + * In this case, a minimum of VFP w/ D0-D15. + */ + return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) > 0; +} + +static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id) +{ + /* Return true if D16-D31 are implemented */ + return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) >= 2; +} + +static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id) +{ + return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0; +} + +static inline bool isar_feature_aa32_fpsp_v2(const ARMISARegisters *id) +{ + /* Return true if CPU supports single precision floating point, VFPv2 */ + return FIELD_EX32(id->mvfr0, MVFR0, FPSP) > 0; +} + +static inline bool isar_feature_aa32_fpsp_v3(const ARMISARegisters *id) +{ + /* Return true if CPU supports single precision floating point, VFPv3 */ + return FIELD_EX32(id->mvfr0, MVFR0, FPSP) >= 2; +} + +static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id) +{ + /* Return true if CPU supports double precision floating point, VFPv2 */ + return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0; +} + +static inline bool isar_feature_aa32_fpdp_v3(const ARMISARegisters *id) +{ + /* Return true if CPU supports double precision floating point, VFPv3 */ + return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >= 2; +} + +static inline bool isar_feature_aa32_vfp(const ARMISARegisters *id) +{ + return isar_feature_aa32_fpsp_v2(id) || isar_feature_aa32_fpdp_v2(id); +} + +/* + * We always set the FP and SIMD FP16 fields to indicate identical + * levels of support (assuming SIMD is implemented at all), so + * we only need one set of accessors. + */ +static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id) +{ + return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 0; +} + +static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id) +{ + return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 1; +} + +/* + * Note that this ID register field covers both VFP and Neon FMAC, + * so should usually be tested in combination with some other + * check that confirms the presence of whichever of VFP or Neon is + * relevant, to avoid accidentally enabling a Neon feature on + * a VFP-no-Neon core or vice-versa. + */ +static inline bool isar_feature_aa32_simdfmac(const ARMISARegisters *id) +{ + return FIELD_EX32(id->mvfr1, MVFR1, SIMDFMAC) != 0; +} + +static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id) +{ + return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 1; +} + +static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id) +{ + return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 2; +} + +static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id) +{ + return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 3; +} + +static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id) +{ + return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 4; +} + +static inline bool isar_feature_aa32_pxn(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_mmfr0, ID_MMFR0, VMSA) >= 4; +} + +static inline bool isar_feature_aa32_pan(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) != 0; +} + +static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) >= 2; +} + +static inline bool isar_feature_aa32_pmuv3p1(const ARMISARegisters *id) +{ + /* 0xf means "non-standard IMPDEF PMU" */ + return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 4 && + FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; +} + +static inline bool isar_feature_aa32_pmuv3p4(const ARMISARegisters *id) +{ + /* 0xf means "non-standard IMPDEF PMU" */ + return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 5 && + FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; +} + +static inline bool isar_feature_aa32_pmuv3p5(const ARMISARegisters *id) +{ + /* 0xf means "non-standard IMPDEF PMU" */ + return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 6 && + FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; +} + +static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_mmfr4, ID_MMFR4, HPDS) != 0; +} + +static inline bool isar_feature_aa32_ac2(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_mmfr4, ID_MMFR4, AC2) != 0; +} + +static inline bool isar_feature_aa32_ccidx(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_mmfr4, ID_MMFR4, CCIDX) != 0; +} + +static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) != 0; +} + +static inline bool isar_feature_aa32_half_evt(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_mmfr4, ID_MMFR4, EVT) >= 1; +} + +static inline bool isar_feature_aa32_evt(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_mmfr4, ID_MMFR4, EVT) >= 2; +} + +static inline bool isar_feature_aa32_dit(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_pfr0, ID_PFR0, DIT) != 0; +} + +static inline bool isar_feature_aa32_ssbs(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_pfr2, ID_PFR2, SSBS) != 0; +} + +static inline bool isar_feature_aa32_debugv7p1(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >= 5; +} + +static inline bool isar_feature_aa32_debugv8p2(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >= 8; +} + +static inline bool isar_feature_aa32_doublelock(const ARMISARegisters *id) +{ + return FIELD_EX32(id->dbgdevid, DBGDEVID, DOUBLELOCK) > 0; +} + +/* + * 64-bit feature tests via id registers. + */ +static inline bool isar_feature_aa64_aes(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) != 0; +} + +static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) > 1; +} + +static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA1) != 0; +} + +static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) != 0; +} + +static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) > 1; +} + +static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, CRC32) != 0; +} + +static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) != 0; +} + +static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) != 0; +} + +static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA3) != 0; +} + +static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM3) != 0; +} + +static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM4) != 0; +} + +static inline bool isar_feature_aa64_dp(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0; +} + +static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0; +} + +static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0; +} + +static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >= 2; +} + +static inline bool isar_feature_aa64_rndr(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RNDR) != 0; +} + +static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0; +} + +static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0; +} + +/* + * These are the values from APA/API/APA3. + * In general these must be compared '>=', per the normal Arm ARM + * treatment of fields in ID registers. + */ +typedef enum { + PauthFeat_None = 0, + PauthFeat_1 = 1, + PauthFeat_EPAC = 2, + PauthFeat_2 = 3, + PauthFeat_FPAC = 4, + PauthFeat_FPACCOMBINED = 5, +} ARMPauthFeature; + +static inline ARMPauthFeature +isar_feature_pauth_feature(const ARMISARegisters *id) +{ + /* + * Architecturally, only one of {APA,API,APA3} may be active (non-zero) + * and the other two must be zero. Thus we may avoid conditionals. + */ + return (FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) | + FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, API) | + FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, APA3)); +} + +static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id) +{ + /* + * Return true if any form of pauth is enabled, as this + * predicate controls migration of the 128-bit keys. + */ + return isar_feature_pauth_feature(id) != PauthFeat_None; +} + +static inline bool isar_feature_aa64_pauth_qarma5(const ARMISARegisters *id) +{ + /* + * Return true if pauth is enabled with the architected QARMA5 algorithm. + * QEMU will always enable or disable both APA and GPA. + */ + return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) != 0; +} + +static inline bool isar_feature_aa64_pauth_qarma3(const ARMISARegisters *id) +{ + /* + * Return true if pauth is enabled with the architected QARMA3 algorithm. + * QEMU will always enable or disable both APA3 and GPA3. + */ + return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, APA3) != 0; +} + +static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) == 2; +} + +static inline bool isar_feature_aa64_tlbios(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) != 0; +} + +static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0; +} + +static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0; +} + +static inline bool isar_feature_aa64_frint(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) != 0; +} + +static inline bool isar_feature_aa64_dcpop(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) != 0; +} + +static inline bool isar_feature_aa64_dcpodp(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) >= 2; +} + +static inline bool isar_feature_aa64_bf16(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, BF16) != 0; +} + +static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id) +{ + /* We always set the AdvSIMD and FP fields identically. */ + return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) != 0xf; +} + +static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) +{ + /* We always set the AdvSIMD and FP fields identically wrt FP16. */ + return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1; +} + +static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2; +} + +static inline bool isar_feature_aa64_aa32_el1(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >= 2; +} + +static inline bool isar_feature_aa64_aa32_el2(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL2) >= 2; +} + +static inline bool isar_feature_aa64_ras(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) != 0; +} + +static inline bool isar_feature_aa64_doublefault(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) >= 2; +} + +static inline bool isar_feature_aa64_sve(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0; +} + +static inline bool isar_feature_aa64_sel2(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SEL2) != 0; +} + +static inline bool isar_feature_aa64_rme(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RME) != 0; +} + +static inline bool isar_feature_aa64_vh(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0; +} + +static inline bool isar_feature_aa64_lor(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0; +} + +static inline bool isar_feature_aa64_pan(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) != 0; +} + +static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2; +} + +static inline bool isar_feature_aa64_pan3(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 3; +} + +static inline bool isar_feature_aa64_hcx(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HCX) != 0; +} + +static inline bool isar_feature_aa64_tidcp1(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR1, TIDCP1) != 0; +} + +static inline bool isar_feature_aa64_uao(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0; +} + +static inline bool isar_feature_aa64_st(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) != 0; +} + +static inline bool isar_feature_aa64_lse2(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, AT) != 0; +} + +static inline bool isar_feature_aa64_fwb(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, FWB) != 0; +} + +static inline bool isar_feature_aa64_ids(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, IDS) != 0; +} + +static inline bool isar_feature_aa64_half_evt(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, EVT) >= 1; +} + +static inline bool isar_feature_aa64_evt(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, EVT) >= 2; +} + +static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; +} + +static inline bool isar_feature_aa64_mte_insn_reg(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) != 0; +} + +static inline bool isar_feature_aa64_mte(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >= 2; +} + +static inline bool isar_feature_aa64_sme(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SME) != 0; +} + +static inline bool isar_feature_aa64_pmuv3p1(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 && + FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; +} + +static inline bool isar_feature_aa64_pmuv3p4(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 && + FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; +} + +static inline bool isar_feature_aa64_pmuv3p5(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 6 && + FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; +} + +static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0; +} + +static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >= 2; +} + +static inline bool isar_feature_aa64_i8mm(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, I8MM) != 0; +} + +static inline bool isar_feature_aa64_hbc(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, BC) != 0; +} + +static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id) +{ + return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 1; +} + +static inline bool isar_feature_aa64_tgran4_2_lpa2(const ARMISARegisters *id) +{ + unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2); + return t >= 3 || (t == 0 && isar_feature_aa64_tgran4_lpa2(id)); +} + +static inline bool isar_feature_aa64_tgran16_lpa2(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 2; +} + +static inline bool isar_feature_aa64_tgran16_2_lpa2(const ARMISARegisters *id) +{ + unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2); + return t >= 3 || (t == 0 && isar_feature_aa64_tgran16_lpa2(id)); +} + +static inline bool isar_feature_aa64_tgran4(const ARMISARegisters *id) +{ + return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 0; +} + +static inline bool isar_feature_aa64_tgran16(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 1; +} + +static inline bool isar_feature_aa64_tgran64(const ARMISARegisters *id) +{ + return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64) >= 0; +} + +static inline bool isar_feature_aa64_tgran4_2(const ARMISARegisters *id) +{ + unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2); + return t >= 2 || (t == 0 && isar_feature_aa64_tgran4(id)); +} + +static inline bool isar_feature_aa64_tgran16_2(const ARMISARegisters *id) +{ + unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2); + return t >= 2 || (t == 0 && isar_feature_aa64_tgran16(id)); +} + +static inline bool isar_feature_aa64_tgran64_2(const ARMISARegisters *id) +{ + unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64_2); + return t >= 2 || (t == 0 && isar_feature_aa64_tgran64(id)); +} + +static inline bool isar_feature_aa64_fgt(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, FGT) != 0; +} + +static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0; +} + +static inline bool isar_feature_aa64_lva(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, VARANGE) != 0; +} + +static inline bool isar_feature_aa64_e0pd(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, E0PD) != 0; +} + +static inline bool isar_feature_aa64_hafs(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) != 0; +} + +static inline bool isar_feature_aa64_hdbs(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) >= 2; +} + +static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0; +} + +static inline bool isar_feature_aa64_dit(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0; +} + +static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id) +{ + int key = FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, CSV2); + if (key >= 2) { + return true; /* FEAT_CSV2_2 */ + } + if (key == 1) { + key = FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, CSV2_FRAC); + return key >= 2; /* FEAT_CSV2_1p2 */ + } + return false; +} + +static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0; +} + +static inline bool isar_feature_aa64_debugv8p2(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, DEBUGVER) >= 8; +} + +static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SVEVER) != 0; +} + +static inline bool isar_feature_aa64_sve2_aes(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) != 0; +} + +static inline bool isar_feature_aa64_sve2_pmull128(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) >= 2; +} + +static inline bool isar_feature_aa64_sve2_bitperm(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BITPERM) != 0; +} + +static inline bool isar_feature_aa64_sve_bf16(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BFLOAT16) != 0; +} + +static inline bool isar_feature_aa64_sve2_sha3(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SHA3) != 0; +} + +static inline bool isar_feature_aa64_sve2_sm4(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SM4) != 0; +} + +static inline bool isar_feature_aa64_sve_i8mm(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, I8MM) != 0; +} + +static inline bool isar_feature_aa64_sve_f32mm(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F32MM) != 0; +} + +static inline bool isar_feature_aa64_sve_f64mm(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F64MM) != 0; +} + +static inline bool isar_feature_aa64_sme_f64f64(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, F64F64); +} + +static inline bool isar_feature_aa64_sme_i16i64(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, I16I64) == 0xf; +} + +static inline bool isar_feature_aa64_sme_fa64(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, FA64); +} + +static inline bool isar_feature_aa64_doublelock(const ARMISARegisters *id) +{ + return FIELD_SEX64(id->id_aa64dfr0, ID_AA64DFR0, DOUBLELOCK) >= 0; +} + +static inline bool isar_feature_aa64_mops(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, MOPS); +} + +/* + * Feature tests for "does this exist in either 32-bit or 64-bit?" + */ +static inline bool isar_feature_any_fp16(const ARMISARegisters *id) +{ + return isar_feature_aa64_fp16(id) || isar_feature_aa32_fp16_arith(id); +} + +static inline bool isar_feature_any_predinv(const ARMISARegisters *id) +{ + return isar_feature_aa64_predinv(id) || isar_feature_aa32_predinv(id); +} + +static inline bool isar_feature_any_pmuv3p1(const ARMISARegisters *id) +{ + return isar_feature_aa64_pmuv3p1(id) || isar_feature_aa32_pmuv3p1(id); +} + +static inline bool isar_feature_any_pmuv3p4(const ARMISARegisters *id) +{ + return isar_feature_aa64_pmuv3p4(id) || isar_feature_aa32_pmuv3p4(id); +} + +static inline bool isar_feature_any_pmuv3p5(const ARMISARegisters *id) +{ + return isar_feature_aa64_pmuv3p5(id) || isar_feature_aa32_pmuv3p5(id); +} + +static inline bool isar_feature_any_ccidx(const ARMISARegisters *id) +{ + return isar_feature_aa64_ccidx(id) || isar_feature_aa32_ccidx(id); +} + +static inline bool isar_feature_any_tts2uxn(const ARMISARegisters *id) +{ + return isar_feature_aa64_tts2uxn(id) || isar_feature_aa32_tts2uxn(id); +} + +static inline bool isar_feature_any_debugv8p2(const ARMISARegisters *id) +{ + return isar_feature_aa64_debugv8p2(id) || isar_feature_aa32_debugv8p2(id); +} + +static inline bool isar_feature_any_ras(const ARMISARegisters *id) +{ + return isar_feature_aa64_ras(id) || isar_feature_aa32_ras(id); +} + +static inline bool isar_feature_any_half_evt(const ARMISARegisters *id) +{ + return isar_feature_aa64_half_evt(id) || isar_feature_aa32_half_evt(id); +} + +static inline bool isar_feature_any_evt(const ARMISARegisters *id) +{ + return isar_feature_aa64_evt(id) || isar_feature_aa32_evt(id); +} + +/* + * Forward to the above feature tests given an ARMCPU pointer. + */ +#define cpu_isar_feature(name, cpu) \ + ({ ARMCPU *cpu_ = (cpu); isar_feature_##name(&cpu_->isar); }) + +#endif diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 76d4cef9e3a..d51dfe48db0 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3402,975 +3402,4 @@ static inline target_ulong cpu_untagged_addr(CPUState *cs, target_ulong x) } #endif -/* - * Naming convention for isar_feature functions: - * Functions which test 32-bit ID registers should have _aa32_ in - * their name. Functions which test 64-bit ID registers should have - * _aa64_ in their name. These must only be used in code where we - * know for certain that the CPU has AArch32 or AArch64 respectively - * or where the correct answer for a CPU which doesn't implement that - * CPU state is "false" (eg when generating A32 or A64 code, if adding - * system registers that are specific to that CPU state, for "should - * we let this system register bit be set" tests where the 32-bit - * flavour of the register doesn't have the bit, and so on). - * Functions which simply ask "does this feature exist at all" have - * _any_ in their name, and always return the logical OR of the _aa64_ - * and the _aa32_ function. - */ - -/* - * 32-bit feature tests via id registers. - */ -static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id) -{ - return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0; -} - -static inline bool isar_feature_aa32_arm_div(const ARMISARegisters *id) -{ - return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1; -} - -static inline bool isar_feature_aa32_lob(const ARMISARegisters *id) -{ - /* (M-profile) low-overhead loops and branch future */ - return FIELD_EX32(id->id_isar0, ID_ISAR0, CMPBRANCH) >= 3; -} - -static inline bool isar_feature_aa32_jazelle(const ARMISARegisters *id) -{ - return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0; -} - -static inline bool isar_feature_aa32_aes(const ARMISARegisters *id) -{ - return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0; -} - -static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id) -{ - return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1; -} - -static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id) -{ - return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA1) != 0; -} - -static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id) -{ - return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA2) != 0; -} - -static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id) -{ - return FIELD_EX32(id->id_isar5, ID_ISAR5, CRC32) != 0; -} - -static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id) -{ - return FIELD_EX32(id->id_isar5, ID_ISAR5, RDM) != 0; -} - -static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id) -{ - return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) != 0; -} - -static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id) -{ - return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) != 0; -} - -static inline bool isar_feature_aa32_dp(const ARMISARegisters *id) -{ - return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0; -} - -static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id) -{ - return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0; -} - -static inline bool isar_feature_aa32_sb(const ARMISARegisters *id) -{ - return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0; -} - -static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id) -{ - return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0; -} - -static inline bool isar_feature_aa32_bf16(const ARMISARegisters *id) -{ - return FIELD_EX32(id->id_isar6, ID_ISAR6, BF16) != 0; -} - -static inline bool isar_feature_aa32_i8mm(const ARMISARegisters *id) -{ - return FIELD_EX32(id->id_isar6, ID_ISAR6, I8MM) != 0; -} - -static inline bool isar_feature_aa32_ras(const ARMISARegisters *id) -{ - return FIELD_EX32(id->id_pfr0, ID_PFR0, RAS) != 0; -} - -static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id) -{ - return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) != 0; -} - -static inline bool isar_feature_aa32_m_sec_state(const ARMISARegisters *id) -{ - /* - * Return true if M-profile state handling insns - * (VSCCLRM, CLRM, FPCTX access insns) are implemented - */ - return FIELD_EX32(id->id_pfr1, ID_PFR1, SECURITY) >= 3; -} - -static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) -{ - /* Sadly this is encoded differently for A-profile and M-profile */ - if (isar_feature_aa32_mprofile(id)) { - return FIELD_EX32(id->mvfr1, MVFR1, FP16) > 0; - } else { - return FIELD_EX32(id->mvfr1, MVFR1, FPHP) >= 3; - } -} - -static inline bool isar_feature_aa32_mve(const ARMISARegisters *id) -{ - /* - * Return true if MVE is supported (either integer or floating point). - * We must check for M-profile as the MVFR1 field means something - * else for A-profile. - */ - return isar_feature_aa32_mprofile(id) && - FIELD_EX32(id->mvfr1, MVFR1, MVE) > 0; -} - -static inline bool isar_feature_aa32_mve_fp(const ARMISARegisters *id) -{ - /* - * Return true if MVE is supported (either integer or floating point). - * We must check for M-profile as the MVFR1 field means something - * else for A-profile. - */ - return isar_feature_aa32_mprofile(id) && - FIELD_EX32(id->mvfr1, MVFR1, MVE) >= 2; -} - -static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id) -{ - /* - * Return true if either VFP or SIMD is implemented. - * In this case, a minimum of VFP w/ D0-D15. - */ - return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) > 0; -} - -static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id) -{ - /* Return true if D16-D31 are implemented */ - return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) >= 2; -} - -static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id) -{ - return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0; -} - -static inline bool isar_feature_aa32_fpsp_v2(const ARMISARegisters *id) -{ - /* Return true if CPU supports single precision floating point, VFPv2 */ - return FIELD_EX32(id->mvfr0, MVFR0, FPSP) > 0; -} - -static inline bool isar_feature_aa32_fpsp_v3(const ARMISARegisters *id) -{ - /* Return true if CPU supports single precision floating point, VFPv3 */ - return FIELD_EX32(id->mvfr0, MVFR0, FPSP) >= 2; -} - -static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id) -{ - /* Return true if CPU supports double precision floating point, VFPv2 */ - return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0; -} - -static inline bool isar_feature_aa32_fpdp_v3(const ARMISARegisters *id) -{ - /* Return true if CPU supports double precision floating point, VFPv3 */ - return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >= 2; -} - -static inline bool isar_feature_aa32_vfp(const ARMISARegisters *id) -{ - return isar_feature_aa32_fpsp_v2(id) || isar_feature_aa32_fpdp_v2(id); -} - -/* - * We always set the FP and SIMD FP16 fields to indicate identical - * levels of support (assuming SIMD is implemented at all), so - * we only need one set of accessors. - */ -static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id) -{ - return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 0; -} - -static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id) -{ - return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 1; -} - -/* - * Note that this ID register field covers both VFP and Neon FMAC, - * so should usually be tested in combination with some other - * check that confirms the presence of whichever of VFP or Neon is - * relevant, to avoid accidentally enabling a Neon feature on - * a VFP-no-Neon core or vice-versa. - */ -static inline bool isar_feature_aa32_simdfmac(const ARMISARegisters *id) -{ - return FIELD_EX32(id->mvfr1, MVFR1, SIMDFMAC) != 0; -} - -static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id) -{ - return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 1; -} - -static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id) -{ - return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 2; -} - -static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id) -{ - return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 3; -} - -static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id) -{ - return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 4; -} - -static inline bool isar_feature_aa32_pxn(const ARMISARegisters *id) -{ - return FIELD_EX32(id->id_mmfr0, ID_MMFR0, VMSA) >= 4; -} - -static inline bool isar_feature_aa32_pan(const ARMISARegisters *id) -{ - return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) != 0; -} - -static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id) -{ - return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) >= 2; -} - -static inline bool isar_feature_aa32_pmuv3p1(const ARMISARegisters *id) -{ - /* 0xf means "non-standard IMPDEF PMU" */ - return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 4 && - FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; -} - -static inline bool isar_feature_aa32_pmuv3p4(const ARMISARegisters *id) -{ - /* 0xf means "non-standard IMPDEF PMU" */ - return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 5 && - FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; -} - -static inline bool isar_feature_aa32_pmuv3p5(const ARMISARegisters *id) -{ - /* 0xf means "non-standard IMPDEF PMU" */ - return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 6 && - FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; -} - -static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id) -{ - return FIELD_EX32(id->id_mmfr4, ID_MMFR4, HPDS) != 0; -} - -static inline bool isar_feature_aa32_ac2(const ARMISARegisters *id) -{ - return FIELD_EX32(id->id_mmfr4, ID_MMFR4, AC2) != 0; -} - -static inline bool isar_feature_aa32_ccidx(const ARMISARegisters *id) -{ - return FIELD_EX32(id->id_mmfr4, ID_MMFR4, CCIDX) != 0; -} - -static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id) -{ - return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) != 0; -} - -static inline bool isar_feature_aa32_half_evt(const ARMISARegisters *id) -{ - return FIELD_EX32(id->id_mmfr4, ID_MMFR4, EVT) >= 1; -} - -static inline bool isar_feature_aa32_evt(const ARMISARegisters *id) -{ - return FIELD_EX32(id->id_mmfr4, ID_MMFR4, EVT) >= 2; -} - -static inline bool isar_feature_aa32_dit(const ARMISARegisters *id) -{ - return FIELD_EX32(id->id_pfr0, ID_PFR0, DIT) != 0; -} - -static inline bool isar_feature_aa32_ssbs(const ARMISARegisters *id) -{ - return FIELD_EX32(id->id_pfr2, ID_PFR2, SSBS) != 0; -} - -static inline bool isar_feature_aa32_debugv7p1(const ARMISARegisters *id) -{ - return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >= 5; -} - -static inline bool isar_feature_aa32_debugv8p2(const ARMISARegisters *id) -{ - return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >= 8; -} - -static inline bool isar_feature_aa32_doublelock(const ARMISARegisters *id) -{ - return FIELD_EX32(id->dbgdevid, DBGDEVID, DOUBLELOCK) > 0; -} - -/* - * 64-bit feature tests via id registers. - */ -static inline bool isar_feature_aa64_aes(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) != 0; -} - -static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) > 1; -} - -static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA1) != 0; -} - -static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) != 0; -} - -static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) > 1; -} - -static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, CRC32) != 0; -} - -static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) != 0; -} - -static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) != 0; -} - -static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA3) != 0; -} - -static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM3) != 0; -} - -static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM4) != 0; -} - -static inline bool isar_feature_aa64_dp(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0; -} - -static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0; -} - -static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0; -} - -static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >= 2; -} - -static inline bool isar_feature_aa64_rndr(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RNDR) != 0; -} - -static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0; -} - -static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0; -} - -/* - * These are the values from APA/API/APA3. - * In general these must be compared '>=', per the normal Arm ARM - * treatment of fields in ID registers. - */ -typedef enum { - PauthFeat_None = 0, - PauthFeat_1 = 1, - PauthFeat_EPAC = 2, - PauthFeat_2 = 3, - PauthFeat_FPAC = 4, - PauthFeat_FPACCOMBINED = 5, -} ARMPauthFeature; - -static inline ARMPauthFeature -isar_feature_pauth_feature(const ARMISARegisters *id) -{ - /* - * Architecturally, only one of {APA,API,APA3} may be active (non-zero) - * and the other two must be zero. Thus we may avoid conditionals. - */ - return (FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) | - FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, API) | - FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, APA3)); -} - -static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id) -{ - /* - * Return true if any form of pauth is enabled, as this - * predicate controls migration of the 128-bit keys. - */ - return isar_feature_pauth_feature(id) != PauthFeat_None; -} - -static inline bool isar_feature_aa64_pauth_qarma5(const ARMISARegisters *id) -{ - /* - * Return true if pauth is enabled with the architected QARMA5 algorithm. - * QEMU will always enable or disable both APA and GPA. - */ - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) != 0; -} - -static inline bool isar_feature_aa64_pauth_qarma3(const ARMISARegisters *id) -{ - /* - * Return true if pauth is enabled with the architected QARMA3 algorithm. - * QEMU will always enable or disable both APA3 and GPA3. - */ - return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, APA3) != 0; -} - -static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) == 2; -} - -static inline bool isar_feature_aa64_tlbios(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) != 0; -} - -static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0; -} - -static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0; -} - -static inline bool isar_feature_aa64_frint(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) != 0; -} - -static inline bool isar_feature_aa64_dcpop(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) != 0; -} - -static inline bool isar_feature_aa64_dcpodp(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) >= 2; -} - -static inline bool isar_feature_aa64_bf16(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, BF16) != 0; -} - -static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id) -{ - /* We always set the AdvSIMD and FP fields identically. */ - return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) != 0xf; -} - -static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) -{ - /* We always set the AdvSIMD and FP fields identically wrt FP16. */ - return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1; -} - -static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2; -} - -static inline bool isar_feature_aa64_aa32_el1(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >= 2; -} - -static inline bool isar_feature_aa64_aa32_el2(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL2) >= 2; -} - -static inline bool isar_feature_aa64_ras(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) != 0; -} - -static inline bool isar_feature_aa64_doublefault(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) >= 2; -} - -static inline bool isar_feature_aa64_sve(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0; -} - -static inline bool isar_feature_aa64_sel2(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SEL2) != 0; -} - -static inline bool isar_feature_aa64_rme(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RME) != 0; -} - -static inline bool isar_feature_aa64_vh(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0; -} - -static inline bool isar_feature_aa64_lor(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0; -} - -static inline bool isar_feature_aa64_pan(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) != 0; -} - -static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2; -} - -static inline bool isar_feature_aa64_pan3(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 3; -} - -static inline bool isar_feature_aa64_hcx(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HCX) != 0; -} - -static inline bool isar_feature_aa64_tidcp1(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR1, TIDCP1) != 0; -} - -static inline bool isar_feature_aa64_uao(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0; -} - -static inline bool isar_feature_aa64_st(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) != 0; -} - -static inline bool isar_feature_aa64_lse2(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, AT) != 0; -} - -static inline bool isar_feature_aa64_fwb(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, FWB) != 0; -} - -static inline bool isar_feature_aa64_ids(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, IDS) != 0; -} - -static inline bool isar_feature_aa64_half_evt(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, EVT) >= 1; -} - -static inline bool isar_feature_aa64_evt(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, EVT) >= 2; -} - -static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; -} - -static inline bool isar_feature_aa64_mte_insn_reg(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) != 0; -} - -static inline bool isar_feature_aa64_mte(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >= 2; -} - -static inline bool isar_feature_aa64_sme(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SME) != 0; -} - -static inline bool isar_feature_aa64_pmuv3p1(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 && - FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; -} - -static inline bool isar_feature_aa64_pmuv3p4(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 && - FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; -} - -static inline bool isar_feature_aa64_pmuv3p5(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 6 && - FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; -} - -static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0; -} - -static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >= 2; -} - -static inline bool isar_feature_aa64_i8mm(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, I8MM) != 0; -} - -static inline bool isar_feature_aa64_hbc(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, BC) != 0; -} - -static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id) -{ - return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 1; -} - -static inline bool isar_feature_aa64_tgran4_2_lpa2(const ARMISARegisters *id) -{ - unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2); - return t >= 3 || (t == 0 && isar_feature_aa64_tgran4_lpa2(id)); -} - -static inline bool isar_feature_aa64_tgran16_lpa2(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 2; -} - -static inline bool isar_feature_aa64_tgran16_2_lpa2(const ARMISARegisters *id) -{ - unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2); - return t >= 3 || (t == 0 && isar_feature_aa64_tgran16_lpa2(id)); -} - -static inline bool isar_feature_aa64_tgran4(const ARMISARegisters *id) -{ - return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 0; -} - -static inline bool isar_feature_aa64_tgran16(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 1; -} - -static inline bool isar_feature_aa64_tgran64(const ARMISARegisters *id) -{ - return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64) >= 0; -} - -static inline bool isar_feature_aa64_tgran4_2(const ARMISARegisters *id) -{ - unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2); - return t >= 2 || (t == 0 && isar_feature_aa64_tgran4(id)); -} - -static inline bool isar_feature_aa64_tgran16_2(const ARMISARegisters *id) -{ - unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2); - return t >= 2 || (t == 0 && isar_feature_aa64_tgran16(id)); -} - -static inline bool isar_feature_aa64_tgran64_2(const ARMISARegisters *id) -{ - unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64_2); - return t >= 2 || (t == 0 && isar_feature_aa64_tgran64(id)); -} - -static inline bool isar_feature_aa64_fgt(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, FGT) != 0; -} - -static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0; -} - -static inline bool isar_feature_aa64_lva(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, VARANGE) != 0; -} - -static inline bool isar_feature_aa64_e0pd(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, E0PD) != 0; -} - -static inline bool isar_feature_aa64_hafs(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) != 0; -} - -static inline bool isar_feature_aa64_hdbs(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) >= 2; -} - -static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0; -} - -static inline bool isar_feature_aa64_dit(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0; -} - -static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id) -{ - int key = FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, CSV2); - if (key >= 2) { - return true; /* FEAT_CSV2_2 */ - } - if (key == 1) { - key = FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, CSV2_FRAC); - return key >= 2; /* FEAT_CSV2_1p2 */ - } - return false; -} - -static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0; -} - -static inline bool isar_feature_aa64_debugv8p2(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, DEBUGVER) >= 8; -} - -static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SVEVER) != 0; -} - -static inline bool isar_feature_aa64_sve2_aes(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) != 0; -} - -static inline bool isar_feature_aa64_sve2_pmull128(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) >= 2; -} - -static inline bool isar_feature_aa64_sve2_bitperm(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BITPERM) != 0; -} - -static inline bool isar_feature_aa64_sve_bf16(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BFLOAT16) != 0; -} - -static inline bool isar_feature_aa64_sve2_sha3(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SHA3) != 0; -} - -static inline bool isar_feature_aa64_sve2_sm4(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SM4) != 0; -} - -static inline bool isar_feature_aa64_sve_i8mm(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, I8MM) != 0; -} - -static inline bool isar_feature_aa64_sve_f32mm(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F32MM) != 0; -} - -static inline bool isar_feature_aa64_sve_f64mm(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F64MM) != 0; -} - -static inline bool isar_feature_aa64_sme_f64f64(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, F64F64); -} - -static inline bool isar_feature_aa64_sme_i16i64(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, I16I64) == 0xf; -} - -static inline bool isar_feature_aa64_sme_fa64(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, FA64); -} - -static inline bool isar_feature_aa64_doublelock(const ARMISARegisters *id) -{ - return FIELD_SEX64(id->id_aa64dfr0, ID_AA64DFR0, DOUBLELOCK) >= 0; -} - -static inline bool isar_feature_aa64_mops(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, MOPS); -} - -/* - * Feature tests for "does this exist in either 32-bit or 64-bit?" - */ -static inline bool isar_feature_any_fp16(const ARMISARegisters *id) -{ - return isar_feature_aa64_fp16(id) || isar_feature_aa32_fp16_arith(id); -} - -static inline bool isar_feature_any_predinv(const ARMISARegisters *id) -{ - return isar_feature_aa64_predinv(id) || isar_feature_aa32_predinv(id); -} - -static inline bool isar_feature_any_pmuv3p1(const ARMISARegisters *id) -{ - return isar_feature_aa64_pmuv3p1(id) || isar_feature_aa32_pmuv3p1(id); -} - -static inline bool isar_feature_any_pmuv3p4(const ARMISARegisters *id) -{ - return isar_feature_aa64_pmuv3p4(id) || isar_feature_aa32_pmuv3p4(id); -} - -static inline bool isar_feature_any_pmuv3p5(const ARMISARegisters *id) -{ - return isar_feature_aa64_pmuv3p5(id) || isar_feature_aa32_pmuv3p5(id); -} - -static inline bool isar_feature_any_ccidx(const ARMISARegisters *id) -{ - return isar_feature_aa64_ccidx(id) || isar_feature_aa32_ccidx(id); -} - -static inline bool isar_feature_any_tts2uxn(const ARMISARegisters *id) -{ - return isar_feature_aa64_tts2uxn(id) || isar_feature_aa32_tts2uxn(id); -} - -static inline bool isar_feature_any_debugv8p2(const ARMISARegisters *id) -{ - return isar_feature_aa64_debugv8p2(id) || isar_feature_aa32_debugv8p2(id); -} - -static inline bool isar_feature_any_ras(const ARMISARegisters *id) -{ - return isar_feature_aa64_ras(id) || isar_feature_aa32_ras(id); -} - -static inline bool isar_feature_any_half_evt(const ARMISARegisters *id) -{ - return isar_feature_aa64_half_evt(id) || isar_feature_aa32_half_evt(id); -} - -static inline bool isar_feature_any_evt(const ARMISARegisters *id) -{ - return isar_feature_aa64_evt(id) || isar_feature_aa32_evt(id); -} - -/* - * Forward to the above feature tests given an ARMCPU pointer. - */ -#define cpu_isar_feature(name, cpu) \ - ({ ARMCPU *cpu_ = (cpu); isar_feature_##name(&cpu_->isar); }) - #endif diff --git a/target/arm/internals.h b/target/arm/internals.h index 1dd9182a54a..f7224e6f4d9 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -28,6 +28,7 @@ #include "hw/registerfields.h" #include "tcg/tcg-gvec-desc.h" #include "syndrome.h" +#include "cpu-features.h" /* register banks for CPU modes */ #define BANK_USRSYS 0 diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index b4046611f53..9efe00cf6ca 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -8,7 +8,7 @@ #include "exec/translator.h" #include "exec/helper-gen.h" #include "internals.h" - +#include "cpu-features.h" /* internal defines */ diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index 1f78e18872f..d10abb36a8e 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -21,6 +21,7 @@ #include "qemu/module.h" #include "qemu/log.h" #include "target/arm/idau.h" +#include "target/arm/cpu-features.h" #include "migration/vmstate.h" /* Bitbanded IO. Each word corresponds to a single bit. */ diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 03b6b8c986e..942be7bd112 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -21,6 +21,7 @@ #include "sysemu/tcg.h" #include "sysemu/runstate.h" #include "target/arm/cpu.h" +#include "target/arm/cpu-features.h" #include "exec/exec-all.h" #include "exec/memop.h" #include "qemu/log.h" diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index 2e2f7cf2188..8c20dc8a39a 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -25,6 +25,7 @@ #include "qemu/guest-random.h" #include "semihosting/common-semi.h" #include "target/arm/syndrome.h" +#include "target/arm/cpu-features.h" #define get_user_code_u32(x, gaddr, env) \ ({ abi_long __r = get_user_u32((x), (gaddr)); \ diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index b265cfd4706..a1e22d526d8 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -21,6 +21,7 @@ #include "user-internals.h" #include "signal-common.h" #include "linux-user/trace.h" +#include "target/arm/cpu-features.h" struct target_sigcontext { uint64_t fault_address; diff --git a/linux-user/arm/signal.c b/linux-user/arm/signal.c index cf99fd7b8a6..4020601c544 100644 --- a/linux-user/arm/signal.c +++ b/linux-user/arm/signal.c @@ -21,6 +21,7 @@ #include "user-internals.h" #include "signal-common.h" #include "linux-user/trace.h" +#include "target/arm/cpu-features.h" struct target_sigcontext { abi_ulong trap_no; diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 2e3809f03c4..baa69e55352 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -23,6 +23,10 @@ #include "target_signal.h" #include "accel/tcg/debuginfo.h" +#ifdef TARGET_ARM +#include "target/arm/cpu-features.h" +#endif + #ifdef _ARCH_PPC64 #undef ARCH_DLINFO #undef ELF_PLATFORM diff --git a/linux-user/mmap.c b/linux-user/mmap.c index 7b44b9ff49b..96c9433e271 100644 --- a/linux-user/mmap.c +++ b/linux-user/mmap.c @@ -26,6 +26,10 @@ #include "target_mman.h" #include "qemu/interval-tree.h" +#ifdef TARGET_ARM +#include "target/arm/cpu-features.h" +#endif + static pthread_mutex_t mmap_mutex = PTHREAD_MUTEX_INITIALIZER; static __thread int mmap_lock_count; diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c index 2d8e41ab8a3..06cdf4ba281 100644 --- a/target/arm/arch_dump.c +++ b/target/arm/arch_dump.c @@ -22,6 +22,7 @@ #include "cpu.h" #include "elf.h" #include "sysemu/dump.h" +#include "cpu-features.h" /* struct user_pt_regs from arch/arm64/include/uapi/asm/ptrace.h */ struct aarch64_user_regs { diff --git a/target/arm/cpu.c b/target/arm/cpu.c index aa4e006f21a..954328d72a0 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -31,6 +31,7 @@ #include "hw/core/tcg-cpu-ops.h" #endif /* CONFIG_TCG */ #include "internals.h" +#include "cpu-features.h" #include "exec/exec-all.h" #include "hw/qdev-properties.h" #if !defined(CONFIG_USER_ONLY) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 1cb9d5b81aa..1e9c6c85aec 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -32,6 +32,7 @@ #include "qapi/visitor.h" #include "hw/qdev-properties.h" #include "internals.h" +#include "cpu-features.h" #include "cpregs.h" void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index abe72e35ae6..79a3659c0ce 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -9,6 +9,7 @@ #include "qemu/log.h" #include "cpu.h" #include "internals.h" +#include "cpu-features.h" #include "cpregs.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index b7ace24bfc2..28f546a5ff9 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -23,6 +23,7 @@ #include "gdbstub/helpers.h" #include "sysemu/tcg.h" #include "internals.h" +#include "cpu-features.h" #include "cpregs.h" typedef struct RegisterSysregXmlParam { diff --git a/target/arm/helper.c b/target/arm/helper.c index b29edb26af8..5dc0d20a84e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11,6 +11,7 @@ #include "trace.h" #include "cpu.h" #include "internals.h" +#include "cpu-features.h" #include "exec/helper-proto.h" #include "qemu/main-loop.h" #include "qemu/timer.h" diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 4bb68646e43..3c175c93a7a 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -28,6 +28,7 @@ #include "sysemu/kvm_int.h" #include "kvm_arm.h" #include "internals.h" +#include "cpu-features.h" #include "hw/acpi/acpi.h" #include "hw/acpi/ghes.h" diff --git a/target/arm/machine.c b/target/arm/machine.c index fc4a4a40644..9e20b411895 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -5,6 +5,7 @@ #include "sysemu/tcg.h" #include "kvm_arm.h" #include "internals.h" +#include "cpu-features.h" #include "migration/cpu.h" static bool vfp_needed(void *opaque) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 95db9ec4c3b..53713e03006 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -13,6 +13,7 @@ #include "exec/exec-all.h" #include "cpu.h" #include "internals.h" +#include "cpu-features.h" #include "idau.h" #ifdef CONFIG_TCG # include "tcg/oversized-guest.h" diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index a9a8c0a0592..08db1dbcc74 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -26,6 +26,7 @@ #include "hw/qdev-properties.h" #include "qemu/units.h" #include "internals.h" +#include "cpu-features.h" #include "cpregs.h" static uint64_t make_ccsidr64(unsigned assoc, unsigned linesize, diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c index cea1adb7b62..3d7fdce5c3c 100644 --- a/target/arm/tcg/hflags.c +++ b/target/arm/tcg/hflags.c @@ -8,6 +8,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "internals.h" +#include "cpu-features.h" #include "exec/helper-proto.h" #include "cpregs.h" diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c index 0045c18f80f..a26adb75aa2 100644 --- a/target/arm/tcg/m_helper.c +++ b/target/arm/tcg/m_helper.c @@ -9,6 +9,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "internals.h" +#include "cpu-features.h" #include "gdbstub/helpers.h" #include "exec/helper-proto.h" #include "qemu/main-loop.h" diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index 403f8b09d36..ea08936a852 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -21,6 +21,7 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "internals.h" +#include "cpu-features.h" #include "exec/exec-all.h" #include "exec/cpu_ldst.h" #include "cpregs.h" diff --git a/target/arm/tcg/pauth_helper.c b/target/arm/tcg/pauth_helper.c index 4da2962ad5b..c4b143024f3 100644 --- a/target/arm/tcg/pauth_helper.c +++ b/target/arm/tcg/pauth_helper.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "internals.h" +#include "cpu-features.h" #include "exec/exec-all.h" #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c index 59bff8b4527..4fdd85359e1 100644 --- a/target/arm/tcg/tlb_helper.c +++ b/target/arm/tcg/tlb_helper.c @@ -8,6 +8,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "internals.h" +#include "cpu-features.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index 789bba36ccb..3e5e37abbe8 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -21,6 +21,7 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "internals.h" +#include "cpu-features.h" #ifdef CONFIG_TCG #include "qemu/log.h" #include "fpu/softfloat.h" From patchwork Fri Oct 27 14:39:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e2-20020a5d5002000000b0031c6581d55esm1874123wrt.91.2023.10.27.07.39.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Oct 2023 07:39:45 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/41] target/arm: Move ID_AA64MMFR1 and ID_AA64MMFR2 tests together Date: Fri, 27 Oct 2023 15:39:05 +0100 Message-Id: <20231027143942.3413881-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231027143942.3413881-1-peter.maydell@linaro.org> References: <20231027143942.3413881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Oct 2023 14:39:49 -0000 Our list of isar_feature functions is not in any particular order, but tests on fields of the same ID register tend to be grouped together. A few functions that are tests of fields in ID_AA64MMFR1 and ID_AA64MMFR2 are not in the same place as the rest; move them into their groups. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20231024163510.2972081-3-peter.maydell@linaro.org --- target/arm/cpu-features.h | 60 +++++++++++++++++++-------------------- 1 file changed, 30 insertions(+), 30 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index bfc9bfafe70..fc85a8fe130 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -641,6 +641,21 @@ static inline bool isar_feature_aa64_tidcp1(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR1, TIDCP1) != 0; } +static inline bool isar_feature_aa64_hafs(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) != 0; +} + +static inline bool isar_feature_aa64_hdbs(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) >= 2; +} + +static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0; +} + static inline bool isar_feature_aa64_uao(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0; @@ -676,6 +691,21 @@ static inline bool isar_feature_aa64_evt(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, EVT) >= 2; } +static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0; +} + +static inline bool isar_feature_aa64_lva(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, VARANGE) != 0; +} + +static inline bool isar_feature_aa64_e0pd(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, E0PD) != 0; +} + static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; @@ -794,36 +824,6 @@ static inline bool isar_feature_aa64_fgt(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, FGT) != 0; } -static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0; -} - -static inline bool isar_feature_aa64_lva(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, VARANGE) != 0; -} - -static inline bool isar_feature_aa64_e0pd(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, E0PD) != 0; -} - -static inline bool isar_feature_aa64_hafs(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) != 0; -} - -static inline bool isar_feature_aa64_hdbs(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) >= 2; -} - -static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0; -} - static inline bool isar_feature_aa64_dit(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0; From patchwork Fri Oct 27 14:39:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13455619 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1qwO08-0007D0-KI for mharc-qemu-devel@gnu.org; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e2-20020a5d5002000000b0031c6581d55esm1874123wrt.91.2023.10.27.07.39.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Oct 2023 07:39:46 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/41] target/arm: Move ID_AA64MMFR0 tests up to before MMFR1 and MMFR2 Date: Fri, 27 Oct 2023 15:39:06 +0100 Message-Id: <20231027143942.3413881-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231027143942.3413881-1-peter.maydell@linaro.org> References: <20231027143942.3413881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::131; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x131.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Oct 2023 14:39:51 -0000 Move the ID_AA64MMFR0 feature test functions up so they are before the ones for ID_AA64MMFR1 and ID_AA64MMFR2. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20231024163510.2972081-4-peter.maydell@linaro.org --- target/arm/cpu-features.h | 120 +++++++++++++++++++------------------- 1 file changed, 60 insertions(+), 60 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index fc85a8fe130..90200a4b98f 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -606,6 +606,66 @@ static inline bool isar_feature_aa64_rme(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RME) != 0; } +static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id) +{ + return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 1; +} + +static inline bool isar_feature_aa64_tgran4_2_lpa2(const ARMISARegisters *id) +{ + unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2); + return t >= 3 || (t == 0 && isar_feature_aa64_tgran4_lpa2(id)); +} + +static inline bool isar_feature_aa64_tgran16_lpa2(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 2; +} + +static inline bool isar_feature_aa64_tgran16_2_lpa2(const ARMISARegisters *id) +{ + unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2); + return t >= 3 || (t == 0 && isar_feature_aa64_tgran16_lpa2(id)); +} + +static inline bool isar_feature_aa64_tgran4(const ARMISARegisters *id) +{ + return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 0; +} + +static inline bool isar_feature_aa64_tgran16(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 1; +} + +static inline bool isar_feature_aa64_tgran64(const ARMISARegisters *id) +{ + return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64) >= 0; +} + +static inline bool isar_feature_aa64_tgran4_2(const ARMISARegisters *id) +{ + unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2); + return t >= 2 || (t == 0 && isar_feature_aa64_tgran4(id)); +} + +static inline bool isar_feature_aa64_tgran16_2(const ARMISARegisters *id) +{ + unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2); + return t >= 2 || (t == 0 && isar_feature_aa64_tgran16(id)); +} + +static inline bool isar_feature_aa64_tgran64_2(const ARMISARegisters *id) +{ + unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64_2); + return t >= 2 || (t == 0 && isar_feature_aa64_tgran64(id)); +} + +static inline bool isar_feature_aa64_fgt(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, FGT) != 0; +} + static inline bool isar_feature_aa64_vh(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0; @@ -764,66 +824,6 @@ static inline bool isar_feature_aa64_hbc(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, BC) != 0; } -static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id) -{ - return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 1; -} - -static inline bool isar_feature_aa64_tgran4_2_lpa2(const ARMISARegisters *id) -{ - unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2); - return t >= 3 || (t == 0 && isar_feature_aa64_tgran4_lpa2(id)); -} - -static inline bool isar_feature_aa64_tgran16_lpa2(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 2; -} - -static inline bool isar_feature_aa64_tgran16_2_lpa2(const ARMISARegisters *id) -{ - unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2); - return t >= 3 || (t == 0 && isar_feature_aa64_tgran16_lpa2(id)); -} - -static inline bool isar_feature_aa64_tgran4(const ARMISARegisters *id) -{ - return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 0; -} - -static inline bool isar_feature_aa64_tgran16(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 1; -} - -static inline bool isar_feature_aa64_tgran64(const ARMISARegisters *id) -{ - return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64) >= 0; -} - -static inline bool isar_feature_aa64_tgran4_2(const ARMISARegisters *id) -{ - unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2); - return t >= 2 || (t == 0 && isar_feature_aa64_tgran4(id)); -} - -static inline bool isar_feature_aa64_tgran16_2(const ARMISARegisters *id) -{ - unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2); - return t >= 2 || (t == 0 && isar_feature_aa64_tgran16(id)); -} - -static inline bool isar_feature_aa64_tgran64_2(const ARMISARegisters *id) -{ - unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64_2); - return t >= 2 || (t == 0 && isar_feature_aa64_tgran64(id)); -} - -static inline bool isar_feature_aa64_fgt(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, FGT) != 0; -} - static inline bool isar_feature_aa64_dit(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0; From patchwork Fri Oct 27 14:39:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13455622 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1qwO09-0007Dv-TO for mharc-qemu-devel@gnu.org; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e2-20020a5d5002000000b0031c6581d55esm1874123wrt.91.2023.10.27.07.39.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Oct 2023 07:39:46 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/41] target/arm: Move ID_AA64ISAR* test functions together Date: Fri, 27 Oct 2023 15:39:07 +0100 Message-Id: <20231027143942.3413881-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231027143942.3413881-1-peter.maydell@linaro.org> References: <20231027143942.3413881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Oct 2023 14:39:50 -0000 Move the feature test functions that test ID_AA64ISAR* fields together. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20231024163510.2972081-5-peter.maydell@linaro.org --- target/arm/cpu-features.h | 70 +++++++++++++++++++-------------------- 1 file changed, 35 insertions(+), 35 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 90200a4b98f..e73120ef974 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -451,6 +451,16 @@ static inline bool isar_feature_aa64_rndr(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RNDR) != 0; } +static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) == 2; +} + +static inline bool isar_feature_aa64_tlbios(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) != 0; +} + static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0; @@ -514,16 +524,6 @@ static inline bool isar_feature_aa64_pauth_qarma3(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, APA3) != 0; } -static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) == 2; -} - -static inline bool isar_feature_aa64_tlbios(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) != 0; -} - static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0; @@ -554,6 +554,31 @@ static inline bool isar_feature_aa64_bf16(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, BF16) != 0; } +static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0; +} + +static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >= 2; +} + +static inline bool isar_feature_aa64_i8mm(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, I8MM) != 0; +} + +static inline bool isar_feature_aa64_hbc(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, BC) != 0; +} + +static inline bool isar_feature_aa64_mops(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, MOPS); +} + static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id) { /* We always set the AdvSIMD and FP fields identically. */ @@ -804,26 +829,6 @@ static inline bool isar_feature_aa64_pmuv3p5(const ARMISARegisters *id) FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; } -static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0; -} - -static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >= 2; -} - -static inline bool isar_feature_aa64_i8mm(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, I8MM) != 0; -} - -static inline bool isar_feature_aa64_hbc(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, BC) != 0; -} - static inline bool isar_feature_aa64_dit(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0; @@ -922,11 +927,6 @@ static inline bool isar_feature_aa64_doublelock(const ARMISARegisters *id) return FIELD_SEX64(id->id_aa64dfr0, ID_AA64DFR0, DOUBLELOCK) >= 0; } -static inline bool isar_feature_aa64_mops(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, MOPS); -} - /* * Feature tests for "does this exist in either 32-bit or 64-bit?" */ From patchwork Fri Oct 27 14:39:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13455654 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1qwO0x-0001Fu-9f for mharc-qemu-devel@gnu.org; Fri, 27 Oct 2023 10:40:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qwO0I-0007LO-75 for qemu-devel@nongnu.org; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e2-20020a5d5002000000b0031c6581d55esm1874123wrt.91.2023.10.27.07.39.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Oct 2023 07:39:47 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/41] target/arm: Move ID_AA64PFR* tests together Date: Fri, 27 Oct 2023 15:39:08 +0100 Message-Id: <20231027143942.3413881-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231027143942.3413881-1-peter.maydell@linaro.org> References: <20231027143942.3413881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::135; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x135.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Oct 2023 14:40:04 -0000 Move all the ID_AA64PFR* feature test functions together. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20231024163510.2972081-6-peter.maydell@linaro.org --- target/arm/cpu-features.h | 86 +++++++++++++++++++-------------------- 1 file changed, 43 insertions(+), 43 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index e73120ef974..0ed05b8b19e 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -631,6 +631,49 @@ static inline bool isar_feature_aa64_rme(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RME) != 0; } +static inline bool isar_feature_aa64_dit(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0; +} + +static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id) +{ + int key = FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, CSV2); + if (key >= 2) { + return true; /* FEAT_CSV2_2 */ + } + if (key == 1) { + key = FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, CSV2_FRAC); + return key >= 2; /* FEAT_CSV2_1p2 */ + } + return false; +} + +static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0; +} + +static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; +} + +static inline bool isar_feature_aa64_mte_insn_reg(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) != 0; +} + +static inline bool isar_feature_aa64_mte(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >= 2; +} + +static inline bool isar_feature_aa64_sme(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SME) != 0; +} + static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id) { return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 1; @@ -791,26 +834,6 @@ static inline bool isar_feature_aa64_e0pd(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, E0PD) != 0; } -static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; -} - -static inline bool isar_feature_aa64_mte_insn_reg(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) != 0; -} - -static inline bool isar_feature_aa64_mte(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >= 2; -} - -static inline bool isar_feature_aa64_sme(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SME) != 0; -} - static inline bool isar_feature_aa64_pmuv3p1(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 && @@ -829,29 +852,6 @@ static inline bool isar_feature_aa64_pmuv3p5(const ARMISARegisters *id) FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; } -static inline bool isar_feature_aa64_dit(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0; -} - -static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id) -{ - int key = FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, CSV2); - if (key >= 2) { - return true; /* FEAT_CSV2_2 */ - } - if (key == 1) { - key = FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, CSV2_FRAC); - return key >= 2; /* FEAT_CSV2_1p2 */ - } - return false; -} - -static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id) -{ - return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0; -} - static inline bool isar_feature_aa64_debugv8p2(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, DEBUGVER) >= 8; From patchwork Fri Oct 27 14:39:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13455624 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1qwO0A-0007EW-9o for mharc-qemu-devel@gnu.org; Fri, 27 Oct 2023 10:39:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qwO06-0007C4-TL for qemu-devel@nongnu.org; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e2-20020a5d5002000000b0031c6581d55esm1874123wrt.91.2023.10.27.07.39.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Oct 2023 07:39:47 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/41] target/arm: Move ID_AA64DFR* feature tests together Date: Fri, 27 Oct 2023 15:39:09 +0100 Message-Id: <20231027143942.3413881-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231027143942.3413881-1-peter.maydell@linaro.org> References: <20231027143942.3413881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Oct 2023 14:39:51 -0000 Move all the ID_AA64DFR* feature test functions together. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20231024163510.2972081-7-peter.maydell@linaro.org --- target/arm/cpu-features.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 0ed05b8b19e..66212cd7ecc 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -857,6 +857,11 @@ static inline bool isar_feature_aa64_debugv8p2(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, DEBUGVER) >= 8; } +static inline bool isar_feature_aa64_doublelock(const ARMISARegisters *id) +{ + return FIELD_SEX64(id->id_aa64dfr0, ID_AA64DFR0, DOUBLELOCK) >= 0; +} + static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SVEVER) != 0; @@ -922,11 +927,6 @@ static inline bool isar_feature_aa64_sme_fa64(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, FA64); } -static inline bool isar_feature_aa64_doublelock(const ARMISARegisters *id) -{ - return FIELD_SEX64(id->id_aa64dfr0, ID_AA64DFR0, DOUBLELOCK) >= 0; -} - /* * Feature tests for "does this exist in either 32-bit or 64-bit?" */ From patchwork Fri Oct 27 14:39:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13455627 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1qwO0C-0007GT-6V for mharc-qemu-devel@gnu.org; Fri, 27 Oct 2023 10:39:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qwO08-0007Cu-Hb for qemu-devel@nongnu.org; Fri, 27 Oct 2023 10:39:52 -0400 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qwO06-00087k-TD for qemu-devel@nongnu.org; Fri, 27 Oct 2023 10:39:52 -0400 Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-407da05f05aso16210315e9.3 for ; Fri, 27 Oct 2023 07:39:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698417588; x=1699022388; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=ViyXdMoJwR5KQ6odO4W8+Pe+0fluwBTlAfwHWWB/LvM=; b=FAwMmTha8FnZqypx+CbrvV/UZscS1CktD0nuh1xGjCCUEV3gXbfnSk91D2OeRYZRWr 5PkaCuxypRYCo5aItk2NcDUc1m3+QRExslzoEaE5KFrzQyNITtPySlZeXq+x5MF6nfqn vE3LN0LP9wCKvroLUnzDr5me1bWzdPpbPhKpplHhmxKg4pLJ8bKypKfEzwEGXUq+UMXI jEwmWbhVWCk8WFj6wfKMQBpDepnvUwXQ7enE+gYNvu/0zX9aayukcnbnd+Ye0B1Br75X CNW20ZsfBGXnAfqacrDVbAMEOGAAEQhXHLanpga7OF/ytJ8ootR6Ry5eNMZ02yeEa8me Cmlg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698417588; x=1699022388; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ViyXdMoJwR5KQ6odO4W8+Pe+0fluwBTlAfwHWWB/LvM=; b=v8SkQTMCbkOMTqwxco2kyhxIV2aJf3XGCYOpyjQ0wCds8Q8IdQpVBfBZRWa7nXDO5/ 0uqXtBU2oyx3QNYqbiRR2ojvGzSMGszu6KqknsAGA1zXAQbLun4KTJYR6nr3FSkSdFyx HORvTHFP98saCMnJGZLLvSmwJZxSfvWZQHlbdDzkdwKK8/arhusa1Pt3UKdiEFYdG3rK Ncbqmpkl8iaq/larbfuZQSkFv12IOWuM27Pea3KXdfHJGdbvpCSQT2Nbgvcp2+zWjUsZ /U+Ap3xE4/6rCZCYUtsIJNlUlQ+liGqMaP5m6ssjCsi9W/HeD+eQ1NBifdWxp93FGP3D 74Kg== X-Gm-Message-State: AOJu0YzR0sevfMIzpZB0LPuWvgbnLiEIsH0jqY1IoqbdjQFKjw8Cqwzx Yg5/v/e1/2NLWFsvJgqAey+geHjqRj1JoQ0zwxk= X-Google-Smtp-Source: AGHT+IFlw8bcnyCfM+zyhx2YDym24hzf/o+/z0w8XSngGeeM6J2knpC9pZ0TNNVk+6SR+4wpfpldxQ== X-Received: by 2002:a5d:5850:0:b0:32f:71e2:adfb with SMTP id i16-20020a5d5850000000b0032f71e2adfbmr1559294wrf.3.1698417588432; Fri, 27 Oct 2023 07:39:48 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e2-20020a5d5002000000b0031c6581d55esm1874123wrt.91.2023.10.27.07.39.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Oct 2023 07:39:48 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/41] target/arm: Fix syndrome for FGT traps on ERET Date: Fri, 27 Oct 2023 15:39:10 +0100 Message-Id: <20231027143942.3413881-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231027143942.3413881-1-peter.maydell@linaro.org> References: <20231027143942.3413881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Oct 2023 14:39:52 -0000 In commit 442c9d682c94fc2 when we converted the ERET, ERETAA, ERETAB instructions to decodetree, the conversion accidentally lost the correct setting of the syndrome register when taking a trap because of the FEAT_FGT HFGITR_EL1.ERET bit. Instead of reporting a correct full syndrome value with the EC and IL bits, we only reported the low two bits of the syndrome, because the call to syn_erettrap() got dropped. Fix the syndrome values for these traps by reinstating the syn_erettrap() calls. Fixes: 442c9d682c94fc2 ("target/arm: Convert ERET, ERETAA, ERETAB to decodetree") Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20231024172438.2990945-1-peter.maydell@linaro.org --- target/arm/tcg/translate-a64.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index ad78b8b1202..41484d8ae54 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -1606,7 +1606,7 @@ static bool trans_ERET(DisasContext *s, arg_ERET *a) return false; } if (s->fgt_eret) { - gen_exception_insn_el(s, 0, EXCP_UDEF, 0, 2); + gen_exception_insn_el(s, 0, EXCP_UDEF, syn_erettrap(0), 2); return true; } dst = tcg_temp_new_i64(); @@ -1633,7 +1633,7 @@ static bool trans_ERETA(DisasContext *s, arg_reta *a) } /* The FGT trap takes precedence over an auth trap. */ if (s->fgt_eret) { - gen_exception_insn_el(s, 0, EXCP_UDEF, a->m ? 3 : 2, 2); + gen_exception_insn_el(s, 0, EXCP_UDEF, syn_erettrap(a->m ? 3 : 2), 2); return true; } dst = tcg_temp_new_i64(); From patchwork Fri Oct 27 14:39:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13455620 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1qwO08-0007DO-R5 for mharc-qemu-devel@gnu.org; Fri, 27 Oct 2023 10:39:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qwO07-0007Ch-Qw for qemu-devel@nongnu.org; Fri, 27 Oct 2023 10:39:51 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qwO06-000881-37 for qemu-devel@nongnu.org; Fri, 27 Oct 2023 10:39:51 -0400 Received: by mail-wr1-x431.google.com with SMTP id ffacd0b85a97d-32f5b83f254so1475540f8f.3 for ; Fri, 27 Oct 2023 07:39:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698417589; x=1699022389; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=eWOBdgQ7vK1VMcf/yXxF0qOWq66TWAm+9h+xR++3zSQ=; b=EJy4Ll16TiMbgrrPFBiTntQy+0QH9qh6sV0wSPRK+Fd7Ovz9LkSIUt05oXWNC5ogPV wEvsoZNHH+6vd1lM84cSMncq8ntmc1ik+2+lxKusHfIwvLnAnBl4Bw2mMWL8wOyxqfzm sZb2WZ9oADCEO9QAFeLoX7UpKzASpOqALL4D7FCmCC6jzmAduDlkJzDvsUSpqM8Zfubq 2kqoOPzQgL1uWtm8R0ioldVdlesYF7Yo52SQv1T4ntMsKcwDnVNq9bfZtX6WsBVrqZNR Ll9xUl6jQbBJWrp7qGajeJqPF7nJeE9eVBKI74FIfN6wn5iIUUVVDkkjedl2Rr5iklP4 e2Xw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698417589; x=1699022389; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eWOBdgQ7vK1VMcf/yXxF0qOWq66TWAm+9h+xR++3zSQ=; b=O24uoJQ4MNMGiXFyQrmJqYLu5yyzBwkx+mgWAb5u1LUYE9hac/K9t5/frC6Ipgv1tO 3FxElapFC+wp+6wS+8a5wXn2wedYsqr8BOF6C/vOjfX3hdU4EmFnnz2tN/IMsi+csfb9 c6s/8G0v2A6Y189KrZ3M5X2PNi/kupmOCQk+JKNhjFmDHtXzURcK5WKjjaV63pNusoG2 Q+dQvB1AP/oQKYJ/AvsQvBY5Iy5bwBwerpGCckPik30R8zwe2FT+KBXg5x+wD26c0jV0 YwCEu8MvONA7Xf3CVuAZCUFVAOuMnUilPe11xMn4OU5Z2mGIzbYGFhkXPkKlh8oqM7AC bhog== X-Gm-Message-State: AOJu0YzgyOS3st9e04kOrnv8mqbMECj37Wtht2SDqav5pIm+6QBCUclO 62P3LoPJmPQoihunr8dTCLYimgzEKL1ndaX5r34= X-Google-Smtp-Source: AGHT+IE35y/QOQf7Ok7UkN+recCFPW/tH60L7/MVaMP6/0uBO7pEC8OUlzFmNGlsVFQvVjCIpJ3TIQ== X-Received: by 2002:a5d:4d09:0:b0:32d:9d99:94e7 with SMTP id z9-20020a5d4d09000000b0032d9d9994e7mr2473378wrt.49.1698417588857; Fri, 27 Oct 2023 07:39:48 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e2-20020a5d5002000000b0031c6581d55esm1874123wrt.91.2023.10.27.07.39.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Oct 2023 07:39:48 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/41] hw/arm/allwinner-a10: Remove 'hw/arm/boot.h' from header Date: Fri, 27 Oct 2023 15:39:11 +0100 Message-Id: <20231027143942.3413881-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231027143942.3413881-1-peter.maydell@linaro.org> References: <20231027143942.3413881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Oct 2023 14:39:52 -0000 From: Philippe Mathieu-Daudé "hw/arm/boot.h" is only required on the source file. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Luc Michel Message-id: 20231025065316.56817-2-philmd@linaro.org Signed-off-by: Peter Maydell --- include/hw/arm/allwinner-a10.h | 1 - hw/arm/cubieboard.c | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h index cd1465c6138..2eb83a17eae 100644 --- a/include/hw/arm/allwinner-a10.h +++ b/include/hw/arm/allwinner-a10.h @@ -1,7 +1,6 @@ #ifndef HW_ARM_ALLWINNER_A10_H #define HW_ARM_ALLWINNER_A10_H -#include "hw/arm/boot.h" #include "hw/timer/allwinner-a10-pit.h" #include "hw/intc/allwinner-a10-pic.h" #include "hw/net/allwinner_emac.h" diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c index 8c7fa91529e..29146f50181 100644 --- a/hw/arm/cubieboard.c +++ b/hw/arm/cubieboard.c @@ -21,6 +21,7 @@ #include "hw/boards.h" #include "hw/qdev-properties.h" #include "hw/arm/allwinner-a10.h" +#include "hw/arm/boot.h" #include "hw/i2c/i2c.h" static struct arm_boot_info cubieboard_binfo = { From patchwork Fri Oct 27 14:39:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13455625 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1qwO0A-0007Eu-Hq for mharc-qemu-devel@gnu.org; Fri, 27 Oct 2023 10:39:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qwO08-0007Cs-Bv for qemu-devel@nongnu.org; Fri, 27 Oct 2023 10:39:52 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qwO06-00088A-QC for qemu-devel@nongnu.org; Fri, 27 Oct 2023 10:39:52 -0400 Received: by mail-wr1-x42d.google.com with SMTP id ffacd0b85a97d-307d58b3efbso1393834f8f.0 for ; Fri, 27 Oct 2023 07:39:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698417589; x=1699022389; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=HGUtiMRS0+Lv2+oiMjotQOi7uPWbvV9MFPbKTgd0KCU=; b=t9/xTuT40+GWo0Sto9I3G6do2vZsd3hqMZsRxw9L33SxSbvrfISqI0ddmuH6aSxhqQ rOnGZsPZ3Z8HWpf1gID0+y8sBaNHnLfBqwMsPfVk8mn5HTW6x/89Gaxu6R6hF5Rj9cKQ 1nVIYcm0X7VQJV6TxJdiL5sG8470A4qDg+hqI/oTZ6hsmjA4fa8HUwNAB/7Qlx/gWv3r DSBOvImrzPr8SnUIqmgqHL4zOc/xbQepHOMvtbhErTaprSPJad3DoJiF9pvjoYVLcOfV DBln9goGcAqewEpadIQ+oV8nBSXpmffaDIqZ5dczQ6M3qDkUx3BL4J1iEewNfmIY28t7 gRXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698417589; x=1699022389; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HGUtiMRS0+Lv2+oiMjotQOi7uPWbvV9MFPbKTgd0KCU=; b=rUfcnw9LmgqmeGB15HWPE4C4ncH0UaUKj4crLT52klU4JfZvv+fN2KkMRQFDRTuKQ6 JRz2J5rTvAvd3uGqsHEGRYmRaGxfFBpSca4OvRaMM/6ctsLzijcIQ4Vekhz1MLGM29TR ggg2wWo5RIl0tzKdCKztYyqYczATGWzodpjWJqW4p4gCGqkowj8/KrnHQApchvav7GC3 8T75DFtcZnySg+sHvxbZk20fipuLPOZINIZcRzUct7d+KKUU8fEPC8a6AI6xMcb3wvCW kYPUD9BMZE+PiXe+ZQRSvS6BrfNLufG4bWwOGkljEccsik7NkpKltJp0tIw7SJQZQj/R FEYw== X-Gm-Message-State: AOJu0Yw4uTYmj7MCj3s21dVC5g5IssZ7Ftcnn4wYDE7aK+scAGNa7eDJ Alydl9Iatd4bSLKWx59JfglCYp3/U8gWqnX1EDc= X-Google-Smtp-Source: AGHT+IHdUXF2HIsyodz4cV2yOftbjzDDKitiWroz0gCJfcHhYM6g+O8L7hbGi77tJ8wrLl2XR2FY8A== X-Received: by 2002:a05:6000:c8:b0:32d:90e6:c477 with SMTP id q8-20020a05600000c800b0032d90e6c477mr2212244wrx.26.1698417589242; Fri, 27 Oct 2023 07:39:49 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e2-20020a5d5002000000b0031c6581d55esm1874123wrt.91.2023.10.27.07.39.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Oct 2023 07:39:49 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/41] hw/arm/allwinner-h3: Remove 'hw/arm/boot.h' from header Date: Fri, 27 Oct 2023 15:39:12 +0100 Message-Id: <20231027143942.3413881-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231027143942.3413881-1-peter.maydell@linaro.org> References: <20231027143942.3413881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Oct 2023 14:39:52 -0000 From: Philippe Mathieu-Daudé "hw/arm/boot.h" is only required on the source file. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Luc Michel Message-id: 20231025065316.56817-3-philmd@linaro.org Signed-off-by: Peter Maydell --- include/hw/arm/allwinner-h3.h | 1 - hw/arm/orangepi.c | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h index f15d6d7cc7d..24ba4e1bf41 100644 --- a/include/hw/arm/allwinner-h3.h +++ b/include/hw/arm/allwinner-h3.h @@ -36,7 +36,6 @@ #define HW_ARM_ALLWINNER_H3_H #include "qom/object.h" -#include "hw/arm/boot.h" #include "hw/timer/allwinner-a10-pit.h" #include "hw/intc/arm_gic.h" #include "hw/misc/allwinner-h3-ccu.h" diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c index 10653361ed5..d0eca54cd95 100644 --- a/hw/arm/orangepi.c +++ b/hw/arm/orangepi.c @@ -25,6 +25,7 @@ #include "hw/boards.h" #include "hw/qdev-properties.h" #include "hw/arm/allwinner-h3.h" +#include "hw/arm/boot.h" static struct arm_boot_info orangepi_binfo; From patchwork Fri Oct 27 14:39:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13455626 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1qwO0B-0007G8-NQ for mharc-qemu-devel@gnu.org; Fri, 27 Oct 2023 10:39:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qwO0A-0007EA-2J for qemu-devel@nongnu.org; Fri, 27 Oct 2023 10:39:54 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qwO06-00088G-Vb for qemu-devel@nongnu.org; Fri, 27 Oct 2023 10:39:52 -0400 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-40839652b97so15697895e9.3 for ; Fri, 27 Oct 2023 07:39:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698417589; x=1699022389; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=5nN8931Ig5rZThrt4B3zV/ATHc+m9uFhmxFhGMca0VQ=; b=b44j88mQgO7rZGMrEIYj4TZkVsFNyfu7EJritdJ6748mFPb1heoyaG5x1XPXf1pE8i paFcer6foke6J2zNTtsCsiA+R+yk14zTSLMVgzA6ONBZVhA1W+vFvL5u2zh2ZhVMW6xt 2LW73LKQa0U+uiYvJEPWOacTnIrweQxxSArlBQxV9NNWBi99hLVVOJriOE4g386aUPg7 Z8pXH6NQ8oezvnVsU9QQj86BpFE2e9xuT2Pmeh9ZZQwBJNPQwEv3JvvCU6Gbbc2vYR+Z vWKtGVY+LKS2q48wB1RQyhXLBsO2HNq2R9UTFTu+QqK/HF6YU8eCBX3Zp41Wh/TKOOiE OShA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698417589; x=1699022389; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5nN8931Ig5rZThrt4B3zV/ATHc+m9uFhmxFhGMca0VQ=; b=b9+g1Gmdf+rc1midgOcln8WXs5G38B7XO1sUgp8UN4Az1RB10+HyICRM3HjqOT4Z6g OO5tku4Q4eUMV5xfmt7thH8sdXAYDV7TOlUOKqXsp15JWhqIuaygH6XEYczGZOY08toH JRvYDLiefUz4pgwBtgHkkZQ8RgND5niN64ue/hOXo6liDUIL3gr3slAV6X/2OfDZR02t WnREkh/f2KZ7qYZ59BDkv0kWJMlGw+owzh5DcY6zlOHx6V5zVPmKrRjnNG1jLr10gckk eO/5t9MRhuw0jaXlHAv2+RuuOVXejYeZA0Hcr81ynLPtZDhLKNTy/Fcd0CgeOqh0BjeG X8nQ== X-Gm-Message-State: AOJu0YztpJr+vYfLRUEYJuZ4cM+38F13wkm8SL91kdx3nmXPrsbtiagG BEh51kxfQQUfRW0yGorBXdiCKfbRf61C0SSAtFs= X-Google-Smtp-Source: AGHT+IFS/tHcEiJobyH38BY47OwvkOtMrwAkGap3jW9yxLlV6TSdYKYeoZikzKRSD+PU7dcyhbP6AQ== X-Received: by 2002:a5d:6d85:0:b0:31f:f326:766b with SMTP id l5-20020a5d6d85000000b0031ff326766bmr2602391wrs.6.1698417589747; Fri, 27 Oct 2023 07:39:49 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e2-20020a5d5002000000b0031c6581d55esm1874123wrt.91.2023.10.27.07.39.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Oct 2023 07:39:49 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/41] hw/arm/allwinner-r40: Remove 'hw/arm/boot.h' from header Date: Fri, 27 Oct 2023 15:39:13 +0100 Message-Id: <20231027143942.3413881-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231027143942.3413881-1-peter.maydell@linaro.org> References: <20231027143942.3413881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Oct 2023 14:39:54 -0000 From: Philippe Mathieu-Daudé "hw/arm/boot.h" is only required on the source file. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Luc Michel Message-id: 20231025065316.56817-4-philmd@linaro.org Signed-off-by: Peter Maydell --- include/hw/arm/allwinner-r40.h | 1 - hw/arm/bananapi_m2u.c | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/include/hw/arm/allwinner-r40.h b/include/hw/arm/allwinner-r40.h index 72710d3edce..6e1ac9d4c13 100644 --- a/include/hw/arm/allwinner-r40.h +++ b/include/hw/arm/allwinner-r40.h @@ -21,7 +21,6 @@ #define HW_ARM_ALLWINNER_R40_H #include "qom/object.h" -#include "hw/arm/boot.h" #include "hw/timer/allwinner-a10-pit.h" #include "hw/intc/arm_gic.h" #include "hw/sd/allwinner-sdhost.h" diff --git a/hw/arm/bananapi_m2u.c b/hw/arm/bananapi_m2u.c index 74121d89660..a7c7a9f96d7 100644 --- a/hw/arm/bananapi_m2u.c +++ b/hw/arm/bananapi_m2u.c @@ -26,6 +26,7 @@ #include "hw/i2c/i2c.h" #include "hw/qdev-properties.h" #include "hw/arm/allwinner-r40.h" +#include "hw/arm/boot.h" static struct arm_boot_info bpim2u_binfo; From patchwork Fri Oct 27 14:39:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13455628 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1qwO0D-0007H4-C7 for mharc-qemu-devel@gnu.org; Fri, 27 Oct 2023 10:39:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qwO0A-0007FB-Rr for qemu-devel@nongnu.org; Fri, 27 Oct 2023 10:39:54 -0400 Received: from mail-lf1-x136.google.com ([2a00:1450:4864:20::136]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qwO08-00088i-7n for qemu-devel@nongnu.org; Fri, 27 Oct 2023 10:39:54 -0400 Received: by mail-lf1-x136.google.com with SMTP id 2adb3069b0e04-507a55302e0so2761494e87.0 for ; Fri, 27 Oct 2023 07:39:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698417590; x=1699022390; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=bz4quSw4XJYtn+zFkVNPcs33W3qafYQj8GznRVOZI7w=; b=d+PEMrMBea7jgrZf6WMZkecJUbo7KjN65Ksw1o7fF4JKgD1Pov7/y895TtVtA8for6 gMX+MRAkXh/DHgCc3XuGqnozHxjacEbwW8xwoVuEqwjTBO7gDpw7/aLqmf4C6Qp2u+4m yTet+ajOnD9eKoU1DFZV4Rg5jxB52In7RUb+bzCWTuQwF2h3QrC9PwT+e+ngmkCIZ/bI sEc020hU2OAAbM75EQ5JGgQ93CiM1cAV0VeXl1eKkeu7TLCjAozqI4fdDlxWBw1t1Gtf HP98oSRg5YkaI959LOxJURqeiGafEc/ivL1knJdd1CAeqT6SKIgFMt0OgzhL3alzG02/ uuzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698417590; x=1699022390; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bz4quSw4XJYtn+zFkVNPcs33W3qafYQj8GznRVOZI7w=; b=nTC3/j2i6cbbZT9/L9zP1Q4OcyO6Qk2XkJJdE7ddPa4H/eTJBGT1itBHTKlco3iF7j hf0Twqfo1CvlmJRyV6isO8K1bfERSRudZBxR6O3Gc7yc+swm+2tIFSIh88R6Rxz4Fm9L boO32en3ci4OX2sEA9SebdcEpisVnYVKeWc2zKJynHFLa9GHG7nJdGOqm1hQ4HCKZYmB 9j9vyQLG/oQXjxKSSdMLiuK6UIrHSAatVZqysDTzgNDEckOCIcwuPPK+MFqZhbdk0I5t JElUVTFNpaUcuTTuBuvFPGEg9JJibgkYjLfgv4MkNZ05DWlqqaEr18TWbsTC0TXoLwq1 sztQ== X-Gm-Message-State: AOJu0YzWvwvRLVJEePnZmYGbLLfVGqxsHcNk5LNV3lZ5ieg1nmMzknVY T1UUri/Q4G/VekyffkKjUM0CGfRsWzdZi8gtZUg= X-Google-Smtp-Source: AGHT+IHWPHTmV8sLR/oxZUV+Hz8b12aEKhVXQaaG1YYO3FNsO6TI218vmy8FyOh63trDI4+zMftiGQ== X-Received: by 2002:a05:6512:2349:b0:507:bc6b:38a6 with SMTP id p9-20020a056512234900b00507bc6b38a6mr2582107lfu.33.1698417590364; Fri, 27 Oct 2023 07:39:50 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e2-20020a5d5002000000b0031c6581d55esm1874123wrt.91.2023.10.27.07.39.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Oct 2023 07:39:49 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/41] hw/arm/fsl-imx25: Remove 'hw/arm/boot.h' from header Date: Fri, 27 Oct 2023 15:39:14 +0100 Message-Id: <20231027143942.3413881-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231027143942.3413881-1-peter.maydell@linaro.org> References: <20231027143942.3413881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::136; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x136.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Oct 2023 14:39:55 -0000 From: Philippe Mathieu-Daudé "hw/arm/boot.h" is only required on the source file. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Luc Michel Message-id: 20231025065316.56817-5-philmd@linaro.org Signed-off-by: Peter Maydell --- include/hw/arm/fsl-imx25.h | 1 - hw/arm/imx25_pdk.c | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h index 1b1086e9458..df2f83980f0 100644 --- a/include/hw/arm/fsl-imx25.h +++ b/include/hw/arm/fsl-imx25.h @@ -17,7 +17,6 @@ #ifndef FSL_IMX25_H #define FSL_IMX25_H -#include "hw/arm/boot.h" #include "hw/intc/imx_avic.h" #include "hw/misc/imx25_ccm.h" #include "hw/char/imx_serial.h" diff --git a/hw/arm/imx25_pdk.c b/hw/arm/imx25_pdk.c index b4f7f4e8a7f..7dfddd49e23 100644 --- a/hw/arm/imx25_pdk.c +++ b/hw/arm/imx25_pdk.c @@ -27,6 +27,7 @@ #include "qapi/error.h" #include "hw/qdev-properties.h" #include "hw/arm/fsl-imx25.h" +#include "hw/arm/boot.h" #include "hw/boards.h" #include "qemu/error-report.h" #include "sysemu/qtest.h" From patchwork Fri Oct 27 14:39:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13455643 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1qwO0p-0000Cj-Tx for mharc-qemu-devel@gnu.org; Fri, 27 Oct 2023 10:40:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qwO0A-0007FA-RZ for qemu-devel@nongnu.org; Fri, 27 Oct 2023 10:39:54 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qwO08-00088w-A3 for qemu-devel@nongnu.org; Fri, 27 Oct 2023 10:39:54 -0400 Received: by mail-wr1-x429.google.com with SMTP id ffacd0b85a97d-32dff08bbdbso1472825f8f.2 for ; Fri, 27 Oct 2023 07:39:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698417591; x=1699022391; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=1yXp5lXsBt0uFwWt6pWnQ2JZi5Tqj/E4wJ1aMNhTymc=; b=Ab4JXCMkGc4hyCk1oRwzssVTDRJ19l7iowGYI+akFIGMZnSA0jEt+NAdT6BSlVdapI /trlgSasPaXlG61fm9uhLz81S55slhdXRvro8OZ26WkOGEHhI5Xu+2GN3oRSA2/9EJPS 7rAwSKkIQtO6Sk/iNq1qjAugN25VAXRoMeR0SXHGRqQg6u78kV+VqODqr58RxHqS/W4n 4clDX5ABSNtoEZHy/nOGtjhsiNMw2iIO3G7euQrzHLWpSwN+5s0D7AwtNqKiKTm+iIzf qYlaxWHNpoOVdGQmMOCHJSFheQ7IOchdMXqxVPgdinNWEUQ2lRPVEwEXww/Oi+ZjVRxF SgQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698417591; x=1699022391; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1yXp5lXsBt0uFwWt6pWnQ2JZi5Tqj/E4wJ1aMNhTymc=; b=Eze4YGeQlGKKsjxAbKK75KCq/WlZvKCjTEHWz8d1P4hO9LP/xD5CpmpPetn9MolV3f yLXd4HUE084hdIQWs4PI1NeqbUOu8HJaIphR1rptR8ltXxoClaHtlTDAa9lhOY1ZA1fV H+mWDzxEMCcoJ20JteOGj++VdasexQVdTB0E9TIBEuI+InRQTS/U2jKRn75Vz0EhSKqp mJstXDOSrxv9I75aE7g9mbe3R6gsH86tFgCNaxSHwwD3YmmpFMCL4R9RS/RnxFzx/HQM 9G93d1Eia/wPBiMn9GODQqAa1ulb0KNSVhyTshPEBDAv+SLBQdsRB7hWG9Udc8fLRmjM jRNQ== X-Gm-Message-State: AOJu0Yx/AyTYZ30OI+upP3BvShw11bhm9XhJ0dndkn48m1Vfac0xajBx pJ7GD0cE4fBUVNOdn+Wn1WI410QFmj7e8CF4j0s= X-Google-Smtp-Source: AGHT+IFXSf5+ulR+O94F1odPwA04QH8fKqLX8q85xPXqQKyPg1Jchsnq4gvYG5Led+QfIFeJ3jzDyA== X-Received: by 2002:a5d:6749:0:b0:31f:fa38:425f with SMTP id l9-20020a5d6749000000b0031ffa38425fmr2568817wrw.9.1698417590933; Fri, 27 Oct 2023 07:39:50 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e2-20020a5d5002000000b0031c6581d55esm1874123wrt.91.2023.10.27.07.39.50 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Oct 2023 07:39:50 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/41] hw/arm/fsl-imx31: Remove 'hw/arm/boot.h' from header Date: Fri, 27 Oct 2023 15:39:15 +0100 Message-Id: <20231027143942.3413881-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231027143942.3413881-1-peter.maydell@linaro.org> References: <20231027143942.3413881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Oct 2023 14:39:55 -0000 From: Philippe Mathieu-Daudé "hw/arm/boot.h" is only required on the source file. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Luc Michel Message-id: 20231025065316.56817-6-philmd@linaro.org Signed-off-by: Peter Maydell --- include/hw/arm/fsl-imx31.h | 1 - hw/arm/kzm.c | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/include/hw/arm/fsl-imx31.h b/include/hw/arm/fsl-imx31.h index c116a73e0b3..40c593a5cf3 100644 --- a/include/hw/arm/fsl-imx31.h +++ b/include/hw/arm/fsl-imx31.h @@ -17,7 +17,6 @@ #ifndef FSL_IMX31_H #define FSL_IMX31_H -#include "hw/arm/boot.h" #include "hw/intc/imx_avic.h" #include "hw/misc/imx31_ccm.h" #include "hw/char/imx_serial.h" diff --git a/hw/arm/kzm.c b/hw/arm/kzm.c index b1b281c9acb..9be91ebeaaf 100644 --- a/hw/arm/kzm.c +++ b/hw/arm/kzm.c @@ -16,6 +16,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "hw/arm/fsl-imx31.h" +#include "hw/arm/boot.h" #include "hw/boards.h" #include "qemu/error-report.h" #include "exec/address-spaces.h" From patchwork Fri Oct 27 14:39:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13455631 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1qwO0F-0007IW-B9 for mharc-qemu-devel@gnu.org; Fri, 27 Oct 2023 10:39:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qwO0C-0007GS-4Y for qemu-devel@nongnu.org; Fri, 27 Oct 2023 10:39:56 -0400 Received: from mail-lf1-x132.google.com ([2a00:1450:4864:20::132]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qwO09-000898-Bn for qemu-devel@nongnu.org; Fri, 27 Oct 2023 10:39:55 -0400 Received: by mail-lf1-x132.google.com with SMTP id 2adb3069b0e04-507a29c7eefso3112111e87.1 for ; Fri, 27 Oct 2023 07:39:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698417591; x=1699022391; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=qRIOP/ceFHTRk8zEeRjbfMfsx/awJQ+B1yFMqlGEBrY=; b=LOp55dXhH31h+I/6/XAtb+WF0PfTJoxbb+XYrrUrz55mx3yaxwIVIIPltNc+g2NzvG w8Gyh1suP+A2yjtwh90NYVGuqTv7YK1LAy21ebmNFEeHRLDJ0Jt88YHRI/LxDxKyOLEd L1LvrjR8its7y/eaB/82ZsLUyj0weL1jEXkAAKa/PGyMgkrUy9dEiYN3AV7655GiRYXR TueV70JCfxFIhd+X3tIeT9vnDzxcRLu2JH02nRs7uzN0Ir12EdsaykKLvHhw9ky7cVmu VreqT1THuNYGMRDjepkTNNAzJrFOoiKY3IBs2GsF5VDfmcAR8LUwwPItiSuUaV1yTpVN PMYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698417591; x=1699022391; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qRIOP/ceFHTRk8zEeRjbfMfsx/awJQ+B1yFMqlGEBrY=; b=OAmktI+mw3Fs3tOkXGJB1WT1OAI40Pxlp6nbZzOLA9FDRZUb+f20k6N/rnfOYO8Vaw 6Yaq7HuoIh1Jgc+jLf9hG8ypXcjQWc7LCy5nVSi1kTap02Mlzz83B4nS9fyDyIkhmpRl CEKmXDxhuyAiLgkJXCV+CiAcNKq11petWm2yZQ+Y/sWZYR/hCCKz97GeguuUzAuYRuZd CXQgwLwpMhiyK+TkkSnkkLVzJIqlRN0RQU/tlE3aR45WzrEGZOB1WD9+cW3/3KEvxreX GD9nhiD71OQSVkNJ9CwhfbD1SZ83i1jdUOGREO+1fCb0MppCzhhuzfoZh1rng/cYuC8G L3YA== X-Gm-Message-State: AOJu0YzFwRIFk5PTcRiYrT6mX/N671YxLO7K5IfuSPvp5h1Q/HIOAMpr OraM6kOYxLIbN/abWQTJRtxINvt4jRDCtMQQOpo= X-Google-Smtp-Source: AGHT+IGl4jevLKRDpmGfxvzZPJbMtKnDte205JpLfO7OjieyHEyp8xAA8e7X2+if0BOLf4BbhyqOLQ== X-Received: by 2002:a05:6512:39d4:b0:507:b084:d6bb with SMTP id k20-20020a05651239d400b00507b084d6bbmr2852819lfu.43.1698417591379; Fri, 27 Oct 2023 07:39:51 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e2-20020a5d5002000000b0031c6581d55esm1874123wrt.91.2023.10.27.07.39.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Oct 2023 07:39:51 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/41] hw/arm/fsl-imx6: Remove 'hw/arm/boot.h' from header Date: Fri, 27 Oct 2023 15:39:16 +0100 Message-Id: <20231027143942.3413881-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231027143942.3413881-1-peter.maydell@linaro.org> References: <20231027143942.3413881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::132; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x132.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Oct 2023 14:39:56 -0000 From: Philippe Mathieu-Daudé "hw/arm/boot.h" is only required on the source file. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Luc Michel Message-id: 20231025065316.56817-7-philmd@linaro.org Signed-off-by: Peter Maydell --- include/hw/arm/fsl-imx6.h | 1 - hw/arm/sabrelite.c | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h index 5b4d48da084..519b871014a 100644 --- a/include/hw/arm/fsl-imx6.h +++ b/include/hw/arm/fsl-imx6.h @@ -17,7 +17,6 @@ #ifndef FSL_IMX6_H #define FSL_IMX6_H -#include "hw/arm/boot.h" #include "hw/cpu/a9mpcore.h" #include "hw/misc/imx6_ccm.h" #include "hw/misc/imx6_src.h" diff --git a/hw/arm/sabrelite.c b/hw/arm/sabrelite.c index 41191245b81..56f184b9ae7 100644 --- a/hw/arm/sabrelite.c +++ b/hw/arm/sabrelite.c @@ -13,6 +13,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "hw/arm/fsl-imx6.h" +#include "hw/arm/boot.h" #include "hw/boards.h" #include "hw/qdev-properties.h" #include "qemu/error-report.h" From patchwork Fri Oct 27 14:39:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13455629 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1qwO0E-0007Hw-V4 for mharc-qemu-devel@gnu.org; Fri, 27 Oct 2023 10:39:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qwO0B-0007FS-CL for qemu-devel@nongnu.org; Fri, 27 Oct 2023 10:39:55 -0400 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qwO09-00089G-Be for qemu-devel@nongnu.org; Fri, 27 Oct 2023 10:39:55 -0400 Received: by mail-wr1-x42c.google.com with SMTP id ffacd0b85a97d-32d80ae19f8so1451825f8f.2 for ; Fri, 27 Oct 2023 07:39:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698417592; x=1699022392; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=PmrQWRC5NaTWdnVXX29KPny7C1ylyTktaxRIFDqRHdE=; b=UJETF10E/rrw7y8tTbYoReAhtYI8C3GXEzBEAIC9qKhL8/ioCdEn21wqb+WarH7xyt zn1c+S9guhKQJUovafvAjTN2xMAukxIItSC4Anf8Qh0BL+ucEH47SzQwn//pw0+J8QJ5 ySwBkW8Sir8SmAqVr7EamAK8gbG3821vVXDQckLeqRGwRpeIix301ckYUt8FlaSnPnG+ aG/X4UnTBAwgHky9xkFlVvdO1jpj2wIjgDaQ0iAyxU2HFEiXI4lxvlXgCed/f1IflXOh ePnvMtoOljeC0RmuKD//WAhJmAJcl+T5hGr2hm088BnQP3S3sLBJjKs+s/gz/OHiH/Ff rzqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698417592; x=1699022392; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PmrQWRC5NaTWdnVXX29KPny7C1ylyTktaxRIFDqRHdE=; b=vhSIGovTUFPc8TslNFS42LIDfIByTHPUN6K+I5jB7Fz4Q/wEpa4wtqv5eZe/6pNuUs Sk/rAZ3Ix3MenBoXoMXUKRAIdBeqYPdbXUTddpd0D0W9RO9JMt2xJebfKLABDgbw3Efb zli34MX8x/WMRO6pTsrR/kbCwkcHGsskRYmCtGkfYDlt/PmL2pehWy7bwQXPTU8U5aK9 vZamnFz8pztlUHPS2/BbjFElrJ2KifWVoztTlu1zqOLGRjXZI9GXEJg4y1l2gHh7ldAm iTRiOulfX6DfRzvNakS7Jg5Iyc1qK69EB7mZgvBtMIVLdvMQxBzVmlmzLUwg19LVyTfF ZLwA== X-Gm-Message-State: AOJu0Yy7lCKTH+rQ8bYghzYVy9O8AcpJk2HEKZo62t6y8RaQmMCwXUxP CrZucc4boPYeeZn513FHCSmmLcRdirt6q++7BGQ= X-Google-Smtp-Source: AGHT+IEsTbT58KELAkP/dFD09RCEh4+5e58ZMKO6m45/UgUeZSn/QWNUlxRD8BmyVhIrF8qrEGaVhg== X-Received: by 2002:a05:6000:acf:b0:329:6662:ac1d with SMTP id di15-20020a0560000acf00b003296662ac1dmr2660099wrb.24.1698417591844; Fri, 27 Oct 2023 07:39:51 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e2-20020a5d5002000000b0031c6581d55esm1874123wrt.91.2023.10.27.07.39.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Oct 2023 07:39:51 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/41] hw/arm/fsl-imx6ul: Remove 'hw/arm/boot.h' from header Date: Fri, 27 Oct 2023 15:39:17 +0100 Message-Id: <20231027143942.3413881-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231027143942.3413881-1-peter.maydell@linaro.org> References: <20231027143942.3413881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Oct 2023 14:39:55 -0000 From: Philippe Mathieu-Daudé "hw/arm/boot.h" is only required on the source file. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Luc Michel Message-id: 20231025065316.56817-8-philmd@linaro.org Signed-off-by: Peter Maydell --- include/hw/arm/fsl-imx6ul.h | 1 - hw/arm/mcimx6ul-evk.c | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h index 63012628ff0..14390f60144 100644 --- a/include/hw/arm/fsl-imx6ul.h +++ b/include/hw/arm/fsl-imx6ul.h @@ -17,7 +17,6 @@ #ifndef FSL_IMX6UL_H #define FSL_IMX6UL_H -#include "hw/arm/boot.h" #include "hw/cpu/a15mpcore.h" #include "hw/misc/imx6ul_ccm.h" #include "hw/misc/imx6_src.h" diff --git a/hw/arm/mcimx6ul-evk.c b/hw/arm/mcimx6ul-evk.c index 3ac1e2ea9b4..500427e94be 100644 --- a/hw/arm/mcimx6ul-evk.c +++ b/hw/arm/mcimx6ul-evk.c @@ -13,6 +13,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "hw/arm/fsl-imx6ul.h" +#include "hw/arm/boot.h" #include "hw/boards.h" #include "hw/qdev-properties.h" #include "qemu/error-report.h" From patchwork Fri Oct 27 14:39:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13455636 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1qwO0m-0008FH-S3 for mharc-qemu-devel@gnu.org; Fri, 27 Oct 2023 10:40:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qwO0F-0007IV-9c for qemu-devel@nongnu.org; Fri, 27 Oct 2023 10:39:59 -0400 Received: from mail-lf1-x136.google.com ([2a00:1450:4864:20::136]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qwO09-00089V-Or for qemu-devel@nongnu.org; Fri, 27 Oct 2023 10:39:59 -0400 Received: by mail-lf1-x136.google.com with SMTP id 2adb3069b0e04-507c8316abcso2744684e87.1 for ; Fri, 27 Oct 2023 07:39:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698417592; x=1699022392; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=STyU82hPIUpYks6uiomyW9R8nlE5SYdJeoBHFM04RVg=; b=bQBp8D6WbaMwHpTTfABoK3YIei+kNUJqyPuhEtviSq2E4gjnzNJ8IVFXyn/UE9Iwvw rCiFZDeZiR0+/5/OjidBqgpKDDvQxUjWN69/wW4BpNkSRCUO1gabnLFnnBbgL7Buo9fi 9ca9OqVMTKT4tTG2F0cLrETchFdFVRq8dXdsTW48vCnacc8yRumpw42otUEh4nQ9cETr Ycw10oQ4ycMS560e3adLLm0fT63sHDse6gpJkoTrnLCjHkuIgV1luh3W30nSJiGn66WF oUNTUkk26pOEPgYrT4pOHEpYICEcbMtqSrHpu4xlRBA/W/fy+A3O9UqkK3HjbO5iONNS NSBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698417592; x=1699022392; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=STyU82hPIUpYks6uiomyW9R8nlE5SYdJeoBHFM04RVg=; b=gdxMZ0j52Y3CxFAQvsWh61YK3VwECyE4L0B38xJZAQCeX0+uMfMilXvR6B7ZdOBFNY XpRHGjugMtjMkLZlJ1emAcVDW6YM7NWmUc/w/yKgvj6F8SlQUmSCVy7ICGbRn4vdpODr jcpJJInwxHVigwjiToB9RYXiUPzBqzakzhyn1uUHoQdI4r6MePWMxPV3jsLcc/fjHo4h Rylj8ZeeQwCJKKVaUus5O4BlZpbcnePwFNryIhU5IgdqY/SWDzl/BgStwLFMtAqnkLE7 wtx1zkBR3oc9K937wlHVe4Y0SMAY8U5XW5JwIPa/L9olfqUWlQYnuDFoxkA/2uMjBGzv LA3g== X-Gm-Message-State: AOJu0YwP6AYBtmEY0EGqj0QMTTzko3H7533ZxM2zL2r3NVjBc5tQxkIm 6ohFGE+AcnB1KjVp+RIAtdtsx8N4qDnBPXhkSg0= X-Google-Smtp-Source: AGHT+IE5S1FoXcWFQdSHx8aNP79zdUJh6BZYv8VEQ5HQUahOPXlfMM8O93PcxCWBQBRrqTEAzqPfTA== X-Received: by 2002:a19:4f5d:0:b0:500:8022:3dc7 with SMTP id a29-20020a194f5d000000b0050080223dc7mr2095416lfk.10.1698417592273; Fri, 27 Oct 2023 07:39:52 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e2-20020a5d5002000000b0031c6581d55esm1874123wrt.91.2023.10.27.07.39.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Oct 2023 07:39:52 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/41] hw/arm/fsl-imx7: Remove 'hw/arm/boot.h' from header Date: Fri, 27 Oct 2023 15:39:18 +0100 Message-Id: <20231027143942.3413881-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231027143942.3413881-1-peter.maydell@linaro.org> References: <20231027143942.3413881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::136; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x136.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Oct 2023 14:39:59 -0000 From: Philippe Mathieu-Daudé "hw/arm/boot.h" is only required on the source file. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Luc Michel Message-id: 20231025065316.56817-9-philmd@linaro.org Signed-off-by: Peter Maydell --- include/hw/arm/fsl-imx7.h | 1 - hw/arm/mcimx7d-sabre.c | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h index 2cbfc6b2b2c..411fa1c2e37 100644 --- a/include/hw/arm/fsl-imx7.h +++ b/include/hw/arm/fsl-imx7.h @@ -19,7 +19,6 @@ #ifndef FSL_IMX7_H #define FSL_IMX7_H -#include "hw/arm/boot.h" #include "hw/cpu/a15mpcore.h" #include "hw/intc/imx_gpcv2.h" #include "hw/misc/imx7_ccm.h" diff --git a/hw/arm/mcimx7d-sabre.c b/hw/arm/mcimx7d-sabre.c index d1778122b64..693a1023b6c 100644 --- a/hw/arm/mcimx7d-sabre.c +++ b/hw/arm/mcimx7d-sabre.c @@ -15,6 +15,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "hw/arm/fsl-imx7.h" +#include "hw/arm/boot.h" #include "hw/boards.h" #include "hw/qdev-properties.h" #include "qemu/error-report.h" From patchwork Fri Oct 27 14:39:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13455632 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1qwO0K-0007Mw-V3 for mharc-qemu-devel@gnu.org; Fri, 27 Oct 2023 10:40:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qwO0D-0007Gq-27 for qemu-devel@nongnu.org; Fri, 27 Oct 2023 10:39:57 -0400 Received: from mail-ej1-x630.google.com ([2a00:1450:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qwO0A-00089e-4n for qemu-devel@nongnu.org; Fri, 27 Oct 2023 10:39:56 -0400 Received: by mail-ej1-x630.google.com with SMTP id a640c23a62f3a-9c773ac9b15so317375666b.2 for ; Fri, 27 Oct 2023 07:39:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698417592; x=1699022392; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=q1/21Qej9F0ur5kxVcfbwd5gynXPn44FfuU8/fDsIJg=; b=GCtir2hobDjveU1ba5SMDRUzP0mCz7hh1BKmq8a57QbT1ImjFjF3QeekhcI+n6sBpx AVAmMdFkkYaJh6u/T52mwbLZpCeFmt6BGbo4NvMiZouq43zo0/JEYXvrGD4CMnhESJ+Z 6LHo+3ajRtzqfqKdG/jJ2xK2KqTX3PuNK3URYyvd251C403vP11Kysf/1UImgoaZ/tG/ uheK77ViJEdzYPy7eVw+qcm+Kn6Z88Wrqb5B0la/bPicSIy/WLkwWoYCee5IMrqkzT9C ovQCkCflnEMYmV7OD2RbR+xW+DYRFFquaTW7trKFnHNJvK1LwQvVTC15nDe6yjBiH5Yn Dsiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698417592; x=1699022392; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=q1/21Qej9F0ur5kxVcfbwd5gynXPn44FfuU8/fDsIJg=; b=PxdbzFOo0G2qJubJrO9i9M1ML0HhdDlxKDqqFf3i5Ded/JnQS+8+R/mNnCNS+Ic6Im len1nRJjaTMQ5fdC7Pfe9LuF5yuQdZbT+zTnSqNYCIOMedeEOeKHJyLKIoO67o7mLyRZ wB+opew43d8boihzK2cip2qWa5AyRD+wYTuaSH+GX31kFATAIkfnp+chW6tXG4h1CyLw WA+AWWz4DcaGf3s9C/YAjH35mg/wdwXS0z6KQORshUs1r8dIAGb3lonkC3myqn93kM5C BlenFh8r0SJG4SF76S2FkckknW6sfd6kB133yl8KY+X/Doy+qsDNLY5YAJwViVIHLM6L XFpQ== X-Gm-Message-State: AOJu0Yxr3WxG/pD+szi/mC8CJQTIPCewQRScEdh3nHsz6Gm+nD+EevYM cJEx6ixSYiJLing1FOdNF4e3gya88BSQgq4mL6U= X-Google-Smtp-Source: AGHT+IEHKmpZdgtXO9/lDDsRrrLDKaCTcFY0Vfv7wl/IfP91uE/CJ3/cK12BPvr8kdR6HvvY26DVvQ== X-Received: by 2002:a17:907:3603:b0:9be:40ba:5f1 with SMTP id bk3-20020a170907360300b009be40ba05f1mr2637804ejc.60.1698417592757; Fri, 27 Oct 2023 07:39:52 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e2-20020a5d5002000000b0031c6581d55esm1874123wrt.91.2023.10.27.07.39.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Oct 2023 07:39:52 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/41] hw/arm/xlnx-versal: Remove 'hw/arm/boot.h' from header Date: Fri, 27 Oct 2023 15:39:19 +0100 Message-Id: <20231027143942.3413881-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231027143942.3413881-1-peter.maydell@linaro.org> References: <20231027143942.3413881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::630; envelope-from=peter.maydell@linaro.org; helo=mail-ej1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Oct 2023 14:39:57 -0000 From: Philippe Mathieu-Daudé "hw/arm/boot.h" is only required on the source file. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Luc Michel Message-id: 20231025065316.56817-10-philmd@linaro.org Signed-off-by: Peter Maydell --- include/hw/arm/xlnx-versal.h | 1 - hw/arm/xlnx-versal-virt.c | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h index 7b419f88c2c..b710d71fb08 100644 --- a/include/hw/arm/xlnx-versal.h +++ b/include/hw/arm/xlnx-versal.h @@ -13,7 +13,6 @@ #define XLNX_VERSAL_H #include "hw/sysbus.h" -#include "hw/arm/boot.h" #include "hw/cpu/cluster.h" #include "hw/or-irq.h" #include "hw/sd/sdhci.h" diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c index 88c561ff632..537118224fb 100644 --- a/hw/arm/xlnx-versal-virt.c +++ b/hw/arm/xlnx-versal-virt.c @@ -19,6 +19,7 @@ #include "cpu.h" #include "hw/qdev-properties.h" #include "hw/arm/xlnx-versal.h" +#include "hw/arm/boot.h" #include "qom/object.h" #define TYPE_XLNX_VERSAL_VIRT_MACHINE MACHINE_TYPE_NAME("xlnx-versal-virt") From patchwork Fri Oct 27 14:39:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13455633 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1qwO0N-0007O5-6e for mharc-qemu-devel@gnu.org; Fri, 27 Oct 2023 10:40:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qwO0D-0007Gp-1l for qemu-devel@nongnu.org; Fri, 27 Oct 2023 10:39:57 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qwO0A-00089k-Lu for qemu-devel@nongnu.org; Fri, 27 Oct 2023 10:39:56 -0400 Received: by mail-wr1-x435.google.com with SMTP id ffacd0b85a97d-32f5b83f254so1475582f8f.3 for ; Fri, 27 Oct 2023 07:39:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698417593; x=1699022393; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=ujFzQLltW2Suocxr+GhD/2DbHmU0GTzQwzP5CygPT38=; b=HE77PfqFvLGJVdVTcymwZK+DLweHIe6Wg/Jc0Lfv5z62vTJmlMSgQRPCLBz32v0jdR +2WuDAD5GQvpSCTnqn1gZQ1noK+5yrp9Hvc46LGq1eZJl9qZt8vY8hMzA5oZ98iueuRm bBA2jSMKcaUInRySgyeFjNJJMNAAqiUgcjMSark/PJSXt4PUB4zUDfMalRCcXQa4z0mG EyKFdgv6pwkP61boPDpuiWmfzXrjmkmyxwQhz5Gihcm34GOoE2MH2n5q3pBMAErHqC+A YV7hLbH3JfOfLxh3mnL/DEwFxx5I7ZXW2301gY2n5grhGN4WJIKMb529+L4X89CSsqMl ALxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698417593; x=1699022393; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ujFzQLltW2Suocxr+GhD/2DbHmU0GTzQwzP5CygPT38=; b=rk1VpksCK9q6ysnT0jAjHLLOq/bPwwjk6TH0QXIQKy/R94Xw6JfKFZkxIosEwQMiGq 2Xj8CcL0P0cfaK2th4tQSqqm+bHIvuRUQNxnD63AhwbsSpHAglzTRpNx2Zh1l23fcQ6s mbR9GtnJ8frdzm+x8Gm9L9zuylUhxoJDQl66cKrpzOACIMiahyzvICuqdQKrvyLY9duT x+JraEpuGbIDNNDPW7AjlRY1aoAA22cQmgdab50xC8I9XhauxrM8Sn6dM/lUT79Ip1Fk bfFKjlmG18DTcwzMKRylG8vye01y79VB7PkU4MOXVf4aGxefZev/Cqw2Yb2ci2IGVJn5 QqaA== X-Gm-Message-State: AOJu0YzPe8DjSfOR337JS6Jzgo5JPpuLDpOYpqV8y2bC1NAoykmXuk/t y7WwUcRMdGutbaU9+BPaJ+FWvpPQoZJCShszGHc= X-Google-Smtp-Source: AGHT+IG99Ci7wIvi9k4Fgmu3DtpsB1Fnj7c2fgNKWWyY6Qg8rCgzbhRrxPb7gBUQ91y+iyzPsFk2lQ== X-Received: by 2002:a05:6000:c8:b0:32d:9cf2:f82 with SMTP id q8-20020a05600000c800b0032d9cf20f82mr2254960wrx.45.1698417593177; Fri, 27 Oct 2023 07:39:53 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e2-20020a5d5002000000b0031c6581d55esm1874123wrt.91.2023.10.27.07.39.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Oct 2023 07:39:52 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/41] hw/arm/xlnx-zynqmp: Remove 'hw/arm/boot.h' from header Date: Fri, 27 Oct 2023 15:39:20 +0100 Message-Id: <20231027143942.3413881-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231027143942.3413881-1-peter.maydell@linaro.org> References: <20231027143942.3413881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Oct 2023 14:39:57 -0000 From: Philippe Mathieu-Daudé "hw/arm/boot.h" is only required on the source file. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Luc Michel Message-id: 20231025065316.56817-11-philmd@linaro.org Signed-off-by: Peter Maydell --- include/hw/arm/xlnx-zynqmp.h | 1 - hw/arm/xlnx-zcu102.c | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index 687c75e3b03..96358d51ebb 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -18,7 +18,6 @@ #ifndef XLNX_ZYNQMP_H #define XLNX_ZYNQMP_H -#include "hw/arm/boot.h" #include "hw/intc/arm_gic.h" #include "hw/net/cadence_gem.h" #include "hw/char/cadence_uart.h" diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c index c5a07cfe195..4667cb333ca 100644 --- a/hw/arm/xlnx-zcu102.c +++ b/hw/arm/xlnx-zcu102.c @@ -18,6 +18,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "hw/arm/xlnx-zynqmp.h" +#include "hw/arm/boot.h" #include "hw/boards.h" #include "qemu/error-report.h" #include "qemu/log.h" From patchwork Fri Oct 27 14:39:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13455651 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1qwO0w-00018m-BX for mharc-qemu-devel@gnu.org; Fri, 27 Oct 2023 10:40:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qwO0I-0007LW-Jv for qemu-devel@nongnu.org; Fri, 27 Oct 2023 10:40:04 -0400 Received: from mail-lf1-x134.google.com ([2a00:1450:4864:20::134]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qwO0E-00089q-Gz for qemu-devel@nongnu.org; Fri, 27 Oct 2023 10:40:02 -0400 Received: by mail-lf1-x134.google.com with SMTP id 2adb3069b0e04-5082a874098so948818e87.3 for ; Fri, 27 Oct 2023 07:39:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698417593; x=1699022393; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=zos/YT3JrRjqByZMNLI9yBeVZvxMZhI5gX49arsEv1w=; b=B1hmGppgQP++MJAF06zQ39dgzLrIEVj2ZK5bmCAe/WLIiA00f4fACnv0l0CBaIe5TI FNCWAn4/io0P43QswoylqKID4ClY3KGFRQAfKYAEBN4qiWPAcQFCcCKXqPf43TkKx6Kf 77djS2oib7liEIkp1zCzYkdKJincDvNFtZ+Wg8RL8IuFDdQVRRHuF8ZNv9IXWbrQCv2E WBnJ9lR1c4FXUyxpcqvWn9fPkklOTmxJGDEYCtxCoXLFHJq+LSFmry7jd+MwXhqgiHWh xSHUGfNj/wfmfUFFlUhIgw0Fg40k2biTooHDjt1Uq+k6gEjqnZJAvtinvTNB/7cXppxy uEGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698417593; x=1699022393; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zos/YT3JrRjqByZMNLI9yBeVZvxMZhI5gX49arsEv1w=; b=Al2vzDR/ckleabk+CoLbvYPrO2n2gA69io28K0/ozN5EIeN/lpeh6s6Vwk7i0uj2vT kJ6CHX+AMFW0rhMgWREcTLZYi/nKIUoNo3lWtZf/DpSHEdIzbGEGqX6zp8VJL17vDZMI CnLlgM4d+iRzR9sgwY5u2P59RDmtMrVeHF/C8eyivhZ9VqeR+PKMQUnJgSk+fFX5zMJy MsA84wWhN2WNV6Msfex4u8vAilcf/tfj3hvdoHmkD0LyjxCVZ90wN/6zKAAChGtdk3nf Ssnnr6Rpwcmf6SvsceEKsmN6wSRHvJTlJzS+hMhQYEv0Cyn2yKCNEAecaVq1V6qXPulS vopw== X-Gm-Message-State: AOJu0YyYB4yTGxeSxkvipNQM8pF3W0FN3/uSHwI2rBDdKyawT3xwPAaz //6IERhmh8x16HTlISjokhTgss4+qxZ79DvdO24= X-Google-Smtp-Source: AGHT+IF6ijecQTcAwkYNipV9DNsU+/5QyF3PTFb8vmlmNjiqNegBNGplPBcL35/WOzU8rR1cQmOGbQ== X-Received: by 2002:a05:6512:3b87:b0:508:2b98:d6ce with SMTP id g7-20020a0565123b8700b005082b98d6cemr1597359lfv.45.1698417593679; Fri, 27 Oct 2023 07:39:53 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e2-20020a5d5002000000b0031c6581d55esm1874123wrt.91.2023.10.27.07.39.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Oct 2023 07:39:53 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/41] hw/sd/pxa2xx: Realize sysbus device before accessing it Date: Fri, 27 Oct 2023 15:39:21 +0100 Message-Id: <20231027143942.3413881-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231027143942.3413881-1-peter.maydell@linaro.org> References: <20231027143942.3413881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::134; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x134.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Oct 2023 14:40:04 -0000 X-List-Received-Date: Fri, 27 Oct 2023 14:40:04 -0000 From: Philippe Mathieu-Daudé sysbus_mmio_map() and sysbus_connect_irq() should not be called on unrealized device. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth Reviewed-by: Richard Henderson Message-id: 20231020130331.50048-2-philmd@linaro.org Signed-off-by: Peter Maydell --- hw/sd/pxa2xx_mmci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/sd/pxa2xx_mmci.c b/hw/sd/pxa2xx_mmci.c index 124fbf8bbd4..9f7a880bac2 100644 --- a/hw/sd/pxa2xx_mmci.c +++ b/hw/sd/pxa2xx_mmci.c @@ -483,11 +483,11 @@ PXA2xxMMCIState *pxa2xx_mmci_init(MemoryRegion *sysmem, dev = qdev_new(TYPE_PXA2XX_MMCI); sbd = SYS_BUS_DEVICE(dev); + sysbus_realize_and_unref(sbd, &error_fatal); sysbus_mmio_map(sbd, 0, base); sysbus_connect_irq(sbd, 0, irq); qdev_connect_gpio_out_named(dev, "rx-dma", 0, rx_dma); qdev_connect_gpio_out_named(dev, "tx-dma", 0, tx_dma); - sysbus_realize_and_unref(sbd, &error_fatal); return PXA2XX_MMCI(dev); } From patchwork Fri Oct 27 14:39:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13455653 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1qwO0w-0001DG-V4 for mharc-qemu-devel@gnu.org; Fri, 27 Oct 2023 10:40:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qwO0G-0007JB-K0 for qemu-devel@nongnu.org; Fri, 27 Oct 2023 10:40:02 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qwO0E-00089z-HF for qemu-devel@nongnu.org; Fri, 27 Oct 2023 10:40:00 -0400 Received: by mail-wr1-x42d.google.com with SMTP id ffacd0b85a97d-32d80ae19f8so1451849f8f.2 for ; Fri, 27 Oct 2023 07:39:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698417594; x=1699022394; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=imigjsNGXBkOUVZzVBGOXn7dYRW7BzDepKRKFU1uSDY=; b=n4k0x6K/Qsc/48AL9nys34IEMEoZKvYPWt4VvOKd/Se7isB0TEIJCRecFQmYH13O7W ZyB26nKwzFJkzzUBntkQ7soV9rONMxFcMYHA/kcEpf1j2KxAWIH7cUYMk0LPQ6moayRd o4aHgo/wmNg2ePVDHGBzF0snvW/O7IbN8scnGKL/2WfRAyffvwJCumkqTITVu/BCPv4u dSV1AYJ80p7Rzqth+v2klBo5yXKtZTdyR1KVIhFJfAJdAtIHMp3TjYNYPkmRkaPwJ5vz AXmJJBql8tpYC+UIZVga/6Ko+jedPuJZtS3rbw74xuztBPqDpPCW82KJ5qXzkJqbaTVL vknA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698417594; x=1699022394; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=imigjsNGXBkOUVZzVBGOXn7dYRW7BzDepKRKFU1uSDY=; b=Df/3VIUYBIf+dGSer6RO3cZzP2xqP6sDMmsOEZZ8/4X7GUIl3A3d3QiEXVmxRG3q5R u4paFceH+bC0PzFxSIH3BmvLJvApJkCjDlLlG2nlmV6OCaCebCQ1gnNCy3hed8QS59Md bAKWhULEoeu8w5357yF5Hfog+kxGFdTuJc48HjjzzT2STOServ82bFKPMlUAC8hz8nmA nY6wbNuB/r6fmdTB59peg07+1Dizg1/73BKy3HCvCQNe5L4H1rs7l0bQVeAJ919be+GR f3GozrXOKkEyhaXcA7VE2jGRukjbt8bJxI1pO8o2t1JvuGTWXh9R5khki8pJ0jMxkw7v Du1Q== X-Gm-Message-State: AOJu0Yy+ESyyQI2vbOYyWPQapru5bfpPjha5m0xt307bG83v6U/Ozcyy Z75N003J8lE4IJf1tYgIkxtsGqGMVyqvBav1S/Q= X-Google-Smtp-Source: AGHT+IFvKAj0RQY8FAzGm/FJ5Ny9DZ+wGM1kAvn/PlKllLFk+lsP+uU0232GqQUDCHxwiR7eS2uJiA== X-Received: by 2002:adf:cf02:0:b0:32d:baf4:e56f with SMTP id o2-20020adfcf02000000b0032dbaf4e56fmr2413957wrj.12.1698417594137; Fri, 27 Oct 2023 07:39:54 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e2-20020a5d5002000000b0031c6581d55esm1874123wrt.91.2023.10.27.07.39.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Oct 2023 07:39:53 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/41] hw/sd/pxa2xx: Do not open-code sysbus_create_simple() Date: Fri, 27 Oct 2023 15:39:22 +0100 Message-Id: <20231027143942.3413881-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231027143942.3413881-1-peter.maydell@linaro.org> References: <20231027143942.3413881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Oct 2023 14:40:04 -0000 From: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth Reviewed-by: Richard Henderson Message-id: 20231020130331.50048-3-philmd@linaro.org Signed-off-by: Peter Maydell --- hw/sd/pxa2xx_mmci.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/hw/sd/pxa2xx_mmci.c b/hw/sd/pxa2xx_mmci.c index 9f7a880bac2..4749e935d8a 100644 --- a/hw/sd/pxa2xx_mmci.c +++ b/hw/sd/pxa2xx_mmci.c @@ -479,13 +479,8 @@ PXA2xxMMCIState *pxa2xx_mmci_init(MemoryRegion *sysmem, qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma) { DeviceState *dev; - SysBusDevice *sbd; - dev = qdev_new(TYPE_PXA2XX_MMCI); - sbd = SYS_BUS_DEVICE(dev); - sysbus_realize_and_unref(sbd, &error_fatal); - sysbus_mmio_map(sbd, 0, base); - sysbus_connect_irq(sbd, 0, irq); + dev = sysbus_create_simple(TYPE_PXA2XX_MMCI, base, irq); qdev_connect_gpio_out_named(dev, "rx-dma", 0, rx_dma); qdev_connect_gpio_out_named(dev, "tx-dma", 0, tx_dma); From patchwork Fri Oct 27 14:39:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13455634 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1qwO0O-0007OY-1v for mharc-qemu-devel@gnu.org; Fri, 27 Oct 2023 10:40:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qwO0F-0007IN-6F for qemu-devel@nongnu.org; Fri, 27 Oct 2023 10:39:59 -0400 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qwO0B-0008AF-Rh for qemu-devel@nongnu.org; Fri, 27 Oct 2023 10:39:58 -0400 Received: by mail-wr1-x42e.google.com with SMTP id ffacd0b85a97d-31fa15f4cc6so1488326f8f.2 for ; Fri, 27 Oct 2023 07:39:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698417594; x=1699022394; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=ooIxHMi95VXio8x/IzvnYifgViPdiDgXLTDa5pp5B1I=; b=M30YwRnTo5KnoQN8I1Lcsu/mEomArVNHgezrYAi1qhAkc4LFjCttqu+84Od0ScaKfa m7a6x7tiDkLfrTKPRoCGJIHA0M7tZcR6vorbMTroJl0U/JiENrLm/UokZ20coztDOeK/ Je7HKa3Wj1OkoAISBNZxz53AiKWXCbn0CmzQlU5uT402o/6q/toMLMxNw7tdnCoMwZ4S ZcgFoKu8ISne0lPVQAuvuokJyhVtpxpgpcdDRn28nSTw29pq1Z2geDw04AKGnEVy9H43 usEbhs4M8fw6lz1b5fP9C6nkwwdE3AcdZ5zTehweCXu/4JarX7oyTYkaLL9S17oh5ruM rTeg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698417594; x=1699022394; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ooIxHMi95VXio8x/IzvnYifgViPdiDgXLTDa5pp5B1I=; b=Lss7xMyiNtM7okC4NOQq5ZNuJ82jAYzlxMoFS6Cteqsj8jjNch7Hp5bAWSZYTRyD/O vdHLUWnt54z4mjca5QJEYNAtw8I+zUd7QwNuh+++NnZHu0k4F+ZVx4VAjHAQQpgRdfkD wb+OgIMPEO6lrJshxpTxyxOPsreN+uHm4T0jrQ0grzONKbmEVN683cdlWYhULNbscVcE QlN0l40e1tKFl4EO9YyEANudss5sWaVXAngVTQD0p2ugla4O3C2FhlEyKEellFYwl2PM cSrn3O8tQAEhCXK+9DvVelI3dVq/TQ2X2UCKCzLARd1bdF/noSzpd7nP0vXP47l+gaw/ S57g== X-Gm-Message-State: AOJu0Yywh963QoMD45rCErWv4NWxUKAeYq1k9E2dEVNhdAs4dma3dXpA mQbQpgJZMmR8xvVf8APJkzSb80W8x0yHXl5MQJo= X-Google-Smtp-Source: AGHT+IGkKBe+K8xV/B9dRK2rSSObAjdq6qPVY+fSELwRLTHV2rRpsXv+qcTW5l68esGseWG/klUlhA== X-Received: by 2002:adf:ed84:0:b0:32d:a2cd:ad0c with SMTP id c4-20020adfed84000000b0032da2cdad0cmr2128329wro.50.1698417594563; Fri, 27 Oct 2023 07:39:54 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e2-20020a5d5002000000b0031c6581d55esm1874123wrt.91.2023.10.27.07.39.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Oct 2023 07:39:54 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/41] hw/pcmcia/pxa2xx: Realize sysbus device before accessing it Date: Fri, 27 Oct 2023 15:39:23 +0100 Message-Id: <20231027143942.3413881-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231027143942.3413881-1-peter.maydell@linaro.org> References: <20231027143942.3413881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Oct 2023 14:39:59 -0000 From: Philippe Mathieu-Daudé sysbus_mmio_map() should not be called on unrealized device. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth Reviewed-by: Richard Henderson Message-id: 20231020130331.50048-4-philmd@linaro.org Signed-off-by: Peter Maydell --- hw/pcmcia/pxa2xx.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/hw/pcmcia/pxa2xx.c b/hw/pcmcia/pxa2xx.c index fcca7e571b2..e7264feb455 100644 --- a/hw/pcmcia/pxa2xx.c +++ b/hw/pcmcia/pxa2xx.c @@ -142,15 +142,12 @@ PXA2xxPCMCIAState *pxa2xx_pcmcia_init(MemoryRegion *sysmem, hwaddr base) { DeviceState *dev; - PXA2xxPCMCIAState *s; dev = qdev_new(TYPE_PXA2XX_PCMCIA); - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); - s = PXA2XX_PCMCIA(dev); - sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); - return s; + return PXA2XX_PCMCIA(dev); } static void pxa2xx_pcmcia_initfn(Object *obj) From patchwork Fri Oct 27 14:39:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13455638 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1qwO0n-0008Hc-GK for mharc-qemu-devel@gnu.org; Fri, 27 Oct 2023 10:40:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qwO0J-0007Lh-PE for qemu-devel@nongnu.org; Fri, 27 Oct 2023 10:40:04 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qwO0E-0008AP-HO for qemu-devel@nongnu.org; Fri, 27 Oct 2023 10:40:03 -0400 Received: by mail-wr1-x436.google.com with SMTP id ffacd0b85a97d-32d9d8284abso1389366f8f.3 for ; Fri, 27 Oct 2023 07:39:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698417595; x=1699022395; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=7L+ZM2Ew3INynFGy53+roTgbFE4u6NxZeR9zzUy5oKQ=; b=lIzPy6tNEp7MFZB7PUr3MyJtYkQppuN/Bckrdql5Ln8lTxp/vpuV32+MY0B9LRwRxS PfZggdqShXiue/axLzq+kUXXT8T5YKertTXGskebjEOCTEF5fgsSRFe0szN3sDhHVBqR ehjpJaz3cvfI4bbwAYE79xkSG1D2PbBC64KG94cmReReTtziR4fnYxgouA4XoRiLKE2s epSRYYgg2HAW/Qxi7fm5URAC/pNH4BsCtgdDIMDPaaB3mJq4cRKbtcdEnkXPANM72lXi 7SOgUdmXzrc4vbcTx5z3oFdJZWa6c3CwRmm0UlFzRR5xNnt4NLEuHb8suQKbT+sP3ivw HYNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698417595; x=1699022395; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7L+ZM2Ew3INynFGy53+roTgbFE4u6NxZeR9zzUy5oKQ=; b=ocnq0BNfdJfrveJV/4oi5PsWDrPfN7WfSVinYTuADrxXtZtCfYf+qCdW7mqoyPRl7I I1F0ldwoT6Pb9lSSJuOjIS5cJ2uft1diBX4j9vrgNQxmo1db0CUTGoKcEWtawzXFUu8C eGcYWbxg2Zxkre7OIh3xh5IenMTo/zRAJBbBEqzJM5I0A6M+439jDVTfY3sFMBQQbg0F 6jyHALF0V+MYye5JaujnpLaw0iQHGsJHwy2oyAn6p9zBbbVmNBsbDRdb9XCQVU+GeuOx ZEbhtvcmsoM51OCNCpJB/e6sHPMateETatieG7Cv+MPafoYKaTcNVVtB4CsifrIkxQ4f 3yhA== X-Gm-Message-State: AOJu0Yx8RIVuy9WvZOGIoDgFLWfzybL42d8KNGVNaYNwJHDcabVosd9I y8EDgeORtqMmTUhJg2btFklnSkvVUSXEJTUj+cU= X-Google-Smtp-Source: AGHT+IHbVyX3ChRAXk47KcG161lh8lAJJreK7bcS/ti/zKWTYqE/DOpBq8Xx51y/nUhzp6HNIR1g/A== X-Received: by 2002:a5d:64a4:0:b0:320:bae:2dfd with SMTP id m4-20020a5d64a4000000b003200bae2dfdmr2907123wrp.5.1698417595037; Fri, 27 Oct 2023 07:39:55 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e2-20020a5d5002000000b0031c6581d55esm1874123wrt.91.2023.10.27.07.39.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Oct 2023 07:39:54 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/41] hw/pcmcia/pxa2xx: Do not open-code sysbus_create_simple() Date: Fri, 27 Oct 2023 15:39:24 +0100 Message-Id: <20231027143942.3413881-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231027143942.3413881-1-peter.maydell@linaro.org> References: <20231027143942.3413881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Oct 2023 14:40:04 -0000 From: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20231020130331.50048-5-philmd@linaro.org Signed-off-by: Peter Maydell --- hw/pcmcia/pxa2xx.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/hw/pcmcia/pxa2xx.c b/hw/pcmcia/pxa2xx.c index e7264feb455..3d512a292c7 100644 --- a/hw/pcmcia/pxa2xx.c +++ b/hw/pcmcia/pxa2xx.c @@ -143,9 +143,7 @@ PXA2xxPCMCIAState *pxa2xx_pcmcia_init(MemoryRegion *sysmem, { DeviceState *dev; - dev = qdev_new(TYPE_PXA2XX_PCMCIA); - sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); + dev = sysbus_create_simple(TYPE_PXA2XX_PCMCIA, base, NULL); return PXA2XX_PCMCIA(dev); } From patchwork Fri Oct 27 14:39:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13455635 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1qwO0W-0007UD-Di for mharc-qemu-devel@gnu.org; Fri, 27 Oct 2023 10:40:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qwO0I-0007LN-5V for qemu-devel@nongnu.org; Fri, 27 Oct 2023 10:40:02 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qwO0D-0008Ad-5G for qemu-devel@nongnu.org; Fri, 27 Oct 2023 10:40:01 -0400 Received: by mail-wr1-x432.google.com with SMTP id ffacd0b85a97d-32d9effe314so1475451f8f.3 for ; Fri, 27 Oct 2023 07:39:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698417595; x=1699022395; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=UAIcFE1AWWGCfMMgeYKVUiHoLIBp/JRpwlxRycBVAB0=; b=JjVkiWpysoVI1kCaHOCrveKYkCtVrxm27BY1NX+iqTraD/RH3nASBWVGDXLJGbM3rh 0A+SOOykdxvDgVIyr/l7RuB0x0gv2D4aVEP70+AjjppAD4pK52DwOu6NMiEr/GONzXpt kNa0o4nPG4UY9i0SJFqvhNP8Le+bLzhgQFYKvui8j0DHr+XyfLKQsHljg8Z1B2oivTev pQnxumcP6ZZe61EForscSGsFaAHojA+OJaGsfTTdvinlEsJV8ehdG095SdxnFW/uhS45 2m+rIRoAIqmu5evo33iTqtaAXsmZcN8xMcclRPdk5ahsIxQtYe8rzs/pLBo8jTicjVva /TRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698417595; x=1699022395; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UAIcFE1AWWGCfMMgeYKVUiHoLIBp/JRpwlxRycBVAB0=; b=Htsl5R64GEFJ3BQ19/iuvc6wXrkH1N7vrHsqNLkvJhinzKQ77F9ZKWtzu6qTackDqP BsDr+XFnz4YfmOCNiySHST2xGuEu9yg9uenEMzWrPrPLwDSlaMx93zWsvcGUYkdlURtV agWjrZqJHvW/Q6nSTHcIRWltwCOTZWskv19btJ7+a4OCgdOq8X/yhCQo0nbhU0wkSlYc 875dBHVggKFasjyVaY9NxQCM5fLhj8TtcSgCwLbWwjM8ICv8DWO23tu0eK8SDMlOReIq OeQ6+xx82zZ1QWgw52ZedrvLPf2h39yttg5Ul859rFKw401/3/0IAQ9c1kf5YLPCPrjR 7YHQ== X-Gm-Message-State: AOJu0YxToLJ+Du3HoYXDhPr0pVLRkeNAXNMl+e0WeaCws+AnjmLTyy81 6ugZbf2I/7tJrGN+T+6TDk/uXjKB/wJWua1VJ6E= X-Google-Smtp-Source: AGHT+IEONGXZ8oj3l/2uafkx1pkEa/s+BzNEQpLXSJeBl0D8RVD8XyXURw5C/TXiG8Bkp0CUOeYTLA== X-Received: by 2002:adf:f645:0:b0:32d:84c7:2f56 with SMTP id x5-20020adff645000000b0032d84c72f56mr1958002wrp.21.1698417595670; Fri, 27 Oct 2023 07:39:55 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e2-20020a5d5002000000b0031c6581d55esm1874123wrt.91.2023.10.27.07.39.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Oct 2023 07:39:55 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 24/41] hw/pcmcia/pxa2xx: Inline pxa2xx_pcmcia_init() Date: Fri, 27 Oct 2023 15:39:25 +0100 Message-Id: <20231027143942.3413881-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231027143942.3413881-1-peter.maydell@linaro.org> References: <20231027143942.3413881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Oct 2023 14:40:04 -0000 From: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20231020130331.50048-6-philmd@linaro.org Signed-off-by: Peter Maydell --- include/hw/arm/pxa.h | 2 -- hw/arm/pxa2xx.c | 12 ++++++++---- hw/pcmcia/pxa2xx.c | 10 ---------- 3 files changed, 8 insertions(+), 16 deletions(-) diff --git a/include/hw/arm/pxa.h b/include/hw/arm/pxa.h index 54eb895e42a..4c6caee1134 100644 --- a/include/hw/arm/pxa.h +++ b/include/hw/arm/pxa.h @@ -100,8 +100,6 @@ void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly, #define TYPE_PXA2XX_PCMCIA "pxa2xx-pcmcia" OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxPCMCIAState, PXA2XX_PCMCIA) -PXA2xxPCMCIAState *pxa2xx_pcmcia_init(MemoryRegion *sysmem, - hwaddr base); int pxa2xx_pcmcia_attach(void *opaque, PCMCIACardState *card); int pxa2xx_pcmcia_detach(void *opaque); void pxa2xx_pcmcia_set_irq_cb(void *opaque, qemu_irq irq, qemu_irq cd_irq); diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c index 07d5dd8691f..601ddd87666 100644 --- a/hw/arm/pxa2xx.c +++ b/hw/arm/pxa2xx.c @@ -2205,8 +2205,10 @@ PXA2xxState *pxa270_init(unsigned int sdram_size, const char *cpu_type) sysbus_create_simple("sysbus-ohci", 0x4c000000, qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1)); - s->pcmcia[0] = pxa2xx_pcmcia_init(address_space, 0x20000000); - s->pcmcia[1] = pxa2xx_pcmcia_init(address_space, 0x30000000); + s->pcmcia[0] = PXA2XX_PCMCIA(sysbus_create_simple(TYPE_PXA2XX_PCMCIA, + 0x20000000, NULL)); + s->pcmcia[1] = PXA2XX_PCMCIA(sysbus_create_simple(TYPE_PXA2XX_PCMCIA, + 0x30000000, NULL)); sysbus_create_simple(TYPE_PXA2XX_RTC, 0x40900000, qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM)); @@ -2338,8 +2340,10 @@ PXA2xxState *pxa255_init(unsigned int sdram_size) s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi"); } - s->pcmcia[0] = pxa2xx_pcmcia_init(address_space, 0x20000000); - s->pcmcia[1] = pxa2xx_pcmcia_init(address_space, 0x30000000); + s->pcmcia[0] = PXA2XX_PCMCIA(sysbus_create_simple(TYPE_PXA2XX_PCMCIA, + 0x20000000, NULL)); + s->pcmcia[1] = PXA2XX_PCMCIA(sysbus_create_simple(TYPE_PXA2XX_PCMCIA, + 0x30000000, NULL)); sysbus_create_simple(TYPE_PXA2XX_RTC, 0x40900000, qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM)); diff --git a/hw/pcmcia/pxa2xx.c b/hw/pcmcia/pxa2xx.c index 3d512a292c7..e3111fdf1a1 100644 --- a/hw/pcmcia/pxa2xx.c +++ b/hw/pcmcia/pxa2xx.c @@ -138,16 +138,6 @@ static void pxa2xx_pcmcia_set_irq(void *opaque, int line, int level) qemu_set_irq(s->irq, level); } -PXA2xxPCMCIAState *pxa2xx_pcmcia_init(MemoryRegion *sysmem, - hwaddr base) -{ - DeviceState *dev; - - dev = sysbus_create_simple(TYPE_PXA2XX_PCMCIA, base, NULL); - - return PXA2XX_PCMCIA(dev); -} - static void pxa2xx_pcmcia_initfn(Object *obj) { SysBusDevice *sbd = SYS_BUS_DEVICE(obj); From patchwork Fri Oct 27 14:39:26 2023 Content-Type: text/plain; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e2-20020a5d5002000000b0031c6581d55esm1874123wrt.91.2023.10.27.07.39.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Oct 2023 07:39:56 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 25/41] hw/intc/pxa2xx: Convert to Resettable interface Date: Fri, 27 Oct 2023 15:39:26 +0100 Message-Id: <20231027143942.3413881-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231027143942.3413881-1-peter.maydell@linaro.org> References: <20231027143942.3413881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::22b; envelope-from=peter.maydell@linaro.org; helo=mail-lj1-x22b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Oct 2023 14:40:07 -0000 X-List-Received-Date: Fri, 27 Oct 2023 14:40:07 -0000 From: Philippe Mathieu-Daudé Factor reset code out of the DeviceRealize() handler. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Thomas Huth Message-id: 20231020130331.50048-7-philmd@linaro.org Signed-off-by: Peter Maydell --- hw/arm/pxa2xx_pic.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/hw/arm/pxa2xx_pic.c b/hw/arm/pxa2xx_pic.c index 47132ab982b..2eb869a605a 100644 --- a/hw/arm/pxa2xx_pic.c +++ b/hw/arm/pxa2xx_pic.c @@ -271,12 +271,9 @@ static int pxa2xx_pic_post_load(void *opaque, int version_id) return 0; } -DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu) +static void pxa2xx_pic_reset_hold(Object *obj) { - DeviceState *dev = qdev_new(TYPE_PXA2XX_PIC); - PXA2xxPICState *s = PXA2XX_PIC(dev); - - s->cpu = cpu; + PXA2xxPICState *s = PXA2XX_PIC(obj); s->int_pending[0] = 0; s->int_pending[1] = 0; @@ -284,6 +281,14 @@ DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu) s->int_enabled[1] = 0; s->is_fiq[0] = 0; s->is_fiq[1] = 0; +} + +DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu) +{ + DeviceState *dev = qdev_new(TYPE_PXA2XX_PIC); + PXA2xxPICState *s = PXA2XX_PIC(dev); + + s->cpu = cpu; sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); @@ -319,9 +324,11 @@ static const VMStateDescription vmstate_pxa2xx_pic_regs = { static void pxa2xx_pic_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); + ResettableClass *rc = RESETTABLE_CLASS(klass); dc->desc = "PXA2xx PIC"; dc->vmsd = &vmstate_pxa2xx_pic_regs; + rc->phases.hold = pxa2xx_pic_reset_hold; } static const TypeInfo pxa2xx_pic_info = { From patchwork Fri Oct 27 14:39:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13455641 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1qwO0o-0008U2-Qu for mharc-qemu-devel@gnu.org; Fri, 27 Oct 2023 10:40:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qwO0L-0007Nc-Th for qemu-devel@nongnu.org; Fri, 27 Oct 2023 10:40:06 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qwO0E-0008B5-U1 for qemu-devel@nongnu.org; Fri, 27 Oct 2023 10:40:05 -0400 Received: by mail-wr1-x42b.google.com with SMTP id ffacd0b85a97d-32ddfb38c02so1494552f8f.3 for ; Fri, 27 Oct 2023 07:39:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698417597; x=1699022397; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=md/8boBzovKzRvF7b8BqZz7bG8/Ggz8MPHAVAdGqfbE=; b=QexAmBAZlRbpQQjWTTt2OBdf/ENwiFhEwYbiSVDRpUAVVOHshxik7tvwaZuehWm67h otiEzVwUwYvwhay3b5YJsdDs+pG94ypu5XaJb2YczFs6OBif3y8Lr9QAaurBzVj473SJ nn5M8spE5GdyFvtm62j8hCOeEZETMA3cWFt47JVIEQbGkC8hY+ulFUDdm3u9Fg9j+Tug 0IRg6X0dwQv3pMxg9OOvo/IQUR9hUVsp4ijbgt6dyfHTHM6o3GL4fUUAWwdsEARLfKNi CnIM39yPfL9AAoU3KZRL1x5ZhYv/kKj/7Mse+RPzUvc5c/DvTKT3+zVkfX4ROlVnPvlX veRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698417597; x=1699022397; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=md/8boBzovKzRvF7b8BqZz7bG8/Ggz8MPHAVAdGqfbE=; b=GWSo4u1Z+fjQzoHiM5dUjzw9f3K2B8mp/4012THXTCEZ4aohKP7e0dSjRmLjF546U7 IKaIJAF93m6n2WaGUmmAO4qaSh+wylud7AbVL+5BBvXUi1ZscKiXf2CVhwoEA5jGUf8N Jl2RwIHXePs3O0CB1sx2yxyQ6jvHg5WEtOKy4dAj+BBM3t4uPyglpbd24kpWc/9C5bLe +fmS9CN4GPCcyIqZ9Sl6qMswCXxvnHUD1cLYtxzbcQxNvS/CPVz3LceP0JGGndTogwSf eO8PUFWiGjL0wk+UhtaLbnHc/kataIQqmizalK5qsPCFsqmKBUzo6Jx8cBeBN76yNOJS hyug== X-Gm-Message-State: AOJu0YyeTD0rV49i/OHfxSBQVq+wKv/wVio+uj9uSrZCZat14SeH5v4h KHJHX9VD7nWdKW4pLBCQT624iGvJxQbxzrks7ME= X-Google-Smtp-Source: AGHT+IECC4DY/thr2qUjOLXcgRCqxdszEjDqXwes8Lyzck4ThCVRSKXc6E2wQcnwHXe3xEii1yll8w== X-Received: by 2002:a5d:6d81:0:b0:32d:14a4:ab3 with SMTP id l1-20020a5d6d81000000b0032d14a40ab3mr2802062wrs.24.1698417596868; Fri, 27 Oct 2023 07:39:56 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e2-20020a5d5002000000b0031c6581d55esm1874123wrt.91.2023.10.27.07.39.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Oct 2023 07:39:56 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 26/41] hw/intc/pxa2xx: Pass CPU reference using QOM link property Date: Fri, 27 Oct 2023 15:39:27 +0100 Message-Id: <20231027143942.3413881-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231027143942.3413881-1-peter.maydell@linaro.org> References: <20231027143942.3413881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Oct 2023 14:40:07 -0000 From: Philippe Mathieu-Daudé QOM objects shouldn't access each other internals fields except using the QOM API. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Thomas Huth Message-id: 20231020130331.50048-8-philmd@linaro.org Signed-off-by: Peter Maydell --- hw/arm/pxa2xx_pic.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/hw/arm/pxa2xx_pic.c b/hw/arm/pxa2xx_pic.c index 2eb869a605a..7e180635c22 100644 --- a/hw/arm/pxa2xx_pic.c +++ b/hw/arm/pxa2xx_pic.c @@ -15,6 +15,7 @@ #include "cpu.h" #include "hw/arm/pxa.h" #include "hw/sysbus.h" +#include "hw/qdev-properties.h" #include "migration/vmstate.h" #include "qom/object.h" #include "target/arm/cpregs.h" @@ -288,7 +289,8 @@ DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu) DeviceState *dev = qdev_new(TYPE_PXA2XX_PIC); PXA2xxPICState *s = PXA2XX_PIC(dev); - s->cpu = cpu; + object_property_set_link(OBJECT(dev), "arm-cpu", + OBJECT(cpu), &error_abort); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); @@ -321,11 +323,18 @@ static const VMStateDescription vmstate_pxa2xx_pic_regs = { }, }; +static Property pxa2xx_pic_properties[] = { + DEFINE_PROP_LINK("arm-cpu", PXA2xxPICState, cpu, + TYPE_ARM_CPU, ARMCPU *), + DEFINE_PROP_END_OF_LIST(), +}; + static void pxa2xx_pic_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); ResettableClass *rc = RESETTABLE_CLASS(klass); + device_class_set_props(dc, pxa2xx_pic_properties); dc->desc = "PXA2xx PIC"; dc->vmsd = &vmstate_pxa2xx_pic_regs; rc->phases.hold = pxa2xx_pic_reset_hold; From patchwork Fri Oct 27 14:39:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13455648 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1qwO0v-0000yW-3J for mharc-qemu-devel@gnu.org; Fri, 27 Oct 2023 10:40:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qwO0I-0007LV-Jw for qemu-devel@nongnu.org; Fri, 27 Oct 2023 10:40:04 -0400 Received: from mail-lj1-x22f.google.com ([2a00:1450:4864:20::22f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qwO0F-0008BB-2f for qemu-devel@nongnu.org; Fri, 27 Oct 2023 10:40:02 -0400 Received: by mail-lj1-x22f.google.com with SMTP id 38308e7fff4ca-2c50ec238aeso30426801fa.0 for ; Fri, 27 Oct 2023 07:39:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698417597; x=1699022397; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=my7OnQbRaZ6vmyGLjZG5PCWu8hQo8B8j0gxAVZuRna4=; b=ysaDrItfu3Qrmn7P71BGQAXv2R9aAyqI8CNyoJ3NWBCVBp6ez7iqMGJYRv0bga2Thz a8/Ule2h9kKHzIajU9G1ee+lh2/3BIYtg/67IFwdfenyXMv5OV3uCbSU5PO0lZ5uZT3c ZS0mFE+iLBbLttqt3CFqPp7/jxhckXCdadUKe+Bjbtvg94pHfGcyQj+RMQENIj2EaOaz Id0p8rAAqTWPP+gWFMySLY4ZxjRN8y7NeSClK1BWXnLOg8RcIH7qmsWqsY/bxvlqXO2I 2F3IA3WgdemrnZL97H2Ys4ltyFmqcN/Un2aHKIw8WWnalZTxAOQTuOscx0kJwkRk79/h CfoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698417597; x=1699022397; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=my7OnQbRaZ6vmyGLjZG5PCWu8hQo8B8j0gxAVZuRna4=; b=txoNj1H9KjbYQGmldZCQ0naH9OSWhpjZSZGULtNcMZknVhtjPy6G6uAx6mfJcyRM60 TdRKhreMCTGsj+3o64Bf+uPERkoBoviVRc/SYTXQvK6G8x1Ot0dgCWwwkzfivf0wQPw3 aKebcfpc19m+nFtBnFdpdiyBcEcYZWfazd85wgUh1akRLBG0iFi4CbuCLbyGyQYpKcBD QhRFemaRdatLnP+2gXM6OH2bMXzDF959rDHgDjHfbbty6yPs7zW7EK8prrMxwz8DeR4k E99+ubnkfRkqXBGx+v9mOTo6vALSKK2zvZXmJ0QHL3zQ5zXpSWEeUEOisdpIx5oByNjq HuyQ== X-Gm-Message-State: AOJu0YyJ1h+WZ16ZkcHRSIxrrrLbxWVE99xosYOgfZzyOErUN/+JEnB2 jKQwPFCWebaHwQgsOYLfUeTUFwwhBrFjJRgsOzA= X-Google-Smtp-Source: AGHT+IGh0c4sw1HQJFfpH1Z/FQY7jod17HzV0NbU1j1+0ZmCqiaataY+yxRev3UKYqvOZxOkhxB+uQ== X-Received: by 2002:a2e:958e:0:b0:2c5:115c:2d33 with SMTP id w14-20020a2e958e000000b002c5115c2d33mr2444580ljh.3.1698417597289; Fri, 27 Oct 2023 07:39:57 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e2-20020a5d5002000000b0031c6581d55esm1874123wrt.91.2023.10.27.07.39.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Oct 2023 07:39:57 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 27/41] hw/intc/pxa2xx: Factor pxa2xx_pic_realize() out of pxa2xx_pic_init() Date: Fri, 27 Oct 2023 15:39:28 +0100 Message-Id: <20231027143942.3413881-28-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231027143942.3413881-1-peter.maydell@linaro.org> References: <20231027143942.3413881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::22f; envelope-from=peter.maydell@linaro.org; helo=mail-lj1-x22f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Oct 2023 14:40:04 -0000 X-List-Received-Date: Fri, 27 Oct 2023 14:40:04 -0000 From: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Thomas Huth Message-id: 20231020130331.50048-9-philmd@linaro.org Signed-off-by: Peter Maydell --- hw/arm/pxa2xx_pic.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/hw/arm/pxa2xx_pic.c b/hw/arm/pxa2xx_pic.c index 7e180635c22..1373a0d275f 100644 --- a/hw/arm/pxa2xx_pic.c +++ b/hw/arm/pxa2xx_pic.c @@ -287,12 +287,18 @@ static void pxa2xx_pic_reset_hold(Object *obj) DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu) { DeviceState *dev = qdev_new(TYPE_PXA2XX_PIC); - PXA2xxPICState *s = PXA2XX_PIC(dev); object_property_set_link(OBJECT(dev), "arm-cpu", OBJECT(cpu), &error_abort); - sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); + + return dev; +} + +static void pxa2xx_pic_realize(DeviceState *dev, Error **errp) +{ + PXA2xxPICState *s = PXA2XX_PIC(dev); qdev_init_gpio_in(dev, pxa2xx_pic_set_irq, PXA2XX_PIC_SRCS); @@ -300,12 +306,9 @@ DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu) memory_region_init_io(&s->iomem, OBJECT(s), &pxa2xx_pic_ops, s, "pxa2xx-pic", 0x00100000); sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); /* Enable IC coprocessor access. */ - define_arm_cp_regs_with_opaque(cpu, pxa_pic_cp_reginfo, s); - - return dev; + define_arm_cp_regs_with_opaque(s->cpu, pxa_pic_cp_reginfo, s); } static const VMStateDescription vmstate_pxa2xx_pic_regs = { @@ -335,6 +338,7 @@ static void pxa2xx_pic_class_init(ObjectClass *klass, void *data) ResettableClass *rc = RESETTABLE_CLASS(klass); device_class_set_props(dc, pxa2xx_pic_properties); + dc->realize = pxa2xx_pic_realize; dc->desc = "PXA2xx PIC"; dc->vmsd = &vmstate_pxa2xx_pic_regs; rc->phases.hold = pxa2xx_pic_reset_hold; From patchwork Fri Oct 27 14:39:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13455650 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1qwO0w-00016D-2h for mharc-qemu-devel@gnu.org; Fri, 27 Oct 2023 10:40:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qwO0J-0007Li-RV for qemu-devel@nongnu.org; Fri, 27 Oct 2023 10:40:04 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qwO0G-0008BE-Bo for qemu-devel@nongnu.org; Fri, 27 Oct 2023 10:40:03 -0400 Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-32dd70c5401so1403892f8f.0 for ; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e2-20020a5d5002000000b0031c6581d55esm1874123wrt.91.2023.10.27.07.39.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Oct 2023 07:39:57 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 28/41] hw/arm/pxa2xx: Realize PXA2XX_I2C device before accessing it Date: Fri, 27 Oct 2023 15:39:29 +0100 Message-Id: <20231027143942.3413881-29-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231027143942.3413881-1-peter.maydell@linaro.org> References: <20231027143942.3413881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Oct 2023 14:40:04 -0000 From: Philippe Mathieu-Daudé qbus_new(), called in i2c_init_bus(), should not be called on unrealized device. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Thomas Huth Message-id: 20231020130331.50048-10-philmd@linaro.org Signed-off-by: Peter Maydell --- hw/arm/pxa2xx.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c index 601ddd87666..f0bf407e664 100644 --- a/hw/arm/pxa2xx.c +++ b/hw/arm/pxa2xx.c @@ -1513,14 +1513,15 @@ PXA2xxI2CState *pxa2xx_i2c_init(hwaddr base, qdev_prop_set_uint32(dev, "size", region_size + 1); qdev_prop_set_uint32(dev, "offset", base & region_size); + /* FIXME: Should the slave device really be on a separate bus? */ + i2cbus = i2c_init_bus(dev, "dummy"); + i2c_dev = SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(i2c_dev, &error_fatal); sysbus_mmio_map(i2c_dev, 0, base & ~region_size); sysbus_connect_irq(i2c_dev, 0, irq); s = PXA2XX_I2C(i2c_dev); - /* FIXME: Should the slave device really be on a separate bus? */ - i2cbus = i2c_init_bus(dev, "dummy"); s->slave = PXA2XX_I2C_SLAVE(i2c_slave_create_simple(i2cbus, TYPE_PXA2XX_I2C_SLAVE, 0)); From patchwork Fri Oct 27 14:39:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13455639 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1qwO0n-0008O3-Vs for mharc-qemu-devel@gnu.org; Fri, 27 Oct 2023 10:40:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qwO0L-0007Nd-UN for qemu-devel@nongnu.org; Fri, 27 Oct 2023 10:40:06 -0400 Received: from mail-lj1-x22d.google.com ([2a00:1450:4864:20::22d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qwO0G-0008BN-CP for qemu-devel@nongnu.org; Fri, 27 Oct 2023 10:40:05 -0400 Received: by mail-lj1-x22d.google.com with SMTP id 38308e7fff4ca-2c50906f941so32202241fa.2 for ; Fri, 27 Oct 2023 07:39:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698417598; x=1699022398; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=1p9KVKDoDB453y9P2t06KEHsQm3HAkllfoNShv9eI/E=; b=ua2ibiCrlXYt1g9DGNEAZqgV69UukvbYIJc5fYIOvYG9U9U1+neMhsUr4ZxlGtjsZT veEHFYIVbD7v5GIcWP9BeRQJF7/bxO3m34X4o1RteZpTYVXcX9ZY6LPGjRz5Vn4AMsOH N+Dj1gH6o90+YjFzUyqonHYW+byTC1Cu3U+JXAY4KRuv7Tbp0wBWY+NRzNVAGKzP3ZFV WUjztUooWTVLNkE7l9+3n9AXoH1S2U0lSuDG10mzCMmp24ngSx7/pLaJEp5Hct+FjHtQ ltpTMfMh2RiZ3DOLuOXjlD08l35v1aUENAP28qYUJMikfjm0FtcGdBwiTVyr3mKMmfen aDjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698417598; x=1699022398; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1p9KVKDoDB453y9P2t06KEHsQm3HAkllfoNShv9eI/E=; b=FYUAdVycT0ubAniH7rb89/nUxcwzI5flMTbSAzUi0msCGHAsO9GwzrpiZk7SD2n5kB YIkXUsDPubWPOOMe20KBIRQI4YoztEeycgga7rdjIaZIE+z6NoCIHS5QI+vy97vLyaQj nGOprjxjCbk37wHBbP5xAlpwpwvIqaW9x4H7geQDarIvQXAz0340gFKSqHp8/3e4MrFy K5P6Bh1wWr5lzVXtr97XHdNhG3rCopeLmMePjqQggn21fUFZBkYDO+cyIL/iP7wGUneB 48xYarINUiGdFCJnUkf386FDvS9e2eFkUYQx1Xtmqc6ZndQJNYzRvVjsmdYYdlPLrKHt c8YQ== X-Gm-Message-State: AOJu0YysjB5Dy4fnisUZ/qL42FwRsilTyDMdHW7GKLozdK1IotngEOGq EXbsesDP8P4YX7ytd7Io89Cx20jxn6CCSgutWhk= X-Google-Smtp-Source: AGHT+IF4AVepCoQ/nlYOUP1tHs8mnKD2MX25PhfLVTHB/b7w7NQOQfzXaHNA8oeXNh8L1uDOakgQnw== X-Received: by 2002:ac2:4e65:0:b0:500:7efe:313c with SMTP id y5-20020ac24e65000000b005007efe313cmr1898119lfs.24.1698417598418; Fri, 27 Oct 2023 07:39:58 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e2-20020a5d5002000000b0031c6581d55esm1874123wrt.91.2023.10.27.07.39.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Oct 2023 07:39:58 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 29/41] hw/arm: Avoid using 'first_cpu' when first ARM CPU is reachable Date: Fri, 27 Oct 2023 15:39:30 +0100 Message-Id: <20231027143942.3413881-30-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231027143942.3413881-1-peter.maydell@linaro.org> References: <20231027143942.3413881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::22d; envelope-from=peter.maydell@linaro.org; helo=mail-lj1-x22d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Oct 2023 14:40:07 -0000 From: Philippe Mathieu-Daudé Prefer using a well known local first CPU rather than a global one. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20231025065909.57344-1-philmd@linaro.org Signed-off-by: Peter Maydell --- hw/arm/bananapi_m2u.c | 2 +- hw/arm/exynos4_boards.c | 7 ++++--- hw/arm/orangepi.c | 2 +- hw/arm/realview.c | 2 +- hw/arm/xilinx_zynq.c | 2 +- 5 files changed, 8 insertions(+), 7 deletions(-) diff --git a/hw/arm/bananapi_m2u.c b/hw/arm/bananapi_m2u.c index a7c7a9f96d7..8f24b18d8ca 100644 --- a/hw/arm/bananapi_m2u.c +++ b/hw/arm/bananapi_m2u.c @@ -128,7 +128,7 @@ static void bpim2u_init(MachineState *machine) bpim2u_binfo.loader_start = r40->memmap[AW_R40_DEV_SDRAM]; bpim2u_binfo.ram_size = machine->ram_size; bpim2u_binfo.psci_conduit = QEMU_PSCI_CONDUIT_SMC; - arm_load_kernel(ARM_CPU(first_cpu), machine, &bpim2u_binfo); + arm_load_kernel(&r40->cpus[0], machine, &bpim2u_binfo); } static void bpim2u_machine_init(MachineClass *mc) diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c index ef5bcbc212c..b0e13eb4f00 100644 --- a/hw/arm/exynos4_boards.c +++ b/hw/arm/exynos4_boards.c @@ -134,9 +134,10 @@ exynos4_boards_init_common(MachineState *machine, static void nuri_init(MachineState *machine) { - exynos4_boards_init_common(machine, EXYNOS4_BOARD_NURI); + Exynos4BoardState *s = exynos4_boards_init_common(machine, + EXYNOS4_BOARD_NURI); - arm_load_kernel(ARM_CPU(first_cpu), machine, &exynos4_board_binfo); + arm_load_kernel(s->soc.cpu[0], machine, &exynos4_board_binfo); } static void smdkc210_init(MachineState *machine) @@ -146,7 +147,7 @@ static void smdkc210_init(MachineState *machine) lan9215_init(SMDK_LAN9118_BASE_ADDR, qemu_irq_invert(s->soc.irq_table[exynos4210_get_irq(37, 1)])); - arm_load_kernel(ARM_CPU(first_cpu), machine, &exynos4_board_binfo); + arm_load_kernel(s->soc.cpu[0], machine, &exynos4_board_binfo); } static void nuri_class_init(ObjectClass *oc, void *data) diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c index d0eca54cd95..f3784d45caf 100644 --- a/hw/arm/orangepi.c +++ b/hw/arm/orangepi.c @@ -106,7 +106,7 @@ static void orangepi_init(MachineState *machine) orangepi_binfo.loader_start = h3->memmap[AW_H3_DEV_SDRAM]; orangepi_binfo.ram_size = machine->ram_size; orangepi_binfo.psci_conduit = QEMU_PSCI_CONDUIT_SMC; - arm_load_kernel(ARM_CPU(first_cpu), machine, &orangepi_binfo); + arm_load_kernel(&h3->cpus[0], machine, &orangepi_binfo); } static void orangepi_machine_init(MachineClass *mc) diff --git a/hw/arm/realview.c b/hw/arm/realview.c index 8f89526596c..132217b2edd 100644 --- a/hw/arm/realview.c +++ b/hw/arm/realview.c @@ -384,7 +384,7 @@ static void realview_init(MachineState *machine, realview_binfo.ram_size = ram_size; realview_binfo.board_id = realview_board_id[board_type]; realview_binfo.loader_start = (board_type == BOARD_PB_A8 ? 0x70000000 : 0); - arm_load_kernel(ARM_CPU(first_cpu), machine, &realview_binfo); + arm_load_kernel(cpu, machine, &realview_binfo); } static void realview_eb_init(MachineState *machine) diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 8dc2ea83a93..dbb9793aa13 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -349,7 +349,7 @@ static void zynq_init(MachineState *machine) zynq_binfo.board_setup_addr = BOARD_SETUP_ADDR; zynq_binfo.write_board_setup = zynq_write_board_setup; - arm_load_kernel(ARM_CPU(first_cpu), machine, &zynq_binfo); + arm_load_kernel(cpu, machine, &zynq_binfo); } static void zynq_machine_class_init(ObjectClass *oc, void *data) From patchwork Fri Oct 27 14:39:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13455637 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1qwO0n-0008Gb-66 for mharc-qemu-devel@gnu.org; Fri, 27 Oct 2023 10:40:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qwO0J-0007Lk-U2 for qemu-devel@nongnu.org; Fri, 27 Oct 2023 10:40:04 -0400 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qwO0G-0008Bb-CH for qemu-devel@nongnu.org; Fri, 27 Oct 2023 10:40:03 -0400 Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-40859dee28cso17021765e9.0 for ; Fri, 27 Oct 2023 07:39:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698417599; x=1699022399; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=kurXcGyQg+iVSy8QLhx9etYA4XnqvmAMFyclbQPpsa4=; b=Oydjx04eBMNEL+kVPQDzyw3JEXsBM6CwrkdzIkMQNJzHAZYnYf3mEGEDpSjGhOhCBa kHr/shyJATHXGUxULhvR0tjfKa5Dt7Jjbg9IfbQBQL6jUMwcGjfzWkRGc9m4gngUXUtK kJ/sugkw0O6YjrURKEHpc8zvfljrC/iuvKNwDxjEIZk6GshXAIKx0c2hOHTKtpHHsMjD 0DXn5W+BGniWwkUkKWorQFhRGnGur/1GuwR1HhJem4rgsIaOs3bzlwTeyy0zGG3d8Vq7 TFNC5/oTN2/DgxPzm6w2oAhkr8r3ek6TtLaM8HRJxDpJ9yeCywfJI/ZuKFBjBzL7Nn90 6mdA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698417599; x=1699022399; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kurXcGyQg+iVSy8QLhx9etYA4XnqvmAMFyclbQPpsa4=; b=wLQHPypqMD5dB4fz+3PaEA4X+gM6w2bq0oSJv/TpDkaxrgacgqTD92Q/HIcynLSOHV m3uRV2fthTKstoTVRuAS7iwetaM40bTGrb0k6diR02sUaw0P8h+bRq/tnFAGrqgKsOSB Vo/gg0S6WKFvLoP9n1j9AyqtexQNHNwL+xPMH1MVRAw7xGIKueLKsra99DxuSPnyP28P t700D8hb3OxPiAkv+pFu/p5Pvlx0uSJBsxfP66wpfFaqEZTnsM/CesgFcYuuBMO+3dJT nWIAZOhy9UUhj4gYc4Snn3ITJUDFeuFv+GOcjPHJ8qMsMBL3fEmxUrKsHDpd/tC6BTGf YRog== X-Gm-Message-State: AOJu0YyMNwn27S50OM2sfszCw0mEvg/OMPN69MAD5DtkmiaV8456lgQK CavtOtLwi6VocIRWVsBb6tjL1U2JdKkFxH8hmBU= X-Google-Smtp-Source: AGHT+IF9mIO+7dTFl08EIkEdJFEINczrE4/HmBvO/ELKaGQe8aG5gFFWfbKfhOiw3Bi6xWM1Yue2yA== X-Received: by 2002:a05:600c:5119:b0:409:2f7:d771 with SMTP id o25-20020a05600c511900b0040902f7d771mr2690915wms.4.1698417598859; Fri, 27 Oct 2023 07:39:58 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e2-20020a5d5002000000b0031c6581d55esm1874123wrt.91.2023.10.27.07.39.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Oct 2023 07:39:58 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 30/41] misc/led: LED state is set opposite of what is expected Date: Fri, 27 Oct 2023 15:39:31 +0100 Message-Id: <20231027143942.3413881-31-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231027143942.3413881-1-peter.maydell@linaro.org> References: <20231027143942.3413881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Oct 2023 14:40:04 -0000 From: Glenn Miles Testing of the LED state showed that when the LED polarity was set to GPIO_POLARITY_ACTIVE_LOW and a low logic value was set on the input GPIO of the LED, the LED was being turn off when it was expected to be turned on. Fixes: ddb67f6402 ("hw/misc/led: Allow connecting from GPIO output") Signed-off-by: Glenn Miles Reviewed-by: Peter Maydell Reviewed-by: Andrew Jeffery Message-id: 20231024191945.4135036-1-milesg@linux.vnet.ibm.com Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Peter Maydell --- hw/misc/led.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/misc/led.c b/hw/misc/led.c index f6d6d68bce5..42bb43a39a2 100644 --- a/hw/misc/led.c +++ b/hw/misc/led.c @@ -63,7 +63,7 @@ static void led_set_state_gpio_handler(void *opaque, int line, int new_state) LEDState *s = LED(opaque); assert(line == 0); - led_set_state(s, !!new_state != s->gpio_active_high); + led_set_state(s, !!new_state == s->gpio_active_high); } static void led_reset(DeviceState *dev) From patchwork Fri Oct 27 14:39:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13455647 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1qwO0t-0000m9-G5 for mharc-qemu-devel@gnu.org; Fri, 27 Oct 2023 10:40:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qwO0P-0007Os-4u for qemu-devel@nongnu.org; Fri, 27 Oct 2023 10:40:10 -0400 Received: from mail-lf1-x134.google.com ([2a00:1450:4864:20::134]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qwO0H-0008Bk-R1 for qemu-devel@nongnu.org; Fri, 27 Oct 2023 10:40:07 -0400 Received: by mail-lf1-x134.google.com with SMTP id 2adb3069b0e04-50802148be9so2733617e87.2 for ; Fri, 27 Oct 2023 07:40:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698417599; x=1699022399; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=DJmspu/+77H0X0YJS0Z6KrXg04AH+KSa/AXo9P61hHk=; b=Pozm1nFCRmyJB7CFMBzQs7DlUW46T3U4pUimj2O48IR5EAksnDTZ6PXf/9r9QQXMnk vOjA0qFLaEVICutaDSY4kAwtPfMcm26MDdjcF9+qMDu3B4E0Y0E65BGrCFR81sUOmRvH lWotHKSNcu/hjkpQTCi4Dqh/MyxIv89BqkjQiyQWJoLnb8oOluYiKpuPC9YYS3kWvzk4 i7KhnbECs5c4/ClsEab4dORLFPuoxs4NZKc9md64Jy5t4gpCKrSykn/PJ9MY4acr8l8i 1/vaQNQFnLtds9HasBvSrEvNAcMZON8wMvpGuUuclFNfUVRL0SrOVjAjEzpsoMEJwEhz /aXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698417599; x=1699022399; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DJmspu/+77H0X0YJS0Z6KrXg04AH+KSa/AXo9P61hHk=; b=G/jwEizmNLhOfhhkILt4kIiD8kUO5UjnkBJUB9zHqXmZRxvEFALfOU33l1OkA2ZRtG Eai/NugaqWTwtCAoBdryebwU8n18IptTYK9P7ZFKeCrxgokn5oGclkKMDmpWMxdyljcG pnUDE9gUOmvQb4rTZ+Agu2ZuzR+Mh8kT0Fc8p5a76wyRN1Fw0Wjt5yLXD0WNMkNFDKD1 RrzDBcfFaatWd1hO/tmWDqjoqM20D4oTunSrHw86EeHygznb2PaGFpi1CkdT31eIoSiG 8aSVT0IKh5IMfE/cCgisipnq5FWTkQEKjitKyx8zAmEonZJ3g+pZw0PT/yezkpp5cV8M hoTA== X-Gm-Message-State: AOJu0YxFT5//ezBv/Bmn3u/scIzwy55ZncL/lyuYS1/zQWBRR6xgo1tB tp4ggq3ED5+cPxi/1kz4vYf5p9Oi/joxyphfhkU= X-Google-Smtp-Source: AGHT+IGSr1NYiRxysIzzSi4vrHJPmqe5nnlYYoLt2vdpeFysisPC+WRnD68SQkaWHcaC3Bgn3wWXVQ== X-Received: by 2002:a05:6512:15a:b0:507:a701:3206 with SMTP id m26-20020a056512015a00b00507a7013206mr1949519lfo.49.1698417599455; Fri, 27 Oct 2023 07:39:59 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e2-20020a5d5002000000b0031c6581d55esm1874123wrt.91.2023.10.27.07.39.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Oct 2023 07:39:59 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 31/41] hw/net/cadence_gem: use REG32 macro for register definitions Date: Fri, 27 Oct 2023 15:39:32 +0100 Message-Id: <20231027143942.3413881-32-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231027143942.3413881-1-peter.maydell@linaro.org> References: <20231027143942.3413881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::134; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x134.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Oct 2023 14:40:12 -0000 From: Luc Michel Replace register defines with the REG32 macro from registerfields.h in the Cadence GEM device. Signed-off-by: Luc Michel Reviewed-by: sai.pavan.boddu@amd.com Message-id: 20231017194422.4124691-2-luc.michel@amd.com Signed-off-by: Peter Maydell --- hw/net/cadence_gem.c | 527 +++++++++++++++++++++---------------------- 1 file changed, 261 insertions(+), 266 deletions(-) diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index 37e209cda69..bea2224dd8d 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cadence_gem.c @@ -28,6 +28,7 @@ #include "hw/irq.h" #include "hw/net/cadence_gem.h" #include "hw/qdev-properties.h" +#include "hw/registerfields.h" #include "migration/vmstate.h" #include "qapi/error.h" #include "qemu/log.h" @@ -44,136 +45,131 @@ } \ } while (0) -#define GEM_NWCTRL (0x00000000 / 4) /* Network Control reg */ -#define GEM_NWCFG (0x00000004 / 4) /* Network Config reg */ -#define GEM_NWSTATUS (0x00000008 / 4) /* Network Status reg */ -#define GEM_USERIO (0x0000000C / 4) /* User IO reg */ -#define GEM_DMACFG (0x00000010 / 4) /* DMA Control reg */ -#define GEM_TXSTATUS (0x00000014 / 4) /* TX Status reg */ -#define GEM_RXQBASE (0x00000018 / 4) /* RX Q Base address reg */ -#define GEM_TXQBASE (0x0000001C / 4) /* TX Q Base address reg */ -#define GEM_RXSTATUS (0x00000020 / 4) /* RX Status reg */ -#define GEM_ISR (0x00000024 / 4) /* Interrupt Status reg */ -#define GEM_IER (0x00000028 / 4) /* Interrupt Enable reg */ -#define GEM_IDR (0x0000002C / 4) /* Interrupt Disable reg */ -#define GEM_IMR (0x00000030 / 4) /* Interrupt Mask reg */ -#define GEM_PHYMNTNC (0x00000034 / 4) /* Phy Maintenance reg */ -#define GEM_RXPAUSE (0x00000038 / 4) /* RX Pause Time reg */ -#define GEM_TXPAUSE (0x0000003C / 4) /* TX Pause Time reg */ -#define GEM_TXPARTIALSF (0x00000040 / 4) /* TX Partial Store and Forward */ -#define GEM_RXPARTIALSF (0x00000044 / 4) /* RX Partial Store and Forward */ -#define GEM_JUMBO_MAX_LEN (0x00000048 / 4) /* Max Jumbo Frame Size */ -#define GEM_HASHLO (0x00000080 / 4) /* Hash Low address reg */ -#define GEM_HASHHI (0x00000084 / 4) /* Hash High address reg */ -#define GEM_SPADDR1LO (0x00000088 / 4) /* Specific addr 1 low reg */ -#define GEM_SPADDR1HI (0x0000008C / 4) /* Specific addr 1 high reg */ -#define GEM_SPADDR2LO (0x00000090 / 4) /* Specific addr 2 low reg */ -#define GEM_SPADDR2HI (0x00000094 / 4) /* Specific addr 2 high reg */ -#define GEM_SPADDR3LO (0x00000098 / 4) /* Specific addr 3 low reg */ -#define GEM_SPADDR3HI (0x0000009C / 4) /* Specific addr 3 high reg */ -#define GEM_SPADDR4LO (0x000000A0 / 4) /* Specific addr 4 low reg */ -#define GEM_SPADDR4HI (0x000000A4 / 4) /* Specific addr 4 high reg */ -#define GEM_TIDMATCH1 (0x000000A8 / 4) /* Type ID1 Match reg */ -#define GEM_TIDMATCH2 (0x000000AC / 4) /* Type ID2 Match reg */ -#define GEM_TIDMATCH3 (0x000000B0 / 4) /* Type ID3 Match reg */ -#define GEM_TIDMATCH4 (0x000000B4 / 4) /* Type ID4 Match reg */ -#define GEM_WOLAN (0x000000B8 / 4) /* Wake on LAN reg */ -#define GEM_IPGSTRETCH (0x000000BC / 4) /* IPG Stretch reg */ -#define GEM_SVLAN (0x000000C0 / 4) /* Stacked VLAN reg */ -#define GEM_MODID (0x000000FC / 4) /* Module ID reg */ -#define GEM_OCTTXLO (0x00000100 / 4) /* Octets transmitted Low reg */ -#define GEM_OCTTXHI (0x00000104 / 4) /* Octets transmitted High reg */ -#define GEM_TXCNT (0x00000108 / 4) /* Error-free Frames transmitted */ -#define GEM_TXBCNT (0x0000010C / 4) /* Error-free Broadcast Frames */ -#define GEM_TXMCNT (0x00000110 / 4) /* Error-free Multicast Frame */ -#define GEM_TXPAUSECNT (0x00000114 / 4) /* Pause Frames Transmitted */ -#define GEM_TX64CNT (0x00000118 / 4) /* Error-free 64 TX */ -#define GEM_TX65CNT (0x0000011C / 4) /* Error-free 65-127 TX */ -#define GEM_TX128CNT (0x00000120 / 4) /* Error-free 128-255 TX */ -#define GEM_TX256CNT (0x00000124 / 4) /* Error-free 256-511 */ -#define GEM_TX512CNT (0x00000128 / 4) /* Error-free 512-1023 TX */ -#define GEM_TX1024CNT (0x0000012C / 4) /* Error-free 1024-1518 TX */ -#define GEM_TX1519CNT (0x00000130 / 4) /* Error-free larger than 1519 TX */ -#define GEM_TXURUNCNT (0x00000134 / 4) /* TX under run error counter */ -#define GEM_SINGLECOLLCNT (0x00000138 / 4) /* Single Collision Frames */ -#define GEM_MULTCOLLCNT (0x0000013C / 4) /* Multiple Collision Frames */ -#define GEM_EXCESSCOLLCNT (0x00000140 / 4) /* Excessive Collision Frames */ -#define GEM_LATECOLLCNT (0x00000144 / 4) /* Late Collision Frames */ -#define GEM_DEFERTXCNT (0x00000148 / 4) /* Deferred Transmission Frames */ -#define GEM_CSENSECNT (0x0000014C / 4) /* Carrier Sense Error Counter */ -#define GEM_OCTRXLO (0x00000150 / 4) /* Octets Received register Low */ -#define GEM_OCTRXHI (0x00000154 / 4) /* Octets Received register High */ -#define GEM_RXCNT (0x00000158 / 4) /* Error-free Frames Received */ -#define GEM_RXBROADCNT (0x0000015C / 4) /* Error-free Broadcast Frames RX */ -#define GEM_RXMULTICNT (0x00000160 / 4) /* Error-free Multicast Frames RX */ -#define GEM_RXPAUSECNT (0x00000164 / 4) /* Pause Frames Received Counter */ -#define GEM_RX64CNT (0x00000168 / 4) /* Error-free 64 byte Frames RX */ -#define GEM_RX65CNT (0x0000016C / 4) /* Error-free 65-127B Frames RX */ -#define GEM_RX128CNT (0x00000170 / 4) /* Error-free 128-255B Frames RX */ -#define GEM_RX256CNT (0x00000174 / 4) /* Error-free 256-512B Frames RX */ -#define GEM_RX512CNT (0x00000178 / 4) /* Error-free 512-1023B Frames RX */ -#define GEM_RX1024CNT (0x0000017C / 4) /* Error-free 1024-1518B Frames RX */ -#define GEM_RX1519CNT (0x00000180 / 4) /* Error-free 1519-max Frames RX */ -#define GEM_RXUNDERCNT (0x00000184 / 4) /* Undersize Frames Received */ -#define GEM_RXOVERCNT (0x00000188 / 4) /* Oversize Frames Received */ -#define GEM_RXJABCNT (0x0000018C / 4) /* Jabbers Received Counter */ -#define GEM_RXFCSCNT (0x00000190 / 4) /* Frame Check seq. Error Counter */ -#define GEM_RXLENERRCNT (0x00000194 / 4) /* Length Field Error Counter */ -#define GEM_RXSYMERRCNT (0x00000198 / 4) /* Symbol Error Counter */ -#define GEM_RXALIGNERRCNT (0x0000019C / 4) /* Alignment Error Counter */ -#define GEM_RXRSCERRCNT (0x000001A0 / 4) /* Receive Resource Error Counter */ -#define GEM_RXORUNCNT (0x000001A4 / 4) /* Receive Overrun Counter */ -#define GEM_RXIPCSERRCNT (0x000001A8 / 4) /* IP header Checksum Err Counter */ -#define GEM_RXTCPCCNT (0x000001AC / 4) /* TCP Checksum Error Counter */ -#define GEM_RXUDPCCNT (0x000001B0 / 4) /* UDP Checksum Error Counter */ +REG32(NWCTRL, 0x0) /* Network Control reg */ +REG32(NWCFG, 0x4) /* Network Config reg */ +REG32(NWSTATUS, 0x8) /* Network Status reg */ +REG32(USERIO, 0xc) /* User IO reg */ +REG32(DMACFG, 0x10) /* DMA Control reg */ +REG32(TXSTATUS, 0x14) /* TX Status reg */ +REG32(RXQBASE, 0x18) /* RX Q Base address reg */ +REG32(TXQBASE, 0x1c) /* TX Q Base address reg */ +REG32(RXSTATUS, 0x20) /* RX Status reg */ +REG32(ISR, 0x24) /* Interrupt Status reg */ +REG32(IER, 0x28) /* Interrupt Enable reg */ +REG32(IDR, 0x2c) /* Interrupt Disable reg */ +REG32(IMR, 0x30) /* Interrupt Mask reg */ +REG32(PHYMNTNC, 0x34) /* Phy Maintenance reg */ +REG32(RXPAUSE, 0x38) /* RX Pause Time reg */ +REG32(TXPAUSE, 0x3c) /* TX Pause Time reg */ +REG32(TXPARTIALSF, 0x40) /* TX Partial Store and Forward */ +REG32(RXPARTIALSF, 0x44) /* RX Partial Store and Forward */ +REG32(JUMBO_MAX_LEN, 0x48) /* Max Jumbo Frame Size */ +REG32(HASHLO, 0x80) /* Hash Low address reg */ +REG32(HASHHI, 0x84) /* Hash High address reg */ +REG32(SPADDR1LO, 0x88) /* Specific addr 1 low reg */ +REG32(SPADDR1HI, 0x8c) /* Specific addr 1 high reg */ +REG32(SPADDR2LO, 0x90) /* Specific addr 2 low reg */ +REG32(SPADDR2HI, 0x94) /* Specific addr 2 high reg */ +REG32(SPADDR3LO, 0x98) /* Specific addr 3 low reg */ +REG32(SPADDR3HI, 0x9c) /* Specific addr 3 high reg */ +REG32(SPADDR4LO, 0xa0) /* Specific addr 4 low reg */ +REG32(SPADDR4HI, 0xa4) /* Specific addr 4 high reg */ +REG32(TIDMATCH1, 0xa8) /* Type ID1 Match reg */ +REG32(TIDMATCH2, 0xac) /* Type ID2 Match reg */ +REG32(TIDMATCH3, 0xb0) /* Type ID3 Match reg */ +REG32(TIDMATCH4, 0xb4) /* Type ID4 Match reg */ +REG32(WOLAN, 0xb8) /* Wake on LAN reg */ +REG32(IPGSTRETCH, 0xbc) /* IPG Stretch reg */ +REG32(SVLAN, 0xc0) /* Stacked VLAN reg */ +REG32(MODID, 0xfc) /* Module ID reg */ +REG32(OCTTXLO, 0x100) /* Octects transmitted Low reg */ +REG32(OCTTXHI, 0x104) /* Octects transmitted High reg */ +REG32(TXCNT, 0x108) /* Error-free Frames transmitted */ +REG32(TXBCNT, 0x10c) /* Error-free Broadcast Frames */ +REG32(TXMCNT, 0x110) /* Error-free Multicast Frame */ +REG32(TXPAUSECNT, 0x114) /* Pause Frames Transmitted */ +REG32(TX64CNT, 0x118) /* Error-free 64 TX */ +REG32(TX65CNT, 0x11c) /* Error-free 65-127 TX */ +REG32(TX128CNT, 0x120) /* Error-free 128-255 TX */ +REG32(TX256CNT, 0x124) /* Error-free 256-511 */ +REG32(TX512CNT, 0x128) /* Error-free 512-1023 TX */ +REG32(TX1024CNT, 0x12c) /* Error-free 1024-1518 TX */ +REG32(TX1519CNT, 0x130) /* Error-free larger than 1519 TX */ +REG32(TXURUNCNT, 0x134) /* TX under run error counter */ +REG32(SINGLECOLLCNT, 0x138) /* Single Collision Frames */ +REG32(MULTCOLLCNT, 0x13c) /* Multiple Collision Frames */ +REG32(EXCESSCOLLCNT, 0x140) /* Excessive Collision Frames */ +REG32(LATECOLLCNT, 0x144) /* Late Collision Frames */ +REG32(DEFERTXCNT, 0x148) /* Deferred Transmission Frames */ +REG32(CSENSECNT, 0x14c) /* Carrier Sense Error Counter */ +REG32(OCTRXLO, 0x150) /* Octects Received register Low */ +REG32(OCTRXHI, 0x154) /* Octects Received register High */ +REG32(RXCNT, 0x158) /* Error-free Frames Received */ +REG32(RXBROADCNT, 0x15c) /* Error-free Broadcast Frames RX */ +REG32(RXMULTICNT, 0x160) /* Error-free Multicast Frames RX */ +REG32(RXPAUSECNT, 0x164) /* Pause Frames Received Counter */ +REG32(RX64CNT, 0x168) /* Error-free 64 byte Frames RX */ +REG32(RX65CNT, 0x16c) /* Error-free 65-127B Frames RX */ +REG32(RX128CNT, 0x170) /* Error-free 128-255B Frames RX */ +REG32(RX256CNT, 0x174) /* Error-free 256-512B Frames RX */ +REG32(RX512CNT, 0x178) /* Error-free 512-1023B Frames RX */ +REG32(RX1024CNT, 0x17c) /* Error-free 1024-1518B Frames RX */ +REG32(RX1519CNT, 0x180) /* Error-free 1519-max Frames RX */ +REG32(RXUNDERCNT, 0x184) /* Undersize Frames Received */ +REG32(RXOVERCNT, 0x188) /* Oversize Frames Received */ +REG32(RXJABCNT, 0x18c) /* Jabbers Received Counter */ +REG32(RXFCSCNT, 0x190) /* Frame Check seq. Error Counter */ +REG32(RXLENERRCNT, 0x194) /* Length Field Error Counter */ +REG32(RXSYMERRCNT, 0x198) /* Symbol Error Counter */ +REG32(RXALIGNERRCNT, 0x19c) /* Alignment Error Counter */ +REG32(RXRSCERRCNT, 0x1a0) /* Receive Resource Error Counter */ +REG32(RXORUNCNT, 0x1a4) /* Receive Overrun Counter */ +REG32(RXIPCSERRCNT, 0x1a8) /* IP header Checksum Err Counter */ +REG32(RXTCPCCNT, 0x1ac) /* TCP Checksum Error Counter */ +REG32(RXUDPCCNT, 0x1b0) /* UDP Checksum Error Counter */ -#define GEM_1588S (0x000001D0 / 4) /* 1588 Timer Seconds */ -#define GEM_1588NS (0x000001D4 / 4) /* 1588 Timer Nanoseconds */ -#define GEM_1588ADJ (0x000001D8 / 4) /* 1588 Timer Adjust */ -#define GEM_1588INC (0x000001DC / 4) /* 1588 Timer Increment */ -#define GEM_PTPETXS (0x000001E0 / 4) /* PTP Event Frame Transmitted (s) */ -#define GEM_PTPETXNS (0x000001E4 / 4) /* - * PTP Event Frame Transmitted (ns) - */ -#define GEM_PTPERXS (0x000001E8 / 4) /* PTP Event Frame Received (s) */ -#define GEM_PTPERXNS (0x000001EC / 4) /* PTP Event Frame Received (ns) */ -#define GEM_PTPPTXS (0x000001E0 / 4) /* PTP Peer Frame Transmitted (s) */ -#define GEM_PTPPTXNS (0x000001E4 / 4) /* PTP Peer Frame Transmitted (ns) */ -#define GEM_PTPPRXS (0x000001E8 / 4) /* PTP Peer Frame Received (s) */ -#define GEM_PTPPRXNS (0x000001EC / 4) /* PTP Peer Frame Received (ns) */ +REG32(1588S, 0x1d0) /* 1588 Timer Seconds */ +REG32(1588NS, 0x1d4) /* 1588 Timer Nanoseconds */ +REG32(1588ADJ, 0x1d8) /* 1588 Timer Adjust */ +REG32(1588INC, 0x1dc) /* 1588 Timer Increment */ +REG32(PTPETXS, 0x1e0) /* PTP Event Frame Transmitted (s) */ +REG32(PTPETXNS, 0x1e4) /* PTP Event Frame Transmitted (ns) */ +REG32(PTPERXS, 0x1e8) /* PTP Event Frame Received (s) */ +REG32(PTPERXNS, 0x1ec) /* PTP Event Frame Received (ns) */ +REG32(PTPPTXS, 0x1e0) /* PTP Peer Frame Transmitted (s) */ +REG32(PTPPTXNS, 0x1e4) /* PTP Peer Frame Transmitted (ns) */ +REG32(PTPPRXS, 0x1e8) /* PTP Peer Frame Received (s) */ +REG32(PTPPRXNS, 0x1ec) /* PTP Peer Frame Received (ns) */ /* Design Configuration Registers */ -#define GEM_DESCONF (0x00000280 / 4) -#define GEM_DESCONF2 (0x00000284 / 4) -#define GEM_DESCONF3 (0x00000288 / 4) -#define GEM_DESCONF4 (0x0000028C / 4) -#define GEM_DESCONF5 (0x00000290 / 4) -#define GEM_DESCONF6 (0x00000294 / 4) +REG32(DESCONF, 0x280) +REG32(DESCONF2, 0x284) +REG32(DESCONF3, 0x288) +REG32(DESCONF4, 0x28c) +REG32(DESCONF5, 0x290) +REG32(DESCONF6, 0x294) #define GEM_DESCONF6_64B_MASK (1U << 23) -#define GEM_DESCONF7 (0x00000298 / 4) +REG32(DESCONF7, 0x298) -#define GEM_INT_Q1_STATUS (0x00000400 / 4) -#define GEM_INT_Q1_MASK (0x00000640 / 4) +REG32(INT_Q1_STATUS, 0x400) +REG32(INT_Q1_MASK, 0x640) -#define GEM_TRANSMIT_Q1_PTR (0x00000440 / 4) -#define GEM_TRANSMIT_Q7_PTR (GEM_TRANSMIT_Q1_PTR + 6) +REG32(TRANSMIT_Q1_PTR, 0x440) +REG32(TRANSMIT_Q7_PTR, 0x458) -#define GEM_RECEIVE_Q1_PTR (0x00000480 / 4) -#define GEM_RECEIVE_Q7_PTR (GEM_RECEIVE_Q1_PTR + 6) +REG32(RECEIVE_Q1_PTR, 0x480) +REG32(RECEIVE_Q7_PTR, 0x498) -#define GEM_TBQPH (0x000004C8 / 4) -#define GEM_RBQPH (0x000004D4 / 4) +REG32(TBQPH, 0x4c8) +REG32(RBQPH, 0x4d4) -#define GEM_INT_Q1_ENABLE (0x00000600 / 4) -#define GEM_INT_Q7_ENABLE (GEM_INT_Q1_ENABLE + 6) +REG32(INT_Q1_ENABLE, 0x600) +REG32(INT_Q7_ENABLE, 0x618) -#define GEM_INT_Q1_DISABLE (0x00000620 / 4) -#define GEM_INT_Q7_DISABLE (GEM_INT_Q1_DISABLE + 6) +REG32(INT_Q1_DISABLE, 0x620) +REG32(INT_Q7_DISABLE, 0x638) -#define GEM_INT_Q1_MASK (0x00000640 / 4) -#define GEM_INT_Q7_MASK (GEM_INT_Q1_MASK + 6) - -#define GEM_SCREENING_TYPE1_REGISTER_0 (0x00000500 / 4) +REG32(SCREENING_TYPE1_REG0, 0x500) #define GEM_ST1R_UDP_PORT_MATCH_ENABLE (1 << 29) #define GEM_ST1R_DSTC_ENABLE (1 << 28) @@ -184,7 +180,7 @@ #define GEM_ST1R_QUEUE_SHIFT (0) #define GEM_ST1R_QUEUE_WIDTH (3 - GEM_ST1R_QUEUE_SHIFT + 1) -#define GEM_SCREENING_TYPE2_REGISTER_0 (0x00000540 / 4) +REG32(SCREENING_TYPE2_REG0, 0x540) #define GEM_ST2R_COMPARE_A_ENABLE (1 << 18) #define GEM_ST2R_COMPARE_A_SHIFT (13) @@ -196,8 +192,8 @@ #define GEM_ST2R_QUEUE_SHIFT (0) #define GEM_ST2R_QUEUE_WIDTH (3 - GEM_ST2R_QUEUE_SHIFT + 1) -#define GEM_SCREENING_TYPE2_ETHERTYPE_REG_0 (0x000006e0 / 4) -#define GEM_TYPE2_COMPARE_0_WORD_0 (0x00000700 / 4) +REG32(SCREENING_TYPE2_ETHERTYPE_REG0, 0x6e0) +REG32(TYPE2_COMPARE_0_WORD_0, 0x700) #define GEM_T2CW1_COMPARE_OFFSET_SHIFT (7) #define GEM_T2CW1_COMPARE_OFFSET_WIDTH (8 - GEM_T2CW1_COMPARE_OFFSET_SHIFT + 1) @@ -325,7 +321,7 @@ static inline uint64_t tx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc) { uint64_t ret = desc[0]; - if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) { + if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) { ret |= (uint64_t)desc[2] << 32; } return ret; @@ -370,7 +366,7 @@ static inline uint64_t rx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc) { uint64_t ret = desc[0] & ~0x3UL; - if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) { + if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) { ret |= (uint64_t)desc[2] << 32; } return ret; @@ -380,10 +376,10 @@ static inline int gem_get_desc_len(CadenceGEMState *s, bool rx_n_tx) { int ret = 2; - if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) { + if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) { ret += 2; } - if (s->regs[GEM_DMACFG] & (rx_n_tx ? GEM_DMACFG_RX_BD_EXT + if (s->regs[R_DMACFG] & (rx_n_tx ? GEM_DMACFG_RX_BD_EXT : GEM_DMACFG_TX_BD_EXT)) { ret += 2; } @@ -456,8 +452,8 @@ static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; static uint32_t gem_get_max_buf_len(CadenceGEMState *s, bool tx) { uint32_t size; - if (s->regs[GEM_NWCFG] & GEM_NWCFG_JUMBO_FRAME) { - size = s->regs[GEM_JUMBO_MAX_LEN]; + if (s->regs[R_NWCFG] & GEM_NWCFG_JUMBO_FRAME) { + size = s->regs[R_JUMBO_MAX_LEN]; if (size > s->jumbo_max_len) { size = s->jumbo_max_len; qemu_log_mask(LOG_GUEST_ERROR, "GEM_JUMBO_MAX_LEN reg cannot be" @@ -466,7 +462,7 @@ static uint32_t gem_get_max_buf_len(CadenceGEMState *s, bool tx) } else if (tx) { size = 1518; } else { - size = s->regs[GEM_NWCFG] & GEM_NWCFG_RCV_1538 ? 1538 : 1518; + size = s->regs[R_NWCFG] & GEM_NWCFG_RCV_1538 ? 1538 : 1518; } return size; } @@ -474,10 +470,10 @@ static uint32_t gem_get_max_buf_len(CadenceGEMState *s, bool tx) static void gem_set_isr(CadenceGEMState *s, int q, uint32_t flag) { if (q == 0) { - s->regs[GEM_ISR] |= flag & ~(s->regs[GEM_IMR]); + s->regs[R_ISR] |= flag & ~(s->regs[R_IMR]); } else { - s->regs[GEM_INT_Q1_STATUS + q - 1] |= flag & - ~(s->regs[GEM_INT_Q1_MASK + q - 1]); + s->regs[R_INT_Q1_STATUS + q - 1] |= flag & + ~(s->regs[R_INT_Q1_MASK + q - 1]); } } @@ -491,43 +487,43 @@ static void gem_init_register_masks(CadenceGEMState *s) unsigned int i; /* Mask of register bits which are read only */ memset(&s->regs_ro[0], 0, sizeof(s->regs_ro)); - s->regs_ro[GEM_NWCTRL] = 0xFFF80000; - s->regs_ro[GEM_NWSTATUS] = 0xFFFFFFFF; - s->regs_ro[GEM_DMACFG] = 0x8E00F000; - s->regs_ro[GEM_TXSTATUS] = 0xFFFFFE08; - s->regs_ro[GEM_RXQBASE] = 0x00000003; - s->regs_ro[GEM_TXQBASE] = 0x00000003; - s->regs_ro[GEM_RXSTATUS] = 0xFFFFFFF0; - s->regs_ro[GEM_ISR] = 0xFFFFFFFF; - s->regs_ro[GEM_IMR] = 0xFFFFFFFF; - s->regs_ro[GEM_MODID] = 0xFFFFFFFF; + s->regs_ro[R_NWCTRL] = 0xFFF80000; + s->regs_ro[R_NWSTATUS] = 0xFFFFFFFF; + s->regs_ro[R_DMACFG] = 0x8E00F000; + s->regs_ro[R_TXSTATUS] = 0xFFFFFE08; + s->regs_ro[R_RXQBASE] = 0x00000003; + s->regs_ro[R_TXQBASE] = 0x00000003; + s->regs_ro[R_RXSTATUS] = 0xFFFFFFF0; + s->regs_ro[R_ISR] = 0xFFFFFFFF; + s->regs_ro[R_IMR] = 0xFFFFFFFF; + s->regs_ro[R_MODID] = 0xFFFFFFFF; for (i = 0; i < s->num_priority_queues; i++) { - s->regs_ro[GEM_INT_Q1_STATUS + i] = 0xFFFFFFFF; - s->regs_ro[GEM_INT_Q1_ENABLE + i] = 0xFFFFF319; - s->regs_ro[GEM_INT_Q1_DISABLE + i] = 0xFFFFF319; - s->regs_ro[GEM_INT_Q1_MASK + i] = 0xFFFFFFFF; + s->regs_ro[R_INT_Q1_STATUS + i] = 0xFFFFFFFF; + s->regs_ro[R_INT_Q1_ENABLE + i] = 0xFFFFF319; + s->regs_ro[R_INT_Q1_DISABLE + i] = 0xFFFFF319; + s->regs_ro[R_INT_Q1_MASK + i] = 0xFFFFFFFF; } /* Mask of register bits which are clear on read */ memset(&s->regs_rtc[0], 0, sizeof(s->regs_rtc)); - s->regs_rtc[GEM_ISR] = 0xFFFFFFFF; + s->regs_rtc[R_ISR] = 0xFFFFFFFF; for (i = 0; i < s->num_priority_queues; i++) { - s->regs_rtc[GEM_INT_Q1_STATUS + i] = 0x00000CE6; + s->regs_rtc[R_INT_Q1_STATUS + i] = 0x00000CE6; } /* Mask of register bits which are write 1 to clear */ memset(&s->regs_w1c[0], 0, sizeof(s->regs_w1c)); - s->regs_w1c[GEM_TXSTATUS] = 0x000001F7; - s->regs_w1c[GEM_RXSTATUS] = 0x0000000F; + s->regs_w1c[R_TXSTATUS] = 0x000001F7; + s->regs_w1c[R_RXSTATUS] = 0x0000000F; /* Mask of register bits which are write only */ memset(&s->regs_wo[0], 0, sizeof(s->regs_wo)); - s->regs_wo[GEM_NWCTRL] = 0x00073E60; - s->regs_wo[GEM_IER] = 0x07FFFFFF; - s->regs_wo[GEM_IDR] = 0x07FFFFFF; + s->regs_wo[R_NWCTRL] = 0x00073E60; + s->regs_wo[R_IER] = 0x07FFFFFF; + s->regs_wo[R_IDR] = 0x07FFFFFF; for (i = 0; i < s->num_priority_queues; i++) { - s->regs_wo[GEM_INT_Q1_ENABLE + i] = 0x00000CE6; - s->regs_wo[GEM_INT_Q1_DISABLE + i] = 0x00000CE6; + s->regs_wo[R_INT_Q1_ENABLE + i] = 0x00000CE6; + s->regs_wo[R_INT_Q1_DISABLE + i] = 0x00000CE6; } } @@ -561,7 +557,7 @@ static bool gem_can_receive(NetClientState *nc) s = qemu_get_nic_opaque(nc); /* Do nothing if receive is not enabled. */ - if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_RXENA)) { + if (!(s->regs[R_NWCTRL] & GEM_NWCTRL_RXENA)) { if (s->can_rx_state != 1) { s->can_rx_state = 1; DB_PRINT("can't receive - no enable\n"); @@ -598,10 +594,10 @@ static void gem_update_int_status(CadenceGEMState *s) { int i; - qemu_set_irq(s->irq[0], !!s->regs[GEM_ISR]); + qemu_set_irq(s->irq[0], !!s->regs[R_ISR]); for (i = 1; i < s->num_priority_queues; ++i) { - qemu_set_irq(s->irq[i], !!s->regs[GEM_INT_Q1_STATUS + i - 1]); + qemu_set_irq(s->irq[i], !!s->regs[R_INT_Q1_STATUS + i - 1]); } } @@ -615,39 +611,39 @@ static void gem_receive_updatestats(CadenceGEMState *s, const uint8_t *packet, uint64_t octets; /* Total octets (bytes) received */ - octets = ((uint64_t)(s->regs[GEM_OCTRXLO]) << 32) | - s->regs[GEM_OCTRXHI]; + octets = ((uint64_t)(s->regs[R_OCTRXLO]) << 32) | + s->regs[R_OCTRXHI]; octets += bytes; - s->regs[GEM_OCTRXLO] = octets >> 32; - s->regs[GEM_OCTRXHI] = octets; + s->regs[R_OCTRXLO] = octets >> 32; + s->regs[R_OCTRXHI] = octets; /* Error-free Frames received */ - s->regs[GEM_RXCNT]++; + s->regs[R_RXCNT]++; /* Error-free Broadcast Frames counter */ if (!memcmp(packet, broadcast_addr, 6)) { - s->regs[GEM_RXBROADCNT]++; + s->regs[R_RXBROADCNT]++; } /* Error-free Multicast Frames counter */ if (packet[0] == 0x01) { - s->regs[GEM_RXMULTICNT]++; + s->regs[R_RXMULTICNT]++; } if (bytes <= 64) { - s->regs[GEM_RX64CNT]++; + s->regs[R_RX64CNT]++; } else if (bytes <= 127) { - s->regs[GEM_RX65CNT]++; + s->regs[R_RX65CNT]++; } else if (bytes <= 255) { - s->regs[GEM_RX128CNT]++; + s->regs[R_RX128CNT]++; } else if (bytes <= 511) { - s->regs[GEM_RX256CNT]++; + s->regs[R_RX256CNT]++; } else if (bytes <= 1023) { - s->regs[GEM_RX512CNT]++; + s->regs[R_RX512CNT]++; } else if (bytes <= 1518) { - s->regs[GEM_RX1024CNT]++; + s->regs[R_RX1024CNT]++; } else { - s->regs[GEM_RX1519CNT]++; + s->regs[R_RX1519CNT]++; } } @@ -706,13 +702,13 @@ static int gem_mac_address_filter(CadenceGEMState *s, const uint8_t *packet) int i, is_mc; /* Promiscuous mode? */ - if (s->regs[GEM_NWCFG] & GEM_NWCFG_PROMISC) { + if (s->regs[R_NWCFG] & GEM_NWCFG_PROMISC) { return GEM_RX_PROMISCUOUS_ACCEPT; } if (!memcmp(packet, broadcast_addr, 6)) { /* Reject broadcast packets? */ - if (s->regs[GEM_NWCFG] & GEM_NWCFG_BCAST_REJ) { + if (s->regs[R_NWCFG] & GEM_NWCFG_BCAST_REJ) { return GEM_RX_REJECT; } return GEM_RX_BROADCAST_ACCEPT; @@ -720,13 +716,13 @@ static int gem_mac_address_filter(CadenceGEMState *s, const uint8_t *packet) /* Accept packets -w- hash match? */ is_mc = is_multicast_ether_addr(packet); - if ((is_mc && (s->regs[GEM_NWCFG] & GEM_NWCFG_MCAST_HASH)) || - (!is_mc && (s->regs[GEM_NWCFG] & GEM_NWCFG_UCAST_HASH))) { + if ((is_mc && (s->regs[R_NWCFG] & GEM_NWCFG_MCAST_HASH)) || + (!is_mc && (s->regs[R_NWCFG] & GEM_NWCFG_UCAST_HASH))) { uint64_t buckets; unsigned hash_index; hash_index = calc_mac_hash(packet); - buckets = ((uint64_t)s->regs[GEM_HASHHI] << 32) | s->regs[GEM_HASHLO]; + buckets = ((uint64_t)s->regs[R_HASHHI] << 32) | s->regs[R_HASHLO]; if ((buckets >> hash_index) & 1) { return is_mc ? GEM_RX_MULTICAST_HASH_ACCEPT : GEM_RX_UNICAST_HASH_ACCEPT; @@ -734,7 +730,7 @@ static int gem_mac_address_filter(CadenceGEMState *s, const uint8_t *packet) } /* Check all 4 specific addresses */ - gem_spaddr = (uint8_t *)&(s->regs[GEM_SPADDR1LO]); + gem_spaddr = (uint8_t *)&(s->regs[R_SPADDR1LO]); for (i = 3; i >= 0; i--) { if (s->sar_active[i] && !memcmp(packet, gem_spaddr + 8 * i, 6)) { return GEM_RX_SAR_ACCEPT + i; @@ -754,7 +750,7 @@ static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr, int i, j; for (i = 0; i < s->num_type1_screeners; i++) { - reg = s->regs[GEM_SCREENING_TYPE1_REGISTER_0 + i]; + reg = s->regs[R_SCREENING_TYPE1_REG0 + i]; matched = false; mismatched = false; @@ -786,7 +782,7 @@ static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr, } for (i = 0; i < s->num_type2_screeners; i++) { - reg = s->regs[GEM_SCREENING_TYPE2_REGISTER_0 + i]; + reg = s->regs[R_SCREENING_TYPE2_REG0 + i]; matched = false; mismatched = false; @@ -799,7 +795,7 @@ static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr, qemu_log_mask(LOG_GUEST_ERROR, "Out of range ethertype " "register index: %d\n", et_idx); } - if (type == s->regs[GEM_SCREENING_TYPE2_ETHERTYPE_REG_0 + + if (type == s->regs[R_SCREENING_TYPE2_ETHERTYPE_REG0 + et_idx]) { matched = true; } else { @@ -823,8 +819,8 @@ static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr, "register index: %d\n", cr_idx); } - cr0 = s->regs[GEM_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2]; - cr1 = s->regs[GEM_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2 + 1]; + cr0 = s->regs[R_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2]; + cr1 = s->regs[R_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2 + 1]; offset = extract32(cr1, GEM_T2CW1_OFFSET_VALUE_SHIFT, GEM_T2CW1_OFFSET_VALUE_WIDTH); @@ -871,11 +867,11 @@ static uint32_t gem_get_queue_base_addr(CadenceGEMState *s, bool tx, int q) switch (q) { case 0: - base_addr = s->regs[tx ? GEM_TXQBASE : GEM_RXQBASE]; + base_addr = s->regs[tx ? R_TXQBASE : R_RXQBASE]; break; case 1 ... (MAX_PRIORITY_QUEUES - 1): - base_addr = s->regs[(tx ? GEM_TRANSMIT_Q1_PTR : - GEM_RECEIVE_Q1_PTR) + q - 1]; + base_addr = s->regs[(tx ? R_TRANSMIT_Q1_PTR : + R_RECEIVE_Q1_PTR) + q - 1]; break; default: g_assert_not_reached(); @@ -898,8 +894,8 @@ static hwaddr gem_get_desc_addr(CadenceGEMState *s, bool tx, int q) { hwaddr desc_addr = 0; - if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) { - desc_addr = s->regs[tx ? GEM_TBQPH : GEM_RBQPH]; + if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) { + desc_addr = s->regs[tx ? R_TBQPH : R_RBQPH]; } desc_addr <<= 32; desc_addr |= tx ? s->tx_desc_addr[q] : s->rx_desc_addr[q]; @@ -930,7 +926,7 @@ static void gem_get_rx_desc(CadenceGEMState *s, int q) /* Descriptor owned by software ? */ if (rx_desc_get_ownership(s->rx_desc[q]) == 1) { DB_PRINT("descriptor 0x%" HWADDR_PRIx " owned by sw.\n", desc_addr); - s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_NOBUF; + s->regs[R_RXSTATUS] |= GEM_RXSTATUS_NOBUF; gem_set_isr(s, q, GEM_INT_RXUSED); /* Handle interrupt consequences */ gem_update_int_status(s); @@ -958,7 +954,7 @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size) } /* Discard packets with receive length error enabled ? */ - if (s->regs[GEM_NWCFG] & GEM_NWCFG_LERR_DISC) { + if (s->regs[R_NWCFG] & GEM_NWCFG_LERR_DISC) { unsigned type_len; /* Fish the ethertype / length field out of the RX packet */ @@ -975,13 +971,13 @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size) /* * Determine configured receive buffer offset (probably 0) */ - rxbuf_offset = (s->regs[GEM_NWCFG] & GEM_NWCFG_BUFF_OFST_M) >> + rxbuf_offset = (s->regs[R_NWCFG] & GEM_NWCFG_BUFF_OFST_M) >> GEM_NWCFG_BUFF_OFST_S; /* The configure size of each receive buffer. Determines how many * buffers needed to hold this packet. */ - rxbufsize = ((s->regs[GEM_DMACFG] & GEM_DMACFG_RBUFSZ_M) >> + rxbufsize = ((s->regs[R_DMACFG] & GEM_DMACFG_RBUFSZ_M) >> GEM_DMACFG_RBUFSZ_S) * GEM_DMACFG_RBUFSZ_MUL; bytes_to_copy = size; @@ -1001,7 +997,7 @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size) } /* Strip of FCS field ? (usually yes) */ - if (s->regs[GEM_NWCFG] & GEM_NWCFG_STRIP_FCS) { + if (s->regs[R_NWCFG] & GEM_NWCFG_STRIP_FCS) { rxbuf_ptr = (void *)buf; } else { unsigned crc_val; @@ -1107,7 +1103,7 @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size) /* Count it */ gem_receive_updatestats(s, buf, size); - s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_FRMRCVD; + s->regs[R_RXSTATUS] |= GEM_RXSTATUS_FRMRCVD; gem_set_isr(s, q, GEM_INT_RXCMPL); /* Handle interrupt consequences */ @@ -1126,39 +1122,39 @@ static void gem_transmit_updatestats(CadenceGEMState *s, const uint8_t *packet, uint64_t octets; /* Total octets (bytes) transmitted */ - octets = ((uint64_t)(s->regs[GEM_OCTTXLO]) << 32) | - s->regs[GEM_OCTTXHI]; + octets = ((uint64_t)(s->regs[R_OCTTXLO]) << 32) | + s->regs[R_OCTTXHI]; octets += bytes; - s->regs[GEM_OCTTXLO] = octets >> 32; - s->regs[GEM_OCTTXHI] = octets; + s->regs[R_OCTTXLO] = octets >> 32; + s->regs[R_OCTTXHI] = octets; /* Error-free Frames transmitted */ - s->regs[GEM_TXCNT]++; + s->regs[R_TXCNT]++; /* Error-free Broadcast Frames counter */ if (!memcmp(packet, broadcast_addr, 6)) { - s->regs[GEM_TXBCNT]++; + s->regs[R_TXBCNT]++; } /* Error-free Multicast Frames counter */ if (packet[0] == 0x01) { - s->regs[GEM_TXMCNT]++; + s->regs[R_TXMCNT]++; } if (bytes <= 64) { - s->regs[GEM_TX64CNT]++; + s->regs[R_TX64CNT]++; } else if (bytes <= 127) { - s->regs[GEM_TX65CNT]++; + s->regs[R_TX65CNT]++; } else if (bytes <= 255) { - s->regs[GEM_TX128CNT]++; + s->regs[R_TX128CNT]++; } else if (bytes <= 511) { - s->regs[GEM_TX256CNT]++; + s->regs[R_TX256CNT]++; } else if (bytes <= 1023) { - s->regs[GEM_TX512CNT]++; + s->regs[R_TX512CNT]++; } else if (bytes <= 1518) { - s->regs[GEM_TX1024CNT]++; + s->regs[R_TX1024CNT]++; } else { - s->regs[GEM_TX1519CNT]++; + s->regs[R_TX1519CNT]++; } } @@ -1175,7 +1171,7 @@ static void gem_transmit(CadenceGEMState *s) int q = 0; /* Do nothing if transmit is not enabled. */ - if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_TXENA)) { + if (!(s->regs[R_NWCTRL] & GEM_NWCTRL_TXENA)) { return; } @@ -1200,7 +1196,7 @@ static void gem_transmit(CadenceGEMState *s) while (tx_desc_get_used(desc) == 0) { /* Do nothing if transmit is not enabled. */ - if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_TXENA)) { + if (!(s->regs[R_NWCTRL] & GEM_NWCTRL_TXENA)) { return; } print_gem_tx_desc(desc, q); @@ -1258,14 +1254,14 @@ static void gem_transmit(CadenceGEMState *s) } DB_PRINT("TX descriptor next: 0x%08x\n", s->tx_desc_addr[q]); - s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_TXCMPL; + s->regs[R_TXSTATUS] |= GEM_TXSTATUS_TXCMPL; gem_set_isr(s, q, GEM_INT_TXCMPL); /* Handle interrupt consequences */ gem_update_int_status(s); /* Is checksum offload enabled? */ - if (s->regs[GEM_DMACFG] & GEM_DMACFG_TXCSUM_OFFL) { + if (s->regs[R_DMACFG] & GEM_DMACFG_TXCSUM_OFFL) { net_checksum_calculate(s->tx_packet, total_bytes, CSUM_ALL); } @@ -1273,7 +1269,7 @@ static void gem_transmit(CadenceGEMState *s) gem_transmit_updatestats(s, s->tx_packet, total_bytes); /* Send the packet somewhere */ - if (s->phy_loop || (s->regs[GEM_NWCTRL] & + if (s->phy_loop || (s->regs[R_NWCTRL] & GEM_NWCTRL_LOCALLOOP)) { qemu_receive_packet(qemu_get_queue(s->nic), s->tx_packet, total_bytes); @@ -1289,9 +1285,8 @@ static void gem_transmit(CadenceGEMState *s) /* read next descriptor */ if (tx_desc_get_wrap(desc)) { - - if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) { - packet_desc_addr = s->regs[GEM_TBQPH]; + if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) { + packet_desc_addr = s->regs[R_TBQPH]; packet_desc_addr <<= 32; } else { packet_desc_addr = 0; @@ -1307,7 +1302,7 @@ static void gem_transmit(CadenceGEMState *s) } if (tx_desc_get_used(desc)) { - s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_USED; + s->regs[R_TXSTATUS] |= GEM_TXSTATUS_USED; /* IRQ TXUSED is defined only for queue 0 */ if (q == 0) { gem_set_isr(s, 0, GEM_INT_TXUSED); @@ -1353,30 +1348,30 @@ static void gem_reset(DeviceState *d) /* Set post reset register values */ memset(&s->regs[0], 0, sizeof(s->regs)); - s->regs[GEM_NWCFG] = 0x00080000; - s->regs[GEM_NWSTATUS] = 0x00000006; - s->regs[GEM_DMACFG] = 0x00020784; - s->regs[GEM_IMR] = 0x07ffffff; - s->regs[GEM_TXPAUSE] = 0x0000ffff; - s->regs[GEM_TXPARTIALSF] = 0x000003ff; - s->regs[GEM_RXPARTIALSF] = 0x000003ff; - s->regs[GEM_MODID] = s->revision; - s->regs[GEM_DESCONF] = 0x02D00111; - s->regs[GEM_DESCONF2] = 0x2ab10000 | s->jumbo_max_len; - s->regs[GEM_DESCONF5] = 0x002f2045; - s->regs[GEM_DESCONF6] = GEM_DESCONF6_64B_MASK; - s->regs[GEM_INT_Q1_MASK] = 0x00000CE6; - s->regs[GEM_JUMBO_MAX_LEN] = s->jumbo_max_len; + s->regs[R_NWCFG] = 0x00080000; + s->regs[R_NWSTATUS] = 0x00000006; + s->regs[R_DMACFG] = 0x00020784; + s->regs[R_IMR] = 0x07ffffff; + s->regs[R_TXPAUSE] = 0x0000ffff; + s->regs[R_TXPARTIALSF] = 0x000003ff; + s->regs[R_RXPARTIALSF] = 0x000003ff; + s->regs[R_MODID] = s->revision; + s->regs[R_DESCONF] = 0x02D00111; + s->regs[R_DESCONF2] = 0x2ab10000 | s->jumbo_max_len; + s->regs[R_DESCONF5] = 0x002f2045; + s->regs[R_DESCONF6] = GEM_DESCONF6_64B_MASK; + s->regs[R_INT_Q1_MASK] = 0x00000CE6; + s->regs[R_JUMBO_MAX_LEN] = s->jumbo_max_len; if (s->num_priority_queues > 1) { queues_mask = MAKE_64BIT_MASK(1, s->num_priority_queues - 1); - s->regs[GEM_DESCONF6] |= queues_mask; + s->regs[R_DESCONF6] |= queues_mask; } /* Set MAC address */ a = &s->conf.macaddr.a[0]; - s->regs[GEM_SPADDR1LO] = a[0] | (a[1] << 8) | (a[2] << 16) | (a[3] << 24); - s->regs[GEM_SPADDR1HI] = a[4] | (a[5] << 8); + s->regs[R_SPADDR1LO] = a[0] | (a[1] << 8) | (a[2] << 16) | (a[3] << 24); + s->regs[R_SPADDR1HI] = a[4] | (a[5] << 8); for (i = 0; i < 4; i++) { s->sar_active[i] = false; @@ -1437,11 +1432,11 @@ static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size) DB_PRINT("offset: 0x%04x read: 0x%08x\n", (unsigned)offset*4, retval); switch (offset) { - case GEM_ISR: + case R_ISR: DB_PRINT("lowering irqs on ISR read\n"); /* The interrupts get updated at the end of the function. */ break; - case GEM_PHYMNTNC: + case R_PHYMNTNC: if (retval & GEM_PHYMNTNC_OP_R) { uint32_t phy_addr, reg_num; @@ -1495,7 +1490,7 @@ static void gem_write(void *opaque, hwaddr offset, uint64_t val, /* Handle register write side effects */ switch (offset) { - case GEM_NWCTRL: + case R_NWCTRL: if (val & GEM_NWCTRL_RXENA) { for (i = 0; i < s->num_priority_queues; ++i) { gem_get_rx_desc(s, i); @@ -1515,56 +1510,56 @@ static void gem_write(void *opaque, hwaddr offset, uint64_t val, } break; - case GEM_TXSTATUS: + case R_TXSTATUS: gem_update_int_status(s); break; - case GEM_RXQBASE: + case R_RXQBASE: s->rx_desc_addr[0] = val; break; - case GEM_RECEIVE_Q1_PTR ... GEM_RECEIVE_Q7_PTR: - s->rx_desc_addr[offset - GEM_RECEIVE_Q1_PTR + 1] = val; + case R_RECEIVE_Q1_PTR ... R_RECEIVE_Q7_PTR: + s->rx_desc_addr[offset - R_RECEIVE_Q1_PTR + 1] = val; break; - case GEM_TXQBASE: + case R_TXQBASE: s->tx_desc_addr[0] = val; break; - case GEM_TRANSMIT_Q1_PTR ... GEM_TRANSMIT_Q7_PTR: - s->tx_desc_addr[offset - GEM_TRANSMIT_Q1_PTR + 1] = val; + case R_TRANSMIT_Q1_PTR ... R_TRANSMIT_Q7_PTR: + s->tx_desc_addr[offset - R_TRANSMIT_Q1_PTR + 1] = val; break; - case GEM_RXSTATUS: + case R_RXSTATUS: gem_update_int_status(s); break; - case GEM_IER: - s->regs[GEM_IMR] &= ~val; + case R_IER: + s->regs[R_IMR] &= ~val; gem_update_int_status(s); break; - case GEM_JUMBO_MAX_LEN: - s->regs[GEM_JUMBO_MAX_LEN] = val & MAX_JUMBO_FRAME_SIZE_MASK; + case R_JUMBO_MAX_LEN: + s->regs[R_JUMBO_MAX_LEN] = val & MAX_JUMBO_FRAME_SIZE_MASK; break; - case GEM_INT_Q1_ENABLE ... GEM_INT_Q7_ENABLE: - s->regs[GEM_INT_Q1_MASK + offset - GEM_INT_Q1_ENABLE] &= ~val; + case R_INT_Q1_ENABLE ... R_INT_Q7_ENABLE: + s->regs[R_INT_Q1_MASK + offset - R_INT_Q1_ENABLE] &= ~val; gem_update_int_status(s); break; - case GEM_IDR: - s->regs[GEM_IMR] |= val; + case R_IDR: + s->regs[R_IMR] |= val; gem_update_int_status(s); break; - case GEM_INT_Q1_DISABLE ... GEM_INT_Q7_DISABLE: - s->regs[GEM_INT_Q1_MASK + offset - GEM_INT_Q1_DISABLE] |= val; + case R_INT_Q1_DISABLE ... R_INT_Q7_DISABLE: + s->regs[R_INT_Q1_MASK + offset - R_INT_Q1_DISABLE] |= val; gem_update_int_status(s); break; - case GEM_SPADDR1LO: - case GEM_SPADDR2LO: - case GEM_SPADDR3LO: - case GEM_SPADDR4LO: - s->sar_active[(offset - GEM_SPADDR1LO) / 2] = false; + case R_SPADDR1LO: + case R_SPADDR2LO: + case R_SPADDR3LO: + case R_SPADDR4LO: + s->sar_active[(offset - R_SPADDR1LO) / 2] = false; break; - case GEM_SPADDR1HI: - case GEM_SPADDR2HI: - case GEM_SPADDR3HI: - case GEM_SPADDR4HI: - s->sar_active[(offset - GEM_SPADDR1HI) / 2] = true; + case R_SPADDR1HI: + case R_SPADDR2HI: + case R_SPADDR3HI: + case R_SPADDR4HI: + s->sar_active[(offset - R_SPADDR1HI) / 2] = true; break; - case GEM_PHYMNTNC: + case R_PHYMNTNC: if (val & GEM_PHYMNTNC_OP_W) { uint32_t phy_addr, reg_num; From patchwork Fri Oct 27 14:39:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13455640 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1qwO0o-0008QL-Dv for mharc-qemu-devel@gnu.org; Fri, 27 Oct 2023 10:40:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qwO0M-0007Nf-HO for qemu-devel@nongnu.org; Fri, 27 Oct 2023 10:40:06 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qwO0I-0008Bm-KI for qemu-devel@nongnu.org; Fri, 27 Oct 2023 10:40:06 -0400 Received: by mail-wr1-x429.google.com with SMTP id ffacd0b85a97d-32f760cbff3so215292f8f.0 for ; Fri, 27 Oct 2023 07:40:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698417600; x=1699022400; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=51fi7MWk5kopwCoLjbMUmeiyXLaENty65AuGPZ0oGcs=; b=fuH0Juq/WTBnyTnUST578h+wiNZu8TP6b7atb2v28RyUVI3gavG2RoH2haWsfdHAuG 8749eG/eiTe0JxG7QfvKk2SHUHeMA+YwH7Mxj4bBz93jYr+85e3zHHBzTKofG28LxpzQ h3D3Xc/i/IlbrF0997onKOxe5OPngUscvEAbbhOOjr08ULeoNyA+BiIVr3sxxb2kpUcs JbuADztOEMIySZcg6DN2UHqxaFvY9ZlI7KTOjTgQ4GQR2rGcA//LM/gEf8KNYS4NUTt5 0ON1NdA8PzKB7SX+DkY4UDALrCPiWqXI3SJAdsqdKPofpcJR4TGSjlNrHNTRfRQtDNib 7jag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698417600; x=1699022400; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=51fi7MWk5kopwCoLjbMUmeiyXLaENty65AuGPZ0oGcs=; b=n+WaVZnyC+YduWdBi5SxNPYS0Qn+qUFOfJSP6yhV6TJfcxN7WMpfC14nABV/wGfKF0 8lz088y+dshZXoGDvfN3GO9oySI1uW20A3LGI1nn6hABBYQ1fTIO6Frnj6ioZWtR79Fm 9xlrNLfsC6VwrGZyGyS+hmbfa+s0SA3LLFip/fuZiGawDQ4f0uuK6RZOGM4FCY2+vmnw rgcpgxgE0v+u4z3UnIsXzHgdLaJJgL4aR+5QJcafpZu/49I5IEVFjmpVu7FzMJyNcPVR u9DIjPaGiylytnZhHDxISu+WSRL5t1A8IEeBpBR+c/+viOOWnyjzjZR6cdqGClFjXVKy IhzA== X-Gm-Message-State: AOJu0Yw/UYfhubD12QL4xPFiWKlT/DQUoSJ8g9xhdvUVeUqTLj1+00Y1 usyrSAP8i7RBiE29/1Dl9LjffK2HKiztF8mNOY0= X-Google-Smtp-Source: AGHT+IEl1SQsdwhkeLVEYEJPZWhwqWwtwOUc/g5JXhj703kDGnj3o111YGtdFNQ7yya1WsOfPkRmHA== X-Received: by 2002:adf:f98d:0:b0:32d:87c9:1181 with SMTP id f13-20020adff98d000000b0032d87c91181mr1850790wrr.48.1698417599903; Fri, 27 Oct 2023 07:39:59 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e2-20020a5d5002000000b0031c6581d55esm1874123wrt.91.2023.10.27.07.39.59 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Oct 2023 07:39:59 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 32/41] hw/net/cadence_gem: use FIELD for screening registers Date: Fri, 27 Oct 2023 15:39:33 +0100 Message-Id: <20231027143942.3413881-33-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231027143942.3413881-1-peter.maydell@linaro.org> References: <20231027143942.3413881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Oct 2023 14:40:07 -0000 From: Luc Michel Describe screening registers fields using the FIELD macros. Signed-off-by: Luc Michel Reviewed-by: sai.pavan.boddu@amd.com Message-id: 20231017194422.4124691-3-luc.michel@amd.com Signed-off-by: Peter Maydell --- hw/net/cadence_gem.c | 94 ++++++++++++++++++++++---------------------- 1 file changed, 48 insertions(+), 46 deletions(-) diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index bea2224dd8d..dd005562329 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cadence_gem.c @@ -170,35 +170,38 @@ REG32(INT_Q1_DISABLE, 0x620) REG32(INT_Q7_DISABLE, 0x638) REG32(SCREENING_TYPE1_REG0, 0x500) - -#define GEM_ST1R_UDP_PORT_MATCH_ENABLE (1 << 29) -#define GEM_ST1R_DSTC_ENABLE (1 << 28) -#define GEM_ST1R_UDP_PORT_MATCH_SHIFT (12) -#define GEM_ST1R_UDP_PORT_MATCH_WIDTH (27 - GEM_ST1R_UDP_PORT_MATCH_SHIFT + 1) -#define GEM_ST1R_DSTC_MATCH_SHIFT (4) -#define GEM_ST1R_DSTC_MATCH_WIDTH (11 - GEM_ST1R_DSTC_MATCH_SHIFT + 1) -#define GEM_ST1R_QUEUE_SHIFT (0) -#define GEM_ST1R_QUEUE_WIDTH (3 - GEM_ST1R_QUEUE_SHIFT + 1) + FIELD(SCREENING_TYPE1_REG0, QUEUE_NUM, 0, 4) + FIELD(SCREENING_TYPE1_REG0, DSTC_MATCH, 4, 8) + FIELD(SCREENING_TYPE1_REG0, UDP_PORT_MATCH, 12, 16) + FIELD(SCREENING_TYPE1_REG0, DSTC_ENABLE, 28, 1) + FIELD(SCREENING_TYPE1_REG0, UDP_PORT_MATCH_EN, 29, 1) + FIELD(SCREENING_TYPE1_REG0, DROP_ON_MATCH, 30, 1) REG32(SCREENING_TYPE2_REG0, 0x540) - -#define GEM_ST2R_COMPARE_A_ENABLE (1 << 18) -#define GEM_ST2R_COMPARE_A_SHIFT (13) -#define GEM_ST2R_COMPARE_WIDTH (17 - GEM_ST2R_COMPARE_A_SHIFT + 1) -#define GEM_ST2R_ETHERTYPE_ENABLE (1 << 12) -#define GEM_ST2R_ETHERTYPE_INDEX_SHIFT (9) -#define GEM_ST2R_ETHERTYPE_INDEX_WIDTH (11 - GEM_ST2R_ETHERTYPE_INDEX_SHIFT \ - + 1) -#define GEM_ST2R_QUEUE_SHIFT (0) -#define GEM_ST2R_QUEUE_WIDTH (3 - GEM_ST2R_QUEUE_SHIFT + 1) + FIELD(SCREENING_TYPE2_REG0, QUEUE_NUM, 0, 4) + FIELD(SCREENING_TYPE2_REG0, VLAN_PRIORITY, 4, 3) + FIELD(SCREENING_TYPE2_REG0, VLAN_ENABLE, 8, 1) + FIELD(SCREENING_TYPE2_REG0, ETHERTYPE_REG_INDEX, 9, 3) + FIELD(SCREENING_TYPE2_REG0, ETHERTYPE_ENABLE, 12, 1) + FIELD(SCREENING_TYPE2_REG0, COMPARE_A, 13, 5) + FIELD(SCREENING_TYPE2_REG0, COMPARE_A_ENABLE, 18, 1) + FIELD(SCREENING_TYPE2_REG0, COMPARE_B, 19, 5) + FIELD(SCREENING_TYPE2_REG0, COMPARE_B_ENABLE, 24, 1) + FIELD(SCREENING_TYPE2_REG0, COMPARE_C, 25, 5) + FIELD(SCREENING_TYPE2_REG0, COMPARE_C_ENABLE, 30, 1) + FIELD(SCREENING_TYPE2_REG0, DROP_ON_MATCH, 31, 1) REG32(SCREENING_TYPE2_ETHERTYPE_REG0, 0x6e0) -REG32(TYPE2_COMPARE_0_WORD_0, 0x700) -#define GEM_T2CW1_COMPARE_OFFSET_SHIFT (7) -#define GEM_T2CW1_COMPARE_OFFSET_WIDTH (8 - GEM_T2CW1_COMPARE_OFFSET_SHIFT + 1) -#define GEM_T2CW1_OFFSET_VALUE_SHIFT (0) -#define GEM_T2CW1_OFFSET_VALUE_WIDTH (6 - GEM_T2CW1_OFFSET_VALUE_SHIFT + 1) +REG32(TYPE2_COMPARE_0_WORD_0, 0x700) + FIELD(TYPE2_COMPARE_0_WORD_0, MASK_VALUE, 0, 16) + FIELD(TYPE2_COMPARE_0_WORD_0, COMPARE_VALUE, 16, 16) + +REG32(TYPE2_COMPARE_0_WORD_1, 0x704) + FIELD(TYPE2_COMPARE_0_WORD_1, OFFSET_VALUE, 0, 7) + FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_OFFSET, 7, 2) + FIELD(TYPE2_COMPARE_0_WORD_1, DISABLE_MASK, 9, 1) + FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_VLAN_ID, 10, 1) /*****************************************/ #define GEM_NWCTRL_TXSTART 0x00000200 /* Transmit Enable */ @@ -755,10 +758,9 @@ static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr, mismatched = false; /* Screening is based on UDP Port */ - if (reg & GEM_ST1R_UDP_PORT_MATCH_ENABLE) { + if (FIELD_EX32(reg, SCREENING_TYPE1_REG0, UDP_PORT_MATCH_EN)) { uint16_t udp_port = rxbuf_ptr[14 + 22] << 8 | rxbuf_ptr[14 + 23]; - if (udp_port == extract32(reg, GEM_ST1R_UDP_PORT_MATCH_SHIFT, - GEM_ST1R_UDP_PORT_MATCH_WIDTH)) { + if (udp_port == FIELD_EX32(reg, SCREENING_TYPE1_REG0, UDP_PORT_MATCH)) { matched = true; } else { mismatched = true; @@ -766,10 +768,9 @@ static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr, } /* Screening is based on DS/TC */ - if (reg & GEM_ST1R_DSTC_ENABLE) { + if (FIELD_EX32(reg, SCREENING_TYPE1_REG0, DSTC_ENABLE)) { uint8_t dscp = rxbuf_ptr[14 + 1]; - if (dscp == extract32(reg, GEM_ST1R_DSTC_MATCH_SHIFT, - GEM_ST1R_DSTC_MATCH_WIDTH)) { + if (dscp == FIELD_EX32(reg, SCREENING_TYPE1_REG0, DSTC_MATCH)) { matched = true; } else { mismatched = true; @@ -777,7 +778,7 @@ static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr, } if (matched && !mismatched) { - return extract32(reg, GEM_ST1R_QUEUE_SHIFT, GEM_ST1R_QUEUE_WIDTH); + return FIELD_EX32(reg, SCREENING_TYPE1_REG0, QUEUE_NUM); } } @@ -786,10 +787,10 @@ static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr, matched = false; mismatched = false; - if (reg & GEM_ST2R_ETHERTYPE_ENABLE) { + if (FIELD_EX32(reg, SCREENING_TYPE2_REG0, ETHERTYPE_ENABLE)) { uint16_t type = rxbuf_ptr[12] << 8 | rxbuf_ptr[13]; - int et_idx = extract32(reg, GEM_ST2R_ETHERTYPE_INDEX_SHIFT, - GEM_ST2R_ETHERTYPE_INDEX_WIDTH); + int et_idx = FIELD_EX32(reg, SCREENING_TYPE2_REG0, + ETHERTYPE_REG_INDEX); if (et_idx > s->num_type2_screeners) { qemu_log_mask(LOG_GUEST_ERROR, "Out of range ethertype " @@ -805,27 +806,27 @@ static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr, /* Compare A, B, C */ for (j = 0; j < 3; j++) { - uint32_t cr0, cr1, mask; + uint32_t cr0, cr1, mask, compare; uint16_t rx_cmp; int offset; - int cr_idx = extract32(reg, GEM_ST2R_COMPARE_A_SHIFT + j * 6, - GEM_ST2R_COMPARE_WIDTH); + int cr_idx = extract32(reg, R_SCREENING_TYPE2_REG0_COMPARE_A_SHIFT + j * 6, + R_SCREENING_TYPE2_REG0_COMPARE_A_LENGTH); - if (!(reg & (GEM_ST2R_COMPARE_A_ENABLE << (j * 6)))) { + if (!extract32(reg, R_SCREENING_TYPE2_REG0_COMPARE_A_ENABLE_SHIFT + j * 6, + R_SCREENING_TYPE2_REG0_COMPARE_A_ENABLE_LENGTH)) { continue; } + if (cr_idx > s->num_type2_screeners) { qemu_log_mask(LOG_GUEST_ERROR, "Out of range compare " "register index: %d\n", cr_idx); } cr0 = s->regs[R_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2]; - cr1 = s->regs[R_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2 + 1]; - offset = extract32(cr1, GEM_T2CW1_OFFSET_VALUE_SHIFT, - GEM_T2CW1_OFFSET_VALUE_WIDTH); + cr1 = s->regs[R_TYPE2_COMPARE_0_WORD_1 + cr_idx * 2]; + offset = FIELD_EX32(cr1, TYPE2_COMPARE_0_WORD_1, OFFSET_VALUE); - switch (extract32(cr1, GEM_T2CW1_COMPARE_OFFSET_SHIFT, - GEM_T2CW1_COMPARE_OFFSET_WIDTH)) { + switch (FIELD_EX32(cr1, TYPE2_COMPARE_0_WORD_1, COMPARE_OFFSET)) { case 3: /* Skip UDP header */ qemu_log_mask(LOG_UNIMP, "TCP compare offsets" "unimplemented - assuming UDP\n"); @@ -843,9 +844,10 @@ static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr, } rx_cmp = rxbuf_ptr[offset] << 8 | rxbuf_ptr[offset]; - mask = extract32(cr0, 0, 16); + mask = FIELD_EX32(cr0, TYPE2_COMPARE_0_WORD_0, MASK_VALUE); + compare = FIELD_EX32(cr0, TYPE2_COMPARE_0_WORD_0, COMPARE_VALUE); - if ((rx_cmp & mask) == (extract32(cr0, 16, 16) & mask)) { + if ((rx_cmp & mask) == (compare & mask)) { matched = true; } else { mismatched = true; @@ -853,7 +855,7 @@ static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr, } if (matched && !mismatched) { - return extract32(reg, GEM_ST2R_QUEUE_SHIFT, GEM_ST2R_QUEUE_WIDTH); + return FIELD_EX32(reg, SCREENING_TYPE2_REG0, QUEUE_NUM); } } From patchwork Fri Oct 27 14:39:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13455642 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1qwO0p-00007C-84 for mharc-qemu-devel@gnu.org; Fri, 27 Oct 2023 10:40:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qwO0O-0007Om-Lb for qemu-devel@nongnu.org; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e2-20020a5d5002000000b0031c6581d55esm1874123wrt.91.2023.10.27.07.40.00 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Oct 2023 07:40:00 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 33/41] hw/net/cadence_gem: use FIELD to describe NWCTRL register fields Date: Fri, 27 Oct 2023 15:39:34 +0100 Message-Id: <20231027143942.3413881-34-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231027143942.3413881-1-peter.maydell@linaro.org> References: <20231027143942.3413881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::229; envelope-from=peter.maydell@linaro.org; helo=mail-lj1-x229.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Oct 2023 14:40:12 -0000 From: Luc Michel Use the FIELD macro to describe the NWCTRL register fields. Signed-off-by: Luc Michel Reviewed-by: sai.pavan.boddu@amd.com Message-id: 20231017194422.4124691-4-luc.michel@amd.com Signed-off-by: Peter Maydell --- hw/net/cadence_gem.c | 53 +++++++++++++++++++++++++++++++++----------- 1 file changed, 40 insertions(+), 13 deletions(-) diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index dd005562329..1bcc9b6811b 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cadence_gem.c @@ -46,6 +46,38 @@ } while (0) REG32(NWCTRL, 0x0) /* Network Control reg */ + FIELD(NWCTRL, LOOPBACK , 0, 1) + FIELD(NWCTRL, LOOPBACK_LOCAL , 1, 1) + FIELD(NWCTRL, ENABLE_RECEIVE, 2, 1) + FIELD(NWCTRL, ENABLE_TRANSMIT, 3, 1) + FIELD(NWCTRL, MAN_PORT_EN , 4, 1) + FIELD(NWCTRL, CLEAR_ALL_STATS_REGS , 5, 1) + FIELD(NWCTRL, INC_ALL_STATS_REGS, 6, 1) + FIELD(NWCTRL, STATS_WRITE_EN, 7, 1) + FIELD(NWCTRL, BACK_PRESSURE, 8, 1) + FIELD(NWCTRL, TRANSMIT_START , 9, 1) + FIELD(NWCTRL, TRANSMIT_HALT, 10, 1) + FIELD(NWCTRL, TX_PAUSE_FRAME_RE, 11, 1) + FIELD(NWCTRL, TX_PAUSE_FRAME_ZE, 12, 1) + FIELD(NWCTRL, STATS_TAKE_SNAP, 13, 1) + FIELD(NWCTRL, STATS_READ_SNAP, 14, 1) + FIELD(NWCTRL, STORE_RX_TS, 15, 1) + FIELD(NWCTRL, PFC_ENABLE, 16, 1) + FIELD(NWCTRL, PFC_PRIO_BASED, 17, 1) + FIELD(NWCTRL, FLUSH_RX_PKT_PCLK , 18, 1) + FIELD(NWCTRL, TX_LPI_EN, 19, 1) + FIELD(NWCTRL, PTP_UNICAST_ENA, 20, 1) + FIELD(NWCTRL, ALT_SGMII_MODE, 21, 1) + FIELD(NWCTRL, STORE_UDP_OFFSET, 22, 1) + FIELD(NWCTRL, EXT_TSU_PORT_EN, 23, 1) + FIELD(NWCTRL, ONE_STEP_SYNC_MO, 24, 1) + FIELD(NWCTRL, PFC_CTRL , 25, 1) + FIELD(NWCTRL, EXT_RXQ_SEL_EN , 26, 1) + FIELD(NWCTRL, OSS_CORRECTION_FIELD, 27, 1) + FIELD(NWCTRL, SEL_MII_ON_RGMII, 28, 1) + FIELD(NWCTRL, TWO_PT_FIVE_GIG, 29, 1) + FIELD(NWCTRL, IFG_EATS_QAV_CREDIT, 30, 1) + REG32(NWCFG, 0x4) /* Network Config reg */ REG32(NWSTATUS, 0x8) /* Network Status reg */ REG32(USERIO, 0xc) /* User IO reg */ @@ -204,11 +236,6 @@ REG32(TYPE2_COMPARE_0_WORD_1, 0x704) FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_VLAN_ID, 10, 1) /*****************************************/ -#define GEM_NWCTRL_TXSTART 0x00000200 /* Transmit Enable */ -#define GEM_NWCTRL_TXENA 0x00000008 /* Transmit Enable */ -#define GEM_NWCTRL_RXENA 0x00000004 /* Receive Enable */ -#define GEM_NWCTRL_LOCALLOOP 0x00000002 /* Local Loopback */ - #define GEM_NWCFG_STRIP_FCS 0x00020000 /* Strip FCS field */ #define GEM_NWCFG_LERR_DISC 0x00010000 /* Discard RX frames with len err */ #define GEM_NWCFG_BUFF_OFST_M 0x0000C000 /* Receive buffer offset mask */ @@ -560,7 +587,7 @@ static bool gem_can_receive(NetClientState *nc) s = qemu_get_nic_opaque(nc); /* Do nothing if receive is not enabled. */ - if (!(s->regs[R_NWCTRL] & GEM_NWCTRL_RXENA)) { + if (!FIELD_EX32(s->regs[R_NWCTRL], NWCTRL, ENABLE_RECEIVE)) { if (s->can_rx_state != 1) { s->can_rx_state = 1; DB_PRINT("can't receive - no enable\n"); @@ -1173,7 +1200,7 @@ static void gem_transmit(CadenceGEMState *s) int q = 0; /* Do nothing if transmit is not enabled. */ - if (!(s->regs[R_NWCTRL] & GEM_NWCTRL_TXENA)) { + if (!FIELD_EX32(s->regs[R_NWCTRL], NWCTRL, ENABLE_TRANSMIT)) { return; } @@ -1198,7 +1225,7 @@ static void gem_transmit(CadenceGEMState *s) while (tx_desc_get_used(desc) == 0) { /* Do nothing if transmit is not enabled. */ - if (!(s->regs[R_NWCTRL] & GEM_NWCTRL_TXENA)) { + if (!FIELD_EX32(s->regs[R_NWCTRL], NWCTRL, ENABLE_TRANSMIT)) { return; } print_gem_tx_desc(desc, q); @@ -1271,8 +1298,8 @@ static void gem_transmit(CadenceGEMState *s) gem_transmit_updatestats(s, s->tx_packet, total_bytes); /* Send the packet somewhere */ - if (s->phy_loop || (s->regs[R_NWCTRL] & - GEM_NWCTRL_LOCALLOOP)) { + if (s->phy_loop || FIELD_EX32(s->regs[R_NWCTRL], NWCTRL, + LOOPBACK_LOCAL)) { qemu_receive_packet(qemu_get_queue(s->nic), s->tx_packet, total_bytes); } else { @@ -1493,15 +1520,15 @@ static void gem_write(void *opaque, hwaddr offset, uint64_t val, /* Handle register write side effects */ switch (offset) { case R_NWCTRL: - if (val & GEM_NWCTRL_RXENA) { + if (FIELD_EX32(val, NWCTRL, ENABLE_RECEIVE)) { for (i = 0; i < s->num_priority_queues; ++i) { gem_get_rx_desc(s, i); } } - if (val & GEM_NWCTRL_TXSTART) { + if (FIELD_EX32(val, NWCTRL, TRANSMIT_START)) { gem_transmit(s); } - if (!(val & GEM_NWCTRL_TXENA)) { + if (!(FIELD_EX32(val, NWCTRL, ENABLE_TRANSMIT))) { /* Reset to start of Q when transmit disabled. */ for (i = 0; i < s->num_priority_queues; i++) { s->tx_desc_addr[i] = gem_get_tx_queue_base_addr(s, i); From patchwork Fri Oct 27 14:39:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13455657 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1qwO0r-0000Ow-13 for mharc-qemu-devel@gnu.org; Fri, 27 Oct 2023 10:40:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qwO0P-0007Oj-4u for qemu-devel@nongnu.org; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e2-20020a5d5002000000b0031c6581d55esm1874123wrt.91.2023.10.27.07.40.00 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Oct 2023 07:40:00 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 34/41] hw/net/cadence_gem: use FIELD to describe NWCFG register fields Date: Fri, 27 Oct 2023 15:39:35 +0100 Message-Id: <20231027143942.3413881-35-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231027143942.3413881-1-peter.maydell@linaro.org> References: <20231027143942.3413881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Oct 2023 14:40:12 -0000 From: Luc Michel Use de FIELD macro to describe the NWCFG register fields. Signed-off-by: Luc Michel Reviewed-by: sai.pavan.boddu@amd.com Message-id: 20231017194422.4124691-5-luc.michel@amd.com Signed-off-by: Peter Maydell --- hw/net/cadence_gem.c | 60 ++++++++++++++++++++++++++++---------------- 1 file changed, 39 insertions(+), 21 deletions(-) diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index 1bcc9b6811b..cf8b1261ed5 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cadence_gem.c @@ -79,6 +79,35 @@ REG32(NWCTRL, 0x0) /* Network Control reg */ FIELD(NWCTRL, IFG_EATS_QAV_CREDIT, 30, 1) REG32(NWCFG, 0x4) /* Network Config reg */ + FIELD(NWCFG, SPEED, 0, 1) + FIELD(NWCFG, FULL_DUPLEX, 1, 1) + FIELD(NWCFG, DISCARD_NON_VLAN_FRAMES, 2, 1) + FIELD(NWCFG, JUMBO_FRAMES, 3, 1) + FIELD(NWCFG, PROMISC, 4, 1) + FIELD(NWCFG, NO_BROADCAST, 5, 1) + FIELD(NWCFG, MULTICAST_HASH_EN, 6, 1) + FIELD(NWCFG, UNICAST_HASH_EN, 7, 1) + FIELD(NWCFG, RECV_1536_BYTE_FRAMES, 8, 1) + FIELD(NWCFG, EXTERNAL_ADDR_MATCH_EN, 9, 1) + FIELD(NWCFG, GIGABIT_MODE_ENABLE, 10, 1) + FIELD(NWCFG, PCS_SELECT, 11, 1) + FIELD(NWCFG, RETRY_TEST, 12, 1) + FIELD(NWCFG, PAUSE_ENABLE, 13, 1) + FIELD(NWCFG, RECV_BUF_OFFSET, 14, 2) + FIELD(NWCFG, LEN_ERR_DISCARD, 16, 1) + FIELD(NWCFG, FCS_REMOVE, 17, 1) + FIELD(NWCFG, MDC_CLOCK_DIV, 18, 3) + FIELD(NWCFG, DATA_BUS_WIDTH, 21, 2) + FIELD(NWCFG, DISABLE_COPY_PAUSE_FRAMES, 23, 1) + FIELD(NWCFG, RECV_CSUM_OFFLOAD_EN, 24, 1) + FIELD(NWCFG, EN_HALF_DUPLEX_RX, 25, 1) + FIELD(NWCFG, IGNORE_RX_FCS, 26, 1) + FIELD(NWCFG, SGMII_MODE_ENABLE, 27, 1) + FIELD(NWCFG, IPG_STRETCH_ENABLE, 28, 1) + FIELD(NWCFG, NSP_ACCEPT, 29, 1) + FIELD(NWCFG, IGNORE_IPG_RX_ER, 30, 1) + FIELD(NWCFG, UNI_DIRECTION_ENABLE, 31, 1) + REG32(NWSTATUS, 0x8) /* Network Status reg */ REG32(USERIO, 0xc) /* User IO reg */ REG32(DMACFG, 0x10) /* DMA Control reg */ @@ -236,17 +265,6 @@ REG32(TYPE2_COMPARE_0_WORD_1, 0x704) FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_VLAN_ID, 10, 1) /*****************************************/ -#define GEM_NWCFG_STRIP_FCS 0x00020000 /* Strip FCS field */ -#define GEM_NWCFG_LERR_DISC 0x00010000 /* Discard RX frames with len err */ -#define GEM_NWCFG_BUFF_OFST_M 0x0000C000 /* Receive buffer offset mask */ -#define GEM_NWCFG_BUFF_OFST_S 14 /* Receive buffer offset shift */ -#define GEM_NWCFG_RCV_1538 0x00000100 /* Receive 1538 bytes frame */ -#define GEM_NWCFG_UCAST_HASH 0x00000080 /* accept unicast if hash match */ -#define GEM_NWCFG_MCAST_HASH 0x00000040 /* accept multicast if hash match */ -#define GEM_NWCFG_BCAST_REJ 0x00000020 /* Reject broadcast packets */ -#define GEM_NWCFG_PROMISC 0x00000010 /* Accept all packets */ -#define GEM_NWCFG_JUMBO_FRAME 0x00000008 /* Jumbo Frames enable */ - #define GEM_DMACFG_ADDR_64B (1U << 30) #define GEM_DMACFG_TX_BD_EXT (1U << 29) #define GEM_DMACFG_RX_BD_EXT (1U << 28) @@ -482,7 +500,7 @@ static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; static uint32_t gem_get_max_buf_len(CadenceGEMState *s, bool tx) { uint32_t size; - if (s->regs[R_NWCFG] & GEM_NWCFG_JUMBO_FRAME) { + if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, JUMBO_FRAMES)) { size = s->regs[R_JUMBO_MAX_LEN]; if (size > s->jumbo_max_len) { size = s->jumbo_max_len; @@ -492,7 +510,8 @@ static uint32_t gem_get_max_buf_len(CadenceGEMState *s, bool tx) } else if (tx) { size = 1518; } else { - size = s->regs[R_NWCFG] & GEM_NWCFG_RCV_1538 ? 1538 : 1518; + size = FIELD_EX32(s->regs[R_NWCFG], + NWCFG, RECV_1536_BYTE_FRAMES) ? 1538 : 1518; } return size; } @@ -732,13 +751,13 @@ static int gem_mac_address_filter(CadenceGEMState *s, const uint8_t *packet) int i, is_mc; /* Promiscuous mode? */ - if (s->regs[R_NWCFG] & GEM_NWCFG_PROMISC) { + if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, PROMISC)) { return GEM_RX_PROMISCUOUS_ACCEPT; } if (!memcmp(packet, broadcast_addr, 6)) { /* Reject broadcast packets? */ - if (s->regs[R_NWCFG] & GEM_NWCFG_BCAST_REJ) { + if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, NO_BROADCAST)) { return GEM_RX_REJECT; } return GEM_RX_BROADCAST_ACCEPT; @@ -746,8 +765,8 @@ static int gem_mac_address_filter(CadenceGEMState *s, const uint8_t *packet) /* Accept packets -w- hash match? */ is_mc = is_multicast_ether_addr(packet); - if ((is_mc && (s->regs[R_NWCFG] & GEM_NWCFG_MCAST_HASH)) || - (!is_mc && (s->regs[R_NWCFG] & GEM_NWCFG_UCAST_HASH))) { + if ((is_mc && (FIELD_EX32(s->regs[R_NWCFG], NWCFG, MULTICAST_HASH_EN))) || + (!is_mc && FIELD_EX32(s->regs[R_NWCFG], NWCFG, UNICAST_HASH_EN))) { uint64_t buckets; unsigned hash_index; @@ -983,7 +1002,7 @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size) } /* Discard packets with receive length error enabled ? */ - if (s->regs[R_NWCFG] & GEM_NWCFG_LERR_DISC) { + if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, LEN_ERR_DISCARD)) { unsigned type_len; /* Fish the ethertype / length field out of the RX packet */ @@ -1000,8 +1019,7 @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size) /* * Determine configured receive buffer offset (probably 0) */ - rxbuf_offset = (s->regs[R_NWCFG] & GEM_NWCFG_BUFF_OFST_M) >> - GEM_NWCFG_BUFF_OFST_S; + rxbuf_offset = FIELD_EX32(s->regs[R_NWCFG], NWCFG, RECV_BUF_OFFSET); /* The configure size of each receive buffer. Determines how many * buffers needed to hold this packet. @@ -1026,7 +1044,7 @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size) } /* Strip of FCS field ? (usually yes) */ - if (s->regs[R_NWCFG] & GEM_NWCFG_STRIP_FCS) { + if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, FCS_REMOVE)) { rxbuf_ptr = (void *)buf; } else { unsigned crc_val; From patchwork Fri Oct 27 14:39:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13455658 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1qwO0t-0000nW-QW for mharc-qemu-devel@gnu.org; Fri, 27 Oct 2023 10:40:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qwO0P-0007Ol-Kh for qemu-devel@nongnu.org; Fri, 27 Oct 2023 10:40:12 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qwO0J-0008Du-H4 for qemu-devel@nongnu.org; Fri, 27 Oct 2023 10:40:08 -0400 Received: by mail-wr1-x42b.google.com with SMTP id ffacd0b85a97d-32da4ffd7e5so1293110f8f.0 for ; Fri, 27 Oct 2023 07:40:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698417601; x=1699022401; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=69Xdi2XBUCVbdo4LLU2JuEwOaiPWz+F25ncB1rn8HfE=; b=qc/69B+0JAn5Ula0SQkclyFagw8a4JWokWGtJoH3qxOhYUXywpm6DhUmpKRiRXDlFc HiMxF7OP1XOgV/y29ovEK/87f3TMBMPf9B8gvTLILsn+iMvqFTQGdfB+3+DB53i2+SbJ ozRBketF+c/YgbEQTu1jBWDzU28bLT4F1vLZ+ilXQPkdSkVTI54bhz5nEjF3BtE86z0h KfcuJTWMgnVJBiwsZYsl+H5C2Lh9lzDvCC6G25kF9tu2Rqdss5TjKZjm40fQj8L9CkDN YGVOZrdRCKx3wgv1SfAyq5CtJnZtToOZqVvxdXlYdxQwwukp6EXrlm8MMGl8BKAMisvu MdvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698417601; x=1699022401; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=69Xdi2XBUCVbdo4LLU2JuEwOaiPWz+F25ncB1rn8HfE=; b=IyCUJojGYkBdHh2NQL3zpZS7OipuBJJRxJ6KJGp3zCKWQrHNd9xOQ/1E12AX8Cj3K2 ETNPgx45XtFukRiEkhCMI7vHIJ15Ah0p+TUe1eOhZanw/gbzHC5kL3ABo7xUfAYBLGMJ GJWXd9Z12LjYZRpDSVCoMRHkoPdN4eIaabiMNHAQrUZeWXn2Alhv+lgIgSGZpUt3I3Il 4jGltktlSWGm6hJ+JSiY/gWplgXl98vDAHohsDoagBc56GG9Y7Z2xBNpUdMg7QH4uBSt VJ3HiBV8Pfuw5b1rWIgvAmjlD2f0LVlKM20tD5KnMDyeRjLkyc5JOZVhMbmDditPUPDe cvig== X-Gm-Message-State: AOJu0Yx0lufzUnREmVMWGSV8N5YMvfdfu7DxvlLi5CThHbpn5BF4bDi4 u+4ChnqT7l2GiyxpEvd/EfDIYVlA0hQzSo4khCY= X-Google-Smtp-Source: AGHT+IHH+fLCUx/YQxQr489nOPtaoKGpeZdGxjY6EbxtNmk5FNTAHW4FW2RCMXFX/BiOdGsn9uy6GQ== X-Received: by 2002:a5d:5850:0:b0:32f:7341:96bb with SMTP id i16-20020a5d5850000000b0032f734196bbmr1711857wrf.19.1698417601373; Fri, 27 Oct 2023 07:40:01 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e2-20020a5d5002000000b0031c6581d55esm1874123wrt.91.2023.10.27.07.40.01 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Oct 2023 07:40:01 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 35/41] hw/net/cadence_gem: use FIELD to describe DMACFG register fields Date: Fri, 27 Oct 2023 15:39:36 +0100 Message-Id: <20231027143942.3413881-36-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231027143942.3413881-1-peter.maydell@linaro.org> References: <20231027143942.3413881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Oct 2023 14:40:12 -0000 From: Luc Michel Use de FIELD macro to describe the DMACFG register fields. Signed-off-by: Luc Michel Reviewed-by: sai.pavan.boddu@amd.com Message-id: 20231017194422.4124691-6-luc.michel@amd.com Signed-off-by: Peter Maydell --- hw/net/cadence_gem.c | 48 ++++++++++++++++++++++++++++---------------- 1 file changed, 31 insertions(+), 17 deletions(-) diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index cf8b1261ed5..e3724b84471 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cadence_gem.c @@ -110,7 +110,27 @@ REG32(NWCFG, 0x4) /* Network Config reg */ REG32(NWSTATUS, 0x8) /* Network Status reg */ REG32(USERIO, 0xc) /* User IO reg */ + REG32(DMACFG, 0x10) /* DMA Control reg */ + FIELD(DMACFG, SEND_BCAST_TO_ALL_QS, 31, 1) + FIELD(DMACFG, DMA_ADDR_BUS_WIDTH, 30, 1) + FIELD(DMACFG, TX_BD_EXT_MODE_EN , 29, 1) + FIELD(DMACFG, RX_BD_EXT_MODE_EN , 28, 1) + FIELD(DMACFG, FORCE_MAX_AMBA_BURST_TX, 26, 1) + FIELD(DMACFG, FORCE_MAX_AMBA_BURST_RX, 25, 1) + FIELD(DMACFG, FORCE_DISCARD_ON_ERR, 24, 1) + FIELD(DMACFG, RX_BUF_SIZE, 16, 8) + FIELD(DMACFG, CRC_ERROR_REPORT, 13, 1) + FIELD(DMACFG, INF_LAST_DBUF_SIZE_EN, 12, 1) + FIELD(DMACFG, TX_PBUF_CSUM_OFFLOAD, 11, 1) + FIELD(DMACFG, TX_PBUF_SIZE, 10, 1) + FIELD(DMACFG, RX_PBUF_SIZE, 8, 2) + FIELD(DMACFG, ENDIAN_SWAP_PACKET, 7, 1) + FIELD(DMACFG, ENDIAN_SWAP_MGNT, 6, 1) + FIELD(DMACFG, HDR_DATA_SPLIT_EN, 5, 1) + FIELD(DMACFG, AMBA_BURST_LEN , 0, 5) +#define GEM_DMACFG_RBUFSZ_MUL 64 /* DMA RX Buffer Size multiplier */ + REG32(TXSTATUS, 0x14) /* TX Status reg */ REG32(RXQBASE, 0x18) /* RX Q Base address reg */ REG32(TXQBASE, 0x1c) /* TX Q Base address reg */ @@ -265,13 +285,6 @@ REG32(TYPE2_COMPARE_0_WORD_1, 0x704) FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_VLAN_ID, 10, 1) /*****************************************/ -#define GEM_DMACFG_ADDR_64B (1U << 30) -#define GEM_DMACFG_TX_BD_EXT (1U << 29) -#define GEM_DMACFG_RX_BD_EXT (1U << 28) -#define GEM_DMACFG_RBUFSZ_M 0x00FF0000 /* DMA RX Buffer Size mask */ -#define GEM_DMACFG_RBUFSZ_S 16 /* DMA RX Buffer Size shift */ -#define GEM_DMACFG_RBUFSZ_MUL 64 /* DMA RX Buffer Size multiplier */ -#define GEM_DMACFG_TXCSUM_OFFL 0x00000800 /* Transmit checksum offload */ #define GEM_TXSTATUS_TXCMPL 0x00000020 /* Transmit Complete */ #define GEM_TXSTATUS_USED 0x00000001 /* sw owned descriptor encountered */ @@ -369,7 +382,7 @@ static inline uint64_t tx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc) { uint64_t ret = desc[0]; - if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) { + if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) { ret |= (uint64_t)desc[2] << 32; } return ret; @@ -414,7 +427,7 @@ static inline uint64_t rx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc) { uint64_t ret = desc[0] & ~0x3UL; - if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) { + if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) { ret |= (uint64_t)desc[2] << 32; } return ret; @@ -424,11 +437,11 @@ static inline int gem_get_desc_len(CadenceGEMState *s, bool rx_n_tx) { int ret = 2; - if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) { + if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) { ret += 2; } - if (s->regs[R_DMACFG] & (rx_n_tx ? GEM_DMACFG_RX_BD_EXT - : GEM_DMACFG_TX_BD_EXT)) { + if (s->regs[R_DMACFG] & (rx_n_tx ? R_DMACFG_RX_BD_EXT_MODE_EN_MASK + : R_DMACFG_TX_BD_EXT_MODE_EN_MASK)) { ret += 2; } @@ -942,7 +955,7 @@ static hwaddr gem_get_desc_addr(CadenceGEMState *s, bool tx, int q) { hwaddr desc_addr = 0; - if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) { + if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) { desc_addr = s->regs[tx ? R_TBQPH : R_RBQPH]; } desc_addr <<= 32; @@ -1024,8 +1037,9 @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size) /* The configure size of each receive buffer. Determines how many * buffers needed to hold this packet. */ - rxbufsize = ((s->regs[R_DMACFG] & GEM_DMACFG_RBUFSZ_M) >> - GEM_DMACFG_RBUFSZ_S) * GEM_DMACFG_RBUFSZ_MUL; + rxbufsize = FIELD_EX32(s->regs[R_DMACFG], DMACFG, RX_BUF_SIZE); + rxbufsize *= GEM_DMACFG_RBUFSZ_MUL; + bytes_to_copy = size; /* Hardware allows a zero value here but warns against it. To avoid QEMU @@ -1308,7 +1322,7 @@ static void gem_transmit(CadenceGEMState *s) gem_update_int_status(s); /* Is checksum offload enabled? */ - if (s->regs[R_DMACFG] & GEM_DMACFG_TXCSUM_OFFL) { + if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, TX_PBUF_CSUM_OFFLOAD)) { net_checksum_calculate(s->tx_packet, total_bytes, CSUM_ALL); } @@ -1332,7 +1346,7 @@ static void gem_transmit(CadenceGEMState *s) /* read next descriptor */ if (tx_desc_get_wrap(desc)) { - if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) { + if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) { packet_desc_addr = s->regs[R_TBQPH]; packet_desc_addr <<= 32; } else { From patchwork Fri Oct 27 14:39:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13455656 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1qwO0x-0001Ki-Qu for mharc-qemu-devel@gnu.org; Fri, 27 Oct 2023 10:40:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qwO0O-0007Ok-7e for qemu-devel@nongnu.org; Fri, 27 Oct 2023 10:40:10 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qwO0J-0008Eq-H1 for qemu-devel@nongnu.org; Fri, 27 Oct 2023 10:40:07 -0400 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-4084de32db5so17644295e9.0 for ; Fri, 27 Oct 2023 07:40:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698417602; x=1699022402; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=gBpbMgx0c2MAw8YGawXL3AambNIZsBraLqNnstbmnvw=; b=uuNOck1icS+M+n6KF3AEZJbCLKPsbTauHof1K+dkB6RO7cmXPvZtN1qgJjdbbnWYZf nAQHa42bIqPtEB3T9YyyA+3TF4k2I2wECsrwNnnTJz/DE1nN4e+ej+puw2a5ZoRhy6J8 YkSqpNC5S1B0oZCC2bIlllrUiNU031WajvqT9Jnp/AsH62dW6mrCKDk8rR8nZN42MT66 iF3Gbc2ansEU60Hq4Ru/2zIuL3077LjVUihWA5z87KThaXZa2YhpdB6CEg2TBkV+Cvf1 OHTgU4WPfpxXmVbupXNiEfzrWdly/btgw6lpH2FxS68oXqOZfxigUX5s5hch7xR0X3B9 KG+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698417602; x=1699022402; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gBpbMgx0c2MAw8YGawXL3AambNIZsBraLqNnstbmnvw=; b=siM7Ovbsstu/uXb003eSotf9nGzfzT6JAGlIUvFVv7xZF/XBt7w6VCPu1nrCJzPLXY dnW7qh91cux7HvVKvZ7QM7C76mT8+Fl58RCO0bQv3A4LQLvkHS3kCsVOKzW3JdhGyynQ knDFrCOb11lk0RyvMDIl+edztrWG61lBfM65exvZL6dbo/ynDKWh7Ji2UVkB+EjvPjqg oPUmK/P3Y51e0gp8waZ9z+JrxtIy8JMAFtIXnPHOdJ/BfxbzwJj0pcxeyU55C92+YrBf w1/EtxMo9wQfM4huy5v9Jo/Ckl3CiCcW9t4PcZ8gsjAR1v2IVNhbuPUbRugFFrOW+t55 KYIA== X-Gm-Message-State: AOJu0YweBDfFZdbJDWv33kDi5PdoX0LWTi3yXgiIbCIauszfNvRfqMro OUyj9JR12XBh+j/PWaex7NZFdaWw8mEy48vffAY= X-Google-Smtp-Source: AGHT+IGeDQDIDFyGevgwB2wT4yqqJnOw/pMKBo9ARkrOgiNtJJFK4DrS+WZZQ/nZ0ISrdODQ2vF7jg== X-Received: by 2002:a05:600c:19d1:b0:401:be5a:989 with SMTP id u17-20020a05600c19d100b00401be5a0989mr2212382wmq.23.1698417601798; Fri, 27 Oct 2023 07:40:01 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e2-20020a5d5002000000b0031c6581d55esm1874123wrt.91.2023.10.27.07.40.01 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Oct 2023 07:40:01 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 36/41] hw/net/cadence_gem: use FIELD to describe [TX|RX]STATUS register fields Date: Fri, 27 Oct 2023 15:39:37 +0100 Message-Id: <20231027143942.3413881-37-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231027143942.3413881-1-peter.maydell@linaro.org> References: <20231027143942.3413881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Oct 2023 14:40:12 -0000 From: Luc Michel Use de FIELD macro to describe the TXSTATUS and RXSTATUS register fields. Signed-off-by: Luc Michel Reviewed-by: sai.pavan.boddu@amd.com Message-id: 20231017194422.4124691-7-luc.michel@amd.com Signed-off-by: Peter Maydell --- hw/net/cadence_gem.c | 34 +++++++++++++++++++++++++--------- 1 file changed, 25 insertions(+), 9 deletions(-) diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index e3724b84471..d7fdc775146 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cadence_gem.c @@ -132,9 +132,30 @@ REG32(DMACFG, 0x10) /* DMA Control reg */ #define GEM_DMACFG_RBUFSZ_MUL 64 /* DMA RX Buffer Size multiplier */ REG32(TXSTATUS, 0x14) /* TX Status reg */ + FIELD(TXSTATUS, TX_USED_BIT_READ_MIDFRAME, 12, 1) + FIELD(TXSTATUS, TX_FRAME_TOO_LARGE, 11, 1) + FIELD(TXSTATUS, TX_DMA_LOCKUP, 10, 1) + FIELD(TXSTATUS, TX_MAC_LOCKUP, 9, 1) + FIELD(TXSTATUS, RESP_NOT_OK, 8, 1) + FIELD(TXSTATUS, LATE_COLLISION, 7, 1) + FIELD(TXSTATUS, TRANSMIT_UNDER_RUN, 6, 1) + FIELD(TXSTATUS, TRANSMIT_COMPLETE, 5, 1) + FIELD(TXSTATUS, AMBA_ERROR, 4, 1) + FIELD(TXSTATUS, TRANSMIT_GO, 3, 1) + FIELD(TXSTATUS, RETRY_LIMIT, 2, 1) + FIELD(TXSTATUS, COLLISION, 1, 1) + FIELD(TXSTATUS, USED_BIT_READ, 0, 1) + REG32(RXQBASE, 0x18) /* RX Q Base address reg */ REG32(TXQBASE, 0x1c) /* TX Q Base address reg */ REG32(RXSTATUS, 0x20) /* RX Status reg */ + FIELD(RXSTATUS, RX_DMA_LOCKUP, 5, 1) + FIELD(RXSTATUS, RX_MAC_LOCKUP, 4, 1) + FIELD(RXSTATUS, RESP_NOT_OK, 3, 1) + FIELD(RXSTATUS, RECEIVE_OVERRUN, 2, 1) + FIELD(RXSTATUS, FRAME_RECEIVED, 1, 1) + FIELD(RXSTATUS, BUF_NOT_AVAILABLE, 0, 1) + REG32(ISR, 0x24) /* Interrupt Status reg */ REG32(IER, 0x28) /* Interrupt Enable reg */ REG32(IDR, 0x2c) /* Interrupt Disable reg */ @@ -286,11 +307,6 @@ REG32(TYPE2_COMPARE_0_WORD_1, 0x704) /*****************************************/ -#define GEM_TXSTATUS_TXCMPL 0x00000020 /* Transmit Complete */ -#define GEM_TXSTATUS_USED 0x00000001 /* sw owned descriptor encountered */ - -#define GEM_RXSTATUS_FRMRCVD 0x00000002 /* Frame received */ -#define GEM_RXSTATUS_NOBUF 0x00000001 /* Buffer unavailable */ /* GEM_ISR GEM_IER GEM_IDR GEM_IMR */ #define GEM_INT_TXCMPL 0x00000080 /* Transmit Complete */ @@ -987,7 +1003,7 @@ static void gem_get_rx_desc(CadenceGEMState *s, int q) /* Descriptor owned by software ? */ if (rx_desc_get_ownership(s->rx_desc[q]) == 1) { DB_PRINT("descriptor 0x%" HWADDR_PRIx " owned by sw.\n", desc_addr); - s->regs[R_RXSTATUS] |= GEM_RXSTATUS_NOBUF; + s->regs[R_RXSTATUS] |= R_RXSTATUS_BUF_NOT_AVAILABLE_MASK; gem_set_isr(s, q, GEM_INT_RXUSED); /* Handle interrupt consequences */ gem_update_int_status(s); @@ -1164,7 +1180,7 @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size) /* Count it */ gem_receive_updatestats(s, buf, size); - s->regs[R_RXSTATUS] |= GEM_RXSTATUS_FRMRCVD; + s->regs[R_RXSTATUS] |= R_RXSTATUS_FRAME_RECEIVED_MASK; gem_set_isr(s, q, GEM_INT_RXCMPL); /* Handle interrupt consequences */ @@ -1315,7 +1331,7 @@ static void gem_transmit(CadenceGEMState *s) } DB_PRINT("TX descriptor next: 0x%08x\n", s->tx_desc_addr[q]); - s->regs[R_TXSTATUS] |= GEM_TXSTATUS_TXCMPL; + s->regs[R_TXSTATUS] |= R_TXSTATUS_TRANSMIT_COMPLETE_MASK; gem_set_isr(s, q, GEM_INT_TXCMPL); /* Handle interrupt consequences */ @@ -1363,7 +1379,7 @@ static void gem_transmit(CadenceGEMState *s) } if (tx_desc_get_used(desc)) { - s->regs[R_TXSTATUS] |= GEM_TXSTATUS_USED; + s->regs[R_TXSTATUS] |= R_TXSTATUS_USED_BIT_READ_MASK; /* IRQ TXUSED is defined only for queue 0 */ if (q == 0) { gem_set_isr(s, 0, GEM_INT_TXUSED); From patchwork Fri Oct 27 14:39:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13455646 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1qwO0t-0000jg-6u for mharc-qemu-devel@gnu.org; Fri, 27 Oct 2023 10:40:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qwO0O-0007Op-VU for qemu-devel@nongnu.org; Fri, 27 Oct 2023 10:40:10 -0400 Received: from mail-lj1-x22a.google.com ([2a00:1450:4864:20::22a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qwO0K-0008F5-H3 for qemu-devel@nongnu.org; Fri, 27 Oct 2023 10:40:08 -0400 Received: by mail-lj1-x22a.google.com with SMTP id 38308e7fff4ca-2b9d07a8d84so28499281fa.3 for ; Fri, 27 Oct 2023 07:40:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698417602; x=1699022402; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=vK0k6KfB8EoPx36PVM/3nfj6ufISuLpuOo8hIV8R6+I=; b=LyuZKN9zLVntBR+rXUq9bMYggzuywJ5101qKkC5nCrbNyFn/SGy5DP+7PPLacs82te xZk4R331Y4Ft2Y23yLM1R5Qbq6cf5bCG88VqhO39hylmuEpGKwjja1Yg+lhQEaLUIc6k rrx1xRMKsMUoEcF7+p3Os/oPh4MvMlJew2zW8prdJF44ADilrXiURnYfRi24+hamsaza 0yuujz5SFxxQ4wONrwIYGUGKws8hNeuGXkNIz+ftVy5Hilf4M+P/ODDAbd56F6KLm+0/ W95U0EGilqngf59kYTTsmgwXfI3c8h5NQHShAwy9+Sc1+OVYXIdZ2DeYP1fsCQu/AaHw YxhQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698417602; x=1699022402; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vK0k6KfB8EoPx36PVM/3nfj6ufISuLpuOo8hIV8R6+I=; b=l5730dvVOddD5VhKtYNo31xWbSO5/Bf5zEELuxyqrhBisxpwUIpn+rpls6z7/cC3RZ Uq8YIi7wZ1QtqCwe87HJajR8fXPfgIBYfn9DoXm47w7peC0L66er9qqvcaGOiyL6ops+ 8u0+uL9Yj4EmIb6a2IIVmbdRjRUGqEomitq8GqS6x/bRZk48/Yf5s70weEju7XM9tOFz 6DO1gtWPRGRjGqg6ONZynynjhnMsH3whIFmiu+NpvJmKlhP+9ruTAh67pwg3MSLhPj5G y3E9ak7cHwyP+LYGFaYSNWTY3HBdDE3B1tkLs3ULXhvyyIAh2d3MuHqTRjk7hAFSOSQ7 toJg== X-Gm-Message-State: AOJu0YzPnZiOtW29BL8A3VwyU0fzVr5Ix0cudArx8a8C76KKcTYMwHj2 qZioxrMXy/ed5UMQJ4cquNvFLL6ih6sD3zoQomk= X-Google-Smtp-Source: AGHT+IEYvmlDgrCOPWWh3+lZos5bhVPPdag1dUBhngUEDPcxWo1J4OGinCb49g2EVPsXguouqnJe9A== X-Received: by 2002:a2e:b748:0:b0:2c5:1ca8:d433 with SMTP id k8-20020a2eb748000000b002c51ca8d433mr2092370ljo.36.1698417602326; Fri, 27 Oct 2023 07:40:02 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e2-20020a5d5002000000b0031c6581d55esm1874123wrt.91.2023.10.27.07.40.01 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Oct 2023 07:40:02 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 37/41] hw/net/cadence_gem: use FIELD to describe IRQ register fields Date: Fri, 27 Oct 2023 15:39:38 +0100 Message-Id: <20231027143942.3413881-38-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231027143942.3413881-1-peter.maydell@linaro.org> References: <20231027143942.3413881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::22a; envelope-from=peter.maydell@linaro.org; helo=mail-lj1-x22a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Oct 2023 14:40:12 -0000 From: Luc Michel Use de FIELD macro to describe the IRQ related register fields. Signed-off-by: Luc Michel Reviewed-by: sai.pavan.boddu@amd.com Message-id: 20231017194422.4124691-8-luc.michel@amd.com Signed-off-by: Peter Maydell --- hw/net/cadence_gem.c | 51 +++++++++++++++++++++++++++++++++----------- 1 file changed, 39 insertions(+), 12 deletions(-) diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index d7fdc775146..7e6cab71071 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cadence_gem.c @@ -157,9 +157,42 @@ REG32(RXSTATUS, 0x20) /* RX Status reg */ FIELD(RXSTATUS, BUF_NOT_AVAILABLE, 0, 1) REG32(ISR, 0x24) /* Interrupt Status reg */ + FIELD(ISR, TX_LOCKUP, 31, 1) + FIELD(ISR, RX_LOCKUP, 30, 1) + FIELD(ISR, TSU_TIMER, 29, 1) + FIELD(ISR, WOL, 28, 1) + FIELD(ISR, RECV_LPI, 27, 1) + FIELD(ISR, TSU_SEC_INCR, 26, 1) + FIELD(ISR, PTP_PDELAY_RESP_XMIT, 25, 1) + FIELD(ISR, PTP_PDELAY_REQ_XMIT, 24, 1) + FIELD(ISR, PTP_PDELAY_RESP_RECV, 23, 1) + FIELD(ISR, PTP_PDELAY_REQ_RECV, 22, 1) + FIELD(ISR, PTP_SYNC_XMIT, 21, 1) + FIELD(ISR, PTP_DELAY_REQ_XMIT, 20, 1) + FIELD(ISR, PTP_SYNC_RECV, 19, 1) + FIELD(ISR, PTP_DELAY_REQ_RECV, 18, 1) + FIELD(ISR, PCS_LP_PAGE_RECV, 17, 1) + FIELD(ISR, PCS_AN_COMPLETE, 16, 1) + FIELD(ISR, EXT_IRQ, 15, 1) + FIELD(ISR, PAUSE_FRAME_XMIT, 14, 1) + FIELD(ISR, PAUSE_TIME_ELAPSED, 13, 1) + FIELD(ISR, PAUSE_FRAME_RECV, 12, 1) + FIELD(ISR, RESP_NOT_OK, 11, 1) + FIELD(ISR, RECV_OVERRUN, 10, 1) + FIELD(ISR, LINK_CHANGE, 9, 1) + FIELD(ISR, USXGMII_INT, 8, 1) + FIELD(ISR, XMIT_COMPLETE, 7, 1) + FIELD(ISR, AMBA_ERROR, 6, 1) + FIELD(ISR, RETRY_EXCEEDED, 5, 1) + FIELD(ISR, XMIT_UNDER_RUN, 4, 1) + FIELD(ISR, TX_USED, 3, 1) + FIELD(ISR, RX_USED, 2, 1) + FIELD(ISR, RECV_COMPLETE, 1, 1) + FIELD(ISR, MGNT_FRAME_SENT, 0, 1) REG32(IER, 0x28) /* Interrupt Enable reg */ REG32(IDR, 0x2c) /* Interrupt Disable reg */ REG32(IMR, 0x30) /* Interrupt Mask reg */ + REG32(PHYMNTNC, 0x34) /* Phy Maintenance reg */ REG32(RXPAUSE, 0x38) /* RX Pause Time reg */ REG32(TXPAUSE, 0x3c) /* TX Pause Time reg */ @@ -308,12 +341,6 @@ REG32(TYPE2_COMPARE_0_WORD_1, 0x704) /*****************************************/ -/* GEM_ISR GEM_IER GEM_IDR GEM_IMR */ -#define GEM_INT_TXCMPL 0x00000080 /* Transmit Complete */ -#define GEM_INT_AMBA_ERR 0x00000040 -#define GEM_INT_TXUSED 0x00000008 -#define GEM_INT_RXUSED 0x00000004 -#define GEM_INT_RXCMPL 0x00000002 #define GEM_PHYMNTNC_OP_R 0x20000000 /* read operation */ #define GEM_PHYMNTNC_OP_W 0x10000000 /* write operation */ @@ -1004,7 +1031,7 @@ static void gem_get_rx_desc(CadenceGEMState *s, int q) if (rx_desc_get_ownership(s->rx_desc[q]) == 1) { DB_PRINT("descriptor 0x%" HWADDR_PRIx " owned by sw.\n", desc_addr); s->regs[R_RXSTATUS] |= R_RXSTATUS_BUF_NOT_AVAILABLE_MASK; - gem_set_isr(s, q, GEM_INT_RXUSED); + gem_set_isr(s, q, R_ISR_RX_USED_MASK); /* Handle interrupt consequences */ gem_update_int_status(s); } @@ -1104,7 +1131,7 @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size) if (size > gem_get_max_buf_len(s, false)) { qemu_log_mask(LOG_GUEST_ERROR, "rx frame too long\n"); - gem_set_isr(s, q, GEM_INT_AMBA_ERR); + gem_set_isr(s, q, R_ISR_AMBA_ERROR_MASK); return -1; } @@ -1181,7 +1208,7 @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size) gem_receive_updatestats(s, buf, size); s->regs[R_RXSTATUS] |= R_RXSTATUS_FRAME_RECEIVED_MASK; - gem_set_isr(s, q, GEM_INT_RXCMPL); + gem_set_isr(s, q, R_ISR_RECV_COMPLETE_MASK); /* Handle interrupt consequences */ gem_update_int_status(s); @@ -1294,7 +1321,7 @@ static void gem_transmit(CadenceGEMState *s) HWADDR_PRIx " too large: size 0x%x space 0x%zx\n", packet_desc_addr, tx_desc_get_length(desc), gem_get_max_buf_len(s, true) - (p - s->tx_packet)); - gem_set_isr(s, q, GEM_INT_AMBA_ERR); + gem_set_isr(s, q, R_ISR_AMBA_ERROR_MASK); break; } @@ -1332,7 +1359,7 @@ static void gem_transmit(CadenceGEMState *s) DB_PRINT("TX descriptor next: 0x%08x\n", s->tx_desc_addr[q]); s->regs[R_TXSTATUS] |= R_TXSTATUS_TRANSMIT_COMPLETE_MASK; - gem_set_isr(s, q, GEM_INT_TXCMPL); + gem_set_isr(s, q, R_ISR_XMIT_COMPLETE_MASK); /* Handle interrupt consequences */ gem_update_int_status(s); @@ -1382,7 +1409,7 @@ static void gem_transmit(CadenceGEMState *s) s->regs[R_TXSTATUS] |= R_TXSTATUS_USED_BIT_READ_MASK; /* IRQ TXUSED is defined only for queue 0 */ if (q == 0) { - gem_set_isr(s, 0, GEM_INT_TXUSED); + gem_set_isr(s, 0, R_ISR_TX_USED_MASK); } gem_update_int_status(s); } From patchwork Fri Oct 27 14:39:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13455652 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1qwO0w-0001BE-Mo for mharc-qemu-devel@gnu.org; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e2-20020a5d5002000000b0031c6581d55esm1874123wrt.91.2023.10.27.07.40.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Oct 2023 07:40:02 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 38/41] hw/net/cadence_gem: use FIELD to describe DESCONF6 register fields Date: Fri, 27 Oct 2023 15:39:39 +0100 Message-Id: <20231027143942.3413881-39-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231027143942.3413881-1-peter.maydell@linaro.org> References: <20231027143942.3413881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Oct 2023 14:40:12 -0000 From: Luc Michel Use the FIELD macro to describe the DESCONF6 register fields. Signed-off-by: Luc Michel Reviewed-by: Philippe Mathieu-Daudé Message-id: 20231017194422.4124691-9-luc.michel@amd.com Signed-off-by: Peter Maydell --- hw/net/cadence_gem.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index 7e6cab71071..dffcc64df25 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cadence_gem.c @@ -283,7 +283,7 @@ REG32(DESCONF3, 0x288) REG32(DESCONF4, 0x28c) REG32(DESCONF5, 0x290) REG32(DESCONF6, 0x294) -#define GEM_DESCONF6_64B_MASK (1U << 23) + FIELD(DESCONF6, DMA_ADDR_64B, 23, 1) REG32(DESCONF7, 0x298) REG32(INT_Q1_STATUS, 0x400) @@ -1463,7 +1463,7 @@ static void gem_reset(DeviceState *d) s->regs[R_DESCONF] = 0x02D00111; s->regs[R_DESCONF2] = 0x2ab10000 | s->jumbo_max_len; s->regs[R_DESCONF5] = 0x002f2045; - s->regs[R_DESCONF6] = GEM_DESCONF6_64B_MASK; + s->regs[R_DESCONF6] = R_DESCONF6_DMA_ADDR_64B_MASK; s->regs[R_INT_Q1_MASK] = 0x00000CE6; s->regs[R_JUMBO_MAX_LEN] = s->jumbo_max_len; From patchwork Fri Oct 27 14:39:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13455645 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1qwO0r-0000QY-9t for mharc-qemu-devel@gnu.org; Fri, 27 Oct 2023 10:40:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qwO0P-0007P1-KM for qemu-devel@nongnu.org; Fri, 27 Oct 2023 10:40:12 -0400 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qwO0L-0008Gt-KD for qemu-devel@nongnu.org; Fri, 27 Oct 2023 10:40:09 -0400 Received: by mail-wr1-x42a.google.com with SMTP id ffacd0b85a97d-32dc9ff4a8fso1387645f8f.1 for ; Fri, 27 Oct 2023 07:40:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698417603; x=1699022403; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=C/6VeNVqAYw8mGQFBhg791eUfLvyqSXTXHYdCSjH8yk=; b=vZEtMhPzKekhXh76WmTClQQ8SjmGWPldSizovVdp9dniFOHODLpWlAxsRqhFWdfMjD VB3OUo8oMxzpasmL2OCEUVzZHoEVNu43GvBreoRyi5erbvcnRkPPNC2BdSPDAHh6rnmQ mLv+bnSlU8sh2wYjhHBS6bAHMww4+Wm/gHjpCUNALcjPFOYBcu4t/ojjIBgED/qARn6H JT04unsR9JaAoS9UBKvFXx9rbZZxKlu73v6K0AJwhs1ElWyPncA/fHfB4HCN7LsiyZk6 GoLUFE1G3bIx8OTHK1U16Jq9X77UWmexDfuY9orqCIcehyNS2Fb8RWTvRd24pcvHtgOY /WKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698417603; x=1699022403; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=C/6VeNVqAYw8mGQFBhg791eUfLvyqSXTXHYdCSjH8yk=; b=J/NbrYIory/RiyhpJVICTJpDMel3RGsPA2kWEwgg8RVdEAhxuQ4EeN0d9keGOOQi+E VbSMNUFrzsylURqloW/w81wEXd974brqv0HqoRL5NVow/WkMx0dk93wOrczGSOK9RdnE 8FEmegttrY9ed/JEqXxw2QBVKPHVAk0/joSBGJN8JLsHoBYB16yby1C7w1108GOYXvH+ 39rLqCHXiGGPKDr2T/uh089M6ND6218be4p+anZDaA9fx7/Sudl5+X7wCYf51M57ZxCu lIzovw/pPf9u9OKVKX5oOVEl0HOTzOQddCdPkxud7LbsjwGIO42Gbxhu8C5pqSXKaq0z qq4Q== X-Gm-Message-State: AOJu0Yyby4r1dSPUuRAKZiiIWaRb/cw1Pe7gS222+EjnqPJ2rkNaBmxq I06oN7+UrNmX0sTZ/Z69yEm8G7O/8WewPsKsYII= X-Google-Smtp-Source: AGHT+IFYULLe289uqZsSsu7lSewBrYb8QneHffZF34djgKrdapc7Aqy/dc1jkJaw00QMqSHbhL1Kvw== X-Received: by 2002:a5d:4fc9:0:b0:31f:9b4f:1910 with SMTP id h9-20020a5d4fc9000000b0031f9b4f1910mr2335234wrw.63.1698417603370; Fri, 27 Oct 2023 07:40:03 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e2-20020a5d5002000000b0031c6581d55esm1874123wrt.91.2023.10.27.07.40.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Oct 2023 07:40:03 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 39/41] hw/net/cadence_gem: use FIELD to describe PHYMNTNC register fields Date: Fri, 27 Oct 2023 15:39:40 +0100 Message-Id: <20231027143942.3413881-40-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231027143942.3413881-1-peter.maydell@linaro.org> References: <20231027143942.3413881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Oct 2023 14:40:12 -0000 From: Luc Michel Use the FIELD macro to describe the PHYMNTNC register fields. Signed-off-by: Luc Michel Reviewed-by: sai.pavan.boddu@amd.com Message-id: 20231017194422.4124691-10-luc.michel@amd.com Signed-off-by: Peter Maydell --- hw/net/cadence_gem.c | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index dffcc64df25..373d3ee0712 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cadence_gem.c @@ -194,6 +194,14 @@ REG32(IDR, 0x2c) /* Interrupt Disable reg */ REG32(IMR, 0x30) /* Interrupt Mask reg */ REG32(PHYMNTNC, 0x34) /* Phy Maintenance reg */ + FIELD(PHYMNTNC, DATA, 0, 16) + FIELD(PHYMNTNC, REG_ADDR, 18, 5) + FIELD(PHYMNTNC, PHY_ADDR, 23, 5) + FIELD(PHYMNTNC, OP, 28, 2) + FIELD(PHYMNTNC, ST, 30, 2) +#define MDIO_OP_READ 0x3 +#define MDIO_OP_WRITE 0x2 + REG32(RXPAUSE, 0x38) /* RX Pause Time reg */ REG32(TXPAUSE, 0x3c) /* TX Pause Time reg */ REG32(TXPARTIALSF, 0x40) /* TX Partial Store and Forward */ @@ -342,13 +350,6 @@ REG32(TYPE2_COMPARE_0_WORD_1, 0x704) -#define GEM_PHYMNTNC_OP_R 0x20000000 /* read operation */ -#define GEM_PHYMNTNC_OP_W 0x10000000 /* write operation */ -#define GEM_PHYMNTNC_ADDR 0x0F800000 /* Address bits */ -#define GEM_PHYMNTNC_ADDR_SHFT 23 -#define GEM_PHYMNTNC_REG 0x007C0000 /* register bits */ -#define GEM_PHYMNTNC_REG_SHIFT 18 - /* Marvell PHY definitions */ #define BOARD_PHY_ADDRESS 0 /* PHY address we will emulate a device at */ @@ -1541,12 +1542,12 @@ static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size) /* The interrupts get updated at the end of the function. */ break; case R_PHYMNTNC: - if (retval & GEM_PHYMNTNC_OP_R) { + if (FIELD_EX32(retval, PHYMNTNC, OP) == MDIO_OP_READ) { uint32_t phy_addr, reg_num; - phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT; + phy_addr = FIELD_EX32(retval, PHYMNTNC, PHY_ADDR); if (phy_addr == s->phy_addr) { - reg_num = (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT; + reg_num = FIELD_EX32(retval, PHYMNTNC, REG_ADDR); retval &= 0xFFFF0000; retval |= gem_phy_read(s, reg_num); } else { @@ -1664,12 +1665,12 @@ static void gem_write(void *opaque, hwaddr offset, uint64_t val, s->sar_active[(offset - R_SPADDR1HI) / 2] = true; break; case R_PHYMNTNC: - if (val & GEM_PHYMNTNC_OP_W) { + if (FIELD_EX32(val, PHYMNTNC, OP) == MDIO_OP_WRITE) { uint32_t phy_addr, reg_num; - phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT; + phy_addr = FIELD_EX32(val, PHYMNTNC, PHY_ADDR); if (phy_addr == s->phy_addr) { - reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT; + reg_num = FIELD_EX32(val, PHYMNTNC, REG_ADDR); gem_phy_write(s, reg_num, val); } } From patchwork Fri Oct 27 14:39:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13455655 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1qwO0x-0001JW-Iq for mharc-qemu-devel@gnu.org; Fri, 27 Oct 2023 10:40:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qwO0Q-0007P4-25 for qemu-devel@nongnu.org; Fri, 27 Oct 2023 10:40:12 -0400 Received: from mail-lf1-x12c.google.com ([2a00:1450:4864:20::12c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qwO0N-0008MD-S4 for qemu-devel@nongnu.org; Fri, 27 Oct 2023 10:40:09 -0400 Received: by mail-lf1-x12c.google.com with SMTP id 2adb3069b0e04-5079f6efd64so2961397e87.2 for ; Fri, 27 Oct 2023 07:40:06 -0700 (PDT) DKIM-Signature: v=1; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e2-20020a5d5002000000b0031c6581d55esm1874123wrt.91.2023.10.27.07.40.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Oct 2023 07:40:03 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 40/41] hw/net/cadence_gem: perform PHY access on write only Date: Fri, 27 Oct 2023 15:39:41 +0100 Message-Id: <20231027143942.3413881-41-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231027143942.3413881-1-peter.maydell@linaro.org> References: <20231027143942.3413881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::12c; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x12c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Oct 2023 14:40:12 -0000 From: Luc Michel The MDIO access is done only on a write to the PHYMNTNC register. A subsequent read is used to retrieve the result but does not trigger an MDIO access by itself. Refactor the PHY access logic to perform all accesses (MDIO reads and writes) at PHYMNTNC write time. Signed-off-by: Luc Michel Reviewed-by: sai.pavan.boddu@amd.com Message-id: 20231017194422.4124691-11-luc.michel@amd.com Signed-off-by: Peter Maydell --- hw/net/cadence_gem.c | 56 ++++++++++++++++++++++++++------------------ 1 file changed, 33 insertions(+), 23 deletions(-) diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index 373d3ee0712..06a101bfcd4 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cadence_gem.c @@ -1521,6 +1521,38 @@ static void gem_phy_write(CadenceGEMState *s, unsigned reg_num, uint16_t val) s->phy_regs[reg_num] = val; } +static void gem_handle_phy_access(CadenceGEMState *s) +{ + uint32_t val = s->regs[R_PHYMNTNC]; + uint32_t phy_addr, reg_num; + + phy_addr = FIELD_EX32(val, PHYMNTNC, PHY_ADDR); + + if (phy_addr != s->phy_addr) { + /* no phy at this address */ + if (FIELD_EX32(val, PHYMNTNC, OP) == MDIO_OP_READ) { + s->regs[R_PHYMNTNC] = FIELD_DP32(val, PHYMNTNC, DATA, 0xffff); + } + return; + } + + reg_num = FIELD_EX32(val, PHYMNTNC, REG_ADDR); + + switch (FIELD_EX32(val, PHYMNTNC, OP)) { + case MDIO_OP_READ: + s->regs[R_PHYMNTNC] = FIELD_DP32(val, PHYMNTNC, DATA, + gem_phy_read(s, reg_num)); + break; + + case MDIO_OP_WRITE: + gem_phy_write(s, reg_num, val); + break; + + default: + break; /* only clause 22 operations are supported */ + } +} + /* * gem_read32: * Read a GEM register. @@ -1541,20 +1573,6 @@ static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size) DB_PRINT("lowering irqs on ISR read\n"); /* The interrupts get updated at the end of the function. */ break; - case R_PHYMNTNC: - if (FIELD_EX32(retval, PHYMNTNC, OP) == MDIO_OP_READ) { - uint32_t phy_addr, reg_num; - - phy_addr = FIELD_EX32(retval, PHYMNTNC, PHY_ADDR); - if (phy_addr == s->phy_addr) { - reg_num = FIELD_EX32(retval, PHYMNTNC, REG_ADDR); - retval &= 0xFFFF0000; - retval |= gem_phy_read(s, reg_num); - } else { - retval |= 0xFFFF; /* No device at this address */ - } - } - break; } /* Squash read to clear bits */ @@ -1665,15 +1683,7 @@ static void gem_write(void *opaque, hwaddr offset, uint64_t val, s->sar_active[(offset - R_SPADDR1HI) / 2] = true; break; case R_PHYMNTNC: - if (FIELD_EX32(val, PHYMNTNC, OP) == MDIO_OP_WRITE) { - uint32_t phy_addr, reg_num; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e2-20020a5d5002000000b0031c6581d55esm1874123wrt.91.2023.10.27.07.40.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Oct 2023 07:40:04 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 41/41] hw/net/cadence_gem: enforce 32 bits variable size for CRC Date: Fri, 27 Oct 2023 15:39:42 +0100 Message-Id: <20231027143942.3413881-42-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231027143942.3413881-1-peter.maydell@linaro.org> References: <20231027143942.3413881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::231; envelope-from=peter.maydell@linaro.org; helo=mail-lj1-x231.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Oct 2023 14:40:12 -0000 From: Luc Michel The CRC was stored in an unsigned variable in gem_receive. Change it for a uint32_t to ensure we have the correct variable size here. Signed-off-by: Luc Michel Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: sai.pavan.boddu@amd.com Message-id: 20231017194422.4124691-12-luc.michel@amd.com Signed-off-by: Peter Maydell --- hw/net/cadence_gem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index 06a101bfcd4..5b989f5b523 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cadence_gem.c @@ -1105,7 +1105,7 @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size) if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, FCS_REMOVE)) { rxbuf_ptr = (void *)buf; } else { - unsigned crc_val; + uint32_t crc_val; if (size > MAX_FRAME_SIZE - sizeof(crc_val)) { size = MAX_FRAME_SIZE - sizeof(crc_val);