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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , CC: Ido Schimmel , Petr Machata , "Amit Cohen" , , Jiri Pirko Subject: [PATCH net-next 01/14] devlink: Move private netlink flags to C file Date: Wed, 15 Nov 2023 13:17:10 +0100 Message-ID: X-Mailer: git-send-email 2.41.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D7:EE_|PH7PR12MB6610:EE_ X-MS-Office365-Filtering-Correlation-Id: 9dde8808-d26a-459a-ca10-08dbe5d521d1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: dMfInb9Hh9lSi3KLAVa4UTyYaUwjx/+CPHtMG0h8V8KLMaBWmizj4BOAa119ID5HWviDTqWopGX/Me0ePtJBizPopJ0zU76q4O4lms6Q15Oc8QY5xEbzzbcFnoKT9dWEEdgq6tVf72ihwnmWLifI9SJY9MUAyh+wRSrfBkIfZ3rKUNdSWEwDUPqstrr8j+7ayfXU1PihEgnTEz6+7wFmFuXP0/h2L1rb6UaEC5N7LtBgiHE37KNnAt4pOAJ/9+4svQVVBCueEuazQ9s0jNqJgB/p7FmRatr4NpahsmsyXnH4QgmP7rD5ZmYnVUOmT0XLTl6FPC7vgYdUprszGlkqUZ+A+7ns0yWqFKtaeDLyapmZpgynrMsuF+xhsTmkd6cFhi4CGFBSfjBthJJO3qSIJedX8RVPVDbYjbUoFeLYBFOIfI6fC6MEZqPyHNpFyvO2nyLAqIpZl7g45omDeg7anyT6dPELimxBjwIjhXeEjYGZcKZ+n6rvrfniuOSxtzlBhmPzvGmU2xEdfofid6toSyF7f6Z58VUwVPUbje+1UCo9zXNze7Am0GFKEiL8D+sAklp3Ea+vHY/RzMhFSL4mZPcEbME8vkRJhxA+A3tYL87h6sL3E7Xz7PMrLLxbqbOzdbXVGUNRnsd96ux7CRFCsUJm1b5erDCzIGXEOi1dak0lWogotaGYKLpjefGRS0nNJjTAxNnMAw+Cr1VsO3i9J9VGbh10EzoNKYlcYpVUWkS+zq49ucq4NsfnQwlg1nWr X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(346002)(376002)(39860400002)(136003)(396003)(230922051799003)(186009)(64100799003)(82310400011)(1800799009)(451199024)(46966006)(40470700004)(36840700001)(2906002)(40460700003)(5660300002)(41300700001)(54906003)(356005)(7636003)(36756003)(478600001)(2616005)(26005)(6666004)(107886003)(82740400003)(16526019)(86362001)(426003)(47076005)(336012)(36860700001)(110136005)(8676002)(83380400001)(4326008)(8936002)(70586007)(316002)(70206006)(40480700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Nov 2023 12:19:36.0155 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9dde8808-d26a-459a-ca10-08dbe5d521d1 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D7.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6610 X-Patchwork-Delegate: kuba@kernel.org From: Ido Schimmel The flags are not used outside of the C file so move them there. Suggested-by: Jiri Pirko Signed-off-by: Ido Schimmel Reviewed-by: Jiri Pirko Signed-off-by: Petr Machata Reviewed-by: Simon Horman --- net/devlink/devl_internal.h | 3 --- net/devlink/netlink.c | 3 +++ 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/net/devlink/devl_internal.h b/net/devlink/devl_internal.h index 183dbe3807ab..2a9b263300a4 100644 --- a/net/devlink/devl_internal.h +++ b/net/devlink/devl_internal.h @@ -111,9 +111,6 @@ int devlink_rel_devlink_handle_put(struct sk_buff *msg, struct devlink *devlink, bool *msg_updated); /* Netlink */ -#define DEVLINK_NL_FLAG_NEED_PORT BIT(0) -#define DEVLINK_NL_FLAG_NEED_DEVLINK_OR_PORT BIT(1) - enum devlink_multicast_groups { DEVLINK_MCGRP_CONFIG, }; diff --git a/net/devlink/netlink.c b/net/devlink/netlink.c index d0b90ebc8b15..7350138c8bb4 100644 --- a/net/devlink/netlink.c +++ b/net/devlink/netlink.c @@ -9,6 +9,9 @@ #include "devl_internal.h" +#define DEVLINK_NL_FLAG_NEED_PORT BIT(0) +#define DEVLINK_NL_FLAG_NEED_DEVLINK_OR_PORT BIT(1) + static const struct genl_multicast_group devlink_nl_mcgrps[] = { [DEVLINK_MCGRP_CONFIG] = { .name = DEVLINK_GENL_MCGRP_CONFIG_NAME }, }; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , CC: Ido Schimmel , Petr Machata , "Amit Cohen" , , Jiri Pirko Subject: [PATCH net-next 02/14] devlink: Acquire device lock during netns dismantle Date: Wed, 15 Nov 2023 13:17:11 +0100 Message-ID: X-Mailer: git-send-email 2.41.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D9:EE_|DS0PR12MB8416:EE_ X-MS-Office365-Filtering-Correlation-Id: c624aabc-d2fa-498f-a497-08dbe5d523f0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: PvP1tuOOnxk0ME7EWuhPX3FZIV5sN+sFh+A2wp2i4XSYniPI4Bqlzseh1jlm7flVcdTiDUX0s7QezMYG3GihBGRo9iRdkZk1jykG0be3GnVFx62reoYx18P9xgV3MOhLcBXq4VBKof+ZQB9reBFjVuo2V2Gt6csJSzurEl9N+veJz70d25EVavbeVYqhrGoCoH0/aejUqOyd6svXgVmiBBiRHg0vdW5mOAeGNPiU8lD0Zr6Ss5DbqutaIhr56TPcRZlu5J4ygDU2emp8aOy5k3V3ldj8sd3iKnT8jZTBmWstKxoY8U3M/Zl3ZHV0C6rn2rVklKSvaYYOmYGqctQDBxya9s9oQYmTinLCkbDdSLqd8EYPcMPVAFFhhTb8+Ux43ohzZ+6Gh0bjUS71XximNVyA8XKPxSXodXCNHoIi6bLzs4Y6M9B5/gLNcglVe4WG/ebMcKXpi3xTd8d9fIgUzh7GbwMr3auZM5qkcDQzoPCJqP+JB5imBru4qEKk76nQDpgdimDTYyoFZ45b8RD0uLdcGAnixW47NC1+Z9Z+HXWeV6xqOOTXEVPEl4x0xyiycWXpMu/ZVPvo4gEctB5Ya/45caajQ+HDcHxsYUZypTQMkLlyO9fhar9fuGPnWRb37bpxhwLy27+n0DRPzRMg9AAeBObgf5JoUG1UyVS9aDBPXZ9uQMxZnZZ12ExY+5mOhoMkyCE9HdbMnOmBPfWTpk9wmZDsn5AsNIxot+4oNFltgpyack1ixwZBzkfwAX6G X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(396003)(39860400002)(136003)(346002)(376002)(230922051799003)(451199024)(82310400011)(64100799003)(186009)(1800799009)(40470700004)(36840700001)(46966006)(356005)(40480700001)(7636003)(83380400001)(36860700001)(54906003)(110136005)(8936002)(4326008)(8676002)(70206006)(70586007)(336012)(426003)(107886003)(36756003)(41300700001)(47076005)(82740400003)(16526019)(26005)(2616005)(6666004)(478600001)(2906002)(40460700003)(316002)(86362001)(5660300002);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Nov 2023 12:19:39.5731 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c624aabc-d2fa-498f-a497-08dbe5d523f0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D9.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8416 X-Patchwork-Delegate: kuba@kernel.org From: Ido Schimmel Device drivers register with devlink from their probe routines (under the device lock) by acquiring the devlink instance lock and calling devl_register(). Drivers that support a devlink reload usually implement the reload_{down, up}() operations in a similar fashion to their remove and probe routines, respectively. However, while the remove and probe routines are invoked with the device lock held, the reload operations are only invoked with the devlink instance lock held. It is therefore impossible for drivers to acquire the device lock from their reload operations, as this would result in lock inversion. The motivating use case for invoking the reload operations with the device lock held is in mlxsw which needs to trigger a PCI reset as part of the reload. The driver cannot call pci_reset_function() as this function acquires the device lock. Instead, it needs to call __pci_reset_function_locked which expects the device lock to be held. To that end, adjust devlink to always acquire the device lock before the devlink instance lock when performing a reload. For now, only do that when reload is triggered as part of netns dismantle. Subsequent patches will handle the case where reload is explicitly triggered by user space. Signed-off-by: Ido Schimmel Reviewed-by: Jiri Pirko Signed-off-by: Petr Machata Reviewed-by: Simon Horman --- net/devlink/core.c | 4 ++-- net/devlink/devl_internal.h | 15 +++++++++++++++ 2 files changed, 17 insertions(+), 2 deletions(-) diff --git a/net/devlink/core.c b/net/devlink/core.c index 6984877e9f10..4275a2bc6d8e 100644 --- a/net/devlink/core.c +++ b/net/devlink/core.c @@ -503,14 +503,14 @@ static void __net_exit devlink_pernet_pre_exit(struct net *net) * all devlink instances from this namespace into init_net. */ devlinks_xa_for_each_registered_get(net, index, devlink) { - devl_lock(devlink); + devl_dev_lock(devlink, true); err = 0; if (devl_is_registered(devlink)) err = devlink_reload(devlink, &init_net, DEVLINK_RELOAD_ACTION_DRIVER_REINIT, DEVLINK_RELOAD_LIMIT_UNSPEC, &actions_performed, NULL); - devl_unlock(devlink); + devl_dev_unlock(devlink, true); devlink_put(devlink); if (err && err != -EOPNOTSUPP) pr_warn("Failed to reload devlink instance into init_net\n"); diff --git a/net/devlink/devl_internal.h b/net/devlink/devl_internal.h index 2a9b263300a4..178abaf74a10 100644 --- a/net/devlink/devl_internal.h +++ b/net/devlink/devl_internal.h @@ -3,6 +3,7 @@ * Copyright (c) 2016 Jiri Pirko */ +#include #include #include #include @@ -96,6 +97,20 @@ static inline bool devl_is_registered(struct devlink *devlink) return xa_get_mark(&devlinks, devlink->index, DEVLINK_REGISTERED); } +static inline void devl_dev_lock(struct devlink *devlink, bool dev_lock) +{ + if (dev_lock) + device_lock(devlink->dev); + devl_lock(devlink); +} + +static inline void devl_dev_unlock(struct devlink *devlink, bool dev_lock) +{ + devl_unlock(devlink); + if (dev_lock) + device_unlock(devlink->dev); +} + typedef void devlink_rel_notify_cb_t(struct devlink *devlink, u32 obj_index); typedef void devlink_rel_cleanup_cb_t(struct devlink *devlink, u32 obj_index, u32 rel_index); From patchwork Wed Nov 15 12:17:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Petr Machata X-Patchwork-Id: 13456622 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DABF8182AA for ; Wed, 15 Nov 2023 12:19:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , CC: Ido Schimmel , Petr Machata , "Amit Cohen" , , Jiri Pirko Subject: [PATCH net-next 03/14] devlink: Enable the use of private flags in post_doit operations Date: Wed, 15 Nov 2023 13:17:12 +0100 Message-ID: <63d7e04fdfaf44a33d683270d95627afbf90e932.1700047319.git.petrm@nvidia.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D9:EE_|DM4PR12MB5101:EE_ X-MS-Office365-Filtering-Correlation-Id: f9cdfb19-7281-4ed6-f8b1-08dbe5d526ce X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: BzsFf+9UeiWj/a6pcLL7A26kE3TdMH+i+XLWZMWulhwgYixAYBmVU/EO3Yoq0QQ0RdRtFzEir68Ghz7Hp5Bo/5dXcG/sg/ewjjHPgDdguEQFtUNPajtxzNLSbnTuClPQ1CACTrucpGBqvzKWAgrNV3IyBZtkO9DdfiNmp89xjUaZjt6rjlwebF/mQQgpGk/ZPFD2LbSSjEImxuzi7liZjmoQcFZ0rjSIt28KOyJSGkRF2fPVGYZfHlefX5IPQ6RwTAGQNzUBEOw/1XB+b3+Ns5NGQec/HzPjgq2YDMusZY0KRmAH6Z1+/I2snFokOLFpgncO7gB58FHl++pyh/HJJrtLGdvmWdo61KNnBIKFX937PNoI+FWEHxCv1SE8jSHwEoWqNODdJtFBuwWBwECZrXAFVRYWzWbs1Yu1El0LL+TWdSPTpIMorK4v4r0WjVWzBJynf+O7DVJk+Xv2A2zzYVX/r1smr2eLKjg28cS5R8BTQpbnazza0eYKYhO3A7oMoxMgXnWn+iqD5APBl7X3Gn4vJXU4crfLjfzMjxBNc0Lggg/OBHqbLptni9i+2LM2H147AtA/ux9XQf1jkLf8U0qPJSxgsWKoADBDz65ZC4Dnr0sLk25OPGUQBRb81mNrEthDfqJW6wdHdDcIobkEJDC5mMSU9tWa6338pYgfuTQq5jWRiCsr+mXhjti79cPmR5IfJLBE/+5JVajHSXDpvhthVOYuj8MkKywSMZNzm6ydL1KoxADU9RDzX9jM9P0S X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(376002)(39860400002)(396003)(136003)(346002)(230922051799003)(82310400011)(64100799003)(451199024)(1800799009)(186009)(36840700001)(40470700004)(46966006)(40480700001)(40460700003)(70206006)(70586007)(110136005)(7636003)(356005)(82740400003)(36756003)(54906003)(86362001)(478600001)(36860700001)(336012)(83380400001)(426003)(16526019)(26005)(6666004)(2616005)(2906002)(316002)(107886003)(8676002)(4326008)(8936002)(5660300002)(47076005)(41300700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Nov 2023 12:19:44.3700 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f9cdfb19-7281-4ed6-f8b1-08dbe5d526ce X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D9.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5101 X-Patchwork-Delegate: kuba@kernel.org From: Ido Schimmel Currently, private flags (e.g., 'DEVLINK_NL_FLAG_NEED_PORT') are only used in pre_doit operations, but a subsequent patch will need to conditionally lock and unlock the device lock in pre and post doit operations, respectively. As a preparation, enable the use of private flags in post_doit operations in a similar fashion to how it is done for pre_doit operations. No functional changes intended. Signed-off-by: Ido Schimmel Reviewed-by: Jiri Pirko Signed-off-by: Petr Machata Reviewed-by: Simon Horman --- net/devlink/netlink.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/net/devlink/netlink.c b/net/devlink/netlink.c index 7350138c8bb4..5bb6624f3288 100644 --- a/net/devlink/netlink.c +++ b/net/devlink/netlink.c @@ -141,14 +141,20 @@ int devlink_nl_pre_doit_port_optional(const struct genl_split_ops *ops, return __devlink_nl_pre_doit(skb, info, DEVLINK_NL_FLAG_NEED_DEVLINK_OR_PORT); } +static void __devlink_nl_post_doit(struct sk_buff *skb, struct genl_info *info, + u8 flags) +{ + struct devlink *devlink; + + devlink = info->user_ptr[0]; + devl_unlock(devlink); + devlink_put(devlink); +} + void devlink_nl_post_doit(const struct genl_split_ops *ops, struct sk_buff *skb, struct genl_info *info) { - struct devlink *devlink; - - devlink = info->user_ptr[0]; - devl_unlock(devlink); - devlink_put(devlink); + __devlink_nl_post_doit(skb, info, 0); } static int devlink_nl_inst_single_dumpit(struct sk_buff *msg, From patchwork Wed Nov 15 12:17:13 2023 Content-Type: text/plain; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , CC: Ido Schimmel , Petr Machata , "Amit Cohen" , , Jiri Pirko Subject: [PATCH net-next 04/14] devlink: Allow taking device lock in pre_doit operations Date: Wed, 15 Nov 2023 13:17:13 +0100 Message-ID: X-Mailer: git-send-email 2.41.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D7:EE_|DM6PR12MB4332:EE_ X-MS-Office365-Filtering-Correlation-Id: 05d9c311-fae5-4b4f-202e-08dbe5d5283a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: FnmdaEl5yQDwOJvxO3D2AqoToAffPS1HssEkQrwPVeQEP8tYeyLRxKkP8MSe+mS5zSLcZOZMY27rDB2VlCCnnOSRP945i4qn7TyHXmYHWdVqhaUgTIt2/CSVzanAZuath6//pKbNtOUgsDyZ1Xt6BYYN48eJCYRETjZE0dq/6cNAcklPZB8olHnuIvSNlXMNalWbl6syMc2EdW68dtEX0oKomT184PYSS31C2iIuTNO6NO1O7kknJrImYNkoNx0czgHGhlkMHlSJy2jpGHhEKLKATXvhv7Y/rvVguNcgbQNc4JwF1bs5o/avfYPOFrmZ2ZmaeFkkRjhgQ9Nfyi7XuXghd+wcFW3wrX3x+5jhizpfFC/PFy+Pbl4ZZRlNcNYqLdsgmhXuvAoCnxD0Uz2beSHHa+SapQgu507JUfA6ZnX0BYiMqvd7CkrBTN46TmnPISxpO3Bko2B9Juq43IhYQbGJTKBVeDRNJ47ESys6Z6nyVjw3CSxU4fqZ2yQlCe4VDR5/v41Nh5SCOo5N9ScwP0GmL8iExtpuOqK8JGGqnmKqpLieAylzbbfjXloTOD73dcmvzfxHvymyQhH5t+AFSrKIYQCKfj52vthWt6I2SmrqXE8YnRlMb6Dut+gSFG3tTjoGoD8XjXn+Mu4rMMCddE1Lf5vGc528d1lCo3DGMR5eVAfbyapgYkWklf3JeoRMHdXAIro8HnKR6bpUJZaX/bZZqBWJ7no9DlLZpXyCgtJTi9WL4hphn/QvegkF13nk X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(396003)(39860400002)(376002)(136003)(346002)(230922051799003)(1800799009)(64100799003)(186009)(451199024)(82310400011)(46966006)(40470700004)(36840700001)(6666004)(478600001)(47076005)(7636003)(82740400003)(36860700001)(356005)(40480700001)(83380400001)(426003)(336012)(40460700003)(107886003)(2616005)(16526019)(26005)(41300700001)(8676002)(36756003)(8936002)(4326008)(86362001)(5660300002)(316002)(2906002)(54906003)(70206006)(70586007)(110136005);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Nov 2023 12:19:46.7812 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 05d9c311-fae5-4b4f-202e-08dbe5d5283a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D7.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4332 X-Patchwork-Delegate: kuba@kernel.org From: Ido Schimmel Introduce a new private flag ('DEVLINK_NL_FLAG_NEED_DEV_LOCK') to allow netlink commands to specify that they need to acquire the device lock in their pre_doit operation and release it in their post_doit operation. The reload command will use this flag in the subsequent patch. No functional changes intended. Signed-off-by: Ido Schimmel Reviewed-by: Jiri Pirko Signed-off-by: Petr Machata Reviewed-by: Simon Horman --- net/devlink/devl_internal.h | 3 ++- net/devlink/health.c | 3 ++- net/devlink/netlink.c | 19 ++++++++++++------- net/devlink/region.c | 3 ++- 4 files changed, 18 insertions(+), 10 deletions(-) diff --git a/net/devlink/devl_internal.h b/net/devlink/devl_internal.h index 178abaf74a10..5ea2e2012e93 100644 --- a/net/devlink/devl_internal.h +++ b/net/devlink/devl_internal.h @@ -152,7 +152,8 @@ typedef int devlink_nl_dump_one_func_t(struct sk_buff *msg, int flags); struct devlink * -devlink_get_from_attrs_lock(struct net *net, struct nlattr **attrs); +devlink_get_from_attrs_lock(struct net *net, struct nlattr **attrs, + bool dev_lock); int devlink_nl_dumpit(struct sk_buff *msg, struct netlink_callback *cb, devlink_nl_dump_one_func_t *dump_one); diff --git a/net/devlink/health.c b/net/devlink/health.c index 695df61f8ac2..71ae121dc739 100644 --- a/net/devlink/health.c +++ b/net/devlink/health.c @@ -1151,7 +1151,8 @@ devlink_health_reporter_get_from_cb_lock(struct netlink_callback *cb) struct nlattr **attrs = info->attrs; struct devlink *devlink; - devlink = devlink_get_from_attrs_lock(sock_net(cb->skb->sk), attrs); + devlink = devlink_get_from_attrs_lock(sock_net(cb->skb->sk), attrs, + false); if (IS_ERR(devlink)) return NULL; diff --git a/net/devlink/netlink.c b/net/devlink/netlink.c index 5bb6624f3288..86f12531bf99 100644 --- a/net/devlink/netlink.c +++ b/net/devlink/netlink.c @@ -11,6 +11,7 @@ #define DEVLINK_NL_FLAG_NEED_PORT BIT(0) #define DEVLINK_NL_FLAG_NEED_DEVLINK_OR_PORT BIT(1) +#define DEVLINK_NL_FLAG_NEED_DEV_LOCK BIT(2) static const struct genl_multicast_group devlink_nl_mcgrps[] = { [DEVLINK_MCGRP_CONFIG] = { .name = DEVLINK_GENL_MCGRP_CONFIG_NAME }, @@ -64,7 +65,8 @@ int devlink_nl_msg_reply_and_new(struct sk_buff **msg, struct genl_info *info) } struct devlink * -devlink_get_from_attrs_lock(struct net *net, struct nlattr **attrs) +devlink_get_from_attrs_lock(struct net *net, struct nlattr **attrs, + bool dev_lock) { struct devlink *devlink; unsigned long index; @@ -78,12 +80,12 @@ devlink_get_from_attrs_lock(struct net *net, struct nlattr **attrs) devname = nla_data(attrs[DEVLINK_ATTR_DEV_NAME]); devlinks_xa_for_each_registered_get(net, index, devlink) { - devl_lock(devlink); + devl_dev_lock(devlink, dev_lock); if (devl_is_registered(devlink) && strcmp(devlink->dev->bus->name, busname) == 0 && strcmp(dev_name(devlink->dev), devname) == 0) return devlink; - devl_unlock(devlink); + devl_dev_unlock(devlink, dev_lock); devlink_put(devlink); } @@ -93,11 +95,13 @@ devlink_get_from_attrs_lock(struct net *net, struct nlattr **attrs) static int __devlink_nl_pre_doit(struct sk_buff *skb, struct genl_info *info, u8 flags) { + bool dev_lock = flags & DEVLINK_NL_FLAG_NEED_DEV_LOCK; struct devlink_port *devlink_port; struct devlink *devlink; int err; - devlink = devlink_get_from_attrs_lock(genl_info_net(info), info->attrs); + devlink = devlink_get_from_attrs_lock(genl_info_net(info), info->attrs, + dev_lock); if (IS_ERR(devlink)) return PTR_ERR(devlink); @@ -117,7 +121,7 @@ static int __devlink_nl_pre_doit(struct sk_buff *skb, struct genl_info *info, return 0; unlock: - devl_unlock(devlink); + devl_dev_unlock(devlink, dev_lock); devlink_put(devlink); return err; } @@ -144,10 +148,11 @@ int devlink_nl_pre_doit_port_optional(const struct genl_split_ops *ops, static void __devlink_nl_post_doit(struct sk_buff *skb, struct genl_info *info, u8 flags) { + bool dev_lock = flags & DEVLINK_NL_FLAG_NEED_DEV_LOCK; struct devlink *devlink; devlink = info->user_ptr[0]; - devl_unlock(devlink); + devl_dev_unlock(devlink, dev_lock); devlink_put(devlink); } @@ -165,7 +170,7 @@ static int devlink_nl_inst_single_dumpit(struct sk_buff *msg, struct devlink *devlink; int err; - devlink = devlink_get_from_attrs_lock(sock_net(msg->sk), attrs); + devlink = devlink_get_from_attrs_lock(sock_net(msg->sk), attrs, false); if (IS_ERR(devlink)) return PTR_ERR(devlink); err = dump_one(msg, devlink, cb, flags | NLM_F_DUMP_FILTERED); diff --git a/net/devlink/region.c b/net/devlink/region.c index 0aab7b82d678..e3bab458db94 100644 --- a/net/devlink/region.c +++ b/net/devlink/region.c @@ -883,7 +883,8 @@ int devlink_nl_region_read_dumpit(struct sk_buff *skb, start_offset = state->start_offset; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , CC: Ido Schimmel , Petr Machata , "Amit Cohen" , , Jiri Pirko Subject: [PATCH net-next 05/14] devlink: Acquire device lock during reload command Date: Wed, 15 Nov 2023 13:17:14 +0100 Message-ID: <03cf077ca8d3a1a0a755866df1a99031e5badb14.1700047319.git.petrm@nvidia.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D9:EE_|PH7PR12MB7453:EE_ X-MS-Office365-Filtering-Correlation-Id: 1a860b34-537a-45ac-1300-08dbe5d52b39 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 4f+/dwIKAFC4dDouSqJchN4dPreQ74mvME9N6nSlvomxssEhBmJjZUeVVabGsZAqQXyZk0W3dP6TRxSvWo9mSoaZQyyf5TMrjsRIGH+K1/Jztj0/eYQnwzE8WY63eoIXIK8c0MAVvp3X9JXMg2fp7WgKHslJXKoOYmcLckDWzCc2ph4OoQ1CVhPSFfRDCO4lMoQr6U6Ct550DaNSUuk71QJ7GuBmDT343IKBON5ce7g5r4LjZLRLhv+mikg8O9JkThhOipr1qLghpHK5GpCPVwix2325IsVB/3IWlLS5KbjvlUxxOkJlkdwQZe0fMF3CFsVpLa/oEiHdHhw0TEE8xXMA34HQdrO6yysV/52lYkx92AjM9F7YUDCgxeV4zw1TNit1U57I9EnOI7xTazQj4JGeFhBaoFt0MvqVYbQHWWlNYIgL9f0kh2Rj6GUmva4QH6SF5GDonllb1MIM4GKOO+1v1DbCer6elm36rEWcq7sDP/v+Wk3O686wRen2m0BuBS9f4UVF9xg920CWqCa8pAchhwD57DI9NogQx8xKBgmoQuEFvFZe7PUtttv6KKMLGhQYOcSyEiD4dN6nUT/7xQ0Nst1dQ4Uyoa37Xl5cQdnIMG7rC2xgx80Po19RfJd/oUY9Jq/rI7Sn+4VdzEZRm4jL4pQojUiQ8OU5IWO79gbX9QE22xLPX/HEYJQnFOOQqOPwIZqZu0Zhu7kShVeoJXnJ95u2obhnc0VdZD2H3Pt4zH65I2BP9WoNY7SRz4YT X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(396003)(346002)(136003)(39860400002)(376002)(230922051799003)(64100799003)(451199024)(186009)(1800799009)(82310400011)(40470700004)(36840700001)(46966006)(40460700003)(8936002)(54906003)(70586007)(316002)(4326008)(8676002)(110136005)(2906002)(41300700001)(86362001)(5660300002)(83380400001)(2616005)(47076005)(7636003)(356005)(82740400003)(107886003)(426003)(336012)(26005)(16526019)(478600001)(36860700001)(70206006)(36756003)(6666004)(40480700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Nov 2023 12:19:51.7918 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1a860b34-537a-45ac-1300-08dbe5d52b39 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D9.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7453 X-Patchwork-Delegate: kuba@kernel.org From: Ido Schimmel Device drivers register with devlink from their probe routines (under the device lock) by acquiring the devlink instance lock and calling devl_register(). Drivers that support a devlink reload usually implement the reload_{down, up}() operations in a similar fashion to their remove and probe routines, respectively. However, while the remove and probe routines are invoked with the device lock held, the reload operations are only invoked with the devlink instance lock held. It is therefore impossible for drivers to acquire the device lock from their reload operations, as this would result in lock inversion. The motivating use case for invoking the reload operations with the device lock held is in mlxsw which needs to trigger a PCI reset as part of the reload. The driver cannot call pci_reset_function() as this function acquires the device lock. Instead, it needs to call __pci_reset_function_locked which expects the device lock to be held. To that end, adjust devlink to always acquire the device lock before the devlink instance lock when performing a reload. Do that when reload is explicitly triggered by user space by specifying the 'DEVLINK_NL_FLAG_NEED_DEV_LOCK' flag in the pre_doit and post_doit operations of the reload command. A previous patch already handled the case where reload is invoked as part of netns dismantle. Signed-off-by: Ido Schimmel Reviewed-by: Jiri Pirko Signed-off-by: Petr Machata Reviewed-by: Simon Horman --- Documentation/netlink/specs/devlink.yaml | 4 ++-- net/devlink/netlink.c | 13 +++++++++++++ net/devlink/netlink_gen.c | 4 ++-- net/devlink/netlink_gen.h | 5 +++++ 4 files changed, 22 insertions(+), 4 deletions(-) diff --git a/Documentation/netlink/specs/devlink.yaml b/Documentation/netlink/specs/devlink.yaml index 572d83a414d0..43067e1f63aa 100644 --- a/Documentation/netlink/specs/devlink.yaml +++ b/Documentation/netlink/specs/devlink.yaml @@ -1484,8 +1484,8 @@ operations: dont-validate: [ strict ] flags: [ admin-perm ] do: - pre: devlink-nl-pre-doit - post: devlink-nl-post-doit + pre: devlink-nl-pre-doit-dev-lock + post: devlink-nl-post-doit-dev-lock request: attributes: - bus-name diff --git a/net/devlink/netlink.c b/net/devlink/netlink.c index 86f12531bf99..fa9afe3e6d9b 100644 --- a/net/devlink/netlink.c +++ b/net/devlink/netlink.c @@ -138,6 +138,12 @@ int devlink_nl_pre_doit_port(const struct genl_split_ops *ops, return __devlink_nl_pre_doit(skb, info, DEVLINK_NL_FLAG_NEED_PORT); } +int devlink_nl_pre_doit_dev_lock(const struct genl_split_ops *ops, + struct sk_buff *skb, struct genl_info *info) +{ + return __devlink_nl_pre_doit(skb, info, DEVLINK_NL_FLAG_NEED_DEV_LOCK); +} + int devlink_nl_pre_doit_port_optional(const struct genl_split_ops *ops, struct sk_buff *skb, struct genl_info *info) @@ -162,6 +168,13 @@ void devlink_nl_post_doit(const struct genl_split_ops *ops, __devlink_nl_post_doit(skb, info, 0); } +void +devlink_nl_post_doit_dev_lock(const struct genl_split_ops *ops, + struct sk_buff *skb, struct genl_info *info) +{ + __devlink_nl_post_doit(skb, info, DEVLINK_NL_FLAG_NEED_DEV_LOCK); +} + static int devlink_nl_inst_single_dumpit(struct sk_buff *msg, struct netlink_callback *cb, int flags, devlink_nl_dump_one_func_t *dump_one, diff --git a/net/devlink/netlink_gen.c b/net/devlink/netlink_gen.c index 788dfdc498a9..95f9b4350ab7 100644 --- a/net/devlink/netlink_gen.c +++ b/net/devlink/netlink_gen.c @@ -846,9 +846,9 @@ const struct genl_split_ops devlink_nl_ops[73] = { { .cmd = DEVLINK_CMD_RELOAD, .validate = GENL_DONT_VALIDATE_STRICT, - .pre_doit = devlink_nl_pre_doit, + .pre_doit = devlink_nl_pre_doit_dev_lock, .doit = devlink_nl_reload_doit, - .post_doit = devlink_nl_post_doit, + .post_doit = devlink_nl_post_doit_dev_lock, .policy = devlink_reload_nl_policy, .maxattr = DEVLINK_ATTR_RELOAD_LIMITS, .flags = GENL_ADMIN_PERM | GENL_CMD_CAP_DO, diff --git a/net/devlink/netlink_gen.h b/net/devlink/netlink_gen.h index 0e9e89c31c31..02f3c0bfae0e 100644 --- a/net/devlink/netlink_gen.h +++ b/net/devlink/netlink_gen.h @@ -22,12 +22,17 @@ int devlink_nl_pre_doit(const struct genl_split_ops *ops, struct sk_buff *skb, struct genl_info *info); int devlink_nl_pre_doit_port(const struct genl_split_ops *ops, struct sk_buff *skb, struct genl_info *info); +int devlink_nl_pre_doit_dev_lock(const struct genl_split_ops *ops, + struct sk_buff *skb, struct genl_info *info); int devlink_nl_pre_doit_port_optional(const struct genl_split_ops *ops, struct sk_buff *skb, struct genl_info *info); void devlink_nl_post_doit(const struct genl_split_ops *ops, struct sk_buff *skb, struct genl_info *info); +void +devlink_nl_post_doit_dev_lock(const struct genl_split_ops *ops, + struct sk_buff *skb, struct genl_info *info); int devlink_nl_get_doit(struct sk_buff *skb, struct genl_info *info); int devlink_nl_get_dumpit(struct sk_buff *skb, struct netlink_callback *cb); From patchwork Wed Nov 15 12:17:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Petr Machata X-Patchwork-Id: 13456625 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5A4A818041 for ; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , CC: Ido Schimmel , Petr Machata , "Amit Cohen" , , Jiri Pirko Subject: [PATCH net-next 06/14] devlink: Add device lock assert in reload operation Date: Wed, 15 Nov 2023 13:17:15 +0100 Message-ID: X-Mailer: git-send-email 2.41.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A0FB:EE_|SA1PR12MB6945:EE_ X-MS-Office365-Filtering-Correlation-Id: b8d4a76d-8164-4fee-b594-08dbe5d52e63 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 2JDY142s4Zk+uE2xHzNPpXGtEo0Zf0UBUZNOh/aWtPYwSx1MOHys4yriN9B5jvKuSUBVAaAhGsMP/68cax6BlqV/b4pdBEnAiuPI7bC3yUYa2r52XFJ8mAMLW0NMPqR/uDarxuM6Etb9LcyxjeGO578kY6x1xS9xEbAq5Ut1pvq0Zg0kg1iLsIukUamzRMpE0EL35QvFFMaEGFjMr6Zo80j2jdXy0qSl03MZRs2cnVY/NR0Bp4xNIwApPN6PJbg3JotaSTVgSJtRt2Xo6a3mfnq/ArgtVii76RNqA81jDN8P/Bq96dsMCZEQNvvSAyNvQj/PQLBgOs5uoTzo/rKSjq3p/TjV8nA4awyW02nkX0aNpbIlHCQDcfGG+kN+GVMMWeP0+kVRqtwQ8iZEra9XL07LEx7ntouMEsgEXWz48pPIBIYWi8zide78xDfVfLXljILAa4uLFi09E+fJVlbn00WDeJjXZvj8fTgpkdUjSqSvauoHaasr1ijzQMHdQepOHSF743QJqn4LKlJaCSzGLl76LwYQVeZEbwaC/2XgijoAWKuZ9YoYAE9zAJ5oy+1cYgcd9zkfN0yz2Rb5CVNpQhSbKd2r+NL2dlsf4eApMlgg8NdS8qCApP0NbS8MEIa9pwz4VRNL3Z9IMk3vTCv/+EbGpjz8vW9HvgrKmkVcSbvF9gW0p1FpPRdrpa0tnOx9hKi5kkrQFJZ+jYNvMPb5qcZQHKtuzPeGNtr4KYm7OGc= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(396003)(39860400002)(346002)(136003)(376002)(230922051799003)(1800799009)(186009)(82310400011)(451199024)(64100799003)(36840700001)(40470700004)(46966006)(36756003)(40460700003)(4326008)(83380400001)(8676002)(8936002)(70206006)(70586007)(110136005)(316002)(26005)(54906003)(426003)(336012)(16526019)(2906002)(47076005)(5660300002)(36860700001)(478600001)(6666004)(2616005)(107886003)(40480700001)(82740400003)(86362001)(41300700001)(356005)(7636003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Nov 2023 12:19:56.9950 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b8d4a76d-8164-4fee-b594-08dbe5d52e63 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A0FB.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB6945 X-Patchwork-Delegate: kuba@kernel.org From: Ido Schimmel Add an assert to verify that the device lock is always held throughout reload operations. Tested the following flows with netdevsim and mlxsw while lockdep is enabled: netdevsim: # echo "10 1" > /sys/bus/netdevsim/new_device # devlink dev reload netdevsim/netdevsim10 # ip netns add bla # devlink dev reload netdevsim/netdevsim10 netns bla # ip netns del bla # echo 10 > /sys/bus/netdevsim/del_device mlxsw: # devlink dev reload pci/0000:01:00.0 # ip netns add bla # devlink dev reload pci/0000:01:00.0 netns bla # ip netns del bla # echo 1 > /sys/bus/pci/devices/0000\:01\:00.0/remove # echo 1 > /sys/bus/pci/rescan Signed-off-by: Ido Schimmel Reviewed-by: Jiri Pirko Signed-off-by: Petr Machata Reviewed-by: Simon Horman --- net/devlink/dev.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/net/devlink/dev.c b/net/devlink/dev.c index 4fc7adb32663..ea6a92f2e6a2 100644 --- a/net/devlink/dev.c +++ b/net/devlink/dev.c @@ -4,6 +4,7 @@ * Copyright (c) 2016 Jiri Pirko */ +#include #include #include #include "devl_internal.h" @@ -433,6 +434,13 @@ int devlink_reload(struct devlink *devlink, struct net *dest_net, struct net *curr_net; int err; + /* Make sure the reload operations are invoked with the device lock + * held to allow drivers to trigger functionality that expects it + * (e.g., PCI reset) and to close possible races between these + * operations and probe/remove. + */ + device_lock_assert(devlink->dev); + memcpy(remote_reload_stats, devlink->stats.remote_reload_stats, sizeof(remote_reload_stats)); From patchwork Wed Nov 15 12:17:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Petr Machata X-Patchwork-Id: 13456626 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AC3B418646 for ; Wed, 15 Nov 2023 12:20:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="cPbV2ICE" Received: from NAM02-SN1-obe.outbound.protection.outlook.com (mail-sn1nam02on2059.outbound.protection.outlook.com [40.107.96.59]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5E31C123 for ; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , CC: Ido Schimmel , Petr Machata , "Amit Cohen" , , Bjorn Helgaas Subject: [PATCH net-next 07/14] PCI: Add no PM reset quirk for NVIDIA Spectrum devices Date: Wed, 15 Nov 2023 13:17:16 +0100 Message-ID: X-Mailer: git-send-email 2.41.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000989E7:EE_|IA1PR12MB6553:EE_ X-MS-Office365-Filtering-Correlation-Id: da0be9bf-f4c2-43d3-8ee8-08dbe5d52f90 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: CZmqus1Rbm0o8VQ5FBwHD5+7NZ/cHNjeDVYMq4deL/84tw0CZ0gFiQCwAW9YlswxX41fpjvURlvZlk3L8DoowEaZm6q1x28JswKPlBpSbcrY+htBWfu8S/fj3+qCeXn5bZckaNObv5u3Jno6gqrpqAy2F4CEtwavzOLeIPXq7jjRtF5zmBuMemWnMegP1RRZh0Up7kCMyA6GpAW7lL8B7bjs3saIdnKYYfUE0dkGTiaXq/vrhKxSzftdjFz/i9uuCmXc+BTTHZOUd3yEJ9aQifniIBkJ5hEJVO6DCHuyt7bezdrIbvacWcwNBloSGFAj0UfJJGc967tdE9Z/5FF6aZucqf5n3NLSZ33kJcGCUDhgsx9nU/aDkuAc4x0oVB4YO27DSa7Ow2hG/TJB+8KlbeZgPGZzersqtR6ARSw5EAChuqAFznYShq/mbYagUUbrRgwaxKyn9QwEgOqY2vHZ5zLLntNWc9lGckdubR6er06/rGwehYmiWVuxMVdCioHNbOcfWq6/M1oapvku/vYJbtvGrPd5zcRCWAtBrVtrg1SyKSdcb+vs8tY07CGQMQE2ysvgBR3/GJmZ46L8ICcOL5/idmbA6KxJClxcUme6FRo2a3lDcwwzw1egzOsqgfw0O/pUhPSrdn3c50Bvx5yWz1b38TE8j2PBJ9/AVCVZxhU+fxo+xq1TcYZ5vdwytHrpRRZkRQfUUBdagP8tjclpH+s89L08RO/KuspEOcLMOWP0e2PbUY3pmguCydn4FjAN X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(39860400002)(346002)(376002)(396003)(136003)(230922051799003)(451199024)(64100799003)(82310400011)(186009)(1800799009)(46966006)(36840700001)(40470700004)(47076005)(7636003)(356005)(40480700001)(6666004)(36860700001)(40460700003)(426003)(336012)(5660300002)(26005)(82740400003)(2616005)(86362001)(2906002)(70206006)(54906003)(8676002)(8936002)(4326008)(316002)(36756003)(70586007)(110136005)(41300700001)(16526019)(478600001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Nov 2023 12:19:59.0292 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: da0be9bf-f4c2-43d3-8ee8-08dbe5d52f90 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000989E7.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6553 X-Patchwork-Delegate: kuba@kernel.org From: Ido Schimmel Spectrum-{1,2,3,4} devices report that a D3hot->D0 transition causes a reset (i.e., they advertise NoSoftRst-). However, this transition does not have any effect on the device: It continues to be operational and network ports remain up. Advertising this support makes it seem as if a PM reset is viable for these devices. Mark it as unavailable to skip it when testing reset methods. Before: # cat /sys/bus/pci/devices/0000\:03\:00.0/reset_method pm bus After: # cat /sys/bus/pci/devices/0000\:03\:00.0/reset_method bus Signed-off-by: Ido Schimmel Acked-by: Bjorn Helgaas Signed-off-by: Petr Machata --- drivers/pci/quirks.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index ea476252280a..d208047d1b8f 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -3786,6 +3786,19 @@ static void quirk_no_pm_reset(struct pci_dev *dev) DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset); +/* + * Spectrum-{1,2,3,4} devices report that a D3hot->D0 transition causes a reset + * (i.e., they advertise NoSoftRst-). However, this transition does not have + * any effect on the device: It continues to be operational and network ports + * remain up. Advertising this support makes it seem as if a PM reset is viable + * for these devices. Mark it as unavailable to skip it when testing reset + * methods. + */ +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcb84, quirk_no_pm_reset); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcf6c, quirk_no_pm_reset); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcf70, quirk_no_pm_reset); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcf80, quirk_no_pm_reset); + /* * Thunderbolt controllers with broken MSI hotplug signaling: * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part From patchwork Wed Nov 15 12:17:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Petr Machata X-Patchwork-Id: 13456627 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D8BC018AEB for ; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , CC: Ido Schimmel , Petr Machata , "Amit Cohen" , , Bjorn Helgaas Subject: [PATCH net-next 08/14] PCI: Add debug print for device ready delay Date: Wed, 15 Nov 2023 13:17:17 +0100 Message-ID: <63fca173195f5a9d3a2b78da700650a29cf80f96.1700047319.git.petrm@nvidia.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A0FB:EE_|PH0PR12MB5434:EE_ X-MS-Office365-Filtering-Correlation-Id: 732c6a9d-c492-44c2-8fe9-08dbe5d5316a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: qOx/qLnMwKZxz9cgEoQXBP7TjmJObFQRu7ajWBZgAf9AHa4djUWNJPmZhgSJlSb6CSXtCnVtLZMsXtIZB+p7NtnQDWXrifGR6xmroooooHOwtWUhuw3twkRq8O/FVkxRMB7qLG3+zJDZ29YqmNZ/Hhl37jv1DoEkdZq9Va44HRpX3/LNKVZ+XfcXxlirgCURhDUXBe/hj2wBiVwRy6QtvB+ShZdto8RlUSpu+BhRbQBl0AAkbD8SzGhRqzrBaI7Y1FIL/mq86mwUi2gOrb4yqnDD9vmGkFf1KR3X6s7gLNl1M4EB2ZXflwjYswHDQp3PbP/f/CyShWM0WfR5vIoHDQo0sBhsG0chZ4Tk1aBFVh2+JV9nVrdzkjptckmuvZo4nuN0qmAD0tkzJrKpOuoWwgYnId9pHp520kiBBj9af92h/+Fifp2PKy5F/iiE9kyDIR7XjPO0P6NVcDJnDi5sJ9Cr1CookVkCTvUvVYCznhLaqMmSm5tYQVUz3VcFSTUjl45ek0SlDFbCCkZoBN4SAKFdihnnA1K/cuBDAeqHyOUa/ppqYm5srWcfXuZCs5u4yeDXxIKXgDHVaaTNI3jwRVBtyj7CL5cXFSW4cKCOIwEui2dNhE/YG4SGqi6Lsfv2bxkuI35rwExf8dENyy3Ou2rGs86wyfT2VE68umtrjuu94pr7ZTgsulLrdlQEuKrgX0aWo1wWxO3kz+V+ICE+rwkHVT+vCMHEzQDRVjJNb41W/KMFEo2UbFs/Otwfw+xt X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(346002)(39860400002)(376002)(396003)(136003)(230922051799003)(64100799003)(82310400011)(451199024)(186009)(1800799009)(36840700001)(46966006)(40470700004)(36756003)(83380400001)(82740400003)(2616005)(40460700003)(336012)(2906002)(426003)(16526019)(26005)(41300700001)(36860700001)(356005)(7636003)(47076005)(86362001)(70586007)(110136005)(70206006)(8936002)(54906003)(8676002)(316002)(4326008)(478600001)(6666004)(5660300002)(40480700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Nov 2023 12:20:02.0731 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 732c6a9d-c492-44c2-8fe9-08dbe5d5316a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A0FB.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5434 X-Patchwork-Delegate: kuba@kernel.org From: Ido Schimmel Currently, the time it took a PCI device to become ready after reset is only printed if it was longer than 1000ms ('PCI_RESET_WAIT'). However, for debugging purposes it is useful to know this time even if it was shorter. For example, with the device I am working on, hardware engineers asked to verify that it becomes ready on the first try (no delay). To that end, add a debug level print that can be enabled using dynamic debug. Example: # echo 1 > /sys/bus/pci/devices/0000\:01\:00.0/reset # dmesg -c | grep ready # echo "file drivers/pci/pci.c +p" > /sys/kernel/debug/dynamic_debug/control # echo 1 > /sys/bus/pci/devices/0000\:01\:00.0/reset # dmesg -c | grep ready [ 396.060335] mlxsw_spectrum4 0000:01:00.0: ready 0ms after bus reset # echo "file drivers/pci/pci.c -p" > /sys/kernel/debug/dynamic_debug/control # echo 1 > /sys/bus/pci/devices/0000\:01\:00.0/reset # dmesg -c | grep ready Signed-off-by: Ido Schimmel Acked-by: Bjorn Helgaas Signed-off-by: Petr Machata Reviewed-by: Simon Horman --- drivers/pci/pci.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 55bc3576a985..69d20d585f88 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -1219,6 +1219,9 @@ static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout) if (delay > PCI_RESET_WAIT) pci_info(dev, "ready %dms after %s\n", delay - 1, reset_type); + else + pci_dbg(dev, "ready %dms after %s\n", delay - 1, + reset_type); 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , CC: Ido Schimmel , Petr Machata , "Amit Cohen" , Subject: [PATCH net-next 09/14] mlxsw: Extend MRSR pack() function to support new commands Date: Wed, 15 Nov 2023 13:17:18 +0100 Message-ID: <07ddefc8ba97f401402ba2e43a7d37677b26cc16.1700047319.git.petrm@nvidia.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A0F9:EE_|CY5PR12MB6058:EE_ X-MS-Office365-Filtering-Correlation-Id: aee02fe4-c16a-4ee2-1f62-08dbe5d532e5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 4XO97t7LOuQb0pxuq1M9AmhRuiFCCzwM30qFM3quOGDdv84I/1/FvUCbVLbNpf07Djab4j5Yj09Mszy4xha4g9vMk2BQmcXQ4IJR8tBIXOBnJp76OCdRgvVYqmWzOi7nhIvyQ8CE2sPmZmwx0jfmy8UG9eC00Le0QgV8V9J3TBpRo6d7PQVLCddHrFnKBBwmlpTjAvIPciAbVrC3Jf1MGApKbKjUWi0iaxfxI0sYWpHYe1AbrWwrYpPTAUEEKy8orcOzCqilG27ufZ9iMM5MSsXJObCW7+ZT+7FCucWyFso2TVTq8+7J4z+f1qzqM04c/H1Dx+SbIxXYyYb68BdWLjoKB+jivUCiy4HMq15ig8HzNL33fLL3YgKrNu2VjqTQwrxv4BxUkK4u4Z7TIuBnHSHZJok3WyTmgJ4YPPsu6lHtEOeDHxVsY4/+qh39b94BI/n9s3HOAttjZLgsZ3xtL70bgi3RWem5gbiE8rsklXl1FtSEJJR6ZO8AzJxQ1HbVuOTdrleWNCjvlBflSHAu+x3HRZTTynNSVWPyf/ih4OcUIgbpi8YQwGyqnqKMDrUQsIlvgLzF7RSC5cw8roGb4EuQaIOBoEAKZM51BK4aReptBrAsY7JqiBh58WVq6K+g+e9FWNTY8aXf8d6acfqAQZnNYhbgoZwLSOSBXJI0oB2WvSMQ+BkjWKyudy+BwKIhfYFXwBHT8BHlwT1pg8cnyF3k0JNX88Y0lpQJmk/tK0c= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(396003)(136003)(376002)(39860400002)(346002)(230922051799003)(64100799003)(186009)(1800799009)(82310400011)(451199024)(36840700001)(40470700004)(46966006)(47076005)(36860700001)(36756003)(5660300002)(8676002)(41300700001)(336012)(83380400001)(426003)(82740400003)(356005)(7636003)(40480700001)(2616005)(16526019)(26005)(6666004)(40460700003)(86362001)(107886003)(54906003)(70206006)(70586007)(4326008)(2906002)(478600001)(8936002)(110136005)(316002);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Nov 2023 12:20:04.5853 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: aee02fe4-c16a-4ee2-1f62-08dbe5d532e5 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A0F9.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6058 X-Patchwork-Delegate: kuba@kernel.org From: Amit Cohen Currently mlxsw_reg_mrsr_pack() always sets 'command=1'. As preparation for support of new reset flow, pass the command as an argument to the function and add an enum for this field. For now, always pass 'command=1' to the pack() function. Signed-off-by: Amit Cohen Reviewed-by: Petr Machata Signed-off-by: Ido Schimmel Signed-off-by: Petr Machata Reviewed-by: Simon Horman --- drivers/net/ethernet/mellanox/mlxsw/pci.c | 2 +- drivers/net/ethernet/mellanox/mlxsw/reg.h | 14 ++++++++++++-- 2 files changed, 13 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlxsw/pci.c b/drivers/net/ethernet/mellanox/mlxsw/pci.c index e4b25e187467..7af37f78ed1a 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/pci.c +++ b/drivers/net/ethernet/mellanox/mlxsw/pci.c @@ -1491,7 +1491,7 @@ static int mlxsw_pci_sw_reset(struct mlxsw_pci *mlxsw_pci, return err; } - mlxsw_reg_mrsr_pack(mrsr_pl); + mlxsw_reg_mrsr_pack(mrsr_pl, MLXSW_REG_MRSR_COMMAND_SOFTWARE_RESET); err = mlxsw_reg_write(mlxsw_pci->core, MLXSW_REG(mrsr), mrsr_pl); if (err) return err; diff --git a/drivers/net/ethernet/mellanox/mlxsw/reg.h b/drivers/net/ethernet/mellanox/mlxsw/reg.h index 25b294fdeb3d..13c0ff994537 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/reg.h +++ b/drivers/net/ethernet/mellanox/mlxsw/reg.h @@ -10122,6 +10122,15 @@ mlxsw_reg_mgir_unpack(char *payload, u32 *hw_rev, char *fw_info_psid, MLXSW_REG_DEFINE(mrsr, MLXSW_REG_MRSR_ID, MLXSW_REG_MRSR_LEN); +enum mlxsw_reg_mrsr_command { + /* Switch soft reset, does not reset PCI firmware. */ + MLXSW_REG_MRSR_COMMAND_SOFTWARE_RESET = 1, + /* Reset will be done when PCI link will be disabled. + * This command will reset PCI firmware also. + */ + MLXSW_REG_MRSR_COMMAND_RESET_AT_PCI_DISABLE = 6, +}; + /* reg_mrsr_command * Reset/shutdown command * 0 - do nothing @@ -10130,10 +10139,11 @@ MLXSW_REG_DEFINE(mrsr, MLXSW_REG_MRSR_ID, MLXSW_REG_MRSR_LEN); */ MLXSW_ITEM32(reg, mrsr, command, 0x00, 0, 4); -static inline void mlxsw_reg_mrsr_pack(char *payload) +static inline void mlxsw_reg_mrsr_pack(char *payload, + enum mlxsw_reg_mrsr_command command) { MLXSW_REG_ZERO(mrsr, payload); - mlxsw_reg_mrsr_command_set(payload, 1); + mlxsw_reg_mrsr_command_set(payload, command); } /* MLCR - Management LED Control Register From patchwork Wed Nov 15 12:17:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Petr Machata X-Patchwork-Id: 13456629 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7208918C20 for ; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , CC: Ido Schimmel , Petr Machata , "Amit Cohen" , Subject: [PATCH net-next 10/14] mlxsw: pci: Rename mlxsw_pci_sw_reset() Date: Wed, 15 Nov 2023 13:17:19 +0100 Message-ID: X-Mailer: git-send-email 2.41.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A0FF:EE_|MN2PR12MB4256:EE_ X-MS-Office365-Filtering-Correlation-Id: 91b9d4cd-b564-41c9-3a54-08dbe5d53442 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: brk3oSKOqNPbbcBEJnml2LKJaXDkDq5qkDZz3aVCbrXVUiycIRBTLHpOAd7CLsYibVqErHLE+H4GY/DQbiGIDVPZq4X8NLYCDQpR4UfWHqEu3PZNoxfDpUdh8MmFR009ZX6E+6MAzrElC6fZUMGcka/czJAcKP85B77nidig69Brs9KVz9IurIKPN6VkbDS0puOP85j32w+SZzfBvRXL6fq1+5GkMey9v680hwxYt9BQDMlSebx+r+WdN1NNAaOAv8vhjvmTRS1d47Mf2czs6VIYFcBw0jde5s3ay5MvbZ6xJsWcGqKPVLv1j21u5bPbTCNmzOpPnQnesK0hrnITW9uVETu95V+rxx4eIzg6BXn+WjgPqnc/45VC6R2/zcFp8Qsn1sqRnAUsKHS2fZW2xdx3dPsp2WzIYaSrBq8jVdTQh5AmoVGiWkDH+tuetpIW2Lma6zC0D8M9iRIhd8LOh+iw/pHDx4mrwf3o/K3Cvz2x5QYDaS1R55LCmu7vWjJic18SmqMh82P8lGgCkBe7jD0Gu2Q7gOI9x9cvmiUeyyAAlKjpMLv6gYZW22llUj2Rp51yQJpL33+weE2oESiWgVmwSxDPrmbvSTceMOSXg1/f3bbynsiUHIFS3EPs6/r61zXKWTOx55U3t6fYypBPEhVqO+Q3UJJQGDmhmet7EcsNi1TPCMpoX6aPvZ1zH2Bk3SZCgA1XF6T3f3o/WDW3JDwzAdNxXcv4KFL0YZoQ+u6r/ijf+ckHs/TGvd1SEDrs X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(346002)(39860400002)(376002)(136003)(396003)(230922051799003)(451199024)(82310400011)(64100799003)(1800799009)(186009)(40470700004)(46966006)(36840700001)(2906002)(41300700001)(36756003)(36860700001)(356005)(7636003)(40460700003)(86362001)(47076005)(5660300002)(316002)(478600001)(2616005)(70206006)(54906003)(70586007)(110136005)(82740400003)(26005)(16526019)(107886003)(336012)(426003)(83380400001)(40480700001)(6666004)(4326008)(8936002)(8676002);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Nov 2023 12:20:06.8576 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 91b9d4cd-b564-41c9-3a54-08dbe5d53442 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A0FF.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4256 X-Patchwork-Delegate: kuba@kernel.org From: Amit Cohen In the next patches, mlxsw_pci_sw_reset() will be extended to support more reset types and will not necessarily issue a software reset. Rename the function to reflect that. Signed-off-by: Amit Cohen Reviewed-by: Petr Machata Signed-off-by: Ido Schimmel Signed-off-by: Petr Machata Reviewed-by: Simon Horman --- drivers/net/ethernet/mellanox/mlxsw/pci.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlxsw/pci.c b/drivers/net/ethernet/mellanox/mlxsw/pci.c index 7af37f78ed1a..fe0b8a38d44e 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/pci.c +++ b/drivers/net/ethernet/mellanox/mlxsw/pci.c @@ -1476,8 +1476,8 @@ static int mlxsw_pci_sys_ready_wait(struct mlxsw_pci *mlxsw_pci, return -EBUSY; } -static int mlxsw_pci_sw_reset(struct mlxsw_pci *mlxsw_pci, - const struct pci_device_id *id) +static int +mlxsw_pci_reset(struct mlxsw_pci *mlxsw_pci, const struct pci_device_id *id) { struct pci_dev *pdev = mlxsw_pci->pdev; char mrsr_pl[MLXSW_REG_MRSR_LEN]; @@ -1537,9 +1537,9 @@ static int mlxsw_pci_init(void *bus_priv, struct mlxsw_core *mlxsw_core, if (!mbox) return -ENOMEM; - err = mlxsw_pci_sw_reset(mlxsw_pci, mlxsw_pci->id); + err = mlxsw_pci_reset(mlxsw_pci, mlxsw_pci->id); if (err) - goto err_sw_reset; + goto err_reset; err = mlxsw_pci_alloc_irq_vectors(mlxsw_pci); if (err < 0) { @@ -1672,7 +1672,7 @@ static int mlxsw_pci_init(void *bus_priv, struct mlxsw_core *mlxsw_core, err_query_fw: mlxsw_pci_free_irq_vectors(mlxsw_pci); err_alloc_irq: -err_sw_reset: +err_reset: mbox_put: mlxsw_cmd_mbox_free(mbox); return err; From patchwork Wed Nov 15 12:17:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Petr Machata X-Patchwork-Id: 13456630 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F41EC18055 for ; Wed, 15 Nov 2023 12:20:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="qKqPxnfp" Received: from NAM02-SN1-obe.outbound.protection.outlook.com (mail-sn1nam02on20614.outbound.protection.outlook.com [IPv6:2a01:111:f400:7ea9::614]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0B5B19B for ; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , CC: Ido Schimmel , Petr Machata , "Amit Cohen" , Subject: [PATCH net-next 11/14] mlxsw: pci: Move software reset code to a separate function Date: Wed, 15 Nov 2023 13:17:20 +0100 Message-ID: <395237a59d495700926cefa8bb713cdd9364fbc7.1700047319.git.petrm@nvidia.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A0FE:EE_|PH0PR12MB7931:EE_ X-MS-Office365-Filtering-Correlation-Id: 2d12ec4e-76f6-4136-2a6e-08dbe5d535d9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: sB/KvxRxYt+xHQS6l95FUawFUXGWV5oTil7tpX/B29XPuSM0GziWBw3d9+C8joPv44Pimh46IjgN6qOm+hTIS098KxwFJW/pAqIZM9scKuQd+vgDhpdowUHS/XdwLabdX3j3pJ2nWziTcttXLE2S555EocwHGvMbx5KMXTpqWzghGdE1bgX3Hj/IO3LjSsBsmuoWLF4ID6EFEb+DTcPQ+RKaV+LK4A5rGEC5CNuYEmRjfd9ue09HaggK0DpQeI9r0ZK/RVZZ8R6twNuq9M8zgo/ShHDBcbESvsfp3aabQfeRt+mBCjs5HjOqDmbKaxnjh2zwvWrKH0DkCXHrT94c4cJjuhun5p1UDRODc8uDBXLBO3GXKwI3kAn3INKFe10RI1Q4QeYHuDaZWXusK+gWs2HsQAmk/xoPnRru+Dw7YWtByWfaAKaHvVYCma/tkZXPCujGKEpNQvVRrpxPchPOPBDtqK+8zls/6/l/Yzw9b4JjlvPiRwbJXZ2o5nOe9ovDSBQbfi5qku5aJxKtnv9k3hGm1HuoSCGRVVe8K7/g1vPP0mS7MA1EmpojrEBKBxoDvRGiK2K2796XG8QaLnjc14NMZNjdB6lzQxjV3VebDCnturBKKmcV970iA2aMcok1bua/ddgJbOnd6TkZ8UORZRxLT/UeNw03qveQ9mn9flbqfNnJovQgwgWfXRpX0ddmvGjPjlKa7eype+fe0C7o1KMM47gTi7Bq3+h8c5Gamyo= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(376002)(39860400002)(396003)(346002)(136003)(230922051799003)(451199024)(1800799009)(82310400011)(186009)(64100799003)(36840700001)(46966006)(40470700004)(86362001)(70206006)(70586007)(40460700003)(478600001)(47076005)(6666004)(82740400003)(54906003)(316002)(110136005)(336012)(426003)(83380400001)(16526019)(7636003)(107886003)(26005)(356005)(2616005)(41300700001)(36860700001)(8676002)(8936002)(2906002)(5660300002)(4326008)(36756003)(40480700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Nov 2023 12:20:09.5245 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2d12ec4e-76f6-4136-2a6e-08dbe5d535d9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A0FE.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB7931 X-Patchwork-Delegate: kuba@kernel.org From: Amit Cohen In general, the existing flow of software reset in the driver is: 1. Wait for system ready status. 2. Send MRSR command, to start the reset. 3. Wait for system ready status. This flow will be extended once a new reset command is supported. As a preparation, move step #2 to a separate function. Signed-off-by: Amit Cohen Reviewed-by: Petr Machata Signed-off-by: Ido Schimmel Signed-off-by: Petr Machata Reviewed-by: Simon Horman --- drivers/net/ethernet/mellanox/mlxsw/pci.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlxsw/pci.c b/drivers/net/ethernet/mellanox/mlxsw/pci.c index fe0b8a38d44e..080881c94c5a 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/pci.c +++ b/drivers/net/ethernet/mellanox/mlxsw/pci.c @@ -1476,11 +1476,18 @@ static int mlxsw_pci_sys_ready_wait(struct mlxsw_pci *mlxsw_pci, return -EBUSY; } -static int -mlxsw_pci_reset(struct mlxsw_pci *mlxsw_pci, const struct pci_device_id *id) +static int mlxsw_pci_reset_sw(struct mlxsw_pci *mlxsw_pci) { - struct pci_dev *pdev = mlxsw_pci->pdev; char mrsr_pl[MLXSW_REG_MRSR_LEN]; + + mlxsw_reg_mrsr_pack(mrsr_pl, MLXSW_REG_MRSR_COMMAND_SOFTWARE_RESET); + return mlxsw_reg_write(mlxsw_pci->core, MLXSW_REG(mrsr), mrsr_pl); +} + +static int +mlxsw_pci_reset(struct mlxsw_pci *mlxsw_pci, const struct pci_device_id *id) +{ + struct pci_dev *pdev = mlxsw_pci->pdev; u32 sys_status; int err; @@ -1491,8 +1498,7 @@ mlxsw_pci_reset(struct mlxsw_pci *mlxsw_pci, const struct pci_device_id *id) return err; } - mlxsw_reg_mrsr_pack(mrsr_pl, MLXSW_REG_MRSR_COMMAND_SOFTWARE_RESET); - err = mlxsw_reg_write(mlxsw_pci->core, MLXSW_REG(mrsr), mrsr_pl); + err = mlxsw_pci_reset_sw(mlxsw_pci); if (err) return err; From patchwork Wed Nov 15 12:17:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Petr Machata X-Patchwork-Id: 13456631 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 02AFF1946A for ; Wed, 15 Nov 2023 12:20:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="VPKktwqC" Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2049.outbound.protection.outlook.com [40.107.220.49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AE01011F for ; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , CC: Ido Schimmel , Petr Machata , "Amit Cohen" , Subject: [PATCH net-next 12/14] mlxsw: pci: Add support for new reset flow Date: Wed, 15 Nov 2023 13:17:21 +0100 Message-ID: <2b6629170e815abed5dfc7f560a69a1accaeb1f2.1700047319.git.petrm@nvidia.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000989EC:EE_|CH0PR12MB5218:EE_ X-MS-Office365-Filtering-Correlation-Id: 92e6f9c2-798b-4991-abf8-08dbe5d5368a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: vr15i2pUTkHdlL9fntyvC/SW+Z0Ccch2hS4Qw8D+zdGEtD0tRpl1xg/lX6tNclrPLAMx/GarQaBW72oOGEagj49EUsleo64XjwBA1zCgfSsRN9AnVT5KgbACB3J1ngh9sM+KQoRG2qGyIksL0eRjRMEcN5ZM5MrH9sxVUG5hCy61Czoord4hi1Xz7rulPOp+b+yfrs982n9BE3OdLZAIhCBdnbKrkpa8QlAUmHjAeLYnjlvdUWAVbquU3mVitAA9h4JKF0wnB4EJomxaNcsxx3gCBezVQNx4txEkpzsVD4338nl1b9ma7Z3BE9AUFKh2d/QvYpZ8FFr4/37IWZZ4A8VMJj7QHK8z8fdvkzZpvRpAPVvb/472/+HC7eh/qky3rvhJ3sKzn+LDgkTSfw1MJE5XRCsKFIQ8TYCgya3mRQt+UgsfInW98YEvd8QlGGydTVJ2GOjBOCXRFyMNugrUh4PIu9XB/SrSDwyyivmL2A93OebyUZ6TkFufzbdYkByEYHHYVbbnxvvAU2skftj/DP6nVAyJdiFXIB7XKw8arHVnbfARtt6otu3Rne5fTjpYtGqDghpyQW8OB7bfN5cCR0C3IcXeloC+bakfHftHgTYV8PfsAvGagPjtworLEgftF0UhzZCAv1POJwYuSG4aud3qz00nCjJXgL3ioPJBkbH79i/RAA8e/BwcLlTRNb+0wP1sQrIXNWVC4Y6oooG7yJz9p1CjczcSv3G4iH2DB46Izulz+/r+g01KKi0/dU/S X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(136003)(396003)(376002)(346002)(39860400002)(230922051799003)(82310400011)(64100799003)(186009)(1800799009)(451199024)(40470700004)(46966006)(36840700001)(41300700001)(47076005)(4326008)(8676002)(8936002)(36860700001)(316002)(26005)(336012)(426003)(36756003)(83380400001)(40480700001)(107886003)(16526019)(82740400003)(356005)(7636003)(2616005)(6666004)(40460700003)(478600001)(2906002)(5660300002)(110136005)(70206006)(70586007)(54906003)(86362001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Nov 2023 12:20:10.7347 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 92e6f9c2-798b-4991-abf8-08dbe5d5368a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000989EC.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5218 X-Patchwork-Delegate: kuba@kernel.org From: Ido Schimmel The driver resets the device during probe and during a devlink reload. The current reset method reloads the current firmware version or a pending one, if one was previously flashed using devlink. However, the current reset method does not result in a PCI hot reset, preventing the PCI firmware from being upgraded, unless the system is rebooted. To solve this problem, a new reset command (6) was implemented in the firmware. Unlike the current command (1), after issuing the new command the device will not start the reset immediately, but only after a PCI hot reset. Implement the new reset method by first verifying that it is supported by the current firmware version by querying the Management Capabilities Mask (MCAM) register. If supported, issue the new reset command (6) via MRSR register followed by a PCI reset by calling __pci_reset_function_locked(). Once the PCI firmware is operational, go back to the regular reset flow and wait for the entire device to become ready. That is, repeatedly read the "system_status" register from the BAR until a value of "FW_READY" (0x5E) appears. Tested: # for i in $(seq 1 10); do devlink dev reload pci/0000:01:00.0; done Signed-off-by: Ido Schimmel Reviewed-by: Petr Machata Signed-off-by: Petr Machata Reviewed-by: Simon Horman --- drivers/net/ethernet/mellanox/mlxsw/pci.c | 44 ++++++++++++++++++++++- drivers/net/ethernet/mellanox/mlxsw/reg.h | 2 ++ 2 files changed, 45 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlxsw/pci.c b/drivers/net/ethernet/mellanox/mlxsw/pci.c index 080881c94c5a..726ed707e27b 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/pci.c +++ b/drivers/net/ethernet/mellanox/mlxsw/pci.c @@ -1476,6 +1476,33 @@ static int mlxsw_pci_sys_ready_wait(struct mlxsw_pci *mlxsw_pci, return -EBUSY; } +static int mlxsw_pci_reset_at_pci_disable(struct mlxsw_pci *mlxsw_pci) +{ + struct pci_dev *pdev = mlxsw_pci->pdev; + char mrsr_pl[MLXSW_REG_MRSR_LEN]; + int err; + + mlxsw_reg_mrsr_pack(mrsr_pl, + MLXSW_REG_MRSR_COMMAND_RESET_AT_PCI_DISABLE); + err = mlxsw_reg_write(mlxsw_pci->core, MLXSW_REG(mrsr), mrsr_pl); + if (err) + return err; + + device_lock_assert(&pdev->dev); + + pci_cfg_access_lock(pdev); + pci_save_state(pdev); + + err = __pci_reset_function_locked(pdev); + if (err) + pci_err(pdev, "PCI function reset failed with %d\n", err); + + pci_restore_state(pdev); + pci_cfg_access_unlock(pdev); + + return err; +} + static int mlxsw_pci_reset_sw(struct mlxsw_pci *mlxsw_pci) { char mrsr_pl[MLXSW_REG_MRSR_LEN]; @@ -1488,6 +1515,8 @@ static int mlxsw_pci_reset(struct mlxsw_pci *mlxsw_pci, const struct pci_device_id *id) { struct pci_dev *pdev = mlxsw_pci->pdev; + char mcam_pl[MLXSW_REG_MCAM_LEN]; + bool pci_reset_supported; u32 sys_status; int err; @@ -1498,10 +1527,23 @@ mlxsw_pci_reset(struct mlxsw_pci *mlxsw_pci, const struct pci_device_id *id) return err; } - err = mlxsw_pci_reset_sw(mlxsw_pci); + mlxsw_reg_mcam_pack(mcam_pl, + MLXSW_REG_MCAM_FEATURE_GROUP_ENHANCED_FEATURES); + err = mlxsw_reg_query(mlxsw_pci->core, MLXSW_REG(mcam), mcam_pl); if (err) return err; + mlxsw_reg_mcam_unpack(mcam_pl, MLXSW_REG_MCAM_PCI_RESET, + &pci_reset_supported); + + if (pci_reset_supported) { + pci_dbg(pdev, "Starting PCI reset flow\n"); + err = mlxsw_pci_reset_at_pci_disable(mlxsw_pci); + } else { + pci_dbg(pdev, "Starting software reset flow\n"); + err = mlxsw_pci_reset_sw(mlxsw_pci); + } + err = mlxsw_pci_sys_ready_wait(mlxsw_pci, id, &sys_status); if (err) { dev_err(&pdev->dev, "Failed to reach system ready status after reset. Status is 0x%x\n", diff --git a/drivers/net/ethernet/mellanox/mlxsw/reg.h b/drivers/net/ethernet/mellanox/mlxsw/reg.h index 13c0ff994537..e26e9d06bd72 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/reg.h +++ b/drivers/net/ethernet/mellanox/mlxsw/reg.h @@ -10594,6 +10594,8 @@ MLXSW_ITEM32(reg, mcam, feature_group, 0x00, 16, 8); enum mlxsw_reg_mcam_mng_feature_cap_mask_bits { /* If set, MCIA supports 128 bytes payloads. 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , CC: Ido Schimmel , Petr Machata , "Amit Cohen" , Subject: [PATCH net-next 13/14] mlxsw: pci: Implement PCI reset handlers Date: Wed, 15 Nov 2023 13:17:22 +0100 Message-ID: <3bb150e9efd7fbf2ced0a2fb6f3ea321fbcf6046.1700047319.git.petrm@nvidia.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A0F9:EE_|CH0PR12MB5027:EE_ X-MS-Office365-Filtering-Correlation-Id: e4284965-87fc-4e53-4783-08dbe5d53946 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: dpgMDDK3XebWXK/cuTbXKdiu1MnNIF78yhImZsijtlgrLNIQdpgleX7sBn/74HDjQa+isnvcSctyatu4GeyDs1PiWJSS/3nguwou0c5xdF1LUY8Ls3gPNNsBTJhPWGLPeX3Dacy8t7gN+kACyL5ld5VdVow9TlxOhfL22VE/74+mMQdMFZEtUVO5zNwdH8vpQK6zOPhQOxyNcmII4/Dg/lmvjNjQxdnRe0AEqdByA+N+6AiVHLffwDu7zuFszMPbNd9g4dv5wJcA9lu44l7U9LsMbTwfYhruNdccqk4kdzRtpfmPNTh8bVYTa/duMgFRK8ioPWQxXryuvBMEeaiHkpDVRz7Aw1VzAlnx9NV77n8Iy4ERg57EyXoDRtiSrgzkJ0CIuvTHDghG1AjmTqy1OyozbOrK3qjbd6FUQQa4BlaH/68MJr+fSx86g1z0AcismrLoIQjsZDGfi3erzhWfuN462lL4qMOat5BXL06+IB+Xyhkt2A8d9pCc/41cD3XiuWWrVBTpo33oTmuii7v1ESW4N6YrY/OG5rKb+6+i3b8TmIVcsjtX92nOqekjaljG+BwNDLy481qMTjPVFonvjqLbSnRuJOuZHJnm1JQdi2qekklUwFc5KgF2DTbTq25xWmnE89+JCKt85faGzBD2TefArL+Jsp6K1IJ7B8eRPZpU1wLXGjZ7uQ+z7lxVkt21bQ24YETVL0LnIMDXe5sC4SzD4a0sFN8ijKfdvIjUyc2xXeLry309qUPshmJIGNuI X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(396003)(39860400002)(136003)(376002)(346002)(230922051799003)(1800799009)(451199024)(186009)(64100799003)(82310400011)(46966006)(36840700001)(40470700004)(40480700001)(40460700003)(36860700001)(47076005)(2906002)(356005)(5660300002)(7636003)(86362001)(16526019)(336012)(426003)(82740400003)(107886003)(26005)(2616005)(478600001)(6666004)(36756003)(41300700001)(110136005)(70586007)(70206006)(316002)(8936002)(4326008)(8676002)(54906003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Nov 2023 12:20:15.2884 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e4284965-87fc-4e53-4783-08dbe5d53946 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A0F9.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5027 X-Patchwork-Delegate: kuba@kernel.org From: Ido Schimmel Implement reset_prepare() and reset_done() handlers that are invoked by the PCI core before and after issuing a PCI reset, respectively. Specifically, implement reset_prepare() by calling mlxsw_core_bus_device_unregister() and reset_done() by calling mlxsw_core_bus_device_register(). This is the same implementation as the reload_{down,up}() devlink operations with the following differences: 1. The devlink instance is unregistered and then registered again after the reset. 2. A reset via the device's command interface (using MRSR register) is not issued during reset_done() as PCI core already issued a PCI reset. Tested: # for i in $(seq 1 10); do echo 1 > /sys/bus/pci/devices/0000\:01\:00.0/reset; done Reviewed-by: Petr Machata Signed-off-by: Ido Schimmel Signed-off-by: Petr Machata Reviewed-by: Simon Horman --- drivers/net/ethernet/mellanox/mlxsw/pci.c | 28 +++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlxsw/pci.c b/drivers/net/ethernet/mellanox/mlxsw/pci.c index 726ed707e27b..5b1f2483a3cc 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/pci.c +++ b/drivers/net/ethernet/mellanox/mlxsw/pci.c @@ -130,6 +130,7 @@ struct mlxsw_pci { const struct pci_device_id *id; enum mlxsw_pci_cqe_v max_cqe_ver; /* Maximal supported CQE version */ u8 num_sdq_cqs; /* Number of CQs used for SDQs */ + bool skip_reset; }; static void mlxsw_pci_queue_tasklet_schedule(struct mlxsw_pci_queue *q) @@ -1527,6 +1528,10 @@ mlxsw_pci_reset(struct mlxsw_pci *mlxsw_pci, const struct pci_device_id *id) return err; } + /* PCI core already issued a PCI reset, do not issue another reset. */ + if (mlxsw_pci->skip_reset) + return 0; + mlxsw_reg_mcam_pack(mcam_pl, MLXSW_REG_MCAM_FEATURE_GROUP_ENHANCED_FEATURES); err = mlxsw_reg_query(mlxsw_pci->core, MLXSW_REG(mcam), mcam_pl); @@ -2107,11 +2112,34 @@ static void mlxsw_pci_remove(struct pci_dev *pdev) kfree(mlxsw_pci); } +static void mlxsw_pci_reset_prepare(struct pci_dev *pdev) +{ + struct mlxsw_pci *mlxsw_pci = pci_get_drvdata(pdev); + + mlxsw_core_bus_device_unregister(mlxsw_pci->core, false); +} + +static void mlxsw_pci_reset_done(struct pci_dev *pdev) +{ + struct mlxsw_pci *mlxsw_pci = pci_get_drvdata(pdev); + + mlxsw_pci->skip_reset = true; + mlxsw_core_bus_device_register(&mlxsw_pci->bus_info, &mlxsw_pci_bus, + mlxsw_pci, false, NULL, NULL); + mlxsw_pci->skip_reset = false; +} + +static const struct pci_error_handlers mlxsw_pci_err_handler = { + .reset_prepare = mlxsw_pci_reset_prepare, + .reset_done = mlxsw_pci_reset_done, +}; + int mlxsw_pci_driver_register(struct pci_driver *pci_driver) { pci_driver->probe = mlxsw_pci_probe; pci_driver->remove = mlxsw_pci_remove; pci_driver->shutdown = mlxsw_pci_remove; + pci_driver->err_handler = &mlxsw_pci_err_handler; return pci_register_driver(pci_driver); } EXPORT_SYMBOL(mlxsw_pci_driver_register); From patchwork Wed Nov 15 12:17:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Petr Machata X-Patchwork-Id: 13456633 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 06B2E18B0C for ; Wed, 15 Nov 2023 12:20:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="uoGU9DYZ" Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2089.outbound.protection.outlook.com [40.107.244.89]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A5C8C9B for ; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , CC: Ido Schimmel , Petr Machata , "Amit Cohen" , Subject: [PATCH net-next 14/14] selftests: mlxsw: Add PCI reset test Date: Wed, 15 Nov 2023 13:17:23 +0100 Message-ID: X-Mailer: git-send-email 2.41.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000989EC:EE_|MN2PR12MB4455:EE_ X-MS-Office365-Filtering-Correlation-Id: 01731c17-1019-4b73-82a4-08dbe5d53bf1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: jLvMefUY3i2sN8trfgCQkTdWJEzTsCxZjyjkbD0E7LfC/D9rSkI8mJiiCRvS9o5Yvh/37BL0rUdmeoou6Es+CY9++jMLd1uua5d+i3eRLAnOIczP7bb3UdwbW/vUJJGn0TQQEEeBm/VVNXUG9nC+ZqfvtH8r4BqEkq4VimZihpQRSSFAsd1Rjv3JC3g0PkFj311uh4Z0fT0A0OHKBpl0DsCW8oZ7FkpzvdWi+0gRHWtmpcgKMNCHXOYwHeZ5Bpj9CWV0oRRC/jY90qlg3kxrGLRVbne6VN0ncMzS0ANpyThCZXOvuL4+6HK6yDx7UP4oLuHBxmuf/FLiTKXAJdbtfDohNW1VV4v24nt4roNGLQw6uBxXo4+dSa99S+Gx99YjpWfXh6PF0Afe8Lw2frd/mTeiV8yVp97zb9iqshMaphKktmAsw9qFPtCiUp1ePVEtthTsPsRnHwKgG/tYcINk0coVgCv9p5tqdb6OLmC4Xc0G9aKC/TYlkAniugbZF9lOjWOD83h5EYPN5+DS9vXoQnhiQrUTMpmdjezUlHcknovXVrtW3BNTGQrehk1WCbzXL8a4i7Ec3R+lCSa07AB3WZYOlQFMHJUCFK7g3SH1vGHvvgOkrQQQODM6R+uSC4XqtTKGhH8kQ4X+9MPDb1RbgmrXf7zNqk6uj6k9rnWw2iYYGnWwolmHRKNVYLXKTda02RhRD9iyU6eDZcwLTj4avXs3fCbTLJR0p+jxSuIIyupuAjjOGPvrbMDj6///9Vc5 X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(376002)(346002)(39860400002)(396003)(136003)(230922051799003)(451199024)(82310400011)(186009)(1800799009)(64100799003)(40470700004)(36840700001)(46966006)(2906002)(5660300002)(40460700003)(7636003)(478600001)(356005)(316002)(82740400003)(86362001)(36860700001)(36756003)(70206006)(70586007)(107886003)(2616005)(16526019)(110136005)(26005)(6666004)(47076005)(336012)(41300700001)(426003)(83380400001)(4326008)(8676002)(8936002)(40480700001)(54906003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Nov 2023 12:20:19.7972 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 01731c17-1019-4b73-82a4-08dbe5d53bf1 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000989EC.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4455 X-Patchwork-Delegate: kuba@kernel.org From: Ido Schimmel Test that PCI reset works correctly by verifying that only the expected reset methods are supported and that after issuing the reset the ifindex of the port changes. Signed-off-by: Ido Schimmel Reviewed-by: Petr Machata Signed-off-by: Petr Machata Reviewed-by: Simon Horman --- .../selftests/drivers/net/mlxsw/pci_reset.sh | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100755 tools/testing/selftests/drivers/net/mlxsw/pci_reset.sh diff --git a/tools/testing/selftests/drivers/net/mlxsw/pci_reset.sh b/tools/testing/selftests/drivers/net/mlxsw/pci_reset.sh new file mode 100755 index 000000000000..fe0343b95e6c --- /dev/null +++ b/tools/testing/selftests/drivers/net/mlxsw/pci_reset.sh @@ -0,0 +1,58 @@ +#!/bin/bash +# SPDX-License-Identifier: GPL-2.0 +# +# Test that PCI reset works correctly by verifying that only the expected reset +# methods are supported and that after issuing the reset the ifindex of the +# port changes. + +lib_dir=$(dirname $0)/../../../net/forwarding + +ALL_TESTS=" + pci_reset_test +" +NUM_NETIFS=1 +source $lib_dir/lib.sh +source $lib_dir/devlink_lib.sh + +pci_reset_test() +{ + RET=0 + + local bus=$(echo $DEVLINK_DEV | cut -d '/' -f 1) + local bdf=$(echo $DEVLINK_DEV | cut -d '/' -f 2) + + if [ $bus != "pci" ]; then + check_err 1 "devlink device is not a PCI device" + log_test "pci reset" + return + fi + + if [ ! -f /sys/bus/pci/devices/$bdf/reset_method ]; then + check_err 1 "reset is not supported" + log_test "pci reset" + return + fi + + [[ $(cat /sys/bus/pci/devices/$bdf/reset_method) == "bus" ]] + check_err $? "only \"bus\" reset method should be supported" + + local ifindex_pre=$(ip -j link show dev $swp1 | jq '.[]["ifindex"]') + + echo 1 > /sys/bus/pci/devices/$bdf/reset + check_err $? "reset failed" + + # Wait for udev to rename newly created netdev. + udevadm settle + + local ifindex_post=$(ip -j link show dev $swp1 | jq '.[]["ifindex"]') + + [[ $ifindex_pre != $ifindex_post ]] + check_err $? "reset not performed" + + log_test "pci reset" +} + +swp1=${NETIFS[p1]} +tests_run + +exit $EXIT_STATUS