From patchwork Wed Nov 15 13:43:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Golani, Mitulkumar Ajitkumar" X-Patchwork-Id: 13456722 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CDDBDC48BFA for ; Wed, 15 Nov 2023 13:48:46 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C44E410E077; Wed, 15 Nov 2023 13:48:45 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4EA7710E046 for ; Wed, 15 Nov 2023 13:48:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1700056123; x=1731592123; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2ICoBIxiqc5NR4hzr9cFUVPhj9PWAzVMh5CzetbGMnw=; b=XDa3nZniZKDnJRD4VY7Xk2FiHrOyVJnex69iDP48O/Qd0AGbXVvVG4f/ EGwhfCGvbAWJ/ZNSYr97HxIszrdBfCN4hsV4UM7OMdcI5DvJBhHWpZg1n c27iCdwsMl8S/imi0hyn1xVhe3VjUxhG0Ci2PmU/2P85CqFD8LqBuM8Vj PQMJOomXZ0X1Jv4Khi6Rcm5z3B9TybJOI7MoutxSQHp7uwpm1IEz2oOcj Xqr5Lwdqwdg2Rwzhb8fZTDbwR0NldrKv7WhZCoqRXJ4N9VeKnF9tuar3i Nxz74B0LhzNtMepP7TavKBKqs64bMLQVd8L+/zqrgWbs8BdPkpHBo8AhX Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10894"; a="421975277" X-IronPort-AV: E=Sophos;i="6.03,305,1694761200"; d="scan'208";a="421975277" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Nov 2023 05:48:43 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.03,305,1694761200"; d="scan'208";a="6170500" Received: from mgolanimitul-x299-ud4-pro.iind.intel.com ([10.190.239.114]) by orviesa002.jf.intel.com with ESMTP; 15 Nov 2023 05:48:41 -0800 From: Mitul Golani To: intel-gfx@lists.freedesktop.org Date: Wed, 15 Nov 2023 19:13:24 +0530 Message-Id: <20231115134326.3794326-2-mitulkumar.ajitkumar.golani@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231115134326.3794326-1-mitulkumar.ajitkumar.golani@intel.com> References: <20231115134326.3794326-1-mitulkumar.ajitkumar.golani@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 1/3] drm/i915: Define and compute Transcoder CMRR registers X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com, ville.syrjala@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add register definitions for Transcoder Fixed Average Vtotal mode/CMRR function, with the necessary bitfields. Compute these registers when CMRR is enabled, extending Adaptive refresh rate capabilities. Signed-off-by: Mitul Golani --- drivers/gpu/drm/i915/display/intel_display.c | 23 ++++++++++++++++++- .../drm/i915/display/intel_display_types.h | 6 +++++ drivers/gpu/drm/i915/display/intel_vrr.c | 22 ++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 10 ++++++++ 4 files changed, 60 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 125903007a29..f99d2de840bc 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -921,6 +921,13 @@ static bool vrr_params_changed(const struct intel_crtc_state *old_crtc_state, old_crtc_state->vrr.pipeline_full != new_crtc_state->vrr.pipeline_full; } +static bool cmrr_params_changed(const struct intel_crtc_state *old_crtc_state, + const struct intel_crtc_state *new_crtc_state) +{ + return old_crtc_state->cmrr.cmrr_m != new_crtc_state->cmrr.cmrr_m || + old_crtc_state->cmrr.cmrr_n != new_crtc_state->cmrr.cmrr_n; +} + static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state, const struct intel_crtc_state *new_crtc_state) { @@ -5067,6 +5074,16 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, } \ } while (0) +#define PIPE_CONF_CHECK_LLI(name) do { \ + if (current_config->name != pipe_config->name) { \ + pipe_config_mismatch(fastset, crtc, __stringify(name), \ + "(expected %lli, found %lli)", \ + current_config->name, \ + pipe_config->name); \ + ret = false; \ + } \ +} while (0) + #define PIPE_CONF_CHECK_BOOL(name) do { \ if (current_config->name != pipe_config->name) { \ pipe_config_mismatch(fastset, crtc, __stringify(name), \ @@ -5447,10 +5464,13 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_I(vrr.flipline); PIPE_CONF_CHECK_I(vrr.pipeline_full); PIPE_CONF_CHECK_I(vrr.guardband); + PIPE_CONF_CHECK_LLI(cmrr.cmrr_m); + PIPE_CONF_CHECK_LLI(cmrr.cmrr_n); } #undef PIPE_CONF_CHECK_X #undef PIPE_CONF_CHECK_I +#undef PIPE_CONF_CHECK_LLI #undef PIPE_CONF_CHECK_BOOL #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE #undef PIPE_CONF_CHECK_P @@ -6790,7 +6810,8 @@ static void intel_pre_update_crtc(struct intel_atomic_state *state, intel_crtc_needs_fastset(new_crtc_state)) icl_set_pipe_chicken(new_crtc_state); - if (vrr_params_changed(old_crtc_state, new_crtc_state)) + if (vrr_params_changed(old_crtc_state, new_crtc_state) || + cmrr_params_changed(old_crtc_state, new_crtc_state)) intel_vrr_set_transcoder_timings(new_crtc_state); } diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 9a44350ba05d..e42a0807227b 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1406,6 +1406,12 @@ struct intel_crtc_state { u16 flipline, vmin, vmax, guardband; } vrr; + /* Content Match Refresh Rate state */ + struct { + bool enable; + u64 cmrr_n, cmrr_m; + } cmrr; + /* Stream Splitter for eDP MSO */ struct { bool enable; diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 5d905f932cb4..c889b0aa69a4 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -199,6 +199,19 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state) return; } + if (crtc_state->cmrr.enable) { + intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), + VRR_CTL_CMRR_ENABLE | trans_vrr_ctl(crtc_state)); + intel_de_write(dev_priv, TRANS_CMRR_M_HI(cpu_transcoder), + upper_32_bits(crtc_state->cmrr.cmrr_m)); + intel_de_write(dev_priv, TRANS_CMRR_M_LO(cpu_transcoder), + lower_32_bits(crtc_state->cmrr.cmrr_m)); + intel_de_write(dev_priv, TRANS_CMRR_N_HI(cpu_transcoder), + upper_32_bits(crtc_state->cmrr.cmrr_n)); + intel_de_write(dev_priv, TRANS_CMRR_N_LO(cpu_transcoder), + lower_32_bits(crtc_state->cmrr.cmrr_n)); + } + intel_de_write(dev_priv, TRANS_VRR_VMIN(cpu_transcoder), crtc_state->vrr.vmin - 1); intel_de_write(dev_priv, TRANS_VRR_VMAX(cpu_transcoder), crtc_state->vrr.vmax - 1); intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), trans_vrr_ctl(crtc_state)); @@ -269,6 +282,15 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state) crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE; + if (crtc_state->cmrr.enable) { + crtc_state->cmrr.cmrr_n = + intel_de_read64_2x32(dev_priv, TRANS_CMRR_N_LO(cpu_transcoder), + TRANS_CMRR_N_HI(cpu_transcoder)); + crtc_state->cmrr.cmrr_m = + intel_de_read64_2x32(dev_priv, TRANS_CMRR_M_LO(cpu_transcoder), + TRANS_CMRR_M_HI(cpu_transcoder)); + } + if (DISPLAY_VER(dev_priv) >= 13) crtc_state->vrr.guardband = REG_FIELD_GET(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, trans_vrr_ctl); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 135e8d8dbdf0..06c1e1c47e0d 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2013,6 +2013,7 @@ #define VRR_CTL_VRR_ENABLE REG_BIT(31) #define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30) #define VRR_CTL_FLIP_LINE_EN REG_BIT(29) +#define VRR_CTL_CMRR_ENABLE REG_BIT(27) #define VRR_CTL_PIPELINE_FULL_MASK REG_GENMASK(10, 3) #define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x)) #define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0) @@ -2089,6 +2090,15 @@ #define TRANS_VRR_STATUS2(trans) _MMIO_TRANS2(trans, _TRANS_VRR_STATUS2_A) #define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0) +#define _TRANS_CMRR_M_LO_A 0x604F0 +#define TRANS_CMRR_M_LO(trans) _MMIO_TRANS2(trans, _TRANS_CMRR_M_LO_A) +#define _TRANS_CMRR_M_HI_A 0x604F4 +#define TRANS_CMRR_M_HI(trans) _MMIO_TRANS2(trans, _TRANS_CMRR_M_HI_A) +#define _TRANS_CMRR_N_LO_A 0x604F8 +#define TRANS_CMRR_N_LO(trans) _MMIO_TRANS2(trans, _TRANS_CMRR_N_LO_A) +#define _TRANS_CMRR_N_HI_A 0x604FC +#define TRANS_CMRR_N_HI(trans) _MMIO_TRANS2(trans, _TRANS_CMRR_N_HI_A) + #define _TRANS_PUSH_A 0x60A70 #define _TRANS_PUSH_B 0x61A70 #define _TRANS_PUSH_C 0x62A70 From patchwork Wed Nov 15 13:43:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Golani, Mitulkumar Ajitkumar" X-Patchwork-Id: 13456723 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3FFDBC48BF9 for ; Wed, 15 Nov 2023 13:48:51 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A246410E06B; Wed, 15 Nov 2023 13:48:50 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id BE4D610E06B for ; Wed, 15 Nov 2023 13:48:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1700056125; x=1731592125; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fOIthrZHu8jXzW5XGOxB6DX4xPP/XQBgpGt+doVCkac=; b=U5GNxegt/dWCJNce1PkKf6l8O6pMDk/9BjjLZ6nuCaU9WgZwWPmBJ5BL 5WV1D0YL62kQmNGIEUi1uoGWkQ/TUCzgpNs+PMB1Pzv9S47eSfLTG8IVl jVEQPSfQb69qvnv+SVPC2T0eF4gZ6vzskThrA2Pa+g1E7rY/NtU5wO4dO 2BJQao2IPW04SHvp7a/2h7VHeLcxtWWhc2Bie8tT52LCUZUjLrC+m5zaL AknuedJHpFwRBI16NJjfxyakf6UsRojhKMyM6cWbEY4H1k/TfqSReUUCO gAizbZcOZAmpgvjZAURh6nnO55jdphcB5VzPomoP83CmKXlHoyp9+1gcj w==; X-IronPort-AV: E=McAfee;i="6600,9927,10894"; a="421975286" X-IronPort-AV: E=Sophos;i="6.03,305,1694761200"; d="scan'208";a="421975286" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Nov 2023 05:48:45 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.03,305,1694761200"; d="scan'208";a="6170505" Received: from mgolanimitul-x299-ud4-pro.iind.intel.com ([10.190.239.114]) by orviesa002.jf.intel.com with ESMTP; 15 Nov 2023 05:48:44 -0800 From: Mitul Golani To: intel-gfx@lists.freedesktop.org Date: Wed, 15 Nov 2023 19:13:25 +0530 Message-Id: <20231115134326.3794326-3-mitulkumar.ajitkumar.golani@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231115134326.3794326-1-mitulkumar.ajitkumar.golani@intel.com> References: <20231115134326.3794326-1-mitulkumar.ajitkumar.golani@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/3] drm/i915: Add Enable/Disable for CMRR based on VRR state X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com, ville.syrjala@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add CMRR/Fixed Average Vtotal mode enable and disable functions based on change in VRR mode of operation. When Adaptive Sync Vtotal is enabled, Fixed Average Vtotal mode is disabled and vice versa. With this commit setting the stage for subsequent CMRR enablement. Signed-off-by: Mitul Golani --- .../drm/i915/display/intel_crtc_state_dump.c | 4 ++- drivers/gpu/drm/i915/display/intel_display.c | 27 +++++++++++++++--- drivers/gpu/drm/i915/display/intel_vrr.c | 28 +++++++++++++------ 3 files changed, 46 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c index 2d15e82c0b3d..908a4c4ccb00 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c @@ -299,7 +299,9 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config, intel_dump_buffer(i915, "ELD: ", pipe_config->eld, drm_eld_size(pipe_config->eld)); - drm_dbg_kms(&i915->drm, "vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, guardband: %d flipline: %d, vmin vblank: %d, vmax vblank: %d\n", + drm_dbg_kms(&i915->drm, + "cmrr: %s, vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, guardband: %d, flipline: %d, vmin vblank: %d, vmax vblank: %d\n", + str_yes_no(pipe_config->cmrr.enable), str_yes_no(pipe_config->vrr.enable), pipe_config->vrr.vmin, pipe_config->vrr.vmax, pipe_config->vrr.pipeline_full, pipe_config->vrr.guardband, diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index f99d2de840bc..ae7cc4eca064 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -937,6 +937,15 @@ static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state, vrr_params_changed(old_crtc_state, new_crtc_state))); } +static bool cmrr_enabling(const struct intel_crtc_state *old_crtc_state, + const struct intel_crtc_state *new_crtc_state) +{ + if (!new_crtc_state->hw.active) + return false; + + return is_enabling(cmrr.enable, old_crtc_state, new_crtc_state); +} + static bool vrr_disabling(const struct intel_crtc_state *old_crtc_state, const struct intel_crtc_state *new_crtc_state) { @@ -946,6 +955,12 @@ static bool vrr_disabling(const struct intel_crtc_state *old_crtc_state, vrr_params_changed(old_crtc_state, new_crtc_state))); } +static bool cmrr_disabling(const struct intel_crtc_state *old_crtc_state, + const struct intel_crtc_state *new_crtc_state) +{ + return is_disabling(cmrr.enable, old_crtc_state, new_crtc_state); +} + #undef is_disabling #undef is_enabling @@ -1064,7 +1079,8 @@ static void intel_pre_plane_update(struct intel_atomic_state *state, intel_atomic_get_new_crtc_state(state, crtc); enum pipe pipe = crtc->pipe; - if (vrr_disabling(old_crtc_state, new_crtc_state)) { + if (vrr_disabling(old_crtc_state, new_crtc_state) || + cmrr_disabling(old_crtc_state, new_crtc_state)) { intel_vrr_disable(old_crtc_state); intel_crtc_update_active_timings(old_crtc_state, false); } @@ -6754,7 +6770,8 @@ static void commit_pipe_post_planes(struct intel_atomic_state *state, !intel_crtc_needs_modeset(new_crtc_state)) skl_detach_scalers(new_crtc_state); - if (vrr_enabling(old_crtc_state, new_crtc_state)) + if (vrr_enabling(old_crtc_state, new_crtc_state) || + cmrr_enabling(old_crtc_state, new_crtc_state)) intel_vrr_enable(new_crtc_state); } @@ -6851,9 +6868,11 @@ static void intel_update_crtc(struct intel_atomic_state *state, * FIXME Should be synchronized with the start of vblank somehow... */ if (vrr_enabling(old_crtc_state, new_crtc_state) || - new_crtc_state->update_m_n || new_crtc_state->update_lrr) + new_crtc_state->update_m_n || new_crtc_state->update_lrr || + cmrr_enabling(old_crtc_state, new_crtc_state)) intel_crtc_update_active_timings(new_crtc_state, - new_crtc_state->vrr.enable); + new_crtc_state->vrr.enable || + new_crtc_state->cmrr.enable); /* * We usually enable FIFO underrun interrupts as part of the diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index c889b0aa69a4..6da14c18a3e3 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -224,7 +224,7 @@ void intel_vrr_send_push(const struct intel_crtc_state *crtc_state) struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; - if (!crtc_state->vrr.enable) + if (!(crtc_state->vrr.enable || crtc_state->cmrr.enable)) return; intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), @@ -237,7 +237,7 @@ bool intel_vrr_is_push_sent(const struct intel_crtc_state *crtc_state) struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; - if (!crtc_state->vrr.enable) + if (!(crtc_state->vrr.enable || crtc_state->cmrr.enable)) return false; return intel_de_read(dev_priv, TRANS_PUSH(cpu_transcoder)) & TRANS_PUSH_SEND; @@ -248,12 +248,24 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state) struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; - if (!crtc_state->vrr.enable) + if (drm_WARN_ON(&dev_priv->drm, crtc_state->vrr.enable && + crtc_state->cmrr.enable)) return; - intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), TRANS_PUSH_EN); - intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), - VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state)); + if (!crtc_state->vrr.enable && crtc_state->cmrr.enable) { + intel_de_write(dev_priv, + TRANS_PUSH(cpu_transcoder), TRANS_PUSH_EN); + intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), + VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state)); + } + + if (!crtc_state->vrr.enable && crtc_state->cmrr.enable) { + intel_de_write(dev_priv, + TRANS_PUSH(cpu_transcoder), TRANS_PUSH_EN); + intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), + VRR_CTL_VRR_ENABLE | VRR_CTL_CMRR_ENABLE | + trans_vrr_ctl(crtc_state)); + } } void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state) @@ -262,7 +274,7 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state) struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; - if (!old_crtc_state->vrr.enable) + if (!(old_crtc_state->vrr.enable || old_crtc_state->cmrr.enable)) return; intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), @@ -305,6 +317,6 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state) crtc_state->vrr.vmin = intel_de_read(dev_priv, TRANS_VRR_VMIN(cpu_transcoder)) + 1; } - if (crtc_state->vrr.enable) + if (crtc_state->vrr.enable || crtc_state->cmrr.enable) crtc_state->mode_flags |= I915_MODE_FLAG_VRR; } From patchwork Wed Nov 15 13:43:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Golani, Mitulkumar Ajitkumar" X-Patchwork-Id: 13456724 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A424AC48BD7 for ; Wed, 15 Nov 2023 13:48:52 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0057010E54E; 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15 Nov 2023 05:48:47 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.03,305,1694761200"; d="scan'208";a="6170512" Received: from mgolanimitul-x299-ud4-pro.iind.intel.com ([10.190.239.114]) by orviesa002.jf.intel.com with ESMTP; 15 Nov 2023 05:48:46 -0800 From: Mitul Golani To: intel-gfx@lists.freedesktop.org Date: Wed, 15 Nov 2023 19:13:26 +0530 Message-Id: <20231115134326.3794326-4-mitulkumar.ajitkumar.golani@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231115134326.3794326-1-mitulkumar.ajitkumar.golani@intel.com> References: <20231115134326.3794326-1-mitulkumar.ajitkumar.golani@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 3/3] drm/i915: Compute CMRR and calculate vtotal X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com, ville.syrjala@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Compute Fixed Average Vtotal/CMRR with resepect to userspace VRR enablement. Also calculate required parameters in case of CMRR is enabled. During intel_vrr_compute_config, CMRR is getting enabled based on userspace has enabled Adaptive Sync Vtotal mode (Legacy VRR) or not. Signed-off-by: Mitul Golani --- drivers/gpu/drm/i915/display/intel_display.c | 1 + .../drm/i915/display/intel_display_device.h | 1 + drivers/gpu/drm/i915/display/intel_vrr.c | 76 +++++++++++++++++-- 3 files changed, 72 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index ae7cc4eca064..7e38ac4d6185 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -5482,6 +5482,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_I(vrr.guardband); PIPE_CONF_CHECK_LLI(cmrr.cmrr_m); PIPE_CONF_CHECK_LLI(cmrr.cmrr_n); + PIPE_CONF_CHECK_BOOL(cmrr.enable); } #undef PIPE_CONF_CHECK_X diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h index 4299cc452e05..66cbc3a6bbe8 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.h +++ b/drivers/gpu/drm/i915/display/intel_display_device.h @@ -68,6 +68,7 @@ struct drm_printer; #define HAS_TRANSCODER(i915, trans) ((DISPLAY_RUNTIME_INFO(i915)->cpu_transcoder_mask & \ BIT(trans)) != 0) #define HAS_VRR(i915) (DISPLAY_VER(i915) >= 11) +#define HAS_CMRR(i915) (DISPLAY_VER(i915) >= 20) #define INTEL_NUM_PIPES(i915) (hweight8(DISPLAY_RUNTIME_INFO(i915)->pipe_mask)) #define I915_HAS_HOTPLUG(i915) (DISPLAY_INFO(i915)->has_hotplug) #define OVERLAY_NEEDS_PHYSICAL(i915) (DISPLAY_INFO(i915)->overlay_needs_physical) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 6da14c18a3e3..ab124e997ef2 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -105,6 +105,52 @@ int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state) return crtc_state->vrr.vmax - intel_vrr_vblank_exit_length(crtc_state); } +static bool +is_cmrr_frac_required(struct intel_crtc_state *crtc_state) +{ + int calculated_refresh_k, actual_refresh_k; + struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; + + actual_refresh_k = drm_mode_vrefresh(adjusted_mode) * 1000; + calculated_refresh_k = DIV_ROUND_UP(adjusted_mode->crtc_clock * 1000, + adjusted_mode->crtc_htotal) * 1000; + calculated_refresh_k /= adjusted_mode->crtc_vtotal; + + if (calculated_refresh_k == actual_refresh_k) + return false; + + return true; +} + +static unsigned int +cmrr_get_vtotal(struct intel_crtc_state *crtc_state) +{ + int multiplier_m = 1, multiplier_n = 1, vtotal; + int actual_refresh_rate, desired_refresh_rate; + long long actual_pixel_rate, adjusted_pixel_rate; + struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; + + actual_refresh_rate = DIV_ROUND_UP(adjusted_mode->crtc_clock * 1000, + adjusted_mode->crtc_htotal) * 1000; + actual_refresh_rate /= adjusted_mode->crtc_vtotal; + desired_refresh_rate = drm_mode_vrefresh(adjusted_mode); + actual_pixel_rate = actual_refresh_rate * adjusted_mode->crtc_vtotal; + actual_pixel_rate = (actual_pixel_rate * adjusted_mode->crtc_htotal) / 1000; + + if (is_cmrr_frac_required(crtc_state)) { + multiplier_m = 1001; + multiplier_n = 1000; + } + + crtc_state->cmrr.cmrr_n = DIV_ROUND_UP(desired_refresh_rate * + adjusted_mode->crtc_htotal * multiplier_n, multiplier_m) * multiplier_n; + vtotal = DIV_ROUND_UP(actual_pixel_rate * multiplier_n, crtc_state->cmrr.cmrr_n); + adjusted_pixel_rate = actual_pixel_rate * multiplier_m; + crtc_state->cmrr.cmrr_m = do_div(adjusted_pixel_rate, crtc_state->cmrr.cmrr_n); + + return vtotal; +} + void intel_vrr_compute_config(struct intel_crtc_state *crtc_state, struct drm_connector_state *conn_state) @@ -149,6 +195,22 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, crtc_state->vrr.flipline = crtc_state->vrr.vmin + 1; + /* + * When panel is VRR capable and userspace has + * not enabled adaptive sync mode then Fixed Average + * Vtotal mode should be enabled. + */ + if (crtc_state->uapi.vrr_enabled) { + crtc_state->vrr.enable = true; + crtc_state->mode_flags |= I915_MODE_FLAG_VRR; + } else if (HAS_CMRR(i915)) { + crtc_state->cmrr.enable = true; + crtc_state->vrr.vmax = cmrr_get_vtotal(crtc_state); + crtc_state->vrr.vmin = crtc_state->vrr.vmax; + crtc_state->vrr.flipline = crtc_state->vrr.vmin; + crtc_state->mode_flags |= I915_MODE_FLAG_VRR; + } + /* * For XE_LPD+, we use guardband and pipeline override * is deprecated. @@ -161,11 +223,6 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, min(255, crtc_state->vrr.vmin - adjusted_mode->crtc_vblank_start - crtc_state->framestart_delay - 1); } - - if (crtc_state->uapi.vrr_enabled) { - crtc_state->vrr.enable = true; - crtc_state->mode_flags |= I915_MODE_FLAG_VRR; - } } static u32 trans_vrr_ctl(const struct intel_crtc_state *crtc_state) @@ -292,7 +349,14 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state) trans_vrr_ctl = intel_de_read(dev_priv, TRANS_VRR_CTL(cpu_transcoder)); - crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE; + if (HAS_CMRR(dev_priv)) { + crtc_state->cmrr.enable = (trans_vrr_ctl & VRR_CTL_CMRR_ENABLE) && + (trans_vrr_ctl & VRR_CTL_VRR_ENABLE); + crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE && + !(trans_vrr_ctl & VRR_CTL_CMRR_ENABLE); + } else { + crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE; + } if (crtc_state->cmrr.enable) { crtc_state->cmrr.cmrr_n =