From patchwork Wed Nov 15 14:27:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13456802 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8C020C48BF9 for ; Wed, 15 Nov 2023 14:28:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344106AbjKOO2n (ORCPT ); Wed, 15 Nov 2023 09:28:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37706 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343995AbjKOO2m (ORCPT ); Wed, 15 Nov 2023 09:28:42 -0500 Received: from mail-ej1-x62e.google.com (mail-ej1-x62e.google.com [IPv6:2a00:1450:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3D81D123 for ; Wed, 15 Nov 2023 06:28:39 -0800 (PST) Received: by mail-ej1-x62e.google.com with SMTP id a640c23a62f3a-9de7a43bd1aso965709766b.3 for ; Wed, 15 Nov 2023 06:28:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1700058518; x=1700663318; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0dTX6msw9z6skyilnKqLPZuHp7mBZQKZUfa82STaeHA=; b=Q3v2MhpqiYklfdxY+wabX+gqiTz4xSps9TpPLY5/HAZaKTr8eA7TCWvZdRp9iuOU/5 fd+6F7Z3gs71/s4dZRdu2yzZ7naEGcKHMbTblqBP6iR/6uzCj3TbwLx2pecFqCG3E52i 2WB05ew+hAK4xnA1r4AzSsEQNpdLET90JtpYXz5+UiyXkJG5LFRy0H9Bn11hNXc/2R/I eWSR326a9r243a+RPPoLh/TK6dGgVfuDD9nAGpRJzXD6oXmZ0469/A4dX7ey1m4w+S0G 8/KCptAoNJDZFpMpwoJaDouYUejMTuAYtV81la89TiY1yMK81ab4jVhKL6eVmZj8rQtq wXIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700058518; x=1700663318; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0dTX6msw9z6skyilnKqLPZuHp7mBZQKZUfa82STaeHA=; b=CJgtlEck3qu2+RXuPK9UaaK2l8LNIfRcT5cTiQBVQkcpF5uVrbbqbQ1WXoDH7/MfF9 dw98ewHn+VZQPSJVhZ/2mgME/yAJO2EVQO2wBw6884KMcJSed1N2H2K1Bf5g2FiIC2+e BJiZydKIyPFH235vW3LeYEs/rG3KH2YgDvMTnKvahK0LcWKwklkACWvBqRNt26jQXqAl zwf3GQQsOc3S0U0P6bXj3rFm/PrRZmngALn54VqBDFKTh08Cvd1MVPh5Tsv/Dh8PH4Ig Q1WZF3vnodrowHa5Wh7103DvBbsFewxueyeKmwz5h5p0e6QKYqXjsguT9iMLlBLdsE23 MbmQ== X-Gm-Message-State: AOJu0YwtkJylv72p+FzFTksWqMXtbhPJIhpO6F4pU0sLMaoftlHQIKsD b4q4GN8ayVNwS9DX4h3doLNX4w== X-Google-Smtp-Source: AGHT+IF8sEsLU/SFq5g4LrZoT/tLOUEvnKEWckZJZrHKmsPxT0xhvzQ0DuCUO8+eKKsBUTngfX/FlQ== X-Received: by 2002:a17:906:f293:b0:9e2:af56:c380 with SMTP id gu19-20020a170906f29300b009e2af56c380mr10048889ejb.6.1700058517819; Wed, 15 Nov 2023 06:28:37 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.119]) by smtp.gmail.com with ESMTPSA id i11-20020a170906264b00b0099bd5d28dc4sm7186394ejc.195.2023.11.15.06.28.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Nov 2023 06:28:37 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: tglx@linutronix.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, prabhakar.mahadev-lad.rj@bp.renesas.com Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Claudiu Beznea , Conor Dooley Subject: [PATCH v2 1/9] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G3S Date: Wed, 15 Nov 2023 16:27:41 +0200 Message-Id: <20231115142749.853106-2-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231115142749.853106-1-claudiu.beznea.uj@bp.renesas.com> References: <20231115142749.853106-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org From: Claudiu Beznea Document RZ/G3S (R9108G045) interrupt controller. This has few extra functionalities compared with RZ/G2UL but the already existing driver could still be used. Acked-by: Conor Dooley Signed-off-by: Claudiu Beznea --- Changes in v2: - collected tag .../bindings/interrupt-controller/renesas,rzg2l-irqc.yaml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml index 2ef3081eaaf3..d3b5aec0a3f7 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml @@ -26,6 +26,7 @@ properties: - renesas,r9a07g043u-irqc # RZ/G2UL - renesas,r9a07g044-irqc # RZ/G2{L,LC} - renesas,r9a07g054-irqc # RZ/V2L + - renesas,r9a08g045-irqc # RZ/G3S - const: renesas,rzg2l-irqc '#interrupt-cells': @@ -167,7 +168,9 @@ allOf: properties: compatible: contains: - const: renesas,r9a07g043u-irqc + enum: + - renesas,r9a07g043u-irqc + - renesas,r9a08g045-irqc then: properties: interrupts: From patchwork Wed Nov 15 14:27:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13456803 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BB0DFC48BD7 for ; Wed, 15 Nov 2023 14:28:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344191AbjKOO2p (ORCPT ); Wed, 15 Nov 2023 09:28:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37732 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343995AbjKOO2o (ORCPT ); Wed, 15 Nov 2023 09:28:44 -0500 Received: from mail-ej1-x636.google.com (mail-ej1-x636.google.com [IPv6:2a00:1450:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E84ADE7 for ; Wed, 15 Nov 2023 06:28:40 -0800 (PST) Received: by mail-ej1-x636.google.com with SMTP id a640c23a62f3a-9c2a0725825so1022574266b.2 for ; Wed, 15 Nov 2023 06:28:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1700058519; x=1700663319; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3qoow4kLikA+1u6jbWCEh/oPcxwlTJy8Hg8XLdol66k=; b=L5zoAHDYLaE5H7JMegrsMLypbsiGZy6In6T6hoZJyniUi5LijhyR/dO2oisLpIltNS xO08fKP+h5kn1ebZ5tJS7m0ZcQmLfe4DL0HAjlLSN5lgoxoaZ6UheMGDwgXBoQwJNZ0f UxFa8aRfFXNkdsjyw62Af/6sM1uhM4vHvrhR3vlvguxpY/DxVUIrMtbgeJrn05OmqC5a iTy3BhtXEInZlCjmhXwdHMXtyJ9RTotdYV3OUvGPF63Og0kWv4LCTbwcgGQB0K8JNvxJ ns60/FlgR5ad8wF+3CLGvDwvzlWy2GB7t5WaswxoRHeuF0GiuAfABJI6MRROAsLNlF/q K7Cg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700058519; x=1700663319; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3qoow4kLikA+1u6jbWCEh/oPcxwlTJy8Hg8XLdol66k=; b=d7IkcfZhi0/Y1E318gy1QzM2opiDHmYgXy1b1p0YgcWgvSRndrXSHX5jQDkbUJdnti Zm0FSRoLl8AnAAfgFjskkfEN0VTPtEWSheNm9DuG11ZZ0Snxt3NFaR0ZcB8mp06CQjp9 jjPhdWGUOlwC6e8Ir3fToseMRrzmGc4ZvWlhOaIuwcX9BFMM/La6g+YLCPumXqv+zcXl jYy7HWdKZvCGmZ3fG8hHeV/w5hyIYl9BWSlm8c0AOY6npj1b9djxX4uBEvaAvisLy53r CB7B7QH1/y9HNDV+up3SVwU9BiPqMeO+azUUcyFzMysmMROBNEWFHAMY527hnP+SezEd +9bA== X-Gm-Message-State: AOJu0Yxt0EipCeiiAboc5s9h/UHpcDuyK3m/ZIdfZ5Jr2ON9F7ho8075 jcB5fSo/tHJHYDsLuOsbsjVL5g== X-Google-Smtp-Source: AGHT+IG27julUbeRslohrR6DkKjdpij1y3db2XTxUpwRQy3NUDxkM1NFWB7ljy8nLBGFjD8zM35dPQ== X-Received: by 2002:a17:906:1e17:b0:9d2:5cf8:e61 with SMTP id g23-20020a1709061e1700b009d25cf80e61mr8615809ejj.35.1700058519319; Wed, 15 Nov 2023 06:28:39 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.119]) by smtp.gmail.com with ESMTPSA id i11-20020a170906264b00b0099bd5d28dc4sm7186394ejc.195.2023.11.15.06.28.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Nov 2023 06:28:38 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: tglx@linutronix.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, prabhakar.mahadev-lad.rj@bp.renesas.com Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Claudiu Beznea Subject: [PATCH v2 2/9] clk: renesas: r9a08g045: Add IA55 pclk and its reset Date: Wed, 15 Nov 2023 16:27:42 +0200 Message-Id: <20231115142749.853106-3-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231115142749.853106-1-claudiu.beznea.uj@bp.renesas.com> References: <20231115142749.853106-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org From: Claudiu Beznea IA55 interrupt controller is available on RZ/G3S SoC. Add IA55 pclk and its reset. Signed-off-by: Claudiu Beznea --- Changes in v2: - updated commit description drivers/clk/renesas/r9a08g045-cpg.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/renesas/r9a08g045-cpg.c b/drivers/clk/renesas/r9a08g045-cpg.c index 4394cb241d99..ea3beca8b4e0 100644 --- a/drivers/clk/renesas/r9a08g045-cpg.c +++ b/drivers/clk/renesas/r9a08g045-cpg.c @@ -188,6 +188,7 @@ static const struct cpg_core_clk r9a08g045_core_clks[] __initconst = { static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = { DEF_MOD("gic_gicclk", R9A08G045_GIC600_GICCLK, R9A08G045_CLK_P1, 0x514, 0), + DEF_MOD("ia55_pclk", R9A08G045_IA55_PCLK, R9A08G045_CLK_P2, 0x518, 0), DEF_MOD("ia55_clk", R9A08G045_IA55_CLK, R9A08G045_CLK_P1, 0x518, 1), DEF_MOD("dmac_aclk", R9A08G045_DMAC_ACLK, R9A08G045_CLK_P3, 0x52c, 0), DEF_MOD("sdhi0_imclk", R9A08G045_SDHI0_IMCLK, CLK_SD0_DIV4, 0x554, 0), @@ -209,6 +210,7 @@ static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = { static const struct rzg2l_reset r9a08g045_resets[] = { DEF_RST(R9A08G045_GIC600_GICRESET_N, 0x814, 0), DEF_RST(R9A08G045_GIC600_DBG_GICRESET_N, 0x814, 1), + DEF_RST(R9A08G045_IA55_RESETN, 0x818, 0), DEF_RST(R9A08G045_SDHI0_IXRST, 0x854, 0), DEF_RST(R9A08G045_SDHI1_IXRST, 0x854, 1), DEF_RST(R9A08G045_SDHI2_IXRST, 0x854, 2), @@ -220,6 +222,7 @@ static const struct rzg2l_reset r9a08g045_resets[] = { static const unsigned int r9a08g045_crit_mod_clks[] __initconst = { MOD_CLK_BASE + R9A08G045_GIC600_GICCLK, + MOD_CLK_BASE + R9A08G045_IA55_PCLK, MOD_CLK_BASE + R9A08G045_IA55_CLK, MOD_CLK_BASE + R9A08G045_DMAC_ACLK, }; From patchwork Wed Nov 15 14:27:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13456804 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B3066C48BD7 for ; Wed, 15 Nov 2023 14:28:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344065AbjKOO2s (ORCPT ); Wed, 15 Nov 2023 09:28:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37754 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344193AbjKOO2p (ORCPT ); Wed, 15 Nov 2023 09:28:45 -0500 Received: from mail-ej1-x631.google.com (mail-ej1-x631.google.com [IPv6:2a00:1450:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2E214124 for ; Wed, 15 Nov 2023 06:28:42 -0800 (PST) Received: by mail-ej1-x631.google.com with SMTP id a640c23a62f3a-9e1021dbd28so1018866666b.3 for ; Wed, 15 Nov 2023 06:28:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1700058520; x=1700663320; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bS8qg7v/mSX4sJHwfdJG3kD1BNBszOYIoRYlKPnXKMg=; b=WMPnnI2acNiJvNjPNuDA+Vs3sVYWWVI0Bdpuc2fP1cksMErkEedALjdvXZZY/tQj+N HFg/AXnEqPa4w1JSshB6Jt+8Ewp/Hm/ImG31wCHsC3U6RhAWb5OJ6Pt/i0GoLyV1ytrK iwdSirriG65i9hFn3k1EBKceH7vBmDoLx82dYhG+FCOxZ91qgy/TRXkq2W8G6LwsN8Py ohh3fA7eIlLRLe4JeDwALcls5Rh06xDPS8uztdZ3RJJa+9IUQqbbNJy4R+r5aqiK/E/O QenMJcP2P3tiwvOU47rxbnilgxt4O2+zsqpvqBEznALM66r+jBkNcm8Mgti9G3zMkl2d g3xg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700058520; x=1700663320; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bS8qg7v/mSX4sJHwfdJG3kD1BNBszOYIoRYlKPnXKMg=; b=MNa4O3n7U1NoyNjMbkTSJRM9PIElYEAHZFQ5rqHsPV5OVkS0IsOxe/X5sRZVpsCmR7 5JPKHrf0KPTIn935mVFvuy0fmfk9wCqDJJO9TZHEidwlXdJ0nvPcmYtoY2Ewk+CG7A7G 0KuqFs/RwbdJJXzqL08i6KvMoFzo3qnslpATnvBoN8NFsFrfcdNcdguTSh4fHB1elbP2 n+tu7MwDDZ2+oDmN0z1oM51P94Z1JDn7sbt0pxZr/NgpPVGVNoW0I+xBWtMjuZGdQP3g RAzlfqbMmbxIEQHQXYJ3K9zFxby6FiG3rp0meCrdZsmxUO8iQofcXIvKS8W1jWT+U+3B R2hQ== X-Gm-Message-State: AOJu0YxJQEkP6kz4SdttlHAB0yK1o+QqrP2OQWqilQU31+zVrRW7YfTM TCyCJuqjYYN5mVDHyn7vHPxp0w== X-Google-Smtp-Source: AGHT+IGIZlRywh2OGv/s0LdNKxDjI8m0OS+PXIUtS7vI+Ud9wErXZJ1cvlvhTpGNnIy1WOH1qrYodQ== X-Received: by 2002:a17:907:6d0a:b0:9e7:d1ab:e90b with SMTP id sa10-20020a1709076d0a00b009e7d1abe90bmr11336470ejc.19.1700058520716; Wed, 15 Nov 2023 06:28:40 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.119]) by smtp.gmail.com with ESMTPSA id i11-20020a170906264b00b0099bd5d28dc4sm7186394ejc.195.2023.11.15.06.28.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Nov 2023 06:28:40 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: tglx@linutronix.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, prabhakar.mahadev-lad.rj@bp.renesas.com Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Claudiu Beznea Subject: [PATCH v2 3/9] irqchip/renesas-rzg2l: Use tabs instead of spaces Date: Wed, 15 Nov 2023 16:27:43 +0200 Message-Id: <20231115142749.853106-4-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231115142749.853106-1-claudiu.beznea.uj@bp.renesas.com> References: <20231115142749.853106-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org From: Claudiu Beznea Use tabs instead of spaces in definition of TINT_EXTRACT_HWIRQ() and TINT_EXTRACT_GPIOINT() macros to align with coding style requirements described in Documentation/process/coding-style.rst, "Indentation" chapter. Signed-off-by: Claudiu Beznea --- Changes in v2: - improved commit description - used uppercase letter after ":" in patch title drivers/irqchip/irq-renesas-rzg2l.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c index fe8d516f3614..cc42cbd05762 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -53,8 +53,8 @@ #define IITSR_IITSEL_EDGE_BOTH 3 #define IITSR_IITSEL_MASK(n) IITSR_IITSEL((n), 3) -#define TINT_EXTRACT_HWIRQ(x) FIELD_GET(GENMASK(15, 0), (x)) -#define TINT_EXTRACT_GPIOINT(x) FIELD_GET(GENMASK(31, 16), (x)) +#define TINT_EXTRACT_HWIRQ(x) FIELD_GET(GENMASK(15, 0), (x)) +#define TINT_EXTRACT_GPIOINT(x) FIELD_GET(GENMASK(31, 16), (x)) struct rzg2l_irqc_priv { void __iomem *base; From patchwork Wed Nov 15 14:27:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13456805 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 06874C48BFA for ; Wed, 15 Nov 2023 14:28:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344195AbjKOO2w (ORCPT ); Wed, 15 Nov 2023 09:28:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37794 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344219AbjKOO2r (ORCPT ); Wed, 15 Nov 2023 09:28:47 -0500 Received: from mail-ed1-x530.google.com (mail-ed1-x530.google.com [IPv6:2a00:1450:4864:20::530]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D013012A for ; Wed, 15 Nov 2023 06:28:43 -0800 (PST) Received: by mail-ed1-x530.google.com with SMTP id 4fb4d7f45d1cf-5446c9f3a77so10640362a12.0 for ; Wed, 15 Nov 2023 06:28:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1700058522; x=1700663322; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5pSo7A/cRaiiHr3AOQm4+M5MDktXUCdSbdXvZTsugMw=; b=FbMGKCdVBK/q1uEdDEwrAoWeS/lS9OowEFqLHnlvNv4Ewt4AsV/5pVZYGD4b96+0ox QEs3rZvw6VNRdhlAZz3sBffpCDXASzIdrrVJXk5C+7IzDN7OjEWS/r3bmCZQgVK2nkzz 3b8JjbnsZCP5ZlGv+2QiJKIF3wIVeSJyGsJzxj/TLV2iID34QKG/nOG9p7bi05Smi9fb j+hxqkGvxkwpPmPp3c3hj3RhPuAcJr7fMD68oI+4i3D30+ZhWpxnzMNb+vNv9jvjd6C4 KJM/YaegGwMUYgxDKF4eaZC0IsP31UER4WpNWfZsxHBYVFIgj8wbxwOw7mtEk3GtZqQc PQFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700058522; x=1700663322; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5pSo7A/cRaiiHr3AOQm4+M5MDktXUCdSbdXvZTsugMw=; b=rYIT1Wb2IWGXjsaMcYmPeb1hEz9T0Z+2Cdnpef5/HI6KUsa117V7UTlrb+KFATHp82 /a2CYFlU5G7xr1dCx/MBSuTqtAwNkK7zYCsaDA21W+3LGvSykO/vYffNlYjr48WXix3r R0MlBS28n1YFnDcYi2k+Ei+xq8guIFW1y7zoTSuCEm7cizy7ft7IRM9tU6bNt/UKY+Ic Htd/Bx8ZkEpc+B8yhQE2b+1Q9AYnHqfCyfX4y+QqNBtv77HBrcBXI/JGqn15j3ecrrJn lFLSoLd66YUvKPArU62aEbVWrmZGjoN4orGEKgFu5Ft58ojidRs1TidiV0uUFatwzlWE 16mg== X-Gm-Message-State: AOJu0YzivrtavCgaiBSz2JFrg3QbZXL+zWyTDbrm2oHAvdy/1B/rOfNc kH+PbBskSIdEeY3vVADgMwNJsw== X-Google-Smtp-Source: AGHT+IFtuAr4bSPIlt3KKN4kkvsZkdii103x3XEI8Hp7Lij+rtSttP7xjPk9knXbTEZyrwKB08gSMw== X-Received: by 2002:a17:906:a3c9:b0:9ae:74d1:4b45 with SMTP id ca9-20020a170906a3c900b009ae74d14b45mr9891110ejb.65.1700058522289; Wed, 15 Nov 2023 06:28:42 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.119]) by smtp.gmail.com with ESMTPSA id i11-20020a170906264b00b0099bd5d28dc4sm7186394ejc.195.2023.11.15.06.28.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Nov 2023 06:28:41 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: tglx@linutronix.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, prabhakar.mahadev-lad.rj@bp.renesas.com Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Claudiu Beznea Subject: [PATCH v2 4/9] irqchip/renesas-rzg2l: Align struct member names to tabs Date: Wed, 15 Nov 2023 16:27:44 +0200 Message-Id: <20231115142749.853106-5-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231115142749.853106-1-claudiu.beznea.uj@bp.renesas.com> References: <20231115142749.853106-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org From: Claudiu Beznea Align struct member names to tabs to follow the requirements from maintainer-tip file. 3 tabs were used at the moment as the next commits will add a new member which requires 3 tabs for a better view. Link: https://www.kernel.org/doc/html/latest/process/maintainer-tip.html#struct-declarations-and-initializers Signed-off-by: Claudiu Beznea --- Changes in v2: - this patch is new drivers/irqchip/irq-renesas-rzg2l.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c index cc42cbd05762..90971ab06f0c 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -57,9 +57,9 @@ #define TINT_EXTRACT_GPIOINT(x) FIELD_GET(GENMASK(31, 16), (x)) struct rzg2l_irqc_priv { - void __iomem *base; - struct irq_fwspec fwspec[IRQC_NUM_IRQ]; - raw_spinlock_t lock; + void __iomem *base; + struct irq_fwspec fwspec[IRQC_NUM_IRQ]; + raw_spinlock_t lock; }; static struct rzg2l_irqc_priv *irq_data_to_priv(struct irq_data *data) From patchwork Wed Nov 15 14:27:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13456806 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3735C48BD7 for ; Wed, 15 Nov 2023 14:28:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344236AbjKOO2x (ORCPT ); Wed, 15 Nov 2023 09:28:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37826 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234980AbjKOO2s (ORCPT ); Wed, 15 Nov 2023 09:28:48 -0500 Received: from mail-ej1-x632.google.com (mail-ej1-x632.google.com [IPv6:2a00:1450:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 22224125 for ; Wed, 15 Nov 2023 06:28:45 -0800 (PST) Received: by mail-ej1-x632.google.com with SMTP id a640c23a62f3a-9e623356e59so793967866b.0 for ; Wed, 15 Nov 2023 06:28:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1700058523; x=1700663323; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=r7Hw9o7TS/Xej42E1buaGJPREqe+QW0GFOlVV5jy/SE=; b=S6HvP1hgCb0W42VuaJSX4AnA3o0X065CLpwzFxlfTLf0Otyl98ieMSGnaxAgr6oQwT EuYE3LKhLEt/v+kWYgmeidwuyAkkoRdrWteUmEn7vD36lf9BiKHRZKGGoI8oxyp4esgB w+4O8YOdpYQbgr5A+Zi4bt9PUGmITsNnwJ0xJWWUIbzYOrE3A+jXiVTTxx58CCO5DD8g YndBVIhRtAPsbKA7ODTbdGCbzA//wDU6gH0N2iyX7CKEzW2WGLwKMOYoRlS7kDZgq2Lv a7j9gVuij6IkbvgLAEANUnazwE8gdjahdryeBQnkfy9uDejMWyhvjWgfBqw62dXq8+Cg C2zA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700058523; x=1700663323; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=r7Hw9o7TS/Xej42E1buaGJPREqe+QW0GFOlVV5jy/SE=; b=AQ6Lq8xULfQezY3iBa3f4Jss6ETOjIfGQBjLWAbTVSVcH6R3Epsl4qzgMA8qNbLeEn MtFNeKAux3XmjrJK0wVxe7ebK73CuDnOmdTslmo6lrplKXuu2bG/LLYfDetSOBtt/S4J MkknMZ16bp0PdK4jGfob9L1Q1VdTvjOpRcal3wJoXczThOYKU2yC6waELbQNPZTQHMun XOpZFzPjFDeuX57RF4WaLrqq6ADJjGu3KeJby2dQSN11fDsWVZxbjFNJ8qHYkazstHAb CHT9AFG+Cyfsl4mWNKgPDFN2QjMClxmbw8+z+ACqCnHpaTz+z0HI3n0KalFc9D2kdKT7 Ov/A== X-Gm-Message-State: AOJu0YzUMCoaMI9fvQhUH8Sf7C2cTvGQF7PcRm/+BhqkWrtn6frxHjfH Ns8c1LculZ7SABmtGJWwTrgSTw== X-Google-Smtp-Source: AGHT+IE4l9dM5Czih/3QK37kv9B6Zex7R+xmjQUgr3pcKqtHma3uatRNTil9z6jZ7X6iHucmqLcfPQ== X-Received: by 2002:a17:907:6d15:b0:994:555a:e49f with SMTP id sa21-20020a1709076d1500b00994555ae49fmr13465601ejc.31.1700058523675; Wed, 15 Nov 2023 06:28:43 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.119]) by smtp.gmail.com with ESMTPSA id i11-20020a170906264b00b0099bd5d28dc4sm7186394ejc.195.2023.11.15.06.28.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Nov 2023 06:28:43 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: tglx@linutronix.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, prabhakar.mahadev-lad.rj@bp.renesas.com Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Claudiu Beznea Subject: [PATCH v2 5/9] irqchip/renesas-rzg2l: Document structure members Date: Wed, 15 Nov 2023 16:27:45 +0200 Message-Id: <20231115142749.853106-6-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231115142749.853106-1-claudiu.beznea.uj@bp.renesas.com> References: <20231115142749.853106-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org From: Claudiu Beznea Document structure members to follow the requirements specified in maintainer-tip, section 4.3.7. Struct declarations and initializers. Link: https://www.kernel.org/doc/html/latest/process/maintainer-tip.html#struct-declarations-and-initializers Signed-off-by: Claudiu Beznea --- Changes in v2: - this patch is new drivers/irqchip/irq-renesas-rzg2l.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c index 90971ab06f0c..d666912adc74 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -56,6 +56,12 @@ #define TINT_EXTRACT_HWIRQ(x) FIELD_GET(GENMASK(15, 0), (x)) #define TINT_EXTRACT_GPIOINT(x) FIELD_GET(GENMASK(31, 16), (x)) +/** + * struct rzg2l_irqc_priv - IRQ controller private data structure + * @base: controller's base address + * @fwspec: IRQ firmware specific data + * @lock: lock to protect concurrent access to hardware registers + */ struct rzg2l_irqc_priv { void __iomem *base; struct irq_fwspec fwspec[IRQC_NUM_IRQ]; From patchwork Wed Nov 15 14:27:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13456807 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8F304C48BF9 for ; Wed, 15 Nov 2023 14:29:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344269AbjKOO3B (ORCPT ); Wed, 15 Nov 2023 09:29:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37830 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344223AbjKOO25 (ORCPT ); Wed, 15 Nov 2023 09:28:57 -0500 Received: from mail-ed1-x52f.google.com (mail-ed1-x52f.google.com [IPv6:2a00:1450:4864:20::52f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0FCF8192 for ; Wed, 15 Nov 2023 06:28:47 -0800 (PST) Received: by mail-ed1-x52f.google.com with SMTP id 4fb4d7f45d1cf-5441ba3e53cso10289496a12.1 for ; Wed, 15 Nov 2023 06:28:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1700058525; x=1700663325; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ewZ9xRCba+P0eMIANOBLPqwHZjc7NQgwGPmpIitVuvg=; b=ramrNADHtyRQFkdp114gxzCYwEKCMLSWuntKvmc5fsXBQpLGSjSd2XKJWiHA6tEi43 lc8xzN87POLshqDqEwuIXMcCOPuMEWuOsUmNsyBq6KxGJHcze3Z998qzpx6d03g6DICl /7rIs9teYJvl8cpsE6PoWPIW95bqj5CAW5mNzO5tmHv9s3i5dbnnkJUPc48bHZV1cNhe 3LJ3Ho9wRf4iSPuunhZ6rPHJhO9Xe/IzQgVEot/HlLFpazVrxzdZaLrGSDS6xJveu2/o QIUNg1GvXmgqb6y75Dh1jFrsaiuiaQcQiyK1M5Em+miZSciqRI/K7tEom4Y5eUt/h8xl VgIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700058525; x=1700663325; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ewZ9xRCba+P0eMIANOBLPqwHZjc7NQgwGPmpIitVuvg=; b=CxOauR7/xCnm2+T1N6mfKrlVFCKmQ4EFuu35YgeTdU64wglzf8dArhbptBSW5bQ92j KiQxGv7pzbQdCJfttpGMh425/nIJqcWyVp0GS6YWRcuQ3NN3vLM/8HJUetvc2h3CfXXz xcQm5ufNhScPL5MeIBV1mlXhIAmUqJKWhF+BQDHONE84c7zOao5csWCUrNNqX80h5/W6 9t78Aqi3tAAkat37FyBxuXe6cUv0CNiVdFBx8SpvMEpTqJOsxEp385Pla07zCyTnrd++ Nc74uqdwQPdw2aoFswik3+29X+DzYVG8HOdUyWitVDOAHLR8qFVfiCiBJGNfgBffg0W8 281A== X-Gm-Message-State: AOJu0YwMLeDksquvYipO7sjtsHN83Fb75Eo0Cm1TaXIF3pAW6ntMA8xh oB0NNGCzVAaChGw7VwXqMFOGeQ== X-Google-Smtp-Source: AGHT+IFr/Hvgb/Q5rpptKwRVNx5Ia+XXFIsScjiUsfOiX96bVOTiwcLamrYFhGW1obFHCL06cwdmVQ== X-Received: by 2002:a17:906:e8c:b0:9e5:e9ef:a322 with SMTP id p12-20020a1709060e8c00b009e5e9efa322mr9524778ejf.31.1700058525328; Wed, 15 Nov 2023 06:28:45 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.119]) by smtp.gmail.com with ESMTPSA id i11-20020a170906264b00b0099bd5d28dc4sm7186394ejc.195.2023.11.15.06.28.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Nov 2023 06:28:44 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: tglx@linutronix.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, prabhakar.mahadev-lad.rj@bp.renesas.com Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Claudiu Beznea Subject: [PATCH v2 6/9] irqchip/renesas-rzg2l: Implement restriction when writing ISCR register Date: Wed, 15 Nov 2023 16:27:46 +0200 Message-Id: <20231115142749.853106-7-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231115142749.853106-1-claudiu.beznea.uj@bp.renesas.com> References: <20231115142749.853106-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org From: Claudiu Beznea The RZ/G2L manual (chapter "IRQ Status Control Register (ISCR)") describes the operation to clear interrupts through the ISCR register as follows: [Write operation] When "Falling-edge detection", "Rising-edge detection" or "Falling/Rising-edge detection" is set in IITSR: - In case ISTAT is 1 0: IRQn interrupt detection status is cleared. 1: Invalid to write. - In case ISTAT is 0 Invalid to write. When “Low-level detection” is set in IITSR.: Invalid to write. Take the interrupt type into account when clearing interrupts through the ISCR register to avoid writing the ISCR when interrupt type is level. Signed-off-by: Claudiu Beznea --- Changes in v2: - adapted according to review comments - improved commit description - used uppercase letter after ":" in patch title drivers/irqchip/irq-renesas-rzg2l.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c index d666912adc74..a77ac6e1606f 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -78,11 +78,17 @@ static void rzg2l_irq_eoi(struct irq_data *d) unsigned int hw_irq = irqd_to_hwirq(d) - IRQC_IRQ_START; struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); u32 bit = BIT(hw_irq); - u32 reg; + u32 iitsr, iscr; - reg = readl_relaxed(priv->base + ISCR); - if (reg & bit) - writel_relaxed(reg & ~bit, priv->base + ISCR); + iscr = readl_relaxed(priv->base + ISCR); + iitsr = readl_relaxed(priv->base + IITSR); + + /* + * ISCR can only be cleared if the type is falling-edge, rising-edge or + * falling/rising-edge. + */ + if ((iscr & bit) && (iitsr & IITSR_IITSEL_MASK(hw_irq))) + writel_relaxed(iscr & ~bit, priv->base + ISCR); } static void rzg2l_tint_eoi(struct irq_data *d) From patchwork Wed Nov 15 14:27:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13456808 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2C64FC48BD7 for ; Wed, 15 Nov 2023 14:29:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344302AbjKOO3D (ORCPT ); Wed, 15 Nov 2023 09:29:03 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37808 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344254AbjKOO26 (ORCPT ); Wed, 15 Nov 2023 09:28:58 -0500 Received: from mail-ej1-x62a.google.com (mail-ej1-x62a.google.com [IPv6:2a00:1450:4864:20::62a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8570BC8 for ; Wed, 15 Nov 2023 06:28:48 -0800 (PST) Received: by mail-ej1-x62a.google.com with SMTP id a640c23a62f3a-9df8d0c2505so186694166b.0 for ; Wed, 15 Nov 2023 06:28:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1700058527; x=1700663327; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Z9yO45tOqTYayZtKLR1BCN+tgvteMMBPPdveLUMBPoE=; b=RXLyfsxcWw4Pm1AeeIUTy7ouOQmIIbEdXR60B7qQ0+MAZj7CrcSgP7uoJVyWunxErP cDfEuvNClbJCtBhmqdoMIZGZ0Qb47mhtKP17ErCtrJmieU7gInXOn+En4MCdheR/d2YU HXNz2QVrUC/EvalaifPZxXfVTYcEC/OD23v71/HWncfFiIj9/+5dl2larhOsxEC4/lQi YfFXsHbMQ4j0tef5nRnGM7HZWKnmB2rsbG+At8lfxLUNoRlHJgn8VRs0WOSn6VGeGF/H GzpVl4eLlVFpHNHtGX49OL8NrUaJk/Nm4jWWRilaNRHZ0dA6YST9PnuEyv6kZZRXDNgF T01g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700058527; x=1700663327; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Z9yO45tOqTYayZtKLR1BCN+tgvteMMBPPdveLUMBPoE=; b=JYLYLWB847cPBc3RF57u9+dHB2MA+hlCArVPcxZbofgKwXZXn93nu6heTdf09F0tZL lOOrOCx4gg6/z0vNayP61S+OMSAyOvV8pe27I0YO9eSIEHKV2HaBj8r6xUnZdhH3kKZ4 LmCOFWmHuXOpZyFe8KZPnKt3Q3P8sGcyxdpV6mPtJjzaHCEBIXQcOAmhUfvXis/vPSCN xydDpU/woh+3vOrFKKmy+1JSX67FgMoUvMrGkOUtx8tBEJYz34mGC8MhWb2tn1mYwPjz 6BCyeAgZ5cRSnr/TEZP6FtECCYGeuJRe/rxBE18fZQVHO5gmaMNTMstYrHY2IVmfnEca H+aA== X-Gm-Message-State: AOJu0Yz3JW9ym+Ft+KjS/RlEcCMGmwuoGwz1cPJ+y1yffXErDzBy17DC U0Y9WaqSpTuPKZHQnLCWt2JwnA== X-Google-Smtp-Source: AGHT+IFBU4slTOl6jyBO4mtXPQTN97I0/D+ZxHjdUzWRNvFQAZVsgjvaoRCvC1QzA/fV3kOaRttPUw== X-Received: by 2002:a17:906:3588:b0:9c3:97d7:2c67 with SMTP id o8-20020a170906358800b009c397d72c67mr5169418ejb.25.1700058527190; Wed, 15 Nov 2023 06:28:47 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.119]) by smtp.gmail.com with ESMTPSA id i11-20020a170906264b00b0099bd5d28dc4sm7186394ejc.195.2023.11.15.06.28.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Nov 2023 06:28:46 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: tglx@linutronix.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, prabhakar.mahadev-lad.rj@bp.renesas.com Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Claudiu Beznea Subject: [PATCH v2 7/9] irqchip/renesas-rzg2l: Add macro to retrieve TITSR register offset based on register's index Date: Wed, 15 Nov 2023 16:27:47 +0200 Message-Id: <20231115142749.853106-8-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231115142749.853106-1-claudiu.beznea.uj@bp.renesas.com> References: <20231115142749.853106-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org From: Claudiu Beznea There are 2 TITSR registers available on IA55 interrupt controller. A single macro could be used to access both of them. Add a macro that retrieves TITSR register offset based on it's index. This macro is useful in commit that adds suspend/resume support to access both TITSR registers in a for loop. Signed-off-by: Claudiu Beznea --- Changes in v2: - improved commit description - used uppercase letter after ":" in patch title - kept only the macro that returns the TITSR offset drivers/irqchip/irq-renesas-rzg2l.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c index a77ac6e1606f..45b696db220f 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -28,8 +28,7 @@ #define ISCR 0x10 #define IITSR 0x14 #define TSCR 0x20 -#define TITSR0 0x24 -#define TITSR1 0x28 +#define TITSR(n) (0x24 + (n) * 4) #define TITSR0_MAX_INT 16 #define TITSEL_WIDTH 0x2 #define TSSR(n) (0x30 + ((n) * 4)) @@ -200,8 +199,7 @@ static int rzg2l_tint_set_edge(struct irq_data *d, unsigned int type) struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); unsigned int hwirq = irqd_to_hwirq(d); u32 titseln = hwirq - IRQC_TINT_START; - u32 offset; - u8 sense; + u8 index, sense; u32 reg; switch (type & IRQ_TYPE_SENSE_MASK) { @@ -217,17 +215,17 @@ static int rzg2l_tint_set_edge(struct irq_data *d, unsigned int type) return -EINVAL; } - offset = TITSR0; + index = 0; if (titseln >= TITSR0_MAX_INT) { titseln -= TITSR0_MAX_INT; - offset = TITSR1; + index = 1; } raw_spin_lock(&priv->lock); - reg = readl_relaxed(priv->base + offset); + reg = readl_relaxed(priv->base + TITSR(index)); reg &= ~(IRQ_MASK << (titseln * TITSEL_WIDTH)); reg |= sense << (titseln * TITSEL_WIDTH); - writel_relaxed(reg, priv->base + offset); + writel_relaxed(reg, priv->base + TITSR(index)); raw_spin_unlock(&priv->lock); return 0; From patchwork Wed Nov 15 14:27:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13456809 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 14A2EC48BF9 for ; Wed, 15 Nov 2023 14:29:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344318AbjKOO3F (ORCPT ); Wed, 15 Nov 2023 09:29:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42950 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344242AbjKOO3A (ORCPT ); Wed, 15 Nov 2023 09:29:00 -0500 Received: from mail-ed1-x52a.google.com (mail-ed1-x52a.google.com [IPv6:2a00:1450:4864:20::52a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5952D1A8 for ; Wed, 15 Nov 2023 06:28:50 -0800 (PST) Received: by mail-ed1-x52a.google.com with SMTP id 4fb4d7f45d1cf-543c3756521so10291956a12.2 for ; Wed, 15 Nov 2023 06:28:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1700058528; x=1700663328; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7BLPZlgwgjU+FePQlHgbIPG2vCl4SCwWgBdjofWn3nU=; b=GTiDcY7Evokh/YNFmkHahykayS3MqmdOIxkeiWrCOmbH0IZfLiJvep+PxxjlGQl8qq MYL1YDlX6mltmD60ld79LLnbR6L2O3YkCer5qbEQa0n0fxnWZDEt/p7WlJsS3k5rFOtT T5ELGkn3DT44hR55koeZs03GSsn5GLs8utLTDPw41x1LaD9fLCIOmkD8ymYazKjDrBw9 O9bVTS5mUvfdQcPkNZIOTtkywYDKZhj6CTz16qw4jJgcUbDS11DaxM2JqlDkeRTa/JId xZ9nua20tGDdOq8Ho9WOvxQjZQZGS+VBUiB08ViK8oYCphEHQxLaGFmqyasCJ2kgrovW EL5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700058528; x=1700663328; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7BLPZlgwgjU+FePQlHgbIPG2vCl4SCwWgBdjofWn3nU=; b=VKbN9xMmE5i7MY5yzk1yza9shLG+E25wVe6RmehgUc/SGeKoSL3IlvDY2X4j6jHMtL vAgmoaiDjCfEJYu+wV4cfyNyJg8hoxIzR1zIgzTA9heA4QpRlu+qPIGVWW6kc2Yy8ScA 4j7x01nIQZ74JYPfh+p8W59O/uyEC5xlEiCDldcsfZqyCGzO7nHysw8rNvtKC/PrJ7JC GCwBNH57TssalQvHpVvfyIcg1jFrs7cfcyxYgtH1BZ4sa1LFh4r/wxBchxH1u8qVD1Iy RTNGLZgB5BQuGU6W36YgRpJkvicZp+0Gg5jRHN/+7oe5MsujkikJ4J+upA6//i+2KZn7 oVlQ== X-Gm-Message-State: AOJu0YwZUzL1wOmUItW6AyZUPdPw7KPAwSRe1w74ERYodelRVEvGWXCo /OoyKeBlBoWXiuzCvmwZzHJ5H4xaVQdXyKp2HEo= X-Google-Smtp-Source: AGHT+IF1ZSqG8f1Zf5qwEMpfqdt3g/bOQBZ51KMUPdAwD12httJ7B1Tbtqe/CwwiAYcusAXO/YlahA== X-Received: by 2002:a17:907:b9d5:b0:9be:705:d7d0 with SMTP id xa21-20020a170907b9d500b009be0705d7d0mr9460977ejc.0.1700058528710; Wed, 15 Nov 2023 06:28:48 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.119]) by smtp.gmail.com with ESMTPSA id i11-20020a170906264b00b0099bd5d28dc4sm7186394ejc.195.2023.11.15.06.28.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Nov 2023 06:28:48 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: tglx@linutronix.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, prabhakar.mahadev-lad.rj@bp.renesas.com Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Claudiu Beznea Subject: [PATCH v2 8/9] irqchip/renesas-rzg2l: Add support for suspend to RAM Date: Wed, 15 Nov 2023 16:27:48 +0200 Message-Id: <20231115142749.853106-9-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231115142749.853106-1-claudiu.beznea.uj@bp.renesas.com> References: <20231115142749.853106-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org From: Claudiu Beznea irqchip-renesas-rzg2l driver is used on RZ/G3S SoC. RZ/G3S could go to deep sleep states where power to different SoC's parts are cut off and RAM is switched to self-refresh. The resume from these states is done with the help of bootloader. IA55 IRQ controller needs to be reconfigured when resuming from deep sleep state. For this the IA55 registers are cached in suspend and restored in resume. The IA55 IRQ controller is connected to GPIO controller and GIC as follows: ┌──────────┐ ┌──────────┐ │ │ SPIX │ │ │ ├─────────►│ │ │ │ │ │ │ │ │ │ ┌────────┐IRQ0-7 │ IA55 │ │ GIC │ Pin0 ───────►│ ├─────────────►│ │ │ │ │ │ │ │ PPIY │ │ ... │ GPIO │ │ ├─────────►│ │ │ │GPIOINT0-127 │ │ │ │ PinN ───────►│ ├─────────────►│ │ │ │ └────────┘ └──────────┘ └──────────┘ where: - Pin0 is the first GPIO controller pin - PinN is the last GPIO controller pin - SPIX is the SPI interrupt with identifier X - PPIY is the PPI interrupt with identifier Y Suspend/resume functionality was implemented with syscore_ops to be able to cache/restore the registers after/before GPIO controller suspend/resume was called. As suspend/resume function members of syscore_ops doesn't take any argument, to be able to access the cache data structure and controller's base address from within suspend/resume functions, the driver private data structure was declared as static in file, named rzg2l_irqc_data and driver has been adjusted accordingly for this. Because IA55 IRQC is resumed before GPIO controller and different GPIO pins could be in unwanted state for IA55 IRQC (e.g. HiZ) when IA55 reconfiguration is done on resume path, to avoid spurious interrupts the IA55 resume configures only interrupt type on resume. The interrupt enable operation will be done at the end of GPIO controller resume. The interrupt type reconfiguration was kept in IA55 driver to minimize the number of subsystems interactions on suspend/resume b/w GPIO and IA55 drivers (as the IRQ reconfiguration from GPIO driver is done with IRQ specific APIs). Signed-off-by: Claudiu Beznea --- Changes in v2: - improved commit description - use uppercase letter after ":" in patch title - implemented review comments: used tabs to align initialized structures members, use proper naming for driver's private data structure - use local variable for controller's base address in suspend/resume functions drivers/irqchip/irq-renesas-rzg2l.c | 68 +++++++++++++++++++++++------ 1 file changed, 55 insertions(+), 13 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c index 45b696db220f..bd0dd9fcd68a 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -18,6 +18,7 @@ #include #include #include +#include #define IRQC_IRQ_START 1 #define IRQC_IRQ_COUNT 8 @@ -55,17 +56,29 @@ #define TINT_EXTRACT_HWIRQ(x) FIELD_GET(GENMASK(15, 0), (x)) #define TINT_EXTRACT_GPIOINT(x) FIELD_GET(GENMASK(31, 16), (x)) +/** + * struct rzg2l_irqc_reg_cache - registers cache (necessary for suspend/resume) + * @iitsr: IITSR register + * @titsr: TITSR registers + */ +struct rzg2l_irqc_reg_cache { + u32 iitsr; + u32 titsr[2]; +}; + /** * struct rzg2l_irqc_priv - IRQ controller private data structure * @base: controller's base address * @fwspec: IRQ firmware specific data * @lock: lock to protect concurrent access to hardware registers + * @cache: registers cache (necessary for suspend/resume) */ -struct rzg2l_irqc_priv { +static struct rzg2l_irqc_priv { void __iomem *base; struct irq_fwspec fwspec[IRQC_NUM_IRQ]; raw_spinlock_t lock; -}; + struct rzg2l_irqc_reg_cache cache; +} rzg2l_irqc_data; static struct rzg2l_irqc_priv *irq_data_to_priv(struct irq_data *data) { @@ -246,6 +259,38 @@ static int rzg2l_irqc_set_type(struct irq_data *d, unsigned int type) return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH); } +static int rzg2l_irqc_irq_suspend(void) +{ + struct rzg2l_irqc_reg_cache *cache = &rzg2l_irqc_data.cache; + void __iomem *base = rzg2l_irqc_data.base; + + cache->iitsr = readl_relaxed(base + IITSR); + for (u8 i = 0; i < 2; i++) + cache->titsr[i] = readl_relaxed(base + TITSR(i)); + + return 0; +} + +static void rzg2l_irqc_irq_resume(void) +{ + struct rzg2l_irqc_reg_cache *cache = &rzg2l_irqc_data.cache; + void __iomem *base = rzg2l_irqc_data.base; + + /* + * Restore only interrupt type. TSSRx will be restored at the + * request of pin controller to avoid spurious interrupts due + * to invalid PIN states. + */ + for (u8 i = 0; i < 2; i++) + writel_relaxed(cache->titsr[i], base + TITSR(i)); + writel_relaxed(cache->iitsr, base + IITSR); +} + +static struct syscore_ops rzg2l_irqc_syscore_ops = { + .suspend = rzg2l_irqc_irq_suspend, + .resume = rzg2l_irqc_irq_resume, +}; + static const struct irq_chip irqc_chip = { .name = "rzg2l-irqc", .irq_eoi = rzg2l_irqc_eoi, @@ -331,7 +376,6 @@ static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent) struct irq_domain *irq_domain, *parent_domain; struct platform_device *pdev; struct reset_control *resetn; - struct rzg2l_irqc_priv *priv; int ret; pdev = of_find_device_by_node(node); @@ -344,15 +388,11 @@ static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent) return -ENODEV; } - priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); - if (!priv) - return -ENOMEM; + rzg2l_irqc_data.base = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL); + if (IS_ERR(rzg2l_irqc_data.base)) + return PTR_ERR(rzg2l_irqc_data.base); - priv->base = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL); - if (IS_ERR(priv->base)) - return PTR_ERR(priv->base); - - ret = rzg2l_irqc_parse_interrupts(priv, node); + ret = rzg2l_irqc_parse_interrupts(&rzg2l_irqc_data, node); if (ret) { dev_err(&pdev->dev, "cannot parse interrupts: %d\n", ret); return ret; @@ -375,17 +415,19 @@ static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent) goto pm_disable; } - raw_spin_lock_init(&priv->lock); + raw_spin_lock_init(&rzg2l_irqc_data.lock); irq_domain = irq_domain_add_hierarchy(parent_domain, 0, IRQC_NUM_IRQ, node, &rzg2l_irqc_domain_ops, - priv); + &rzg2l_irqc_data); if (!irq_domain) { dev_err(&pdev->dev, "failed to add irq domain\n"); ret = -ENOMEM; goto pm_put; } + register_syscore_ops(&rzg2l_irqc_syscore_ops); + return 0; pm_put: From patchwork Wed Nov 15 14:27:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13456810 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 69BA5C48BF9 for ; Wed, 15 Nov 2023 14:29:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344277AbjKOO3I (ORCPT ); Wed, 15 Nov 2023 09:29:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35294 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344282AbjKOO3C (ORCPT ); Wed, 15 Nov 2023 09:29:02 -0500 Received: from mail-ej1-x62f.google.com (mail-ej1-x62f.google.com [IPv6:2a00:1450:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 844A8D49 for ; Wed, 15 Nov 2023 06:28:52 -0800 (PST) Received: by mail-ej1-x62f.google.com with SMTP id a640c23a62f3a-9d2e7726d5bso1014995366b.0 for ; Wed, 15 Nov 2023 06:28:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1700058530; x=1700663330; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9Ph5VaXSR4iSREbqKDYWT0/681kulsNQBvjFb+K43E8=; b=gjTXZ05H0n49qYQ6oQwpvkqZQGIqCixrRazZYSMqD1j5FL6nHy97E0r2zAesmWTOeB xPB/ZKG6lqbvng8bXhy+ISAtDHUHDsi7OD70Nzxdhgx+UtsTTVDBg9UEOG/7lr+ouOwi PvoawdUy35CISyIow0UehnBF/5vW7uBJTZO6dnzGWX76MlRcpuDLm/6k/sDLadcfLQAV IIsmGVnWkODZh5e3cMz6uCk7+hj3/mu/vbWilUGsal0drLhjgcofq30XyS+/gz6qI0qc 8cshDGPml1XSBwWKxN0A2d6QL5n/KVFSJMpQuaolhbLo+Yk20vUdHG1ZkNqXOBFNy/wD tUcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700058530; x=1700663330; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9Ph5VaXSR4iSREbqKDYWT0/681kulsNQBvjFb+K43E8=; b=tA9uxvBEhbc0plKtdeZGLdqkHI6KWCLF4GLpe/sU9uZAIEpV2QXaStGnN9ydN6WIRP n2lBgfrBLZeIUFMl75JPBPJBwI04Kq5HxJJvPHLdSxED036xnaAf1wrPieQ9nEYx4FTt s+EYOmvbmCTvXcMoonjd2/zmt/F2SxsbJ8LCr99oiZTNQPAC9vtt3N+iEBqbadt9Qrnq QSeT8Gjgbo5KReo1uMXxp0MxMA4+sl+7o5s97VIjVtARSaoH3k1bGeyC7IhdCg/HgLoQ lh1KDrR0gNXwxewe2xhVAZE1V5JWNysWTpHFU4sDnySmMEqg60u1wHhwUby4RHa+ji2R BA+w== X-Gm-Message-State: AOJu0YxQodK3LV9VJQ1mDmqZstgu9j90fIYJ9WBJJgTjAfb/tj3dqq4y 8VsmdgBmQwROIoVtzpP5ZBVIbA== X-Google-Smtp-Source: AGHT+IEp5vJYHNiETPzIRzWKBALXwyA9+U9jlhj5d94+ulM6YmwXzNJG2E6ChuG2P3H6As4S5NnliQ== X-Received: by 2002:a17:906:2608:b0:9e2:b250:98ca with SMTP id h8-20020a170906260800b009e2b25098camr10111867ejc.28.1700058530266; Wed, 15 Nov 2023 06:28:50 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.119]) by smtp.gmail.com with ESMTPSA id i11-20020a170906264b00b0099bd5d28dc4sm7186394ejc.195.2023.11.15.06.28.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Nov 2023 06:28:49 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: tglx@linutronix.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, prabhakar.mahadev-lad.rj@bp.renesas.com Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Claudiu Beznea Subject: [PATCH v2 9/9] arm64: dts: renesas: r9108g045: Add IA55 interrupt controller node Date: Wed, 15 Nov 2023 16:27:49 +0200 Message-Id: <20231115142749.853106-10-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231115142749.853106-1-claudiu.beznea.uj@bp.renesas.com> References: <20231115142749.853106-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org From: Claudiu Beznea Add IA55 interrupt controller node and set it as interrupt parent for pin controller. Signed-off-by: Claudiu Beznea --- Changes in v2: - none arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 68 ++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index 02a5dc9a0a3e..793512c4b31c 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -101,6 +101,7 @@ pinctrl: pinctrl@11030000 { #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + interrupt-parent = <&irqc>; gpio-ranges = <&pinctrl 0 0 152>; clocks = <&cpg CPG_MOD R9A08G045_GPIO_HCLK>; power-domains = <&cpg>; @@ -109,6 +110,73 @@ pinctrl: pinctrl@11030000 { <&cpg R9A08G045_GPIO_SPARE_RESETN>; }; + irqc: interrupt-controller@11050000 { + compatible = "renesas,r9a08g045-irqc", "renesas,rzg2l-irqc"; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0x11050000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "nmi", + "irq0", "irq1", "irq2", "irq3", + "irq4", "irq5", "irq6", "irq7", + "tint0", "tint1", "tint2", "tint3", + "tint4", "tint5", "tint6", "tint7", + "tint8", "tint9", "tint10", "tint11", + "tint12", "tint13", "tint14", "tint15", + "tint16", "tint17", "tint18", "tint19", + "tint20", "tint21", "tint22", "tint23", + "tint24", "tint25", "tint26", "tint27", + "tint28", "tint29", "tint30", "tint31", + "bus-err"; + clocks = <&cpg CPG_MOD R9A08G045_IA55_CLK>, + <&cpg CPG_MOD R9A08G045_IA55_PCLK>; + clock-names = "clk", "pclk"; + power-domains = <&cpg>; + resets = <&cpg R9A08G045_IA55_RESETN>; + }; + sdhi0: mmc@11c00000 { compatible = "renesas,sdhi-r9a08g045", "renesas,rcar-gen3-sdhi"; reg = <0x0 0x11c00000 0 0x10000>;