From patchwork Fri Nov 17 09:28:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Goud, Srinivas" X-Patchwork-Id: 13458578 X-Patchwork-Delegate: kuba@kernel.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="YhZn56Ao" Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2048.outbound.protection.outlook.com [40.107.237.48]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0C1D7D4E; Fri, 17 Nov 2023 01:29:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=hYPPGd5spEMsc99nuxvX/ApQNHqPF/HDKpQ8kCTHhbYa78zgEaApMxHoXWaSVRoovieUiDJvkZTXlklWhmtVcEG+/PTve5YWEO+VKle/j/3BjK/M8YUHtH+g34VAR9L7fQU1UUVH16yCxO2+zw/Uso5lwlIXi84ToPMTWqmELACjsBkSuCYVEgSliVi6n+dlnWhKBH32xkG9GYNcVIbVsuo5cz0cn8jfuGum/z/21+Iy2v6LnvLdMgIt/GC+x3Rh++Yw6rWLkuGj86uwxZehqtHx4KnoYTaqz1Rq6u/sPdbvUkS4z8hTpuX6WhRxVKiNhoPsHLSSXg483TOtUuF+6g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=QUbvY/iTEPP/u5JXZxOh5w++tkkmci6jPU/QqnLYQwA=; b=CxTZiQQv5tuEXUQiQlMjSgo4K0K1h8GOOVw9lw4mwdRoN/1DDXqhEt+2uFDxUSn2898rIqc6pElRctrnraLRR+FOVcDkhUDdf1kHZ1MQJnmtYzcBlfU8qAZEWnuB+ZouDjBhtz07LY+zFK7rMWrdiwdDDVBpT9FsfVGsh9z0G+7ZUalBSstGZ3N+XjgvhJCS2de2kw4tSLj3XlE6BfW7VfYL0jRxP4HZwdZ9GHCpQX6VPLjC337brDDM91UYPQogk6Cig4Kf9Lb7k/+znw0wOS3Y71ZfNxSaHpxnZl29mHtmrpaV9BXidjBdjpEvegCp/A6tOe3cwpFxe2GHuTo+6w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=grandegger.com smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=QUbvY/iTEPP/u5JXZxOh5w++tkkmci6jPU/QqnLYQwA=; b=YhZn56AoRjHfqvysMExhLkWRc3RxDdh5D9CGjYUHk8P/taq3sqmsAJgK4QuLUoWQzAwio4IOQ9caMFST2aLZaow1CE0byn84Cm2DuZ2c9awgwhFcx6f/TtNKhyIjKi5eXr6zo7lDz+Z5uM0Nok7RiJCTabDyN6BsB8UGpwyYuhs= Received: from SA0PR13CA0010.namprd13.prod.outlook.com (2603:10b6:806:130::15) by MN0PR12MB5882.namprd12.prod.outlook.com (2603:10b6:208:37a::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7002.21; Fri, 17 Nov 2023 09:29:55 +0000 Received: from SA2PEPF000015CD.namprd03.prod.outlook.com (2603:10b6:806:130:cafe::40) by SA0PR13CA0010.outlook.office365.com (2603:10b6:806:130::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7025.11 via Frontend Transport; Fri, 17 Nov 2023 09:29:55 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C Received: from SATLEXMB03.amd.com (165.204.84.17) by SA2PEPF000015CD.mail.protection.outlook.com (10.167.241.203) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7025.12 via Frontend Transport; Fri, 17 Nov 2023 09:29:55 +0000 Received: from SATLEXMB03.amd.com (10.181.40.144) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.32; Fri, 17 Nov 2023 03:29:52 -0600 Received: from xhdvnc205.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2507.32 via Frontend Transport; Fri, 17 Nov 2023 03:29:48 -0600 From: Srinivas Goud To: , , , , , , , , , CC: , , , , , , , , , "Srinivas Goud" Subject: [PATCH v5 1/3] dt-bindings: can: xilinx_can: Add 'xlnx,has-ecc' optional property Date: Fri, 17 Nov 2023 14:58:54 +0530 Message-ID: <1700213336-652-2-git-send-email-srinivas.goud@amd.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1700213336-652-1-git-send-email-srinivas.goud@amd.com> References: <1700213336-652-1-git-send-email-srinivas.goud@amd.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015CD:EE_|MN0PR12MB5882:EE_ X-MS-Office365-Filtering-Correlation-Id: 283d7448-f52e-417b-2cd8-08dbe74fc288 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 2YF6zdIUfNMcY/r7+GUO7IQKTrg4uhKnq9Vs4FGSWI56wn5dio3fmEQEpQJ+cP9eevXTEIjU2LS7NlRBwH8chg4m8+QAokHWeGxDs91qZB0gUQReLNVSrT+9jER3M0P2Ymvn4O9Ed130IleQiuG0NDc9EGDPFNsE0NtbYTzkUnX/+NNOLkHc/zD3NNtFenA+q7rOW6EFFwmufCv0lCkw08WMhT5WecEvaphlNZ9HZ65cCH73PovsVE2rrdXTSDIsz35PO73aVCMpODHT2JIcVWaBv1pmAVCJf0kztvQunkjlZXcTus1I8TAyN4ldXXdjIwMgAlpvd8SVVH3aQ86ZdbPpLsZS2M9Z2md0377cAb/JJbB4quvnJ0+qjW9iBfGaqmtQCtWNl5F73zdhE2BI/ehWYPBUI0+j1gXCBiinKjpse3QlqzQ2wprx+0md3e5UpYSlFwe7ZFgBtT4MzsP2OFvdq09HOdUgP7YYpqkvSQe15H1md2+WQhzAbe1hgwcUGth/y6MQgjUZr4oXA3NszHAlm0xxwUZwFiNlWwEI5onu9Mlxl8/gPsLQnquabtZbLpLB9TTPvwiMESH1Z965mbJKH1L6sgejnIrTE54vc4IJ9QWFZYks4VlLJJRlGFHm9/33loYZtl7vSoS62UpjpZjc2Cf5POHn8xhLnfCym2jFW1WRQ+f1hvFYahu5bzdSebPbruccSKKa+hh3f4sKOWq2Xu3tFx5QbQ6m3hjJrylE5VTtXhTQzauQuKJTP/4swxTBWXPQHOL90wWUjRO1XwMa43AJUtRA6Pl9G1s0IOXFMEoUkC8s8dFJZ10sVLKCAtfalzVFN3VM2FoAj0wzZg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(396003)(376002)(39860400002)(136003)(346002)(230922051799003)(230273577357003)(230173577357003)(82310400011)(1800799009)(186009)(64100799003)(451199024)(40470700004)(46966006)(36840700001)(2906002)(81166007)(356005)(86362001)(82740400003)(36860700001)(47076005)(7416002)(5660300002)(44832011)(40480700001)(4326008)(8936002)(41300700001)(8676002)(83380400001)(336012)(426003)(2616005)(36756003)(54906003)(316002)(26005)(70206006)(70586007)(110136005)(40460700003)(6666004)(478600001)(921008)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Nov 2023 09:29:55.4569 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 283d7448-f52e-417b-2cd8-08dbe74fc288 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015CD.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5882 X-Patchwork-Delegate: kuba@kernel.org ECC feature added to CAN TX_OL, TX_TL and RX FIFOs of Xilinx AXI CAN Controller. Part of this feature configuration and counter registers added in IP for 1bit/2bit ECC errors. 'xlnx,has-ecc' is optional property and added to Xilinx AXI CAN Controller node if ECC block enabled in the HW Signed-off-by: Srinivas Goud Acked-by: Conor Dooley --- Changes in v5: Update property description Changes in v4: Fix binding check warning Update property description Changes in v3: Update commit description Changes in v2: None Documentation/devicetree/bindings/net/can/xilinx,can.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/net/can/xilinx,can.yaml b/Documentation/devicetree/bindings/net/can/xilinx,can.yaml index 64d57c3..8d4e5af 100644 --- a/Documentation/devicetree/bindings/net/can/xilinx,can.yaml +++ b/Documentation/devicetree/bindings/net/can/xilinx,can.yaml @@ -49,6 +49,10 @@ properties: resets: maxItems: 1 + xlnx,has-ecc: + $ref: /schemas/types.yaml#/definitions/flag + description: CAN TX_OL, TX_TL and RX FIFOs have ECC support(AXI CAN) + required: - compatible - reg @@ -137,6 +141,7 @@ examples: interrupts = ; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; + xlnx,has-ecc; }; - | From patchwork Fri Nov 17 09:28:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Goud, Srinivas" X-Patchwork-Id: 13458579 X-Patchwork-Delegate: kuba@kernel.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="ZjJrNjMz" Received: from NAM02-BN1-obe.outbound.protection.outlook.com (mail-bn1nam02on2042.outbound.protection.outlook.com [40.107.212.42]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9EAA0D7A; Fri, 17 Nov 2023 01:30:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=eStAvRDqIzLUgOgvqRs/ZBMxqK+mqQ6BYjo1NUSJNkj5pk1c01RUYX6bqVyZCNX/zpOtRpbouN3hszobeqz1w9SK5uey0vmnDbOsBu5S+j0Vb+Q4Ty28A5KcnrwtEY57mtamrQXAkDJLEW0MDEUfUkeYRxoWQWDjnqURZIccEX9hPk6Qt3DhfUz2SSSYLeJpn4N8TIuhwn1z4K7Z0GJYyPcoXmfnPfKLMnnxuYg68zLvsNrqDwrJna2wQl+EwgcbaVScn6NfBUAmbs7ZyOSSQT3Wa65StY1WaEnMv1Jhx1Nv8J7RrVulKo13VhbjshcACrwacSCWooAFi9dPU0w+Wg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=WSqUIaLKUg4pFLio6Ww6X3/0Xy7t88D1Fq5Xn+n6KYM=; b=eiDGk0z5ZiJ36nhsYssD2ra5Ho+rn3WyoOBjwIqEBNxgV/+wNYmXkurTYuz8RiwH9wziI4IimLgQ1vZZIqzUBVCWk+Hz0y3zhzU1Q7gTofq9gmUzv8TRlR24xSVD/if+lGXf8XBAf8ihCR3I2PgvRMtUV8cwNN4OmJHaz9ahn6JkzbL07JVuXIqPZkBmzLRmNI1AufBaYhGUspwHHsyH16gvlWlnABY6dhgLLBtRZQuaVOrfINd/tPuOx0cr+KahENV639pXFlLX17tK2GzTV2/KXSkS4pnl5XzEca/CUgHuOSLoO8IlfrMaQ0FCjFTJSkZp5uAvHyhfOuk0o4E1MQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=grandegger.com smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=WSqUIaLKUg4pFLio6Ww6X3/0Xy7t88D1Fq5Xn+n6KYM=; b=ZjJrNjMzAcEzuOLSVGd7L9Nq0EbcqcJumJaRTl3bEiI7viP12kejvUAPqa6G12HlLh+di28SE5RdVF6nxij08WJrqrFOMzfqmxAV4UV6NN9bjGntSwXg8zWC9ocZin1gkQA009f6NQbYFMv2yJA0DoXCOovEM7VcOztZLoWB5+4= Received: from SA0PR13CA0022.namprd13.prod.outlook.com (2603:10b6:806:130::27) by BL1PR12MB5221.namprd12.prod.outlook.com (2603:10b6:208:30b::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7002.23; Fri, 17 Nov 2023 09:30:01 +0000 Received: from SA2PEPF000015CD.namprd03.prod.outlook.com (2603:10b6:806:130:cafe::2e) by SA0PR13CA0022.outlook.office365.com (2603:10b6:806:130::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7025.9 via Frontend Transport; Fri, 17 Nov 2023 09:30:01 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C Received: from SATLEXMB03.amd.com (165.204.84.17) by SA2PEPF000015CD.mail.protection.outlook.com (10.167.241.203) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7025.12 via Frontend Transport; Fri, 17 Nov 2023 09:30:01 +0000 Received: from SATLEXMB03.amd.com (10.181.40.144) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.32; Fri, 17 Nov 2023 03:29:58 -0600 Received: from xhdvnc205.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2507.32 via Frontend Transport; Fri, 17 Nov 2023 03:29:54 -0600 From: Srinivas Goud To: , , , , , , , , , CC: , , , , , , , , , "Srinivas Goud" Subject: [PATCH v5 2/3] can: xilinx_can: Add ECC support Date: Fri, 17 Nov 2023 14:58:55 +0530 Message-ID: <1700213336-652-3-git-send-email-srinivas.goud@amd.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1700213336-652-1-git-send-email-srinivas.goud@amd.com> References: <1700213336-652-1-git-send-email-srinivas.goud@amd.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015CD:EE_|BL1PR12MB5221:EE_ X-MS-Office365-Filtering-Correlation-Id: a7865918-a121-4149-f3ce-08dbe74fc5d8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: vb9THgW6wAOEqSj8OIbbiGo8jc07YuDlG6RftFYmUPkpki8fCjhA5KJEDlH7Kbs2HRlWfJvxVhRgiHnz6+70dKUypoIzuJCo86RTqY//JAlUpTHCM2gd34pvSiktKE3cy2YISI+TV8TPSKb1gPzyrQrXl/kvLYODx70TybkZT0I9GCw2nakcgzgL7l/ix2ofJDAj8zYL1QpEI6+dzm3eg97JFumNV3WvvBlgSH5BMnp8XZex5WDyulnd3md96bsMyFdvdkdKiHm6SbahNpxYnBfkWFln0gXD3JwCTUgmNzXZ9uyGIRGB8dWaoRkBTCw+EpsuN5pujQdIJHIE7+pJWea7YoyX+10UPEa4/wEhIarOn1tuEaPpyoqzHQ5D56HRjZ3ARw+b/VKvjnNYcv0kAW3jwsS8RiV49UPUOmFFybZ6Eva77LpZAJQdAzvMa91I6neOK1uA1sGvh+hBhD+tMBWLIINo+ua04X79/kjD4PT7uLKMar6C/ZYiLYbq+7cqtl37HFRJ0fgcrLkMhsEa9rhPaKIqAmIgaZIdezaLCMNMcFDPMdGlHR7/2yOX1OtgsrknIg4fUzbuNC5E77ZVzJAQts4qXan1Uukj4D8KhXhoDigq1g6dQAixoXBHaKVHaCU027n2rIz3KzT7djep3fyo+JE+n+pgKaQzyLvGLj7z6DMDbv6azihDWVmWU0I8/DzYX0ckdpcXmFGuhQ8d2dbBW9QZlwkr+k9G3mCVSwGHGl3xXECwuAj+3aKva6Oi3dyG14JN4yCjKKcDcBujtd0jIknRRBbuFYDEYw+eA7E= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(376002)(39860400002)(136003)(396003)(346002)(230922051799003)(64100799003)(186009)(1800799009)(82310400011)(451199024)(36840700001)(46966006)(40470700004)(40480700001)(478600001)(83380400001)(2616005)(26005)(110136005)(70586007)(54906003)(316002)(426003)(336012)(70206006)(36860700001)(82740400003)(44832011)(5660300002)(2906002)(47076005)(41300700001)(86362001)(356005)(81166007)(7416002)(36756003)(4326008)(40460700003)(8676002)(8936002)(921008)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Nov 2023 09:30:01.0194 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a7865918-a121-4149-f3ce-08dbe74fc5d8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015CD.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5221 X-Patchwork-Delegate: kuba@kernel.org Add ECC support for Xilinx CAN Controller, so this driver reports 1bit/2bit ECC errors for FIFO's based on ECC error interrupt. ECC feature for Xilinx CAN Controller selected through 'xlnx,has-ecc' DT property Signed-off-by: Srinivas Goud --- Changes in v5: Address review comments Change the sequence of updates the stats Use u64 stats helper function Changes in v4: None Changes in v3: None Changes in v2: Address review comments drivers/net/can/xilinx_can.c | 105 +++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 101 insertions(+), 4 deletions(-) diff --git a/drivers/net/can/xilinx_can.c b/drivers/net/can/xilinx_can.c index abe58f1..c8691a1 100644 --- a/drivers/net/can/xilinx_can.c +++ b/drivers/net/can/xilinx_can.c @@ -31,6 +31,7 @@ #include #include #include +#include #define DRIVER_NAME "xilinx_can" @@ -58,6 +59,13 @@ enum xcan_reg { */ XCAN_F_BTR_OFFSET = 0x08C, /* Data Phase Bit Timing */ XCAN_TRR_OFFSET = 0x0090, /* TX Buffer Ready Request */ + + /* only on AXI CAN cores */ + XCAN_ECC_CFG_OFFSET = 0xC8, /* ECC Configuration */ + XCAN_TXTLFIFO_ECC_OFFSET = 0xCC, /* TXTL FIFO ECC error counter */ + XCAN_TXOLFIFO_ECC_OFFSET = 0xD0, /* TXOL FIFO ECC error counter */ + XCAN_RXFIFO_ECC_OFFSET = 0xD4, /* RX FIFO ECC error counter */ + XCAN_AFR_EXT_OFFSET = 0x00E0, /* Acceptance Filter */ XCAN_FSR_OFFSET = 0x00E8, /* RX FIFO Status */ XCAN_TXMSG_BASE_OFFSET = 0x0100, /* TX Message Space */ @@ -124,6 +132,18 @@ enum xcan_reg { #define XCAN_IXR_TXFLL_MASK 0x00000004 /* Tx FIFO Full intr */ #define XCAN_IXR_TXOK_MASK 0x00000002 /* TX successful intr */ #define XCAN_IXR_ARBLST_MASK 0x00000001 /* Arbitration lost intr */ +#define XCAN_IXR_E2BERX_MASK BIT(23) /* RX FIFO two bit ECC error */ +#define XCAN_IXR_E1BERX_MASK BIT(22) /* RX FIFO one bit ECC error */ +#define XCAN_IXR_E2BETXOL_MASK BIT(21) /* TXOL FIFO two bit ECC error */ +#define XCAN_IXR_E1BETXOL_MASK BIT(20) /* TXOL FIFO One bit ECC error */ +#define XCAN_IXR_E2BETXTL_MASK BIT(19) /* TXTL FIFO Two bit ECC error */ +#define XCAN_IXR_E1BETXTL_MASK BIT(18) /* TXTL FIFO One bit ECC error */ +#define XCAN_IXR_ECC_MASK (XCAN_IXR_E2BERX_MASK | \ + XCAN_IXR_E1BERX_MASK | \ + XCAN_IXR_E2BETXOL_MASK | \ + XCAN_IXR_E1BETXOL_MASK | \ + XCAN_IXR_E2BETXTL_MASK | \ + XCAN_IXR_E1BETXTL_MASK) #define XCAN_IDR_ID1_MASK 0xFFE00000 /* Standard msg identifier */ #define XCAN_IDR_SRR_MASK 0x00100000 /* Substitute remote TXreq */ #define XCAN_IDR_IDE_MASK 0x00080000 /* Identifier extension */ @@ -137,6 +157,11 @@ enum xcan_reg { #define XCAN_2_FSR_RI_MASK 0x0000003F /* RX Read Index */ #define XCAN_DLCR_EDL_MASK 0x08000000 /* EDL Mask in DLC */ #define XCAN_DLCR_BRS_MASK 0x04000000 /* BRS Mask in DLC */ +#define XCAN_ECC_CFG_REECRX_MASK BIT(2) /* Reset RX FIFO ECC error counters */ +#define XCAN_ECC_CFG_REECTXOL_MASK BIT(1) /* Reset TXOL FIFO ECC error counters */ +#define XCAN_ECC_CFG_REECTXTL_MASK BIT(0) /* Reset TXTL FIFO ECC error counters */ +#define XCAN_ECC_1BIT_CNT_MASK GENMASK(15, 0) /* FIFO ECC 1bit count mask */ +#define XCAN_ECC_2BIT_CNT_MASK GENMASK(31, 16) /* FIFO ECC 2bit count mask */ /* CAN register bit shift - XCAN___SHIFT */ #define XCAN_BRPR_TDC_ENABLE BIT(16) /* Transmitter Delay Compensation (TDC) Enable */ @@ -202,6 +227,13 @@ struct xcan_devtype_data { * @devtype: Device type specific constants * @transceiver: Optional pointer to associated CAN transceiver * @rstc: Pointer to reset control + * @ecc_enable: ECC enable flag + * @ecc_2bit_rxfifo_cnt: RXFIFO 2bit ECC count + * @ecc_1bit_rxfifo_cnt: RXFIFO 1bit ECC count + * @ecc_2bit_txolfifo_cnt: TXOLFIFO 2bit ECC count + * @ecc_1bit_txolfifo_cnt: TXOLFIFO 1bit ECC count + * @ecc_2bit_txtlfifo_cnt: TXTLFIFO 2bit ECC count + * @ecc_1bit_txtlfifo_cnt: TXTLFIFO 1bit ECC count */ struct xcan_priv { struct can_priv can; @@ -221,6 +253,13 @@ struct xcan_priv { struct xcan_devtype_data devtype; struct phy *transceiver; struct reset_control *rstc; + bool ecc_enable; + u64_stats_t ecc_2bit_rxfifo_cnt; + u64_stats_t ecc_1bit_rxfifo_cnt; + u64_stats_t ecc_2bit_txolfifo_cnt; + u64_stats_t ecc_1bit_txolfifo_cnt; + u64_stats_t ecc_2bit_txtlfifo_cnt; + u64_stats_t ecc_1bit_txtlfifo_cnt; }; /* CAN Bittiming constants as per Xilinx CAN specs */ @@ -523,6 +562,9 @@ static int xcan_chip_start(struct net_device *ndev) XCAN_IXR_ERROR_MASK | XCAN_IXR_RXOFLW_MASK | XCAN_IXR_ARBLST_MASK | xcan_rx_int_mask(priv); + if (priv->ecc_enable) + ier |= XCAN_IXR_ECC_MASK; + if (priv->devtype.flags & XCAN_FLAG_RXMNF) ier |= XCAN_IXR_RXMNF_MASK; @@ -1127,6 +1169,50 @@ static void xcan_err_interrupt(struct net_device *ndev, u32 isr) priv->can.can_stats.bus_error++; } + if (priv->ecc_enable && isr & XCAN_IXR_ECC_MASK) { + u32 reg_rx_ecc, reg_txol_ecc, reg_txtl_ecc; + + reg_rx_ecc = priv->read_reg(priv, XCAN_RXFIFO_ECC_OFFSET); + reg_txol_ecc = priv->read_reg(priv, XCAN_TXOLFIFO_ECC_OFFSET); + reg_txtl_ecc = priv->read_reg(priv, XCAN_TXTLFIFO_ECC_OFFSET); + + /* The counter reaches its maximum at 0xffff and does not overflow. + * Accept the small race window between reading and resetting ECC counters. + */ + priv->write_reg(priv, XCAN_ECC_CFG_OFFSET, XCAN_ECC_CFG_REECRX_MASK | + XCAN_ECC_CFG_REECTXOL_MASK | XCAN_ECC_CFG_REECTXTL_MASK); + + if (isr & XCAN_IXR_E2BERX_MASK) { + u64_stats_add(&priv->ecc_2bit_rxfifo_cnt, + FIELD_GET(XCAN_ECC_2BIT_CNT_MASK, reg_rx_ecc)); + } + + if (isr & XCAN_IXR_E1BERX_MASK) { + u64_stats_add(&priv->ecc_1bit_rxfifo_cnt, + FIELD_GET(XCAN_ECC_1BIT_CNT_MASK, reg_rx_ecc)); + } + + if (isr & XCAN_IXR_E2BETXOL_MASK) { + u64_stats_add(&priv->ecc_2bit_txolfifo_cnt, + FIELD_GET(XCAN_ECC_2BIT_CNT_MASK, reg_txol_ecc)); + } + + if (isr & XCAN_IXR_E1BETXOL_MASK) { + u64_stats_add(&priv->ecc_1bit_txolfifo_cnt, + FIELD_GET(XCAN_ECC_1BIT_CNT_MASK, reg_txol_ecc)); + } + + if (isr & XCAN_IXR_E2BETXTL_MASK) { + u64_stats_add(&priv->ecc_2bit_txtlfifo_cnt, + FIELD_GET(XCAN_ECC_2BIT_CNT_MASK, reg_txtl_ecc)); + } + + if (isr & XCAN_IXR_E1BETXTL_MASK) { + u64_stats_add(&priv->ecc_1bit_txtlfifo_cnt, + FIELD_GET(XCAN_ECC_1BIT_CNT_MASK, reg_txtl_ecc)); + } + } + if (cf.can_id) { struct can_frame *skb_cf; struct sk_buff *skb = alloc_can_err_skb(ndev, &skb_cf); @@ -1355,7 +1441,7 @@ static irqreturn_t xcan_interrupt(int irq, void *dev_id) struct net_device *ndev = (struct net_device *)dev_id; struct xcan_priv *priv = netdev_priv(ndev); u32 isr, ier; - u32 isr_errors; + u32 isr_errors, mask; u32 rx_int_mask = xcan_rx_int_mask(priv); /* Get the interrupt status from Xilinx CAN */ @@ -1374,10 +1460,15 @@ static irqreturn_t xcan_interrupt(int irq, void *dev_id) if (isr & XCAN_IXR_TXOK_MASK) xcan_tx_interrupt(ndev, isr); + mask = XCAN_IXR_ERROR_MASK | XCAN_IXR_RXOFLW_MASK | + XCAN_IXR_BSOFF_MASK | XCAN_IXR_ARBLST_MASK | + XCAN_IXR_RXMNF_MASK; + + if (priv->ecc_enable) + mask |= XCAN_IXR_ECC_MASK; + /* Check for the type of error interrupt and Processing it */ - isr_errors = isr & (XCAN_IXR_ERROR_MASK | XCAN_IXR_RXOFLW_MASK | - XCAN_IXR_BSOFF_MASK | XCAN_IXR_ARBLST_MASK | - XCAN_IXR_RXMNF_MASK); + isr_errors = isr & mask; if (isr_errors) { priv->write_reg(priv, XCAN_ICR_OFFSET, isr_errors); xcan_err_interrupt(ndev, isr); @@ -1796,6 +1887,7 @@ static int xcan_probe(struct platform_device *pdev) return -ENOMEM; priv = netdev_priv(ndev); + priv->ecc_enable = of_property_read_bool(pdev->dev.of_node, "xlnx,has-ecc"); priv->dev = &pdev->dev; priv->can.bittiming_const = devtype->bittiming_const; priv->can.do_set_mode = xcan_do_set_mode; @@ -1912,6 +2004,11 @@ static int xcan_probe(struct platform_device *pdev) priv->reg_base, ndev->irq, priv->can.clock.freq, hw_tx_max, priv->tx_max); + if (priv->ecc_enable) { + /* Reset FIFO ECC counters */ + priv->write_reg(priv, XCAN_ECC_CFG_OFFSET, XCAN_ECC_CFG_REECRX_MASK | + XCAN_ECC_CFG_REECTXOL_MASK | XCAN_ECC_CFG_REECTXTL_MASK); + } return 0; err_disableclks: From patchwork Fri Nov 17 09:28:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Goud, Srinivas" X-Patchwork-Id: 13458580 X-Patchwork-Delegate: kuba@kernel.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="r8M4t6tR" Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2079.outbound.protection.outlook.com [40.107.94.79]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 02D71D72; Fri, 17 Nov 2023 01:30:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=NvB384MRywjKZnXklDYhrDoCHC2CnLbz2nkYAsCkyjLrfuX5U5k3RZrkM3kJSe1yJ2O0ojpbwlQzP8T+bF0ST2vtJVTAgvMGpUFtsxUvwWcI2dFz7OGxy3akKEoXRalhWi2WrsWGo79iGXeIxD9C/ST37oaYDgesyCQsG5jZR9D/5DzEsXKjwfuiJnESXCuPBw1hIeaN2YRkPsGmUs8gEPTTaTfWScOT6uBAMPmCz6n6MvhHojq2g/BumPcj7RlkCIBu8OBGFrWdNJmEV3a+8BaYHg5s/ZVqkCSvWqnCeWa0Ewelq246IfbGAQKcFqyskKN8CRNu5Lal8UULvFZsaA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=ADYf81Hycw0btEuUqlS0DbgN0xoea1hWZrRYHuIyxfE=; b=BIsZw2nMvhFRt5Gmj78JDkfkHB7tBzy3JI0hjGe2ipAw143hi+roBXS5K8Cg5gVK7AIGaIzh8mDoujW0fjvTRLMj4dAIL8n+s3BiPGB5pgtodgtmTwSVFKcj9eu5AhSn7ZUYdrBd7rIzLbfTTCXbU8wg618qoT7Wcorv2iXyDu1kWEFan+lmAOpMMI3OKseE81TOmUlIsX12IA1+snqe6kVAPbUXtT9q83HBT9ZW9AKYBTpuj7HXSYHQ4RX/MiqVP6luvPOjYIBhHh/wZLNapVcAKd2xdc4jFC4c+l8E0YjwZ2RgsQqVdOYxDBidMI9LBJawkEciH6qK6W2VLrqc+Q== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=grandegger.com smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ADYf81Hycw0btEuUqlS0DbgN0xoea1hWZrRYHuIyxfE=; b=r8M4t6tRZr2PFP8Z4B6ns7IvUuqc5/0W/NFjFGCTnm58LWBNCSDsmYYY5exmC9NnCv051Vx7VqJq0546nSONzodhEvhvlQYHBMKsxciPBWZDcsQIjnz9MRQV/0wwNYulv8Yy19Mppm/8YU9MMWH5bE6sSBqimTReFx8OTQ0NoB0= Received: from CH0PR04CA0050.namprd04.prod.outlook.com (2603:10b6:610:77::25) by BL3PR12MB6619.namprd12.prod.outlook.com (2603:10b6:208:38e::5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7002.23; Fri, 17 Nov 2023 09:30:09 +0000 Received: from SA2PEPF000015C8.namprd03.prod.outlook.com (2603:10b6:610:77:cafe::11) by CH0PR04CA0050.outlook.office365.com (2603:10b6:610:77::25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7002.20 via Frontend Transport; Fri, 17 Nov 2023 09:30:08 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C Received: from SATLEXMB03.amd.com (165.204.84.17) by SA2PEPF000015C8.mail.protection.outlook.com (10.167.241.198) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7002.20 via Frontend Transport; Fri, 17 Nov 2023 09:30:08 +0000 Received: from SATLEXMB06.amd.com (10.181.40.147) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.32; Fri, 17 Nov 2023 03:30:04 -0600 Received: from SATLEXMB03.amd.com (10.181.40.144) by SATLEXMB06.amd.com (10.181.40.147) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.32; Fri, 17 Nov 2023 03:30:03 -0600 Received: from xhdvnc205.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2507.32 via Frontend Transport; Fri, 17 Nov 2023 03:29:59 -0600 From: Srinivas Goud To: , , , , , , , , , CC: , , , , , , , , , "Srinivas Goud" Subject: [PATCH v5 3/3] can: xilinx_can: Add ethtool stats interface for ECC errors Date: Fri, 17 Nov 2023 14:58:56 +0530 Message-ID: <1700213336-652-4-git-send-email-srinivas.goud@amd.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1700213336-652-1-git-send-email-srinivas.goud@amd.com> References: <1700213336-652-1-git-send-email-srinivas.goud@amd.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015C8:EE_|BL3PR12MB6619:EE_ X-MS-Office365-Filtering-Correlation-Id: 5a075f94-b650-4b82-72d8-08dbe74fca76 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: GUMDBJYBwDNCsU3pvkF0h1D15Q2al5FQizTTa4vynbJZoz+oFQEqU8GVNP20PjS/qBcQ4dJo9QCFwwQ17yll/xg48QG8+Wgnb5Fqjyhix10ka2vvppaeiL9yAlNNraGUhwLld+Q514Agei0WJZeMZFVzs+1Twaj3+VmvE6mVCWkFHipQlhz5eo0ptIZr4Rzq33fjOiiBGVeITYGn0Nc/3ierFop5AVWgkCGGQnfxJWMEoLsBeh31R8NmW4+nB2TWFc4OWBUXQcRyZwKftMTGejSvFBfT2+K5+6djNhSouGeWWD2xLS8eBfNuSliaCUWFziVm8kMnG3GdnMmfDfwb9wOTgxqKJS9tNmZj7ZQYM8K2T8KPTVQNjqd7IDqLlbVTY8zSv4crxUH7Dt1lHWuaq7NwrXDou3+l0MuzroxRlVqvBIzh2M7M7qwvfWBOjRE3gW+6Wj8ePsc13eYM7r5ri6miDxRXo67RN4ZYjH6suId0BYkJhqpZHWy1KqBzbpNNZmBNR4l5h6onyz2DUzA0jbf1cK8IFRmk6jKjttsCTV0czmReLMmusQ1RV1zcIqvvpQ2jZO4b5BOJD+/fB2YTWIZqYA2G4FSd9RqYCcOLVPZIbmFb7ZSG3EwASqDPcBCoVPdE7hPrxags4dFugqLsvFwiNTJlOXlgYq4jCItO0aZySdaB18JmGD5FatOV7M6gUTISLazC3jJrX7OL4vQrUrjscUWAr7cpQWYGIWi2gvLjP79IGsXeh9YBU5riRX2FSYytHoiRZbGpNrUAnNXV6uz3r/3PzAF3zlVv21VUyxk= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(136003)(39860400002)(376002)(346002)(396003)(230922051799003)(1800799009)(451199024)(186009)(82310400011)(64100799003)(36840700001)(40470700004)(46966006)(41300700001)(44832011)(36756003)(40460700003)(2906002)(7416002)(5660300002)(86362001)(921008)(2616005)(26005)(40480700001)(83380400001)(82740400003)(336012)(426003)(6666004)(478600001)(47076005)(81166007)(356005)(36860700001)(316002)(54906003)(4326008)(8676002)(8936002)(70206006)(70586007)(110136005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Nov 2023 09:30:08.7625 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5a075f94-b650-4b82-72d8-08dbe74fca76 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015C8.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6619 X-Patchwork-Delegate: kuba@kernel.org Add ethtool stats interface for reading FIFO 1bit/2bit ECC errors information. Signed-off-by: Srinivas Goud --- Changes in v5: Address review comments Add get_strings and get_sset_count stats interface Use u64 stats helper function Changes in v4: None Changes in v3: None Changes in v2: Add ethtool stats interface drivers/net/can/xilinx_can.c | 54 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/drivers/net/can/xilinx_can.c b/drivers/net/can/xilinx_can.c index c8691a1..40c912b 100644 --- a/drivers/net/can/xilinx_can.c +++ b/drivers/net/can/xilinx_can.c @@ -228,6 +228,7 @@ struct xcan_devtype_data { * @transceiver: Optional pointer to associated CAN transceiver * @rstc: Pointer to reset control * @ecc_enable: ECC enable flag + * @stats_lock: Lock for synchronizing ECC errors stats * @ecc_2bit_rxfifo_cnt: RXFIFO 2bit ECC count * @ecc_1bit_rxfifo_cnt: RXFIFO 1bit ECC count * @ecc_2bit_txolfifo_cnt: TXOLFIFO 2bit ECC count @@ -254,6 +255,7 @@ struct xcan_priv { struct phy *transceiver; struct reset_control *rstc; bool ecc_enable; + spinlock_t stats_lock; /* Lock for synchronizing ECC errors stats */ u64_stats_t ecc_2bit_rxfifo_cnt; u64_stats_t ecc_1bit_rxfifo_cnt; u64_stats_t ecc_2bit_txolfifo_cnt; @@ -347,6 +349,12 @@ static const struct can_tdc_const xcan_tdc_const_canfd2 = { .tdcf_max = 0, }; +static const char xcan_priv_flags_strings[][ETH_GSTRING_LEN] = { + "err-ecc-rx-2-bit", "err-ecc-rx-1-bit", + "err-ecc-txol-2-bit", "err-ecc-txol-1-bit", + "err-ecc-txtl-2-bit", "err-ecc-txtl-1-bit", +}; + /** * xcan_write_reg_le - Write a value to the device register little endian * @priv: Driver private data structure @@ -1171,6 +1179,9 @@ static void xcan_err_interrupt(struct net_device *ndev, u32 isr) if (priv->ecc_enable && isr & XCAN_IXR_ECC_MASK) { u32 reg_rx_ecc, reg_txol_ecc, reg_txtl_ecc; + unsigned long flags; + + spin_lock_irqsave(&priv->stats_lock, flags); reg_rx_ecc = priv->read_reg(priv, XCAN_RXFIFO_ECC_OFFSET); reg_txol_ecc = priv->read_reg(priv, XCAN_TXOLFIFO_ECC_OFFSET); @@ -1182,6 +1193,8 @@ static void xcan_err_interrupt(struct net_device *ndev, u32 isr) priv->write_reg(priv, XCAN_ECC_CFG_OFFSET, XCAN_ECC_CFG_REECRX_MASK | XCAN_ECC_CFG_REECTXOL_MASK | XCAN_ECC_CFG_REECTXTL_MASK); + spin_unlock_irqrestore(&priv->stats_lock, flags); + if (isr & XCAN_IXR_E2BERX_MASK) { u64_stats_add(&priv->ecc_2bit_rxfifo_cnt, FIELD_GET(XCAN_ECC_2BIT_CNT_MASK, reg_rx_ecc)); @@ -1637,6 +1650,44 @@ static int xcan_get_auto_tdcv(const struct net_device *ndev, u32 *tdcv) return 0; } +static void xcan_get_strings(struct net_device *ndev, u32 stringset, u8 *buf) +{ + switch (stringset) { + case ETH_SS_STATS: + memcpy(buf, &xcan_priv_flags_strings, + sizeof(xcan_priv_flags_strings)); + } +} + +static int xcan_get_sset_count(struct net_device *netdev, int sset) +{ + switch (sset) { + case ETH_SS_STATS: + return ARRAY_SIZE(xcan_priv_flags_strings); + default: + return -EOPNOTSUPP; + } +} + +static void xcan_get_ethtool_stats(struct net_device *ndev, + struct ethtool_stats *stats, u64 *data) +{ + struct xcan_priv *priv = netdev_priv(ndev); + unsigned long flags; + int i = 0; + + spin_lock_irqsave(&priv->stats_lock, flags); + + data[i++] = u64_stats_read(&priv->ecc_2bit_rxfifo_cnt); + data[i++] = u64_stats_read(&priv->ecc_1bit_rxfifo_cnt); + data[i++] = u64_stats_read(&priv->ecc_2bit_txolfifo_cnt); + data[i++] = u64_stats_read(&priv->ecc_1bit_txolfifo_cnt); + data[i++] = u64_stats_read(&priv->ecc_2bit_txtlfifo_cnt); + data[i++] = u64_stats_read(&priv->ecc_1bit_txtlfifo_cnt); + + spin_unlock_irqrestore(&priv->stats_lock, flags); +} + static const struct net_device_ops xcan_netdev_ops = { .ndo_open = xcan_open, .ndo_stop = xcan_close, @@ -1646,6 +1697,9 @@ static const struct net_device_ops xcan_netdev_ops = { static const struct ethtool_ops xcan_ethtool_ops = { .get_ts_info = ethtool_op_get_ts_info, + .get_strings = xcan_get_strings, + .get_sset_count = xcan_get_sset_count, + .get_ethtool_stats = xcan_get_ethtool_stats, }; /**