From patchwork Fri Nov 17 15:19:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Janosch Frank X-Patchwork-Id: 13459033 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ibm.com header.i=@ibm.com header.b="bCKL3huy" Received: from mx0b-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AAB2AD57; Fri, 17 Nov 2023 07:20:00 -0800 (PST) Received: from pps.filterd (m0353724.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3AHFHsld032666; Fri, 17 Nov 2023 15:20:00 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pp1; bh=uXngpEpqKrdvxWVxKscGwesmwSzGjkt0nz0zZlt94vw=; b=bCKL3huy7JPLyWR3boQOkXW2j/yEDPV8gsDh60bIw+tH5wSKteYx6B+rOH//Ou7ON++C OSSxhcKj31Rm7CA0L2fyGP4brAmygAMiWa1iVf8gp2UKQMlZxrwMoTTUC0zceJBdoCCa MUSA4b95EHB1hPYOZl9/PRNeNybYO07uzsSNycHjZgGDBTmiGynVVRBDaWmCFZ8yfbPV euV59PCXY6ZMHBp7/cH3cIGaU2CLR3Hyw49MDiACBB0Jj07nv/kVUUw0TBTovsC36fQp nAnJc+yQDjs+J35QKn8HOk5DAkhpdPGUEsObznykcPQJR8rwVnR6UVQPacSFIaXqWEX5 3A== Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3ueap8r2jn-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 17 Nov 2023 15:19:59 +0000 Received: from m0353724.ppops.net (m0353724.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 3AHFI3W3002015; Fri, 17 Nov 2023 15:19:59 GMT Received: from ppma23.wdc07v.mail.ibm.com (5d.69.3da9.ip4.static.sl-reverse.com [169.61.105.93]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3ueap8r2j6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 17 Nov 2023 15:19:59 +0000 Received: from pps.filterd (ppma23.wdc07v.mail.ibm.com [127.0.0.1]) by ppma23.wdc07v.mail.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id 3AHFJMw6015911; Fri, 17 Nov 2023 15:19:58 GMT Received: from smtprelay06.fra02v.mail.ibm.com ([9.218.2.230]) by ppma23.wdc07v.mail.ibm.com (PPS) with ESMTPS id 3uanem6q3c-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 17 Nov 2023 15:19:58 +0000 Received: from smtpav03.fra02v.mail.ibm.com (smtpav03.fra02v.mail.ibm.com [10.20.54.102]) by smtprelay06.fra02v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 3AHFJtPW45482314 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 17 Nov 2023 15:19:55 GMT Received: from smtpav03.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 284FE20043; Fri, 17 Nov 2023 15:19:55 +0000 (GMT) Received: from smtpav03.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id DC4BE2004F; Fri, 17 Nov 2023 15:19:54 +0000 (GMT) Received: from a46lp67.. (unknown [9.152.108.100]) by smtpav03.fra02v.mail.ibm.com (Postfix) with ESMTP; Fri, 17 Nov 2023 15:19:54 +0000 (GMT) From: Janosch Frank To: kvm@vger.kernel.org Cc: linux-s390@vger.kernel.org, imbrenda@linux.ibm.com, thuth@redhat.com, david@redhat.com, nsg@linux.ibm.com, nrb@linux.ibm.com Subject: [kvm-unit-tests PATCH v3 1/7] lib: s390x: Add ap library Date: Fri, 17 Nov 2023 15:19:33 +0000 Message-Id: <20231117151939.971079-2-frankja@linux.ibm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231117151939.971079-1-frankja@linux.ibm.com> References: <20231117151939.971079-1-frankja@linux.ibm.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: xpRzy0KE5ZQOO-o-ztdt-dr1ToofaDXo X-Proofpoint-ORIG-GUID: B1ZRAI6tDsYCWLbKxzUcQKK2aeWsrq37 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-17_14,2023-11-17_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 lowpriorityscore=0 bulkscore=0 impostorscore=0 priorityscore=1501 adultscore=0 mlxscore=0 mlxlogscore=999 malwarescore=0 clxscore=1015 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311170114 Add functions and definitions needed to test the Adjunct Processor (AP) crypto interface. Signed-off-by: Janosch Frank --- lib/s390x/ap.c | 93 ++++++++++++++++++++++++++++++++++++++++++++++++++ lib/s390x/ap.h | 88 +++++++++++++++++++++++++++++++++++++++++++++++ s390x/Makefile | 1 + 3 files changed, 182 insertions(+) create mode 100644 lib/s390x/ap.c create mode 100644 lib/s390x/ap.h diff --git a/lib/s390x/ap.c b/lib/s390x/ap.c new file mode 100644 index 00000000..17a32d66 --- /dev/null +++ b/lib/s390x/ap.c @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * AP crypto functions + * + * Some parts taken from the Linux AP driver. + * + * Copyright IBM Corp. 2023 + * Author: Janosch Frank + * Tony Krowiak + * Martin Schwidefsky + * Harald Freudenberger + */ + +#include +#include +#include +#include +#include + +int ap_pqap_tapq(uint8_t ap, uint8_t qn, struct ap_queue_status *apqsw, + struct pqap_r2 *r2) +{ + struct pqap_r0 r0 = { + .ap = ap, + .qn = qn, + .fc = PQAP_TEST_APQ + }; + int cc; + + /* + * Test AP Queue + * + * Writes AP configuration information to the memory pointed + * at by GR2. + * + * Inputs: GR0 + * Outputs: GR1 (APQSW), GR2 (tapq data) + * Synchronous + */ + asm volatile( + " lgr 0,%[r0]\n" + " .insn rre,0xb2af0000,0,0\n" /* PQAP */ + " stg 1,%[apqsw]\n" + " stg 2,%[r2]\n" + " ipm %[cc]\n" + " srl %[cc],28\n" + : [apqsw] "=&T" (*apqsw), [r2] "=&T" (*r2), [cc] "=&d" (cc) + : [r0] "d" (r0)); + + return cc; +} + +int ap_pqap_qci(struct ap_config_info *info) +{ + struct pqap_r0 r0 = { .fc = PQAP_QUERY_AP_CONF_INFO }; + int cc; + + /* + * Query AP Configuration Information + * + * Writes AP configuration information to the memory pointed + * at by GR2. + * + * Inputs: GR0, GR2 (QCI block address) + * Outputs: memory at GR2 address + * Synchronous + */ + asm volatile( + " lgr 0,%[r0]\n" + " lgr 2,%[info]\n" + " .insn rre,0xb2af0000,0,0\n" /* PQAP */ + " ipm %[cc]\n" + " srl %[cc],28\n" + : [cc] "=&d" (cc) + : [r0] "d" (r0), [info] "d" (info) + : "cc", "memory", "0", "2"); + + return cc; +} + +/* Will later be extended to a proper setup function */ +bool ap_setup(void) +{ + /* + * Base AP support has no STFLE or SCLP feature bit but the + * PQAP QCI support is indicated via stfle bit 12. As this + * library relies on QCI we bail out if it's not available. + */ + if (!test_facility(12)) + return false; + + return true; +} diff --git a/lib/s390x/ap.h b/lib/s390x/ap.h new file mode 100644 index 00000000..cda1e564 --- /dev/null +++ b/lib/s390x/ap.h @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * AP definitions + * + * Some parts taken from the Linux AP driver. + * + * Copyright IBM Corp. 2023 + * Author: Janosch Frank + * Tony Krowiak + * Martin Schwidefsky + * Harald Freudenberger + */ + +#ifndef _S390X_AP_H_ +#define _S390X_AP_H_ + +enum PQAP_FC { + PQAP_TEST_APQ, + PQAP_RESET_APQ, + PQAP_ZEROIZE_APQ, + PQAP_QUEUE_INT_CONTRL, + PQAP_QUERY_AP_CONF_INFO, + PQAP_QUERY_AP_COMP_TYPE, + PQAP_BEST_AP, +}; + +struct ap_queue_status { + uint32_t pad0; /* Ignored padding for zArch */ + uint32_t empty : 1; + uint32_t replies_waiting: 1; + uint32_t full : 1; + uint32_t pad1 : 4; + uint32_t irq_enabled : 1; + uint32_t rc : 8; + uint32_t pad2 : 16; +} __attribute__((packed)) __attribute__((aligned(8))); +_Static_assert(sizeof(struct ap_queue_status) == sizeof(uint64_t), "APQSW size"); + +struct ap_config_info { + uint8_t apsc : 1; /* S bit */ + uint8_t apxa : 1; /* N bit */ + uint8_t qact : 1; /* C bit */ + uint8_t rc8a : 1; /* R bit */ + uint8_t l : 1; /* L bit */ + uint8_t lext : 3; /* Lext bits */ + uint8_t reserved2[3]; + uint8_t Na; /* max # of APs - 1 */ + uint8_t Nd; /* max # of Domains - 1 */ + uint8_t reserved6[10]; + uint32_t apm[8]; /* AP ID mask */ + uint32_t aqm[8]; /* AP (usage) queue mask */ + uint32_t adm[8]; /* AP (control) domain mask */ + uint8_t _reserved4[16]; +} __attribute__((aligned(8))) __attribute__ ((__packed__)); +_Static_assert(sizeof(struct ap_config_info) == 128, "PQAP QCI size"); + +struct pqap_r0 { + uint32_t pad0; + uint8_t fc; + uint8_t t : 1; /* Test facilities (TAPQ)*/ + uint8_t pad1 : 7; + uint8_t ap; + uint8_t qn; +} __attribute__((packed)) __attribute__((aligned(8))); + +struct pqap_r2 { + uint8_t s : 1; /* Special Command facility */ + uint8_t m : 1; /* AP4KM */ + uint8_t c : 1; /* AP4KC */ + uint8_t cop : 1; /* AP is in coprocessor mode */ + uint8_t acc : 1; /* AP is in accelerator mode */ + uint8_t xcp : 1; /* AP is in XCP-mode */ + uint8_t n : 1; /* AP extended addressing facility */ + uint8_t pad_0 : 1; + uint8_t pad_1[3]; + uint8_t at; + uint8_t nd; + uint8_t pad_6; + uint8_t pad_7 : 4; + uint8_t qd : 4; +} __attribute__((packed)) __attribute__((aligned(8))); +_Static_assert(sizeof(struct pqap_r2) == sizeof(uint64_t), "pqap_r2 size"); + +bool ap_setup(void); +int ap_pqap_tapq(uint8_t ap, uint8_t qn, struct ap_queue_status *apqsw, + struct pqap_r2 *r2); +int ap_pqap_qci(struct ap_config_info *info); +#endif diff --git a/s390x/Makefile b/s390x/Makefile index f79fd009..2199eeba 100644 --- a/s390x/Makefile +++ b/s390x/Makefile @@ -110,6 +110,7 @@ cflatobjs += lib/s390x/malloc_io.o cflatobjs += lib/s390x/uv.o cflatobjs += lib/s390x/sie.o cflatobjs += lib/s390x/fault.o +cflatobjs += lib/s390x/ap.o OBJDIRS += lib/s390x From patchwork Fri Nov 17 15:19:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Janosch Frank X-Patchwork-Id: 13459034 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ibm.com header.i=@ibm.com header.b="GesCaqLm" Received: from mx0b-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2AE84D5D; Fri, 17 Nov 2023 07:20:01 -0800 (PST) Received: from pps.filterd (m0356516.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3AHFGMq0023792; Fri, 17 Nov 2023 15:20:00 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pp1; bh=t13JTT466A/A29EtB1D3V/wekd72I7iQJmIq1hWvAto=; b=GesCaqLmuPJfiMrBk//YgiLaU+XMmT/ch+k8g5FcL1+btmn2djfiOXSbvhYw0L3qC/yT eLZygUsKBs4ILlxMX5OKcJur9K9wjqQ8J/6Dh805ICUtfETUFBFsC1kW9j5M0VxlFR2o OBqTPk4Q5NVUCgUX69GYZCxcRD7P5fsLEUpNLBcO7+S9EEqz3wwwnoBj1egQZRqQe+pb OkiYp2Zl92ikzqiRHTTwnRGvj6N64mhO3wTJWdBA/9K9k4NnODRGEBK3QpJNi07hBjdt PN3xVZSFiojNY56pyGquV9iDUOXwrHxx1nkv1Z+x612zulUXYAtV4cMV9Lf64x4VF1lK TA== Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3ueap083bm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); 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(unknown [9.152.108.100]) by smtpav03.fra02v.mail.ibm.com (Postfix) with ESMTP; Fri, 17 Nov 2023 15:19:55 +0000 (GMT) From: Janosch Frank To: kvm@vger.kernel.org Cc: linux-s390@vger.kernel.org, imbrenda@linux.ibm.com, thuth@redhat.com, david@redhat.com, nsg@linux.ibm.com, nrb@linux.ibm.com Subject: [kvm-unit-tests PATCH v3 2/7] s390x: Add guest 2 AP test Date: Fri, 17 Nov 2023 15:19:34 +0000 Message-Id: <20231117151939.971079-3-frankja@linux.ibm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231117151939.971079-1-frankja@linux.ibm.com> References: <20231117151939.971079-1-frankja@linux.ibm.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: 5K0iN2h4pFz4VM-PF-oB2C0mhnTQLaIT X-Proofpoint-ORIG-GUID: GsTbgUNo7aZfvpu4zQxy0Vg--K-LoIAS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-17_14,2023-11-17_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=901 clxscore=1015 mlxscore=0 bulkscore=0 priorityscore=1501 spamscore=0 lowpriorityscore=0 adultscore=0 malwarescore=0 impostorscore=0 suspectscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311170114 Add a test that checks the exceptions for the PQAP, NQAP and DQAP adjunct processor (AP) crypto instructions. Since triggering the exceptions doesn't require actual AP hardware, this test can run without complicated setup. Signed-off-by: Janosch Frank --- s390x/Makefile | 1 + s390x/ap.c | 309 ++++++++++++++++++++++++++++++++++++++++++++ s390x/unittests.cfg | 3 + 3 files changed, 313 insertions(+) create mode 100644 s390x/ap.c diff --git a/s390x/Makefile b/s390x/Makefile index 2199eeba..ea760c6b 100644 --- a/s390x/Makefile +++ b/s390x/Makefile @@ -42,6 +42,7 @@ tests += $(TEST_DIR)/exittime.elf tests += $(TEST_DIR)/ex.elf tests += $(TEST_DIR)/topology.elf tests += $(TEST_DIR)/sie-dat.elf +tests += $(TEST_DIR)/ap.elf pv-tests += $(TEST_DIR)/pv-diags.elf pv-tests += $(TEST_DIR)/pv-icptcode.elf diff --git a/s390x/ap.c b/s390x/ap.c new file mode 100644 index 00000000..94f08783 --- /dev/null +++ b/s390x/ap.c @@ -0,0 +1,309 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * AP instruction G2 tests + * + * Copyright (c) 2023 IBM Corp + * + * Authors: + * Janosch Frank + */ + +#include +#include +#include +#include +#include +#include +#include + +/* For PQAP PGM checks where we need full control over the input */ +static void pqap(unsigned long grs[3]) +{ + asm volatile( + " lgr 0,%[r0]\n" + " lgr 1,%[r1]\n" + " lgr 2,%[r2]\n" + " .insn rre,0xb2af0000,0,0\n" /* PQAP */ + :: [r0] "d" (grs[0]), [r1] "d" (grs[1]), [r2] "d" (grs[2]) + : "cc", "memory", "0", "1", "2"); +} + +static void test_pgms_pqap(void) +{ + unsigned long grs[3] = {}; + struct pqap_r0 *r0 = (struct pqap_r0 *)grs; + uint8_t *data = alloc_page(); + uint16_t pgm; + int fails = 0; + int i; + + report_prefix_push("pqap"); + + /* Wrong FC code */ + report_prefix_push("invalid fc"); + r0->fc = 42; + expect_pgm_int(); + pqap(grs); + check_pgm_int_code(PGM_INT_CODE_SPECIFICATION); + memset(grs, 0, sizeof(grs)); + report_prefix_pop(); + + report_prefix_push("invalid gr0 bits"); + /* + * GR0 bits 41 - 47 are defined 0 and result in a + * specification exception if set to 1. + */ + for (i = 0; i < 48 - 41; i++) { + grs[0] = BIT(63 - 47 + i); + + expect_pgm_int(); + pqap(grs); + pgm = clear_pgm_int(); + + if (pgm != PGM_INT_CODE_SPECIFICATION) { + report_fail("fail on bit %d", 42 + i); + fails++; + } + } + report(!fails, "All bits tested"); + memset(grs, 0, sizeof(grs)); + fails = 0; + report_prefix_pop(); + + report_prefix_push("alignment"); + report_prefix_push("fc=4"); + r0->fc = PQAP_QUERY_AP_CONF_INFO; + grs[2] = (unsigned long)data; + for (i = 1; i < 8; i++) { + expect_pgm_int(); + grs[2]++; + pqap(grs); + pgm = clear_pgm_int(); + if (pgm != PGM_INT_CODE_SPECIFICATION) { + report_fail("fail on bit %d", i); + fails++; + } + } + report(!fails, "All alignments tested"); + report_prefix_pop(); + report_prefix_push("fc=6"); + r0->fc = PQAP_BEST_AP; + grs[2] = (unsigned long)data; + for (i = 1; i < 8; i++) { + expect_pgm_int(); + grs[2]++; + pqap(grs); + pgm = clear_pgm_int(); + if (pgm != PGM_INT_CODE_SPECIFICATION) { + report_fail("fail on bit %d", i); + fails++; + } + } + report(!fails, "All alignments tested"); + report_prefix_pop(); + report_prefix_pop(); + + free_page(data); + report_prefix_pop(); +} + +static void test_pgms_nqap(void) +{ + uint8_t gr0_zeroes_bits[] = { + 32, 34, 35, 40 + }; + uint64_t gr0; + bool fail; + int i; + + report_prefix_push("nqap"); + + /* Registers 0 and 1 are always used, the others are even/odd pairs */ + report_prefix_push("spec"); + report_prefix_push("r1"); + expect_pgm_int(); + asm volatile ( + ".insn rre,0xb2ad0000,3,6\n" + : : : "cc", "memory", "0", "1", "2", "3", "4", "6", "7"); + check_pgm_int_code(PGM_INT_CODE_SPECIFICATION); + report_prefix_pop(); + + report_prefix_push("r2"); + expect_pgm_int(); + asm volatile ( + ".insn rre,0xb2ad0000,2,7\n" + : : : "cc", "memory", "0", "1", "2", "3", "4", "6", "7"); + check_pgm_int_code(PGM_INT_CODE_SPECIFICATION); + report_prefix_pop(); + + report_prefix_push("both"); + expect_pgm_int(); + asm volatile ( + ".insn rre,0xb2ad0000,3,7\n" + : : : "cc", "memory", "0", "1", "2", "3", "4", "6", "7"); + check_pgm_int_code(PGM_INT_CODE_SPECIFICATION); + report_prefix_pop(); + + report_prefix_push("len==0"); + expect_pgm_int(); + asm volatile ( + "xgr 0,0\n" + "xgr 5,5\n" + ".insn rre,0xb2ad0000,2,4\n" + : : : "cc", "memory", "0", "1", "2", "3", "4", "5", "6", "7"); + check_pgm_int_code(PGM_INT_CODE_SPECIFICATION); + report_prefix_pop(); + + report_prefix_push("gr0_zero_bits"); + fail = false; + for (i = 0; i < ARRAY_SIZE(gr0_zeroes_bits); i++) { + expect_pgm_int(); + gr0 = BIT_ULL(63 - gr0_zeroes_bits[i]); + asm volatile ( + "xgr 5,5\n" + "lghi 5, 128\n" + "lg 0, 0(%[val])\n" + ".insn rre,0xb2ad0000,2,4\n" + : : [val] "a" (&gr0) + : "cc", "memory", "0", "1", "2", "3", "4", "5", "6", "7"); + if (clear_pgm_int() != PGM_INT_CODE_SPECIFICATION) { + report_fail("setting gr0 bit %d did not result in a spec exception", + gr0_zeroes_bits[i]); + fail = true; + } + } + report(!fail, "set bit gr0 pgms"); + report_prefix_pop(); + + report_prefix_pop(); + report_prefix_pop(); +} + +static void test_pgms_dqap(void) +{ + uint8_t gr0_zeroes_bits[] = { + 33, 34, 35, 40, 41 + }; + uint64_t gr0; + bool fail; + int i; + + report_prefix_push("dqap"); + + /* Registers 0 and 1 are always used, the others are even/odd pairs */ + report_prefix_push("spec"); + report_prefix_push("r1"); + expect_pgm_int(); + asm volatile ( + ".insn rre,0xb2ae0000,3,6\n" + : : : "cc", "memory", "0", "1", "2", "3", "4", "6", "7"); + check_pgm_int_code(PGM_INT_CODE_SPECIFICATION); + report_prefix_pop(); + + report_prefix_push("r2"); + expect_pgm_int(); + asm volatile ( + ".insn rre,0xb2ae0000,2,7\n" + : : : "cc", "memory", "0", "1", "2", "3", "4", "6", "7"); + check_pgm_int_code(PGM_INT_CODE_SPECIFICATION); + report_prefix_pop(); + + report_prefix_push("both"); + expect_pgm_int(); + asm volatile ( + ".insn rre,0xb2ae0000,3,7\n" + : : : "cc", "memory", "0", "1", "2", "3", "4", "6", "7"); + check_pgm_int_code(PGM_INT_CODE_SPECIFICATION); + report_prefix_pop(); + + report_prefix_push("len==0"); + expect_pgm_int(); + asm volatile ( + "xgr 0,0\n" + "xgr 5,5\n" + ".insn rre,0xb2ae0000,2,4\n" + : : : "cc", "memory", "0", "1", "2", "3", "4", "5", "6", "7"); + check_pgm_int_code(PGM_INT_CODE_SPECIFICATION); + report_prefix_pop(); + + report_prefix_push("gr0_zero_bits"); + fail = false; + for (i = 0; i < ARRAY_SIZE(gr0_zeroes_bits); i++) { + expect_pgm_int(); + gr0 = BIT_ULL(63 - gr0_zeroes_bits[i]); + asm volatile ( + "xgr 5,5\n" + "lghi 5, 128\n" + "lg 0, 0(%[val])\n" + ".insn rre,0xb2ae0000,2,4\n" + : : [val] "a" (&gr0) + : "cc", "memory", "0", "1", "2", "3", "4", "5", "6", "7"); + if (clear_pgm_int() != PGM_INT_CODE_SPECIFICATION) { + report_info("setting gr0 bit %d did not result in a spec exception", + gr0_zeroes_bits[i]); + fail = true; + } + } + report(!fail, "set bit pgms"); + report_prefix_pop(); + + report_prefix_pop(); + report_prefix_pop(); +} + +static void test_priv(void) +{ + struct ap_config_info info = {}; + + report_prefix_push("privileged"); + + report_prefix_push("pqap"); + expect_pgm_int(); + enter_pstate(); + ap_pqap_qci(&info); + check_pgm_int_code(PGM_INT_CODE_PRIVILEGED_OPERATION); + report_prefix_pop(); + + /* + * Enqueue and dequeue take too many registers so a simple + * inline assembly makes more sense than using the library + * functions. + */ + report_prefix_push("nqap"); + expect_pgm_int(); + enter_pstate(); + asm volatile ( + ".insn rre,0xb2ad0000,0,2\n" + : : : "cc", "memory", "0", "1", "2", "3"); + check_pgm_int_code(PGM_INT_CODE_PRIVILEGED_OPERATION); + report_prefix_pop(); + + report_prefix_push("dqap"); + expect_pgm_int(); + enter_pstate(); + asm volatile ( + ".insn rre,0xb2ae0000,0,2\n" + : : : "cc", "memory", "0", "1", "2", "3"); + check_pgm_int_code(PGM_INT_CODE_PRIVILEGED_OPERATION); + report_prefix_pop(); + + report_prefix_pop(); +} + +int main(void) +{ + report_prefix_push("ap"); + if (!ap_check()) { + report_skip("AP instructions not available"); + goto done; + } + + test_priv(); + test_pgms_pqap(); + test_pgms_nqap(); + test_pgms_dqap(); + +done: + report_prefix_pop(); + return report_summary(); +} diff --git a/s390x/unittests.cfg b/s390x/unittests.cfg index f5024b6e..a2d6b197 100644 --- a/s390x/unittests.cfg +++ b/s390x/unittests.cfg @@ -383,3 +383,6 @@ extra_params = """-cpu max,ctop=on -smp cpus=1,drawers=2,books=2,sockets=2,cores [sie-dat] file = sie-dat.elf + +[ap] +file = ap.elf From patchwork Fri Nov 17 15:19:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Janosch Frank X-Patchwork-Id: 13459032 Authentication-Results: smtp.subspace.kernel.org; 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(unknown [9.152.108.100]) by smtpav03.fra02v.mail.ibm.com (Postfix) with ESMTP; Fri, 17 Nov 2023 15:19:55 +0000 (GMT) From: Janosch Frank To: kvm@vger.kernel.org Cc: linux-s390@vger.kernel.org, imbrenda@linux.ibm.com, thuth@redhat.com, david@redhat.com, nsg@linux.ibm.com, nrb@linux.ibm.com Subject: [kvm-unit-tests PATCH v3 3/7] lib: s390x: ap: Add proper ap setup code Date: Fri, 17 Nov 2023 15:19:35 +0000 Message-Id: <20231117151939.971079-4-frankja@linux.ibm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231117151939.971079-1-frankja@linux.ibm.com> References: <20231117151939.971079-1-frankja@linux.ibm.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: VvI-LHRcSaP2fCw8E736VPksoOT4y7ra X-Proofpoint-GUID: wiRzuTOHUv7XtvkwColG1__ki9ofh8eN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-17_14,2023-11-17_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 bulkscore=0 suspectscore=0 malwarescore=0 mlxlogscore=999 phishscore=0 mlxscore=0 impostorscore=0 priorityscore=1501 adultscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311170114 For the next tests we need a valid queue which means we need to grab the qci info and search the first set bit in the ap and aq masks. Let's move from the stfle 12 check to proper setup code that also returns arrays for the aps and qns. Signed-off-by: Janosch Frank --- lib/s390x/ap.c | 90 +++++++++++++++++++++++++++++++++++++++++++++++--- lib/s390x/ap.h | 17 +++++++++- s390x/ap.c | 4 ++- 3 files changed, 105 insertions(+), 6 deletions(-) diff --git a/lib/s390x/ap.c b/lib/s390x/ap.c index 17a32d66..9ba5a037 100644 --- a/lib/s390x/ap.c +++ b/lib/s390x/ap.c @@ -13,10 +13,18 @@ #include #include +#include +#include #include #include #include +static uint8_t num_ap; +static uint8_t num_queue; +static uint8_t *array_ap; +static uint8_t *array_queue; +static struct ap_config_info qci; + int ap_pqap_tapq(uint8_t ap, uint8_t qn, struct ap_queue_status *apqsw, struct pqap_r2 *r2) { @@ -78,16 +86,90 @@ int ap_pqap_qci(struct ap_config_info *info) return cc; } -/* Will later be extended to a proper setup function */ -bool ap_setup(void) +static int get_entry(uint8_t *ptr, int i, size_t len) { + /* Skip over the last entry */ + if (i) + i++; + + for (; i < 8 * len; i++) { + /* Do we even need to check the byte? */ + if (!ptr[i / 8]) { + i += 7; + continue; + } + + /* Check the bit in big-endian order */ + if (ptr[i / 8] & BIT(7 - (i % 8))) + return i; + } + return -1; +} + +static void setup_info(void) +{ + int i, entry = 0; + + ap_pqap_qci(&qci); + + for (i = 0; i < AP_ARRAY_MAX_NUM; i++) { + entry = get_entry((uint8_t *)qci.apm, entry, sizeof(qci.apm)); + if (entry == -1) + break; + + if (!num_ap) { + /* + * We have at least one AP, time to + * allocate the queue arrays + */ + array_ap = malloc(AP_ARRAY_MAX_NUM); + array_queue = malloc(AP_ARRAY_MAX_NUM); + } + array_ap[num_ap] = entry; + num_ap += 1; + } + + /* Without an AP we don't even need to look at the queues */ + if (!num_ap) + return; + + entry = 0; + for (i = 0; i < AP_ARRAY_MAX_NUM; i++) { + entry = get_entry((uint8_t *)qci.aqm, entry, sizeof(qci.aqm)); + if (entry == -1) + return; + + array_queue[num_queue] = entry; + num_queue += 1; + } + +} + +int ap_setup(uint8_t **ap_array, uint8_t **qn_array, uint8_t *naps, uint8_t *nqns) +{ + assert(!num_ap); + /* * Base AP support has no STFLE or SCLP feature bit but the * PQAP QCI support is indicated via stfle bit 12. As this * library relies on QCI we bail out if it's not available. */ if (!test_facility(12)) - return false; + return AP_SETUP_NOINSTR; - return true; + /* Setup ap and queue arrays */ + setup_info(); + + if (!num_ap) + return AP_SETUP_NOAPQN; + + /* Only provide the data if the caller actually needs it. */ + if (ap_array && qn_array && naps && nqns) { + *ap_array = array_ap; + *qn_array = array_queue; + *naps = num_ap; + *nqns = num_queue; + } + + return AP_SETUP_READY; } diff --git a/lib/s390x/ap.h b/lib/s390x/ap.h index cda1e564..ac9e59d1 100644 --- a/lib/s390x/ap.h +++ b/lib/s390x/ap.h @@ -81,7 +81,22 @@ struct pqap_r2 { } __attribute__((packed)) __attribute__((aligned(8))); _Static_assert(sizeof(struct pqap_r2) == sizeof(uint64_t), "pqap_r2 size"); -bool ap_setup(void); +/* + * Maximum number of APQNs that we keep track of. + * + * This value is already way larger than the number of APQNs a AP test + * is probably going to use. + */ +#define AP_ARRAY_MAX_NUM 16 + +/* Return values of ap_setup() */ +enum { + AP_SETUP_NOINSTR, /* AP instructions not available */ + AP_SETUP_NOAPQN, /* Instructions available but no APQNs */ + AP_SETUP_READY /* Full setup complete, at least one APQN */ +}; + +int ap_setup(uint8_t **ap_array, uint8_t **qn_array, uint8_t *naps, uint8_t *nqns); int ap_pqap_tapq(uint8_t ap, uint8_t qn, struct ap_queue_status *apqsw, struct pqap_r2 *r2); int ap_pqap_qci(struct ap_config_info *info); diff --git a/s390x/ap.c b/s390x/ap.c index 94f08783..32feb8db 100644 --- a/s390x/ap.c +++ b/s390x/ap.c @@ -292,8 +292,10 @@ static void test_priv(void) int main(void) { + int setup_rc = ap_setup(NULL, NULL, NULL, NULL); + report_prefix_push("ap"); - if (!ap_check()) { + if (setup_rc == AP_SETUP_NOINSTR) { report_skip("AP instructions not available"); goto done; } From patchwork Fri Nov 17 15:19:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Janosch Frank X-Patchwork-Id: 13459037 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ibm.com header.i=@ibm.com header.b="qhelr6R1" Received: from mx0b-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7D2E1D5E; Fri, 17 Nov 2023 07:20:01 -0800 (PST) Received: from pps.filterd (m0353724.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3AHFHJwF032182; Fri, 17 Nov 2023 15:20:00 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pp1; bh=qBF6zsmyaj5I0L80762pP709SBEX0yQJZrP31rNAlso=; b=qhelr6R1w8m+8p3UXmOpnzYFkLnYZ+bskhaPcMMaVlQTtDC1eNLf+qgktGo7EVM+4Dkv GVoRCo82ROQIXzU5k6g4ygTT2uE+PIzEhDv9jSoFoig8xn+ykqFU4NLacaXY+4DVqfj0 M5Mjy7lp4IVlZdYGCw7nl/dJOYHHQ3J6ezXHIU22y2UyGYEhhobZAcEN3vUiYBB8HTUE fEW+Ok6mQJIwP6UBikZIvysCAWylalqcqceK5Qzl+5gduSwPVkFWm0N5QczM25ym65no 03BD9MmL0YmOkU7xAq27YHsGgkzI4X+YP6oifnjU22RTHrbfDY0XGNFCE49FIdnEpmzr 0g== Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3ueap8r2m5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 17 Nov 2023 15:20:00 +0000 Received: from m0353724.ppops.net (m0353724.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 3AHFJa6u007384; Fri, 17 Nov 2023 15:19:59 GMT Received: from ppma23.wdc07v.mail.ibm.com (5d.69.3da9.ip4.static.sl-reverse.com [169.61.105.93]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3ueap8r2ka-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 17 Nov 2023 15:19:59 +0000 Received: from pps.filterd (ppma23.wdc07v.mail.ibm.com [127.0.0.1]) by ppma23.wdc07v.mail.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id 3AHD41HQ015851; Fri, 17 Nov 2023 15:19:59 GMT Received: from smtprelay01.fra02v.mail.ibm.com ([9.218.2.227]) by ppma23.wdc07v.mail.ibm.com (PPS) with ESMTPS id 3uanem6q3f-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 17 Nov 2023 15:19:59 +0000 Received: from smtpav03.fra02v.mail.ibm.com (smtpav03.fra02v.mail.ibm.com [10.20.54.102]) by smtprelay01.fra02v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 3AHFJua065995164 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 17 Nov 2023 15:19:56 GMT Received: from smtpav03.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 1BD6E2004B; Fri, 17 Nov 2023 15:19:56 +0000 (GMT) Received: from smtpav03.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D096D20040; Fri, 17 Nov 2023 15:19:55 +0000 (GMT) Received: from a46lp67.. (unknown [9.152.108.100]) by smtpav03.fra02v.mail.ibm.com (Postfix) with ESMTP; Fri, 17 Nov 2023 15:19:55 +0000 (GMT) From: Janosch Frank To: kvm@vger.kernel.org Cc: linux-s390@vger.kernel.org, imbrenda@linux.ibm.com, thuth@redhat.com, david@redhat.com, nsg@linux.ibm.com, nrb@linux.ibm.com Subject: [kvm-unit-tests PATCH v3 4/7] s390x: ap: Add pqap aqic tests Date: Fri, 17 Nov 2023 15:19:36 +0000 Message-Id: <20231117151939.971079-5-frankja@linux.ibm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231117151939.971079-1-frankja@linux.ibm.com> References: <20231117151939.971079-1-frankja@linux.ibm.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: 5sOK0mheNR9_fK1qyuvGFPUIOeHFoq-0 X-Proofpoint-ORIG-GUID: fcRYG3vLFzPJ1CE7-1oW2mju570LRgFb X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-17_14,2023-11-17_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 lowpriorityscore=0 bulkscore=0 impostorscore=0 priorityscore=1501 adultscore=0 mlxscore=0 mlxlogscore=999 malwarescore=0 clxscore=1015 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311170114 Let's check if we can enable/disable interrupts and if all errors are reported if we specify bad addresses for the notification indication byte. Signed-off-by: Janosch Frank --- lib/s390x/ap.c | 33 ++++++++++++++++++++++ lib/s390x/ap.h | 11 ++++++++ s390x/ap.c | 75 +++++++++++++++++++++++++++++++++++++++++++++++++- 3 files changed, 118 insertions(+), 1 deletion(-) diff --git a/lib/s390x/ap.c b/lib/s390x/ap.c index 9ba5a037..23338c2d 100644 --- a/lib/s390x/ap.c +++ b/lib/s390x/ap.c @@ -58,6 +58,39 @@ int ap_pqap_tapq(uint8_t ap, uint8_t qn, struct ap_queue_status *apqsw, return cc; } +int ap_pqap_aqic(uint8_t ap, uint8_t qn, struct ap_queue_status *apqsw, + struct ap_qirq_ctrl aqic, unsigned long addr) +{ + struct pqap_r0 r0 = {}; + int cc; + + /* + * AP-Queue Interruption Control + * + * Enables/disables interrupts for a APQN + * + * Inputs: 0,1,2 + * Outputs: 1 (APQSW) + * Synchronous + */ + r0.ap = ap; + r0.qn = qn; + r0.fc = PQAP_QUEUE_INT_CONTRL; + asm volatile( + " lgr 0,%[r0]\n" + " lgr 1,%[aqic]\n" + " lgr 2,%[addr]\n" + " .insn rre,0xb2af0000,0,0\n" /* PQAP */ + " stg 1, %[apqsw]\n" + " ipm %[cc]\n" + " srl %[cc],28\n" + : [apqsw] "=&T" (*apqsw), [cc] "=&d" (cc) + : [r0] "d" (r0), [aqic] "d" (aqic), [addr] "d" (addr) + : "cc", "memory", "0", "2"); + + return cc; +} + int ap_pqap_qci(struct ap_config_info *info) { struct pqap_r0 r0 = { .fc = PQAP_QUERY_AP_CONF_INFO }; diff --git a/lib/s390x/ap.h b/lib/s390x/ap.h index ac9e59d1..7a91881d 100644 --- a/lib/s390x/ap.h +++ b/lib/s390x/ap.h @@ -81,6 +81,15 @@ struct pqap_r2 { } __attribute__((packed)) __attribute__((aligned(8))); _Static_assert(sizeof(struct pqap_r2) == sizeof(uint64_t), "pqap_r2 size"); +struct ap_qirq_ctrl { + uint64_t res0 : 16; + uint64_t ir : 1; /* ir flag: enable (1) or disable (0) irq */ + uint64_t res1 : 44; + uint64_t isc : 3; /* irq sub class */ +} __attribute__((packed)) __attribute__((aligned(8))); +_Static_assert(sizeof(struct ap_qirq_ctrl) == sizeof(uint64_t), + "struct ap_qirq_ctrl size"); + /* * Maximum number of APQNs that we keep track of. * @@ -100,4 +109,6 @@ int ap_setup(uint8_t **ap_array, uint8_t **qn_array, uint8_t *naps, uint8_t *nqn int ap_pqap_tapq(uint8_t ap, uint8_t qn, struct ap_queue_status *apqsw, struct pqap_r2 *r2); int ap_pqap_qci(struct ap_config_info *info); +int ap_pqap_aqic(uint8_t ap, uint8_t qn, struct ap_queue_status *apqsw, + struct ap_qirq_ctrl aqic, unsigned long addr); #endif diff --git a/s390x/ap.c b/s390x/ap.c index 32feb8db..8ea2b52e 100644 --- a/s390x/ap.c +++ b/s390x/ap.c @@ -12,10 +12,15 @@ #include #include #include +#include +#include #include #include #include +static uint8_t apn; +static uint8_t qn; + /* For PQAP PGM checks where we need full control over the input */ static void pqap(unsigned long grs[3]) { @@ -290,9 +295,63 @@ static void test_priv(void) report_prefix_pop(); } +static void test_pqap_aqic(void) +{ + uint8_t *not_ind_byte = alloc_io_mem(PAGE_SIZE, 0); + struct ap_queue_status apqsw = {}; + struct ap_qirq_ctrl aqic = {}; + struct pqap_r2 r2 = {}; + int cc; + + report_prefix_push("aqic"); + *not_ind_byte = 0; + + aqic.ir = 1; + cc = ap_pqap_aqic(apn, qn, &apqsw, aqic, 0); + report(cc == 3 && apqsw.rc == 6, "invalid addr 0"); + + aqic.ir = 1; + cc = ap_pqap_aqic(apn, qn, &apqsw, aqic, -1); + report(cc == 3 && apqsw.rc == 6, "invalid addr -1"); + + aqic.ir = 0; + cc = ap_pqap_aqic(apn, qn, &apqsw, aqic, (uintptr_t)not_ind_byte); + report(cc == 3 && apqsw.rc == 7, "disable IRQs while already disabled"); + + aqic.ir = 1; + cc = ap_pqap_aqic(apn, qn, &apqsw, aqic, (uintptr_t)not_ind_byte); + report(cc == 0 && apqsw.rc == 0, "enable IRQs"); + + do { + mdelay(20); + cc = ap_pqap_tapq(apn, qn, &apqsw, &r2); + } while (cc == 0 && apqsw.irq_enabled == 0); + report(cc == 0 && apqsw.irq_enabled == 1, "enable IRQs tapq data"); + + cc = ap_pqap_aqic(apn, qn, &apqsw, aqic, (uintptr_t)not_ind_byte); + report(cc == 3 && apqsw.rc == 7, "enable IRQs while already enabled"); + + aqic.ir = 0; + cc = ap_pqap_aqic(apn, qn, &apqsw, aqic, (uintptr_t)not_ind_byte); + report(cc == 0 && apqsw.rc == 0, "disable IRQs"); + + do { + mdelay(20); + cc = ap_pqap_tapq(apn, qn, &apqsw, &r2); + } while (cc == 0 && apqsw.irq_enabled == 1); + report(cc == 0 && apqsw.irq_enabled == 0, "disable IRQs tapq data"); + + report_prefix_pop(); + + free_io_mem(not_ind_byte, PAGE_SIZE); +} + int main(void) { - int setup_rc = ap_setup(NULL, NULL, NULL, NULL); + uint8_t num_ap, num_qn; + uint8_t *apns; + uint8_t *qns; + int setup_rc = ap_setup(&apns, &qns, &num_ap, &num_qn); report_prefix_push("ap"); if (setup_rc == AP_SETUP_NOINSTR) { @@ -305,6 +364,20 @@ int main(void) test_pgms_nqap(); test_pgms_dqap(); + /* The next tests need queues */ + if (setup_rc == AP_SETUP_NOAPQN) { + report_skip("No APQN available"); + goto done; + } + apn = apns[0]; + qn = qns[0]; + report_prefix_push("pqap"); + if (test_facility(65)) + test_pqap_aqic(); + else + report_skip("no AQIC and reset tests without IRQ support"); + report_prefix_pop(); + done: report_prefix_pop(); return report_summary(); From patchwork Fri Nov 17 15:19:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Janosch Frank X-Patchwork-Id: 13459038 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ibm.com header.i=@ibm.com header.b="NuJVq5oc" Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 16407D5F; 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(unknown [9.152.108.100]) by smtpav03.fra02v.mail.ibm.com (Postfix) with ESMTP; Fri, 17 Nov 2023 15:19:56 +0000 (GMT) From: Janosch Frank To: kvm@vger.kernel.org Cc: linux-s390@vger.kernel.org, imbrenda@linux.ibm.com, thuth@redhat.com, david@redhat.com, nsg@linux.ibm.com, nrb@linux.ibm.com Subject: [kvm-unit-tests PATCH v3 5/7] s390x: ap: Add reset tests Date: Fri, 17 Nov 2023 15:19:37 +0000 Message-Id: <20231117151939.971079-6-frankja@linux.ibm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231117151939.971079-1-frankja@linux.ibm.com> References: <20231117151939.971079-1-frankja@linux.ibm.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: sq5NOB5Vf1V8MIPycKz-N2WWeE-9Lx23 X-Proofpoint-GUID: ISZj7PeS0EHMa2ibFsDx5k57MoXrqZ84 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-17_14,2023-11-17_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 bulkscore=0 suspectscore=0 malwarescore=0 mlxlogscore=999 phishscore=0 mlxscore=0 impostorscore=0 priorityscore=1501 adultscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311170114 Test if the IRQ enablement is turned off on a reset or zeroize PQAP. Signed-off-by: Janosch Frank --- lib/s390x/ap.c | 69 ++++++++++++++++++++++++++++++++++++++++++ lib/s390x/ap.h | 4 +++ s390x/ap.c | 81 ++++++++++++++++++++++++++++++++++++++++++++++++-- 3 files changed, 152 insertions(+), 2 deletions(-) diff --git a/lib/s390x/ap.c b/lib/s390x/ap.c index 23338c2d..c1acfda8 100644 --- a/lib/s390x/ap.c +++ b/lib/s390x/ap.c @@ -119,6 +119,75 @@ int ap_pqap_qci(struct ap_config_info *info) return cc; } +static int pqap_reset(uint8_t ap, uint8_t qn, struct ap_queue_status *apqsw, + bool zeroize) +{ + struct pqap_r0 r0 = {}; + int cc; + + /* + * Reset/zeroize AP Queue + * + * Resets/zeroizes a queue and disables IRQs + * + * Inputs: GR0 + * Outputs: GR1 (APQSW) + * Asynchronous + */ + r0.ap = ap; + r0.qn = qn; + r0.fc = zeroize ? PQAP_ZEROIZE_APQ : PQAP_RESET_APQ; + asm volatile( + " lgr 0,%[r0]\n" + " .insn rre,0xb2af0000,0,0\n" /* PQAP */ + " stg 1, %[apqsw]\n" + " ipm %[cc]\n" + " srl %[cc],28\n" + : [apqsw] "=&T" (*apqsw), [cc] "=&d" (cc) + : [r0] "d" (r0) + : "memory"); + + return cc; +} + +static int pqap_reset_wait(uint8_t ap, uint8_t qn, struct ap_queue_status *apqsw, + bool zeroize) +{ + struct pqap_r2 r2 = {}; + int cc; + + cc = pqap_reset(ap, qn, apqsw, zeroize); + + /* On a cc == 3 / error we don't need to wait */ + if (cc) + return cc; + + /* + * TAPQ returns AP_RC_RESET_IN_PROGRESS if a reset is being + * processed + */ + do { + /* Give it some time to process before the retry */ + mdelay(20); + cc = ap_pqap_tapq(ap, qn, apqsw, &r2); + } while (apqsw->rc == AP_RC_RESET_IN_PROGRESS); + + if (apqsw->rc) + printf("Wait for reset failed on ap %d queue %d with tapq rc %d.", + ap, qn, apqsw->rc); + return cc; +} + +int ap_pqap_reset(uint8_t ap, uint8_t qn, struct ap_queue_status *apqsw) +{ + return pqap_reset_wait(ap, qn, apqsw, false); +} + +int ap_pqap_reset_zeroize(uint8_t ap, uint8_t qn, struct ap_queue_status *apqsw) +{ + return pqap_reset_wait(ap, qn, apqsw, true); +} + static int get_entry(uint8_t *ptr, int i, size_t len) { /* Skip over the last entry */ diff --git a/lib/s390x/ap.h b/lib/s390x/ap.h index 7a91881d..e037a974 100644 --- a/lib/s390x/ap.h +++ b/lib/s390x/ap.h @@ -14,6 +14,8 @@ #ifndef _S390X_AP_H_ #define _S390X_AP_H_ +#define AP_RC_RESET_IN_PROGRESS 0x02 + enum PQAP_FC { PQAP_TEST_APQ, PQAP_RESET_APQ, @@ -108,6 +110,8 @@ enum { int ap_setup(uint8_t **ap_array, uint8_t **qn_array, uint8_t *naps, uint8_t *nqns); int ap_pqap_tapq(uint8_t ap, uint8_t qn, struct ap_queue_status *apqsw, struct pqap_r2 *r2); +int ap_pqap_reset(uint8_t ap, uint8_t qn, struct ap_queue_status *apqsw); +int ap_pqap_reset_zeroize(uint8_t ap, uint8_t qn, struct ap_queue_status *apqsw); int ap_pqap_qci(struct ap_config_info *info); int ap_pqap_aqic(uint8_t ap, uint8_t qn, struct ap_queue_status *apqsw, struct ap_qirq_ctrl aqic, unsigned long addr); diff --git a/s390x/ap.c b/s390x/ap.c index 8ea2b52e..0ae2809e 100644 --- a/s390x/ap.c +++ b/s390x/ap.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -346,6 +347,80 @@ static void test_pqap_aqic(void) free_io_mem(not_ind_byte, PAGE_SIZE); } +static void test_pqap_resets(void) +{ + uint8_t *not_ind_byte = alloc_io_mem(sizeof(*not_ind_byte), 0); + struct ap_queue_status apqsw = {}; + struct ap_qirq_ctrl aqic = {}; + struct pqap_r2 r2 = {}; + + int cc; + + report_prefix_push("rapq"); + + /* Enable IRQs which the resets will disable */ + aqic.ir = 1; + cc = ap_pqap_aqic(apn, qn, &apqsw, aqic, (uintptr_t)not_ind_byte); + report(cc == 0 && apqsw.rc == 0, "enable IRQs for reset tests"); + + do { + mdelay(20); + cc = ap_pqap_tapq(apn, qn, &apqsw, &r2); + } while (cc == 0 && apqsw.irq_enabled == 0); + report(apqsw.irq_enabled == 1, "IRQs enabled tapq data"); + + ap_pqap_reset(apn, qn, &apqsw); + cc = ap_pqap_tapq(apn, qn, &apqsw, &r2); + assert(!cc); + report(apqsw.irq_enabled == 0, "IRQs have been disabled via reset"); + + report_prefix_pop(); + + report_prefix_push("zapq"); + + /* Enable IRQs which the resets will disable */ + aqic.ir = 1; + cc = ap_pqap_aqic(apn, qn, &apqsw, aqic, (uintptr_t)not_ind_byte); + report(cc == 0 && apqsw.rc == 0, "enable IRQs for reset tests"); + + do { + mdelay(20); + cc = ap_pqap_tapq(apn, qn, &apqsw, &r2); + } while (cc == 0 && apqsw.irq_enabled == 0); + report(apqsw.irq_enabled == 1, "IRQs enabled tapq data"); + + ap_pqap_reset_zeroize(apn, qn, &apqsw); + cc = ap_pqap_tapq(apn, qn, &apqsw, &r2); + assert(!cc); + report(apqsw.irq_enabled == 0, "IRQs have been disabled via reset"); + + report_prefix_pop(); + /* + * This is a wrinkle in the architecture for PV guests. + * + * The notification byte is pinned shared for PV guests. + * RAPQ, ZAPQ and AQIC can all disable IRQs but there's no + * intercept for resets triggered by a PV guests. Hence the + * host keeps the notification byte page pinned UNTIL IRQs are + * disabled via AQIC. + * + * Firmware will not generate an intercept if the IRQs have + * already been disabled via a reset. Therefore we need to + * enable AND disable to achieve a disable. + */ + if (uv_os_is_guest()) { + aqic.ir = 1; + cc = ap_pqap_aqic(apn, qn, &apqsw, aqic, + (uintptr_t)not_ind_byte); + assert(cc == 0 && apqsw.rc == 0); + aqic.ir = 0; + cc = ap_pqap_aqic(apn, qn, &apqsw, aqic, + (uintptr_t)not_ind_byte); + assert(cc == 0 && apqsw.rc == 0); + } + free_io_mem(not_ind_byte, sizeof(*not_ind_byte)); +} + int main(void) { uint8_t num_ap, num_qn; @@ -372,10 +447,12 @@ int main(void) apn = apns[0]; qn = qns[0]; report_prefix_push("pqap"); - if (test_facility(65)) + if (test_facility(65)) { test_pqap_aqic(); - else + test_pqap_resets(); + } else { report_skip("no AQIC and reset tests without IRQ support"); + } report_prefix_pop(); done: From patchwork Fri Nov 17 15:19:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Janosch Frank X-Patchwork-Id: 13459036 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ibm.com header.i=@ibm.com header.b="fM9nXUPJ" Received: from mx0b-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 25467D56; Fri, 17 Nov 2023 07:20:03 -0800 (PST) Received: from pps.filterd (m0353722.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3AHFGAMo031822; Fri, 17 Nov 2023 15:20:02 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pp1; bh=LdSTOCRF/Y2mm7f4UJzdgFcO5CKZJDr3FoCQzhucFNA=; b=fM9nXUPJIydB2jEB4W11clbjyMPmPTIBUhjdzEqt6Ym9ntZ740HKamk7Mgpk6MMibNKE yE7TI+2UOXboQOGd9MEa+nNFoD3Je94RhTCLHV82XpUAUvnGaxql7S9b2KEvdowwM6Wt PODUBIf1Rerze2aigHfAC7KM+zHeUBBUtyMr2N06cKUTAqaL6DbBK4xWLVws+TvMUyue Gsjyb+WXjzVFewnR2TmCZ04eJy4HZiV9v7CSE2r32BDiFVX/uhpj8rRk0fwTHy0KWa1f 1zV28yYD1jIGzUOmpTiqkU6cDEdQqvOoXvMTASU07MuMzIVbquiyuO8BNChAhjOmdpwF XA== Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3ueanvg41g-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 17 Nov 2023 15:20:00 +0000 Received: from m0353722.ppops.net (m0353722.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 3AHFGKHl000321; Fri, 17 Nov 2023 15:20:00 GMT Received: from ppma12.dal12v.mail.ibm.com (dc.9e.1632.ip4.static.sl-reverse.com [50.22.158.220]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3ueanvg40p-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 17 Nov 2023 15:20:00 +0000 Received: from pps.filterd (ppma12.dal12v.mail.ibm.com [127.0.0.1]) by ppma12.dal12v.mail.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id 3AHD3wkc005145; Fri, 17 Nov 2023 15:19:59 GMT Received: from smtprelay01.fra02v.mail.ibm.com ([9.218.2.227]) by ppma12.dal12v.mail.ibm.com (PPS) with ESMTPS id 3uakxtf7vg-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 17 Nov 2023 15:19:59 +0000 Received: from smtpav03.fra02v.mail.ibm.com (smtpav03.fra02v.mail.ibm.com [10.20.54.102]) by smtprelay01.fra02v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 3AHFJu8T51446046 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 17 Nov 2023 15:19:56 GMT Received: from smtpav03.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B1AF420040; Fri, 17 Nov 2023 15:19:56 +0000 (GMT) Received: from smtpav03.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 7264A20043; Fri, 17 Nov 2023 15:19:56 +0000 (GMT) Received: from a46lp67.. (unknown [9.152.108.100]) by smtpav03.fra02v.mail.ibm.com (Postfix) with ESMTP; Fri, 17 Nov 2023 15:19:56 +0000 (GMT) From: Janosch Frank To: kvm@vger.kernel.org Cc: linux-s390@vger.kernel.org, imbrenda@linux.ibm.com, thuth@redhat.com, david@redhat.com, nsg@linux.ibm.com, nrb@linux.ibm.com Subject: [kvm-unit-tests PATCH v3 6/7] lib: s390x: ap: Add tapq test facility bit Date: Fri, 17 Nov 2023 15:19:38 +0000 Message-Id: <20231117151939.971079-7-frankja@linux.ibm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231117151939.971079-1-frankja@linux.ibm.com> References: <20231117151939.971079-1-frankja@linux.ibm.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: bkKkS7ay5LcPMSm8MSfGzLjpTdhiW7nw X-Proofpoint-GUID: 5UeLMQdZCDScPY_bxImV3pk7Qx1aXuDz X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-17_14,2023-11-17_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 mlxscore=0 phishscore=0 spamscore=0 mlxlogscore=999 lowpriorityscore=0 suspectscore=0 malwarescore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311170114 When the t bit is one the first 32 bits of register 2 are populated on a tapq. Those bits tell us in which mode the queu is and which facilities it supports. Signed-off-by: Janosch Frank --- lib/s390x/ap.c | 5 +++-- lib/s390x/ap.h | 2 +- s390x/ap.c | 12 ++++++------ 3 files changed, 10 insertions(+), 9 deletions(-) diff --git a/lib/s390x/ap.c b/lib/s390x/ap.c index c1acfda8..fbc33227 100644 --- a/lib/s390x/ap.c +++ b/lib/s390x/ap.c @@ -26,11 +26,12 @@ static uint8_t *array_queue; static struct ap_config_info qci; int ap_pqap_tapq(uint8_t ap, uint8_t qn, struct ap_queue_status *apqsw, - struct pqap_r2 *r2) + struct pqap_r2 *r2, bool t) { struct pqap_r0 r0 = { .ap = ap, .qn = qn, + .t = t, .fc = PQAP_TEST_APQ }; int cc; @@ -169,7 +170,7 @@ static int pqap_reset_wait(uint8_t ap, uint8_t qn, struct ap_queue_status *apqsw do { /* Give it some time to process before the retry */ mdelay(20); - cc = ap_pqap_tapq(ap, qn, apqsw, &r2); + cc = ap_pqap_tapq(ap, qn, apqsw, &r2, false); } while (apqsw->rc == AP_RC_RESET_IN_PROGRESS); if (apqsw->rc) diff --git a/lib/s390x/ap.h b/lib/s390x/ap.h index e037a974..17f8016d 100644 --- a/lib/s390x/ap.h +++ b/lib/s390x/ap.h @@ -109,7 +109,7 @@ enum { int ap_setup(uint8_t **ap_array, uint8_t **qn_array, uint8_t *naps, uint8_t *nqns); int ap_pqap_tapq(uint8_t ap, uint8_t qn, struct ap_queue_status *apqsw, - struct pqap_r2 *r2); + struct pqap_r2 *r2, bool t); int ap_pqap_reset(uint8_t ap, uint8_t qn, struct ap_queue_status *apqsw); int ap_pqap_reset_zeroize(uint8_t ap, uint8_t qn, struct ap_queue_status *apqsw); int ap_pqap_qci(struct ap_config_info *info); diff --git a/s390x/ap.c b/s390x/ap.c index 0ae2809e..05664df8 100644 --- a/s390x/ap.c +++ b/s390x/ap.c @@ -325,7 +325,7 @@ static void test_pqap_aqic(void) do { mdelay(20); - cc = ap_pqap_tapq(apn, qn, &apqsw, &r2); + cc = ap_pqap_tapq(apn, qn, &apqsw, &r2, false); } while (cc == 0 && apqsw.irq_enabled == 0); report(cc == 0 && apqsw.irq_enabled == 1, "enable IRQs tapq data"); @@ -338,7 +338,7 @@ static void test_pqap_aqic(void) do { mdelay(20); - cc = ap_pqap_tapq(apn, qn, &apqsw, &r2); + cc = ap_pqap_tapq(apn, qn, &apqsw, &r2, false); } while (cc == 0 && apqsw.irq_enabled == 1); report(cc == 0 && apqsw.irq_enabled == 0, "disable IRQs tapq data"); @@ -365,12 +365,12 @@ static void test_pqap_resets(void) do { mdelay(20); - cc = ap_pqap_tapq(apn, qn, &apqsw, &r2); + cc = ap_pqap_tapq(apn, qn, &apqsw, &r2, false); } while (cc == 0 && apqsw.irq_enabled == 0); report(apqsw.irq_enabled == 1, "IRQs enabled tapq data"); ap_pqap_reset(apn, qn, &apqsw); - cc = ap_pqap_tapq(apn, qn, &apqsw, &r2); + cc = ap_pqap_tapq(apn, qn, &apqsw, &r2, false); assert(!cc); report(apqsw.irq_enabled == 0, "IRQs have been disabled via reset"); @@ -385,12 +385,12 @@ static void test_pqap_resets(void) do { mdelay(20); - cc = ap_pqap_tapq(apn, qn, &apqsw, &r2); + cc = ap_pqap_tapq(apn, qn, &apqsw, &r2, false); } while (cc == 0 && apqsw.irq_enabled == 0); report(apqsw.irq_enabled == 1, "IRQs enabled tapq data"); ap_pqap_reset_zeroize(apn, qn, &apqsw); - cc = ap_pqap_tapq(apn, qn, &apqsw, &r2); + cc = ap_pqap_tapq(apn, qn, &apqsw, &r2, false); assert(!cc); report(apqsw.irq_enabled == 0, "IRQs have been disabled via reset"); From patchwork Fri Nov 17 15:19:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Janosch Frank X-Patchwork-Id: 13459035 Authentication-Results: smtp.subspace.kernel.org; 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(unknown [9.152.108.100]) by smtpav03.fra02v.mail.ibm.com (Postfix) with ESMTP; Fri, 17 Nov 2023 15:19:56 +0000 (GMT) From: Janosch Frank To: kvm@vger.kernel.org Cc: linux-s390@vger.kernel.org, imbrenda@linux.ibm.com, thuth@redhat.com, david@redhat.com, nsg@linux.ibm.com, nrb@linux.ibm.com Subject: [kvm-unit-tests PATCH v3 7/7] s390x: ap: Add nq/dq len test Date: Fri, 17 Nov 2023 15:19:39 +0000 Message-Id: <20231117151939.971079-8-frankja@linux.ibm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231117151939.971079-1-frankja@linux.ibm.com> References: <20231117151939.971079-1-frankja@linux.ibm.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: YBVUBK7Y9Q1V0I0j8_LmGNprubW69iLn X-Proofpoint-GUID: iMWZWFfZvI73_xo7qzwYtQWicImqHyIU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-17_14,2023-11-17_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 priorityscore=1501 mlxscore=0 clxscore=1015 phishscore=0 spamscore=0 mlxlogscore=999 lowpriorityscore=0 suspectscore=0 malwarescore=0 impostorscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311170114 For years the nqap/dqap max length was 12KB but with a recent machine extended message length support was introduced. The support is AP type and generation specific, so it can vary from card to card which complicates testing by a lot. This test will use the APQN that all other tests use no matter if there's extended length support or not. But if longer messages are supported by the APQN we need to adapt our tests. Signed-off-by: Janosch Frank --- lib/s390x/ap.h | 3 +- s390x/ap.c | 103 +++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 105 insertions(+), 1 deletion(-) diff --git a/lib/s390x/ap.h b/lib/s390x/ap.h index 17f8016d..2511074d 100644 --- a/lib/s390x/ap.h +++ b/lib/s390x/ap.h @@ -77,7 +77,8 @@ struct pqap_r2 { uint8_t pad_1[3]; uint8_t at; uint8_t nd; - uint8_t pad_6; + uint8_t pad_6 : 4; + uint8_t ml : 4; uint8_t pad_7 : 4; uint8_t qd : 4; } __attribute__((packed)) __attribute__((aligned(8))); diff --git a/s390x/ap.c b/s390x/ap.c index 05664df8..89c22b81 100644 --- a/s390x/ap.c +++ b/s390x/ap.c @@ -257,6 +257,106 @@ static void test_pgms_dqap(void) report_prefix_pop(); } +/* + * For years the nqap/dqap max length was 12KB but with a recent + * machine extended message length support was introduced. The support + * is AP type and generation specific, so it can vary from card to + * card. + * + * This test will use the APQN that all other tests use no matter if + * there's extended length support or not. But if longer messages are + * supported by the APQN we need to adapt our tests. + */ +static void test_pgms_nqdq_len(void) +{ + struct ap_queue_status apqsw = {}; + struct pqap_r2 r2 = {}; + uint64_t len, mlen; + bool fail; + int i; + + /* Extended message support is reported via tapq with T=1 */ + ap_pqap_tapq(apn, qn, &apqsw, &r2, true); + /* < 3 means 3 because of backwards compatibility */ + mlen = r2.ml ? r2.ml : 3; + /* Len is reported in pages */ + mlen *= PAGE_SIZE; + + report_prefix_push("nqap"); + report_prefix_push("spec"); + + report_prefix_push("len + 1"); + expect_pgm_int(); + len = mlen + 1; + asm volatile ( + "lg 5, 0(%[len])\n" + ".insn rre,0xb2ae0000,2,4\n" + : : [len] "a" (&len) + : "cc", "memory", "0", "1", "2", "3", "4", "5", "6", "7"); + check_pgm_int_code(PGM_INT_CODE_SPECIFICATION); + report_prefix_pop(); + + report_prefix_push("len bits"); + fail = false; + for (i = 12; i < 63; i++) { + len = BIT(i); + if (len < mlen) + continue; + expect_pgm_int(); + asm volatile ( + "lg 5, 0(%[len])\n" + ".insn rre,0xb2ae0000,2,4\n" + : : [len] "a" (&len) + : "cc", "memory", "0", "1", "2", "3", "4", "5", "6", "7"); + if (clear_pgm_int() != PGM_INT_CODE_SPECIFICATION) { + report_fail("setting len to %lx did not result in a spec exception", + len); + fail = true; + } + } + report(!fail, "length pgms"); + report_prefix_pop(); + report_prefix_pop(); + report_prefix_pop(); + + report_prefix_push("dqap"); + report_prefix_push("spec"); + + report_prefix_push("len + 1"); + expect_pgm_int(); + len = mlen + 1; + asm volatile ( + "lg 5, 0(%[len])\n" + ".insn rre,0xb2ae0000,2,4\n" + : : [len] "a" (&len) + : "cc", "memory", "0", "1", "2", "3", "4", "5", "6", "7"); + check_pgm_int_code(PGM_INT_CODE_SPECIFICATION); + report_prefix_pop(); + + report_prefix_push("len bits"); + fail = false; + for (i = 12; i < 63; i++) { + len = BIT(i); + if (len < mlen) + continue; + expect_pgm_int(); + asm volatile ( + "lg 5, 0(%[len])\n" + ".insn rre,0xb2ae0000,2,4\n" + : : [len] "a" (&len) + : "cc", "memory", "0", "1", "2", "3", "4", "5", "6", "7"); + if (clear_pgm_int() != PGM_INT_CODE_SPECIFICATION) { + report_fail("setting len to %lx did not result in a spec exception", + len); + fail = true; + } + } + report(!fail, "length pgms"); + report_prefix_pop(); + report_prefix_pop(); + report_prefix_pop(); +} + static void test_priv(void) { struct ap_config_info info = {}; @@ -446,6 +546,9 @@ int main(void) } apn = apns[0]; qn = qns[0]; + + test_pgms_nqdq_len(); + report_prefix_push("pqap"); if (test_facility(65)) { test_pqap_aqic();