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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BL6PEPF0001AB4E.mail.protection.outlook.com (10.167.242.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7025.12 via Frontend Transport; Sat, 18 Nov 2023 19:33:06 +0000 Received: from quartz-7b1chost.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Sat, 18 Nov 2023 13:33:00 -0600 From: Yazen Ghannam To: CC: , , , , , , , "Yazen Ghannam" Subject: [PATCH 01/20] x86/mce/inject: Clear test status value Date: Sat, 18 Nov 2023 13:32:29 -0600 Message-ID: <20231118193248.1296798-2-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231118193248.1296798-1-yazen.ghannam@amd.com> References: <20231118193248.1296798-1-yazen.ghannam@amd.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB4E:EE_|PH7PR12MB6785:EE_ X-MS-Office365-Filtering-Correlation-Id: cbfb31ff-b962-4960-8b37-08dbe86d30a9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Nov 2023 19:33:06.8085 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cbfb31ff-b962-4960-8b37-08dbe86d30a9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB4E.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6785 AMD systems generally allow MCA "simulation" where MCA registers can be written with valid data and the full MCA handling flow can be tested by software. However, the Platform on Scalable MCA systems, may prevent software from writing data to the MCA registers. There is no architectural way to determine this configuration. Therefore, the MCE Inject module will check for this behavior by writing and reading back a test status value. This is done during module init, and the check can run on any CPU with any valid MCA bank. If MCA_STATUS writes are ignored by the Platform, then there are no side effects on the hardware state. If the writes are not ignored, then the test status value will remain in the hardware MCA_STATUS register. It is likely that the value will not be overwritten by hardware or software, since the tested CPU and bank are arbitrary. Therefore, the user may see a spurious, synthetic MCA error reported whenever MCA is polled for this CPU. Clear the test value immediately after writing it. It is very unlikely that a valid MCA error is logged by hardware during the test. Errors that cause an #MC won't be affected. Fixes: 891e465a1bd8 ("x86/mce: Check whether writes to MCA_STATUS are getting ignored") Signed-off-by: Yazen Ghannam --- arch/x86/kernel/cpu/mce/inject.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/kernel/cpu/mce/inject.c b/arch/x86/kernel/cpu/mce/inject.c index 4d8d4bcf915d..72f0695c3dc1 100644 --- a/arch/x86/kernel/cpu/mce/inject.c +++ b/arch/x86/kernel/cpu/mce/inject.c @@ -746,6 +746,7 @@ static void check_hw_inj_possible(void) wrmsrl_safe(mca_msr_reg(bank, MCA_STATUS), status); rdmsrl_safe(mca_msr_reg(bank, MCA_STATUS), &status); + wrmsrl_safe(mca_msr_reg(bank, MCA_STATUS), 0); if (!status) { hw_injection_possible = false; From patchwork Sat Nov 18 19:32:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 13460253 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="pmcrhlks" Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2071.outbound.protection.outlook.com [40.107.220.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6B613130; 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Sat, 18 Nov 2023 19:33:07 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BL6PEPF0001AB4A.mail.protection.outlook.com (10.167.242.68) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7025.12 via Frontend Transport; Sat, 18 Nov 2023 19:33:07 +0000 Received: from quartz-7b1chost.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Sat, 18 Nov 2023 13:33:00 -0600 From: Yazen Ghannam To: CC: , , , , , , , "Yazen Ghannam" Subject: [PATCH 02/20] x86/mce: Define mce_setup() helpers for global and per-CPU fields Date: Sat, 18 Nov 2023 13:32:30 -0600 Message-ID: <20231118193248.1296798-3-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231118193248.1296798-1-yazen.ghannam@amd.com> References: <20231118193248.1296798-1-yazen.ghannam@amd.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB4A:EE_|CO6PR12MB5427:EE_ X-MS-Office365-Filtering-Correlation-Id: d276c711-0b7f-4bdc-3b5f-08dbe86d30f7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Nov 2023 19:33:07.3332 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d276c711-0b7f-4bdc-3b5f-08dbe86d30f7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB4A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO6PR12MB5427 Generally, MCA information for an error is gathered on the CPU that reported the error. In this case, CPU-specific information from the running CPU will be correct. However, this will be incorrect if the MCA information is gathered while running on a CPU that didn't report the error. One example is creating an MCA record using mce_setup() for errors reported from ACPI. Split mce_setup() so that there is a helper function to gather global, i.e. not CPU-specific, information and another helper for CPU-specific information. Don't set the CPU number in either helper function. This will be set appropriately for each call site of the helpers. Leave mce_setup() defined as-is for the common case when running on the reporting CPU. Get MCG_CAP in the global helper even though the register is per-CPU. This value is not already cached per-CPU like other values. And it does not assist with any per-CPU decoding or handling. Signed-off-by: Yazen Ghannam --- arch/x86/kernel/cpu/mce/core.c | 31 +++++++++++++++++++++---------- 1 file changed, 21 insertions(+), 10 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 1642018dd6c9..7e86086aa19c 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -115,20 +115,31 @@ static struct irq_work mce_irq_work; */ BLOCKING_NOTIFIER_HEAD(x86_mce_decoder_chain); +void mce_setup_global(struct mce *m) +{ + memset(m, 0, sizeof(struct mce)); + + m->cpuid = cpuid_eax(1); + m->cpuvendor = boot_cpu_data.x86_vendor; + m->mcgcap = __rdmsr(MSR_IA32_MCG_CAP); + /* need the internal __ version to avoid deadlocks */ + m->time = __ktime_get_real_seconds(); +} + +void mce_setup_per_cpu(struct mce *m) +{ + m->apicid = cpu_data(m->extcpu).topo.initial_apicid; + m->microcode = cpu_data(m->extcpu).microcode; + m->ppin = cpu_data(m->extcpu).ppin; + m->socketid = cpu_data(m->extcpu).topo.pkg_id; +} + /* Do initial initialization of a struct mce */ void mce_setup(struct mce *m) { - memset(m, 0, sizeof(struct mce)); + mce_setup_global(m); m->cpu = m->extcpu = smp_processor_id(); - /* need the internal __ version to avoid deadlocks */ - m->time = __ktime_get_real_seconds(); - m->cpuvendor = boot_cpu_data.x86_vendor; - m->cpuid = cpuid_eax(1); - m->socketid = cpu_data(m->extcpu).topo.pkg_id; - m->apicid = cpu_data(m->extcpu).topo.initial_apicid; - m->mcgcap = __rdmsr(MSR_IA32_MCG_CAP); - m->ppin = cpu_data(m->extcpu).ppin; - m->microcode = boot_cpu_data.microcode; + mce_setup_per_cpu(m); } DEFINE_PER_CPU(struct mce, injectm); From patchwork Sat Nov 18 19:32:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 13460258 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="erQveuqU" Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2049.outbound.protection.outlook.com [40.107.220.49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D41FD192; 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Sat, 18 Nov 2023 19:33:07 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BL6PEPF0001AB4E.mail.protection.outlook.com (10.167.242.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7025.12 via Frontend Transport; Sat, 18 Nov 2023 19:33:07 +0000 Received: from quartz-7b1chost.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Sat, 18 Nov 2023 13:33:01 -0600 From: Yazen Ghannam To: CC: , , , , , , , "Yazen Ghannam" Subject: [PATCH 03/20] x86/mce: Use mce_setup() helpers for apei_smca_report_x86_error() Date: Sat, 18 Nov 2023 13:32:31 -0600 Message-ID: <20231118193248.1296798-4-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231118193248.1296798-1-yazen.ghannam@amd.com> References: <20231118193248.1296798-1-yazen.ghannam@amd.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB4E:EE_|BN9PR12MB5275:EE_ X-MS-Office365-Filtering-Correlation-Id: 8cb3f286-3c71-4429-fd8c-08dbe86d30fc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Nov 2023 19:33:07.3554 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8cb3f286-3c71-4429-fd8c-08dbe86d30fc X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB4E.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN9PR12MB5275 Current AMD systems may report MCA errors using the ACPI Boot Error Record Table (BERT). The BERT entries for MCA errors will be an x86 Common Platform Error Record (CPER) with an MSR register context that matches the MCAX/SMCA register space. However, the BERT will not necessarily be processed on the CPU that reported the MCA errors. Therefore, the correct CPU number needs to be determined and the information saved in struct mce. The CPU number is determined by searching all possible CPUs for a Local APIC ID matching the value in the x86 CPER. Set up the MCA record after searching for a CPU number. If no possible CPU was found, then return early. Gather the global MCA information first, save the found CPU number, then gather the per-CPU information. Signed-off-by: Yazen Ghannam --- arch/x86/kernel/cpu/mce/apei.c | 18 ++++++++---------- arch/x86/kernel/cpu/mce/internal.h | 2 ++ 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/apei.c b/arch/x86/kernel/cpu/mce/apei.c index 7f7309ff67d0..33cefe6157eb 100644 --- a/arch/x86/kernel/cpu/mce/apei.c +++ b/arch/x86/kernel/cpu/mce/apei.c @@ -97,20 +97,18 @@ int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info, u64 lapic_id) if (ctx_info->reg_arr_size < 48) return -EINVAL; - mce_setup(&m); - - m.extcpu = -1; - m.socketid = -1; - for_each_possible_cpu(cpu) { - if (cpu_data(cpu).topo.initial_apicid == lapic_id) { - m.extcpu = cpu; - m.socketid = cpu_data(m.extcpu).topo.pkg_id; + if (cpu_data(cpu).topo.initial_apicid == lapic_id) break; - } } - m.apicid = lapic_id; + if (!cpu_possible(cpu)) + return -EINVAL; + + mce_setup_global(&m); + m.cpu = m.extcpu = cpu; + mce_setup_per_cpu(&m); + m.bank = (ctx_info->msr_addr >> 4) & 0xFF; m.status = *i_mce; m.addr = *(i_mce + 1); diff --git a/arch/x86/kernel/cpu/mce/internal.h b/arch/x86/kernel/cpu/mce/internal.h index e13a26c9c0ac..424c7461dcf9 100644 --- a/arch/x86/kernel/cpu/mce/internal.h +++ b/arch/x86/kernel/cpu/mce/internal.h @@ -209,6 +209,8 @@ enum mca_msr { /* Decide whether to add MCE record to MCE event pool or filter it out. */ extern bool filter_mce(struct mce *m); +void mce_setup_global(struct mce *m); +void mce_setup_per_cpu(struct mce *m); #ifdef CONFIG_X86_MCE_AMD extern bool amd_filter_mce(struct mce *m); From patchwork Sat Nov 18 19:32:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 13460266 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="E7LvCEZO" Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2071.outbound.protection.outlook.com [40.107.244.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F1777D57; 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Sat, 18 Nov 2023 19:33:07 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BL6PEPF0001AB4E.mail.protection.outlook.com (10.167.242.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7025.12 via Frontend Transport; Sat, 18 Nov 2023 19:33:07 +0000 Received: from quartz-7b1chost.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Sat, 18 Nov 2023 13:33:01 -0600 From: Yazen Ghannam To: CC: , , , , , , , "Yazen Ghannam" Subject: [PATCH 04/20] x86/mce/amd, EDAC/mce_amd: Move long names to decoder module Date: Sat, 18 Nov 2023 13:32:32 -0600 Message-ID: <20231118193248.1296798-5-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231118193248.1296798-1-yazen.ghannam@amd.com> References: <20231118193248.1296798-1-yazen.ghannam@amd.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB4E:EE_|IA0PR12MB8254:EE_ X-MS-Office365-Filtering-Correlation-Id: da7df241-834c-4ac1-7178-08dbe86d3131 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Nov 2023 19:33:07.6991 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: da7df241-834c-4ac1-7178-08dbe86d3131 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB4E.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8254 The "long names" for SMCA banks are only used by the MCE decoder module. Move them out of the arch code and into the decoder module. Signed-off-by: Yazen Ghannam --- arch/x86/include/asm/mce.h | 1 - arch/x86/kernel/cpu/mce/amd.c | 74 ++++++++++++++--------------------- drivers/edac/mce_amd.c | 41 +++++++++++++++++++ 3 files changed, 71 insertions(+), 45 deletions(-) diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index 6de6e1d95952..4ad49afca2db 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -333,7 +333,6 @@ enum smca_bank_types { N_SMCA_BANK_TYPES }; -extern const char *smca_get_long_name(enum smca_bank_types t); extern bool amd_mce_is_memory_error(struct mce *m); extern int mce_threshold_create_device(unsigned int cpu); diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index f3517b8a8e91..6cf8ed9c79be 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -87,42 +87,37 @@ struct smca_bank { static DEFINE_PER_CPU_READ_MOSTLY(struct smca_bank[MAX_NR_BANKS], smca_banks); static DEFINE_PER_CPU_READ_MOSTLY(u8[N_SMCA_BANK_TYPES], smca_bank_counts); -struct smca_bank_name { - const char *name; /* Short name for sysfs */ - const char *long_name; /* Long name for pretty-printing */ -}; - -static struct smca_bank_name smca_names[] = { - [SMCA_LS ... SMCA_LS_V2] = { "load_store", "Load Store Unit" }, - [SMCA_IF] = { "insn_fetch", "Instruction Fetch Unit" }, - [SMCA_L2_CACHE] = { "l2_cache", "L2 Cache" }, - [SMCA_DE] = { "decode_unit", "Decode Unit" }, - [SMCA_RESERVED] = { "reserved", "Reserved" }, - [SMCA_EX] = { "execution_unit", "Execution Unit" }, - [SMCA_FP] = { "floating_point", "Floating Point Unit" }, - [SMCA_L3_CACHE] = { "l3_cache", "L3 Cache" }, - [SMCA_CS ... SMCA_CS_V2] = { "coherent_slave", "Coherent Slave" }, - [SMCA_PIE] = { "pie", "Power, Interrupts, etc." }, +static char *smca_names[] = { + [SMCA_LS ... SMCA_LS_V2] = "load_store", + [SMCA_IF] = "insn_fetch", + [SMCA_L2_CACHE] = "l2_cache", + [SMCA_DE] = "decode_unit", + [SMCA_RESERVED] = "reserved", + [SMCA_EX] = "execution_unit", + [SMCA_FP] = "floating_point", + [SMCA_L3_CACHE] = "l3_cache", + [SMCA_CS ... SMCA_CS_V2] = "coherent_slave", + [SMCA_PIE] = "pie", /* UMC v2 is separate because both of them can exist in a single system. */ - [SMCA_UMC] = { "umc", "Unified Memory Controller" }, - [SMCA_UMC_V2] = { "umc_v2", "Unified Memory Controller v2" }, - [SMCA_PB] = { "param_block", "Parameter Block" }, - [SMCA_PSP ... SMCA_PSP_V2] = { "psp", "Platform Security Processor" }, - [SMCA_SMU ... SMCA_SMU_V2] = { "smu", "System Management Unit" }, - [SMCA_MP5] = { "mp5", "Microprocessor 5 Unit" }, - [SMCA_MPDMA] = { "mpdma", "MPDMA Unit" }, - [SMCA_NBIO] = { "nbio", "Northbridge IO Unit" }, - [SMCA_PCIE ... SMCA_PCIE_V2] = { "pcie", "PCI Express Unit" }, - [SMCA_XGMI_PCS] = { "xgmi_pcs", "Ext Global Memory Interconnect PCS Unit" }, - [SMCA_NBIF] = { "nbif", "NBIF Unit" }, - [SMCA_SHUB] = { "shub", "System Hub Unit" }, - [SMCA_SATA] = { "sata", "SATA Unit" }, - [SMCA_USB] = { "usb", "USB Unit" }, - [SMCA_GMI_PCS] = { "gmi_pcs", "Global Memory Interconnect PCS Unit" }, - [SMCA_XGMI_PHY] = { "xgmi_phy", "Ext Global Memory Interconnect PHY Unit" }, - [SMCA_WAFL_PHY] = { "wafl_phy", "WAFL PHY Unit" }, - [SMCA_GMI_PHY] = { "gmi_phy", "Global Memory Interconnect PHY Unit" }, + [SMCA_UMC] = "umc", + [SMCA_UMC_V2] = "umc_v2", + [SMCA_PB] = "param_block", + [SMCA_PSP ... SMCA_PSP_V2] = "psp", + [SMCA_SMU ... SMCA_SMU_V2] = "smu", + [SMCA_MP5] = "mp5", + [SMCA_MPDMA] = "mpdma", + [SMCA_NBIO] = "nbio", + [SMCA_PCIE ... SMCA_PCIE_V2] = "pcie", + [SMCA_XGMI_PCS] = "xgmi_pcs", + [SMCA_NBIF] = "nbif", + [SMCA_SHUB] = "shub", + [SMCA_SATA] = "sata", + [SMCA_USB] = "usb", + [SMCA_GMI_PCS] = "gmi_pcs", + [SMCA_XGMI_PHY] = "xgmi_phy", + [SMCA_WAFL_PHY] = "wafl_phy", + [SMCA_GMI_PHY] = "gmi_phy", }; static const char *smca_get_name(enum smca_bank_types t) @@ -130,17 +125,8 @@ static const char *smca_get_name(enum smca_bank_types t) if (t >= N_SMCA_BANK_TYPES) return NULL; - return smca_names[t].name; -} - -const char *smca_get_long_name(enum smca_bank_types t) -{ - if (t >= N_SMCA_BANK_TYPES) - return NULL; - - return smca_names[t].long_name; + return smca_names[t]; } -EXPORT_SYMBOL_GPL(smca_get_long_name); enum smca_bank_types smca_get_bank_type(unsigned int cpu, unsigned int bank) { diff --git a/drivers/edac/mce_amd.c b/drivers/edac/mce_amd.c index 9215c06783df..b8765292d26e 100644 --- a/drivers/edac/mce_amd.c +++ b/drivers/edac/mce_amd.c @@ -1163,6 +1163,47 @@ static void decode_mc6_mce(struct mce *m) pr_emerg(HW_ERR "Corrupted MC6 MCE info?\n"); } +static char *smca_names[] = { + [SMCA_LS ... SMCA_LS_V2] = "Load Store Unit", + [SMCA_IF] = "Instruction Fetch Unit", + [SMCA_L2_CACHE] = "L2 Cache", + [SMCA_DE] = "Decode Unit", + [SMCA_RESERVED] = "Reserved", + [SMCA_EX] = "Execution Unit", + [SMCA_FP] = "Floating Point Unit", + [SMCA_L3_CACHE] = "L3 Cache", + [SMCA_CS ... SMCA_CS_V2] = "Coherent Slave", + [SMCA_PIE] = "Power, Interrupts, etc.", + + /* UMC v2 is separate because both of them can exist in a single system. */ + [SMCA_UMC] = "Unified Memory Controller", + [SMCA_UMC_V2] = "Unified Memory Controller v2", + [SMCA_PB] = "Parameter Block", + [SMCA_PSP ... SMCA_PSP_V2] = "Platform Security Processor", + [SMCA_SMU ... SMCA_SMU_V2] = "System Management Unit", + [SMCA_MP5] = "Microprocessor 5 Unit", + [SMCA_MPDMA] = "MPDMA Unit", + [SMCA_NBIO] = "Northbridge IO Unit", + [SMCA_PCIE ... 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Sat, 18 Nov 2023 19:33:08 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BL6PEPF0001AB4E.mail.protection.outlook.com (10.167.242.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7025.12 via Frontend Transport; Sat, 18 Nov 2023 19:33:08 +0000 Received: from quartz-7b1chost.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Sat, 18 Nov 2023 13:33:02 -0600 From: Yazen Ghannam To: CC: , , , , , , , "Yazen Ghannam" Subject: [PATCH 05/20] x86/mce/amd: Use helper for UMC bank type check Date: Sat, 18 Nov 2023 13:32:33 -0600 Message-ID: <20231118193248.1296798-6-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231118193248.1296798-1-yazen.ghannam@amd.com> References: <20231118193248.1296798-1-yazen.ghannam@amd.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB4E:EE_|SJ1PR12MB6196:EE_ X-MS-Office365-Filtering-Correlation-Id: 71159e73-5b23-43a9-82d0-08dbe86d3163 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Nov 2023 19:33:08.0272 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 71159e73-5b23-43a9-82d0-08dbe86d3163 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB4E.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6196 Scalable MCA systems use values in the MCA_IPID register to describe the type of hardware for an MCA bank. This information is used when bank-specific actions or decoding are needed. Otherwise, microarchitectural information, like MCA_STATUS bits, should be used. Currently, the bank type information is cached at boot time for all CPUs and all banks. This uses more memory as the number of CPUs and MCA banks increases. Furthermore, this causes bank-specific actions to rely on the OS "CPU number" to look up cached values. And this can break if the CPU number processing an error is not the same at the CPU that reported the error. The bank type should be determined solely on the MCA_IPID values. And the cached information should be removed. Define a helper function to check for a UMC bank type. This simplifies the common case where software needs to determine if an MCA error is for memory, and where the exact bank type is not needed. Use bitops and rename old mask until removed. Signed-off-by: Yazen Ghannam --- arch/x86/include/asm/mce.h | 3 ++- arch/x86/kernel/cpu/mce/amd.c | 15 +++++++++------ 2 files changed, 11 insertions(+), 7 deletions(-) diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index 4ad49afca2db..c43b41677a3e 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -60,7 +60,8 @@ */ #define MCI_CONFIG_MCAX 0x1 #define MCI_IPID_MCATYPE 0xFFFF0000 -#define MCI_IPID_HWID 0xFFF +#define MCI_IPID_HWID_OLD 0xFFF +#define MCI_IPID_HWID GENMASK_ULL(43, 32) /* * Note that the full MCACOD field of IA32_MCi_STATUS MSR is diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 6cf8ed9c79be..c8fb6c24170f 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -7,6 +7,7 @@ * * All MC4_MISCi registers are shared between cores on a node. */ +#include #include #include #include @@ -143,6 +144,12 @@ enum smca_bank_types smca_get_bank_type(unsigned int cpu, unsigned int bank) } EXPORT_SYMBOL_GPL(smca_get_bank_type); +/* UMCs have HWID=0x96.*/ +static bool smca_umc_bank_type(u64 ipid) +{ + return FIELD_GET(MCI_IPID_HWID, ipid) == 0x96; +} + static const struct smca_hwid smca_hwid_mcatypes[] = { /* { bank_type, hwid_mcatype } */ @@ -304,7 +311,7 @@ static void smca_configure(unsigned int bank, unsigned int cpu) return; } - hwid_mcatype = HWID_MCATYPE(high & MCI_IPID_HWID, + hwid_mcatype = HWID_MCATYPE(high & MCI_IPID_HWID_OLD, (high & MCI_IPID_MCATYPE) >> 16); for (i = 0; i < ARRAY_SIZE(smca_hwid_mcatypes); i++) { @@ -714,14 +721,10 @@ static bool legacy_mce_is_memory_error(struct mce *m) */ static bool smca_mce_is_memory_error(struct mce *m) { - enum smca_bank_types bank_type; - if (XEC(m->status, 0x3f)) return false; - bank_type = smca_get_bank_type(m->extcpu, m->bank); - - return bank_type == SMCA_UMC || bank_type == SMCA_UMC_V2; + return smca_umc_bank_type(m->ipid); } bool amd_mce_is_memory_error(struct mce *m) From patchwork Sat Nov 18 19:32:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 13460252 Authentication-Results: smtp.subspace.kernel.org; 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Sat, 18 Nov 2023 13:33:03 -0600 From: Yazen Ghannam To: CC: , , , , , , , "Yazen Ghannam" Subject: [PATCH 06/20] x86/mce/amd: Use helper for GPU UMC bank type checks Date: Sat, 18 Nov 2023 13:32:34 -0600 Message-ID: <20231118193248.1296798-7-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231118193248.1296798-1-yazen.ghannam@amd.com> References: <20231118193248.1296798-1-yazen.ghannam@amd.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB4A:EE_|SA3PR12MB8761:EE_ X-MS-Office365-Filtering-Correlation-Id: 4b71e3d8-aa50-430f-9653-08dbe86d3194 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: zzIqh3x+LfGwY33WujhQoN1VD8f8XP/JAUElH1elSVCUvVYhJPnliqlTYynkb6fu7iZJS4OJweBzVohQCxeaCaAd5gndYpKcbL9j5E9rFG99PFQ5qYeEfuOjjfSD6Tfv42e1EzguUGLaoVGrHD7Sef0PJARSO81s0dh3ijAjXEYkimFmBeW74usLSQBe6r5jrv39hLuJbCHKh6nrFgIbzQdbbfNHwMHPgqvw3ccRkSUXKqL4T7VwkzCJIjwHhh0UUmIEJI5+YuXiY+O4VXiL1/t9ivc384ETCdM1IPUThYRg02tu/78XC/YQJpE/vOm1XQ4dQLVm6xz8uCoPcwKr2Jx1Kmv6uKrqmHFX6C9AEjClSAw+Jt88+WKbWkJwNUlA+eOePzIf0A6/2ItNyE9QAzKT79rK2CaPAiPxR/b0/Zpvo/KgPz5bzNSCKCZ5lkfi9Wcs0x4Y36rlWUO0FMIYkqqQqGAP3pyZ0kWaLVeCS/ip3NxFNNQWUOiykaS9EbWDepN6MLJesEE7NPumwu8dt1USDg2mIKDdpsZ0nGKxOk+1WFz428MkITiFPEqAPXlnBcZZ/ucdmVCUT/WBOA/0CABgxd1LRJiFK5GoYxlQpgOQU++Gwg9dbP1tqyn2++33U1p6wyTlfbVPcmuP74asVNSfCSZdVXWMbXwhmVwoXA1W7XCcCkaoP0atVdxLBwQeLYwTffjv5ETaQu9jwPQwFzxbKlEWVn8wJFdpNqrB1MwKUqhtO+w5frpCkbdJ6K2ZUdMIlLl3MAitrMY2Cj2vXQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(376002)(136003)(346002)(396003)(39860400002)(230922051799003)(186009)(82310400011)(451199024)(1800799012)(64100799003)(36840700001)(46966006)(40470700004)(36756003)(15650500001)(40460700003)(5660300002)(2906002)(54906003)(41300700001)(336012)(82740400003)(478600001)(6916009)(70206006)(36860700001)(316002)(356005)(26005)(70586007)(16526019)(1076003)(86362001)(7696005)(47076005)(6666004)(2616005)(81166007)(83380400001)(44832011)(426003)(4326008)(8676002)(8936002)(40480700001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Nov 2023 19:33:08.3645 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4b71e3d8-aa50-430f-9653-08dbe86d3194 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB4A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB8761 The type of an Scalable MCA bank should be determined solely using the values in its MCA_IPID register. Define and use a helper function to determine if a bank represents a GPU Unified Memory Controller (UMC), and where the exact bank type is not needed. Use bitops and rename old mask until removed. Signed-off-by: Yazen Ghannam --- arch/x86/include/asm/mce.h | 4 +++- arch/x86/kernel/cpu/mce/amd.c | 12 +++++++++++- drivers/edac/amd64_edac.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 9 ++++----- 4 files changed, 19 insertions(+), 8 deletions(-) diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index c43b41677a3e..012caf68dcbb 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -59,8 +59,9 @@ * - TCC bit is present in MCx_STATUS. */ #define MCI_CONFIG_MCAX 0x1 -#define MCI_IPID_MCATYPE 0xFFFF0000 +#define MCI_IPID_MCATYPE_OLD 0xFFFF0000 #define MCI_IPID_HWID_OLD 0xFFF +#define MCI_IPID_MCATYPE GENMASK_ULL(63, 48) #define MCI_IPID_HWID GENMASK_ULL(43, 32) /* @@ -341,6 +342,7 @@ extern int mce_threshold_remove_device(unsigned int cpu); void mce_amd_feature_init(struct cpuinfo_x86 *c); enum smca_bank_types smca_get_bank_type(unsigned int cpu, unsigned int bank); +bool smca_gpu_umc_bank_type(u64 ipid); #else static inline int mce_threshold_create_device(unsigned int cpu) { return 0; }; diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index c8fb6c24170f..6fc35967b11b 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -150,6 +150,16 @@ static bool smca_umc_bank_type(u64 ipid) return FIELD_GET(MCI_IPID_HWID, ipid) == 0x96; } +/* GPU UMCs have MCATYPE=0x1.*/ +bool smca_gpu_umc_bank_type(u64 ipid) +{ + if (!smca_umc_bank_type(ipid)) + return false; + + return FIELD_GET(MCI_IPID_MCATYPE, ipid) == 0x1; +} +EXPORT_SYMBOL_GPL(smca_gpu_umc_bank_type); + static const struct smca_hwid smca_hwid_mcatypes[] = { /* { bank_type, hwid_mcatype } */ @@ -312,7 +322,7 @@ static void smca_configure(unsigned int bank, unsigned int cpu) } hwid_mcatype = HWID_MCATYPE(high & MCI_IPID_HWID_OLD, - (high & MCI_IPID_MCATYPE) >> 16); + (high & MCI_IPID_MCATYPE_OLD) >> 16); for (i = 0; i < ARRAY_SIZE(smca_hwid_mcatypes); i++) { s_hwid = &smca_hwid_mcatypes[i]; diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 9b6642d00871..b593795e1e6b 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1032,7 +1032,7 @@ static int fixup_node_id(int node_id, struct mce *m) /* MCA_IPID[InstanceIdHi] give the AMD Node ID for the bank. */ u8 nid = (m->ipid >> 44) & 0xF; - if (smca_get_bank_type(m->extcpu, m->bank) != SMCA_UMC_V2) + if (!smca_gpu_umc_bank_type(m->ipid)) return node_id; /* Nodes below the GPU base node are CPU nodes and don't need a fixup. */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 84e5987b14e0..7235668b3cc2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -3279,12 +3279,11 @@ static int amdgpu_bad_page_notifier(struct notifier_block *nb, uint32_t umc_inst = 0, ch_inst = 0; /* - * If the error was generated in UMC_V2, which belongs to GPU UMCs, - * and error occurred in DramECC (Extended error code = 0) then only - * process the error, else bail out. + * If the error was generated in a GPU UMC and error occurred in + * DramECC (Extended error code = 0) then only process the error, + * else bail out. */ - if (!m || !((smca_get_bank_type(m->extcpu, m->bank) == SMCA_UMC_V2) && - (XEC(m->status, 0x3f) == 0x0))) + if (!m || !(smca_gpu_umc_bank_type(m->ipid) && (XEC(m->status, 0x3f) == 0x0))) return NOTIFY_DONE; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Nov 2023 19:33:09.0520 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a7669b20-3fb8-4a78-7df0-08dbe86d31fd X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB4A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR12MB9412 Quirks break micro-architectural definitions. Therefore, quirk conditions don't need to follow micro-architectural requirements. Currently, there is a quirk to filter some errors from the Instruction Fetch (IF) unit on specific models. The IF unit is represented by MCA bank 1 for these models. Related to this quirk is code to disable MCA Thresholding for the IF bank. Check the bank number for the quirks instead of determining the bank type. Signed-off-by: Yazen Ghannam --- arch/x86/kernel/cpu/mce/amd.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 6fc35967b11b..6e100024498a 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -616,13 +616,12 @@ prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr, bool amd_filter_mce(struct mce *m) { - enum smca_bank_types bank_type = smca_get_bank_type(m->extcpu, m->bank); struct cpuinfo_x86 *c = &boot_cpu_data; /* See Family 17h Models 10h-2Fh Erratum #1114. */ if (c->x86 == 0x17 && c->x86_model >= 0x10 && c->x86_model <= 0x2F && - bank_type == SMCA_IF && XEC(m->status, 0x3f) == 10) + m->bank == 1 && XEC(m->status, 0x3f) == 10) return true; /* NB GART TLB error reporting is disabled by default. */ @@ -654,7 +653,7 @@ static void disable_err_thresholding(struct cpuinfo_x86 *c, unsigned int bank) } else if (c->x86 == 0x17 && (c->x86_model >= 0x10 && c->x86_model <= 0x2F)) { - if (smca_get_bank_type(smp_processor_id(), bank) != SMCA_IF) + if (bank != 1) return; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Nov 2023 19:33:09.0741 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4bbc47bd-ecd5-4949-403a-08dbe86d3203 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB4E.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB6837 Scalable MCA systems use values within the MCA_IPID register to describe a bank's type. Other information is not needed. Currently, the bank types are cached during boot and this information is used during boot and run time. The cached values are per-CPU and per-bank. The boot path needs the cached values, but this should be removed. The run time path does not need the cached values. Determine a Scalable MCA bank's type using only the MCA_IPID values. The only current user is the MCE decoder module. But the boot path will be updated to use the same helper function. Keep old code until init path is cleaned up. Signed-off-by: Yazen Ghannam --- arch/x86/include/asm/mce.h | 2 +- arch/x86/kernel/cpu/mce/amd.c | 88 ++++++++++++++++++++++++++++++++--- drivers/edac/mce_amd.c | 2 +- 3 files changed, 84 insertions(+), 8 deletions(-) diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index 012caf68dcbb..9441b89afee3 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -341,7 +341,7 @@ extern int mce_threshold_create_device(unsigned int cpu); extern int mce_threshold_remove_device(unsigned int cpu); void mce_amd_feature_init(struct cpuinfo_x86 *c); -enum smca_bank_types smca_get_bank_type(unsigned int cpu, unsigned int bank); +enum smca_bank_types smca_get_bank_type(u64 ipid); bool smca_gpu_umc_bank_type(u64 ipid); #else diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 6e100024498a..95843ac7979d 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -129,7 +129,7 @@ static const char *smca_get_name(enum smca_bank_types t) return smca_names[t]; } -enum smca_bank_types smca_get_bank_type(unsigned int cpu, unsigned int bank) +static enum smca_bank_types smca_get_bank_type_old(unsigned int cpu, unsigned int bank) { struct smca_bank *b; @@ -142,7 +142,6 @@ enum smca_bank_types smca_get_bank_type(unsigned int cpu, unsigned int bank) return b->hwid->bank_type; } -EXPORT_SYMBOL_GPL(smca_get_bank_type); /* UMCs have HWID=0x96.*/ static bool smca_umc_bank_type(u64 ipid) @@ -160,7 +159,7 @@ bool smca_gpu_umc_bank_type(u64 ipid) } EXPORT_SYMBOL_GPL(smca_gpu_umc_bank_type); -static const struct smca_hwid smca_hwid_mcatypes[] = { +static const struct smca_hwid smca_hwid_mcatypes_old[] = { /* { bank_type, hwid_mcatype } */ /* Reserved type */ @@ -221,6 +220,83 @@ static const struct smca_hwid smca_hwid_mcatypes[] = { { SMCA_GMI_PHY, HWID_MCATYPE(0x269, 0x0) }, }; +/* Keep sorted first by HWID then by McaType. */ +static const u32 smca_hwid_mcatypes[] = { + /* Reserved type */ + [SMCA_RESERVED] = HWID_MCATYPE(0x00, 0x0), + + /* System Management Unit MCA type */ + [SMCA_SMU] = HWID_MCATYPE(0x01, 0x0), + [SMCA_SMU_V2] = HWID_MCATYPE(0x01, 0x1), + + /* Microprocessor 5 Unit MCA type */ + [SMCA_MP5] = HWID_MCATYPE(0x01, 0x2), + + /* MPDMA MCA type */ + [SMCA_MPDMA] = HWID_MCATYPE(0x01, 0x3), + + /* Parameter Block MCA type */ + [SMCA_PB] = HWID_MCATYPE(0x05, 0x0), + + /* Northbridge IO Unit MCA type */ + [SMCA_NBIO] = HWID_MCATYPE(0x18, 0x0), + + /* Data Fabric MCA types */ + [SMCA_CS] = HWID_MCATYPE(0x2E, 0x0), + [SMCA_PIE] = HWID_MCATYPE(0x2E, 0x1), + [SMCA_CS_V2] = HWID_MCATYPE(0x2E, 0x2), + + /* PCI Express Unit MCA type */ + [SMCA_PCIE] = HWID_MCATYPE(0x46, 0x0), + [SMCA_PCIE_V2] = HWID_MCATYPE(0x46, 0x1), + + [SMCA_XGMI_PCS] = HWID_MCATYPE(0x50, 0x0), + [SMCA_NBIF] = HWID_MCATYPE(0x6C, 0x0), + [SMCA_SHUB] = HWID_MCATYPE(0x80, 0x0), + + /* Unified Memory Controller MCA type */ + [SMCA_UMC] = HWID_MCATYPE(0x96, 0x0), + [SMCA_UMC_V2] = HWID_MCATYPE(0x96, 0x1), + + [SMCA_SATA] = HWID_MCATYPE(0xA8, 0x0), + [SMCA_USB] = HWID_MCATYPE(0xAA, 0x0), + + /* ZN Core (HWID=0xB0) MCA types */ + [SMCA_LS] = HWID_MCATYPE(0xB0, 0x0), + [SMCA_IF] = HWID_MCATYPE(0xB0, 0x1), + [SMCA_L2_CACHE] = HWID_MCATYPE(0xB0, 0x2), + [SMCA_DE] = HWID_MCATYPE(0xB0, 0x3), + /* HWID 0xB0 MCATYPE 0x4 is Reserved */ + [SMCA_EX] = HWID_MCATYPE(0xB0, 0x5), + [SMCA_FP] = HWID_MCATYPE(0xB0, 0x6), + [SMCA_L3_CACHE] = HWID_MCATYPE(0xB0, 0x7), + [SMCA_LS_V2] = HWID_MCATYPE(0xB0, 0x10), + + /* Platform Security Processor MCA type */ + [SMCA_PSP] = HWID_MCATYPE(0xFF, 0x0), + [SMCA_PSP_V2] = HWID_MCATYPE(0xFF, 0x1), + + [SMCA_GMI_PCS] = HWID_MCATYPE(0x241, 0x0), + [SMCA_XGMI_PHY] = HWID_MCATYPE(0x259, 0x0), + [SMCA_WAFL_PHY] = HWID_MCATYPE(0x267, 0x0), + [SMCA_GMI_PHY] = HWID_MCATYPE(0x269, 0x0), +}; + +enum smca_bank_types smca_get_bank_type(u64 ipid) +{ + enum smca_bank_types type; + u32 hwid_mcatype = HWID_MCATYPE(FIELD_GET(MCI_IPID_HWID, ipid), + FIELD_GET(MCI_IPID_MCATYPE, ipid)); + + for (type = 0; type < ARRAY_SIZE(smca_hwid_mcatypes); type++) { + if (hwid_mcatype == smca_hwid_mcatypes[type]) + return type; + } + + return N_SMCA_BANK_TYPES; +} +EXPORT_SYMBOL_GPL(smca_get_bank_type); + /* * In SMCA enabled processors, we can have multiple banks for a given IP type. * So to define a unique name for each bank, we use a temp c-string to append @@ -324,8 +400,8 @@ static void smca_configure(unsigned int bank, unsigned int cpu) hwid_mcatype = HWID_MCATYPE(high & MCI_IPID_HWID_OLD, (high & MCI_IPID_MCATYPE_OLD) >> 16); - for (i = 0; i < ARRAY_SIZE(smca_hwid_mcatypes); i++) { - s_hwid = &smca_hwid_mcatypes[i]; + for (i = 0; i < ARRAY_SIZE(smca_hwid_mcatypes_old); i++) { + s_hwid = &smca_hwid_mcatypes_old[i]; if (hwid_mcatype == s_hwid->hwid_mcatype) { this_cpu_ptr(smca_banks)[bank].hwid = s_hwid; @@ -1104,7 +1180,7 @@ static const char *get_name(unsigned int cpu, unsigned int bank, struct threshol return th_names[bank]; } - bank_type = smca_get_bank_type(cpu, bank); + bank_type = smca_get_bank_type_old(cpu, bank); if (bank_type >= N_SMCA_BANK_TYPES) return NULL; diff --git a/drivers/edac/mce_amd.c b/drivers/edac/mce_amd.c index b8765292d26e..701bc9556414 100644 --- a/drivers/edac/mce_amd.c +++ b/drivers/edac/mce_amd.c @@ -1207,7 +1207,7 @@ static const char *smca_get_long_name(enum smca_bank_types t) /* Decode errors according to Scalable MCA specification */ static void decode_smca_error(struct mce *m) { - enum smca_bank_types bank_type = smca_get_bank_type(m->extcpu, m->bank); + enum smca_bank_types bank_type = smca_get_bank_type(m->ipid); const char *ip_name; u8 xec = XEC(m->status, xec_mask); From patchwork Sat Nov 18 19:32:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 13460255 Authentication-Results: smtp.subspace.kernel.org; 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Sat, 18 Nov 2023 13:33:04 -0600 From: Yazen Ghannam To: CC: , , , , , , , "Yazen Ghannam" Subject: [PATCH 09/20] x86/mce/amd: Clean up SMCA configuration Date: Sat, 18 Nov 2023 13:32:37 -0600 Message-ID: <20231118193248.1296798-10-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231118193248.1296798-1-yazen.ghannam@amd.com> References: <20231118193248.1296798-1-yazen.ghannam@amd.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB4A:EE_|MN0PR12MB6149:EE_ X-MS-Office365-Filtering-Correlation-Id: 96356b73-12a2-4a76-7b41-08dbe86d323b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ruzxZSndcahK/siT3DKfzijT+Nw4LvlwjU6frmnLaQHDlr1mRMyxnHwGMdbX+YG8a7lSMG3botXMIZEXl8l7R1JbsKsUKyveacuyoNSwRWJbja69yWeOdu7SY6lQ+PVnUQwiTZy1BHK88Hp/fu0O5JLNrwpvLUAE1dhjHx4eLtFnSVXEbsNcjUyWOKTKP/iR2jvkNemU+xz2UV/JUgEk0QhSGvftScUSR0bhRR76hyjpBXbWn2eYQsWcju7q+uxpUcjdksY76XcOXZGZ+0L8t1vN9QgdXsITDqplpjiJs8p7zm1Kq3WIgh2z7wCyTxmXCKjrOr4tvWNuq9m3JGWGqkj8QthuC0n0IOhd8vJVCKq5Czf1nTwdvUY0wLyrb6Mk+7oVGFueFsDkyaLckiM4sIpEuDE1WKksRAF1tBdfER+4jqDUurQegA4kVAWEtftN22ZQsnCVNF/dV8MBuflNHDhq8+mo+om7hH0Hw9im1b4O+QgdqXvb4sRCWkGqH/nQaHqloOsE48NDMoDnyOse2muNi7MNTpX9bO0XxFEUU1WPM9G2mL2GTjVEPuf83v9ZEouMxNNdIZ5zUl6gFtKA4nJX+DTwAEqZcNgsoRJgJjBt1bIr2TML08jGRsULWQSvFVOFb11NJ+uFEAeRZ5swh9B2CUHUiEODL/ybARVSxGKS3YDolKvboD+83jG7lWvsw1CSQKB49224ZrYj5N0O7IVxeRfuwLXbZKXu8pozkXjcRU8LsFwMXTMCFsZF62BHMF+TJmwpMksPWX6WW6duNA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(396003)(136003)(376002)(346002)(39860400002)(230922051799003)(1800799012)(82310400011)(64100799003)(186009)(451199024)(46966006)(36840700001)(40470700004)(40480700001)(40460700003)(36860700001)(54906003)(70206006)(70586007)(6916009)(316002)(6666004)(478600001)(47076005)(44832011)(8936002)(8676002)(86362001)(2616005)(7696005)(1076003)(26005)(2906002)(4326008)(16526019)(5660300002)(41300700001)(336012)(356005)(36756003)(426003)(83380400001)(82740400003)(81166007)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Nov 2023 19:33:09.4426 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 96356b73-12a2-4a76-7b41-08dbe86d323b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB4A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6149 The current SMCA configuration function does more than just configure SMCA features. It also detects and caches the SMCA bank types. However, the bank type caching flow will be removed during the init path clean up. Define a new function that only configures SMCA features. This will operate on the MCA_CONFIG MSR, so include updated register field definitions using bitops. Leave old code until init path is cleaned up. Signed-off-by: Yazen Ghannam --- arch/x86/kernel/cpu/mce/amd.c | 84 ++++++++++++++++++++--------------- 1 file changed, 49 insertions(+), 35 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 95843ac7979d..c8c92e048f56 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -50,9 +50,16 @@ #define MASK_DEF_INT_TYPE 0x00000006 #define DEF_LVT_OFF 0x2 #define DEF_INT_TYPE_APIC 0x2 +#define INTR_TYPE_APIC 0x1 /* Scalable MCA: */ +/* MCA_CONFIG register, one per MCA bank */ +#define CFG_DFR_INT_TYPE GENMASK_ULL(38, 37) +#define CFG_MCAX_EN BIT_ULL(32) +#define CFG_LSB_IN_STATUS BIT_ULL(8) +#define CFG_DFR_INT_SUPP BIT_ULL(5) + /* Threshold LVT offset is at MSR0xC0000410[15:12] */ #define SMCA_THR_LVT_OFF 0xF000 @@ -350,45 +357,51 @@ static void smca_set_misc_banks_map(unsigned int bank, unsigned int cpu) } -static void smca_configure(unsigned int bank, unsigned int cpu) +/* Set appropriate bits in MCA_CONFIG. */ +static void configure_smca(unsigned int bank) { - u8 *bank_counts = this_cpu_ptr(smca_bank_counts); - const struct smca_hwid *s_hwid; - unsigned int i, hwid_mcatype; - u32 high, low; - u32 smca_config = MSR_AMD64_SMCA_MCx_CONFIG(bank); + u64 mca_config; - /* Set appropriate bits in MCA_CONFIG */ - if (!rdmsr_safe(smca_config, &low, &high)) { - /* - * OS is required to set the MCAX bit to acknowledge that it is - * now using the new MSR ranges and new registers under each - * bank. It also means that the OS will configure deferred - * errors in the new MCx_CONFIG register. If the bit is not set, - * uncorrectable errors will cause a system panic. - * - * MCA_CONFIG[MCAX] is bit 32 (0 in the high portion of the MSR.) - */ - high |= BIT(0); + if (!mce_flags.smca) + return; - /* - * SMCA sets the Deferred Error Interrupt type per bank. - * - * MCA_CONFIG[DeferredIntTypeSupported] is bit 5, and tells us - * if the DeferredIntType bit field is available. - * - * MCA_CONFIG[DeferredIntType] is bits [38:37] ([6:5] in the - * high portion of the MSR). OS should set this to 0x1 to enable - * APIC based interrupt. First, check that no interrupt has been - * set. - */ - if ((low & BIT(5)) && !((high >> 5) & 0x3)) - high |= BIT(5); + if (rdmsrl_safe(MSR_AMD64_SMCA_MCx_CONFIG(bank), &mca_config)) + return; + + /* + * OS is required to set the MCAX enable bit to acknowledge that it is + * now using the new MSR ranges and new registers under each + * bank. It also means that the OS will configure deferred + * errors in the new MCA_CONFIG register. If the bit is not set, + * uncorrectable errors will cause a system panic. + */ + mca_config |= FIELD_PREP(CFG_MCAX_EN, 0x1); - this_cpu_ptr(mce_banks_array)[bank].lsb_in_status = !!(low & BIT(8)); + /* + * SMCA sets the Deferred Error Interrupt type per bank. + * + * MCA_CONFIG[DeferredIntTypeSupported] is bit 5, and tells us + * if the DeferredIntType bit field is available. + * + * MCA_CONFIG[DeferredIntType] is bits [38:37]. OS should set + * this to 0x1 to enable APIC based interrupt. First, check that + * no interrupt has been set. + */ + if (FIELD_GET(CFG_DFR_INT_SUPP, mca_config) && !FIELD_GET(CFG_DFR_INT_TYPE, mca_config)) + mca_config |= FIELD_PREP(CFG_DFR_INT_TYPE, INTR_TYPE_APIC); - wrmsr(smca_config, low, high); - } + if (FIELD_GET(CFG_LSB_IN_STATUS, mca_config)) + this_cpu_ptr(mce_banks_array)[bank].lsb_in_status = true; + + wrmsrl(MSR_AMD64_SMCA_MCx_CONFIG(bank), mca_config); +} + +static void smca_configure_old(unsigned int bank, unsigned int cpu) +{ + u8 *bank_counts = this_cpu_ptr(smca_bank_counts); + const struct smca_hwid *s_hwid; + unsigned int i, hwid_mcatype; + u32 high, low; smca_set_misc_banks_map(bank, cpu); @@ -764,8 +777,9 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c) for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) { if (mce_flags.smca) - smca_configure(bank, cpu); + smca_configure_old(bank, cpu); + configure_smca(bank); disable_err_thresholding(c, bank); for (block = 0; block < NR_BLOCKS; ++block) { From patchwork Sat Nov 18 19:32:38 2023 Content-Type: text/plain; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BL6PEPF0001AB4E.mail.protection.outlook.com (10.167.242.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7025.12 via Frontend Transport; Sat, 18 Nov 2023 19:33:09 +0000 Received: from quartz-7b1chost.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Sat, 18 Nov 2023 13:33:05 -0600 From: Yazen Ghannam To: CC: , , , , , , , "Yazen Ghannam" Subject: [PATCH 10/20] x86/mce/amd: Prep DFR handler before enabling banks Date: Sat, 18 Nov 2023 13:32:38 -0600 Message-ID: <20231118193248.1296798-11-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231118193248.1296798-1-yazen.ghannam@amd.com> References: <20231118193248.1296798-1-yazen.ghannam@amd.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB4E:EE_|IA1PR12MB6164:EE_ X-MS-Office365-Filtering-Correlation-Id: d977341a-2984-4263-00c3-08dbe86d3265 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Nov 2023 19:33:09.7147 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d977341a-2984-4263-00c3-08dbe86d3265 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB4E.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6164 Scalable MCA systems use the per-bank MCA_CONFIG register to enable deferred error interrupts. This is done as part of SMCA configuration. Currently, the deferred error interrupt handler is set up after SMCA configuration. Move the deferred error interrupt handler set up before SMCA configuration. This ensures the kernel is ready to receive the interrupts before the hardware is configured to send them. Signed-off-by: Yazen Ghannam --- arch/x86/kernel/cpu/mce/amd.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index c8c92e048f56..4fddc5c8ae0e 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -595,6 +595,9 @@ static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c) u32 low = 0, high = 0; int def_offset = -1, def_new; + if (!mce_flags.succor) + return; + if (rdmsr_safe(MSR_CU_DEF_ERR, &low, &high)) return; @@ -774,6 +777,7 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c) u32 low = 0, high = 0, address = 0; int offset = -1; + deferred_error_interrupt_enable(c); for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) { if (mce_flags.smca) @@ -800,9 +804,6 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c) offset = prepare_threshold_block(bank, block, address, offset, high); } } - - if (mce_flags.succor) - deferred_error_interrupt_enable(c); } /* From patchwork Sat Nov 18 19:32:39 2023 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Nov 2023 19:33:09.8176 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 559052a5-7495-4265-b39c-08dbe86d3274 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB4A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB7624 AMD systems with the SUCCOR feature can send an APIC LVT interrupt for deferred errors. The LVT offset is 0x2 by convention, i.e. this is the default as listed in hardware documentation. However, the MCA registers may list a different LVT offset for this interrupt. The kernel should honor the value from the hardware. Simplify the enable flow by using the hardware-provided value. Any conflicts will be caught by setup_APIC_eilvt(). Conflicts on production systems can be handled as quirks, if needed. Also, rename the function using a "verb-first" style. Signed-off-by: Yazen Ghannam --- arch/x86/kernel/cpu/mce/amd.c | 33 ++++++++++----------------------- 1 file changed, 10 insertions(+), 23 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 4fddc5c8ae0e..9197badd9929 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -48,7 +48,6 @@ #define MSR_CU_DEF_ERR 0xC0000410 #define MASK_DEF_LVTOFF 0x000000F0 #define MASK_DEF_INT_TYPE 0x00000006 -#define DEF_LVT_OFF 0x2 #define DEF_INT_TYPE_APIC 0x2 #define INTR_TYPE_APIC 0x1 @@ -581,19 +580,9 @@ static int setup_APIC_mce_threshold(int reserved, int new) return reserved; } -static int setup_APIC_deferred_error(int reserved, int new) +static void enable_deferred_error_interrupt(void) { - if (reserved < 0 && !setup_APIC_eilvt(new, DEFERRED_ERROR_VECTOR, - APIC_EILVT_MSG_FIX, 0)) - return new; - - return reserved; -} - -static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c) -{ - u32 low = 0, high = 0; - int def_offset = -1, def_new; + u32 low = 0, high = 0, def_new; if (!mce_flags.succor) return; @@ -601,17 +590,15 @@ static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c) if (rdmsr_safe(MSR_CU_DEF_ERR, &low, &high)) return; + /* + * Trust the value from hardware. + * If there's a conflict, then setup_APIC_eilvt() will throw an error. + */ def_new = (low & MASK_DEF_LVTOFF) >> 4; - if (!(low & MASK_DEF_LVTOFF)) { - pr_err(FW_BUG "Your BIOS is not setting up LVT offset 0x2 for deferred error IRQs correctly.\n"); - def_new = DEF_LVT_OFF; - low = (low & ~MASK_DEF_LVTOFF) | (DEF_LVT_OFF << 4); - } + if (setup_APIC_eilvt(def_new, DEFERRED_ERROR_VECTOR, APIC_EILVT_MSG_FIX, 0)) + return; - def_offset = setup_APIC_deferred_error(def_offset, def_new); - if ((def_offset == def_new) && - (deferred_error_int_vector != amd_deferred_error_interrupt)) - deferred_error_int_vector = amd_deferred_error_interrupt; + deferred_error_int_vector = amd_deferred_error_interrupt; if (!mce_flags.smca) low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC; @@ -777,7 +764,7 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c) u32 low = 0, high = 0, address = 0; int offset = -1; - deferred_error_interrupt_enable(c); + enable_deferred_error_interrupt(); for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) { if (mce_flags.smca) From patchwork Sat Nov 18 19:32:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 13460262 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="Npszxh6Z" Received: from NAM04-MW2-obe.outbound.protection.outlook.com (mail-mw2nam04on2077.outbound.protection.outlook.com [40.107.101.77]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B2459D54; Sat, 18 Nov 2023 11:33:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=I4BYpB1ols22hJ9WtRMJA6ObVVasRBLkpNRlS8pBCP/RN3GSb7lBShGKP1F91nG1dFzimJ4ftxoqa0fdlpDaSkBDmKTyVb2CAhqzjImgJ1RgfoJNzMxbd/y9HzFnmc4vW3ffTFOFbwRobSC2TDz0l/dH1GU2L6hIsVb0ehE0Tya55X0I6L0uxNcwQHpOmg9BemAdCZ4cImkFXcxWd3gdmCiZ704EECkn9Uv+IGfhyLzucJ53AbgGa68PvYgtbOre2emveWVR4VAHeYrTs086rPcvqKUCvG8Y4eT92n9jNkVvMzkPxG8N4ul0xY8/OkdWboGVTPSfWJDKP/qHczOgYg== ARC-Message-Signature: i=1; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Nov 2023 19:33:10.0585 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 922e5fd2-c54a-4051-7483-08dbe86d3299 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB4E.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6889 Switch to bitops to help with clarity. Also, avoid an unnecessary wrmsr() for SMCA systems. Use the updated name for MSR 0xC000_0410 to match the documentation for Family 0x17 and later systems. This MSR is used for setting up both Deferred and MCA Thresholding interrupts on current systems. So read it once during init and pass to functions that need it. Start with the Deferred error interrupt case. The MCA Thresholding interrupt case will be handled during refactoring. Signed-off-by: Yazen Ghannam --- arch/x86/kernel/cpu/mce/amd.c | 46 +++++++++++++++++++++++------------ 1 file changed, 30 insertions(+), 16 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 9197badd9929..83fdbf42a472 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -44,11 +44,11 @@ #define MASK_BLKPTR_LO 0xFF000000 #define MCG_XBLK_ADDR 0xC0000400 -/* Deferred error settings */ +/* MCA Interrupt Configuration register, one per CPU */ #define MSR_CU_DEF_ERR 0xC0000410 -#define MASK_DEF_LVTOFF 0x000000F0 -#define MASK_DEF_INT_TYPE 0x00000006 -#define DEF_INT_TYPE_APIC 0x2 +#define MSR_MCA_INTR_CFG 0xC0000410 +#define INTR_CFG_DFR_LVT_OFFSET GENMASK_ULL(7, 4) +#define INTR_CFG_LEGACY_DFR_INTR_TYPE GENMASK_ULL(2, 1) #define INTR_TYPE_APIC 0x1 /* Scalable MCA: */ @@ -580,30 +580,30 @@ static int setup_APIC_mce_threshold(int reserved, int new) return reserved; } -static void enable_deferred_error_interrupt(void) +static void enable_deferred_error_interrupt(u64 mca_intr_cfg) { - u32 low = 0, high = 0, def_new; + u8 dfr_offset; - if (!mce_flags.succor) - return; - - if (rdmsr_safe(MSR_CU_DEF_ERR, &low, &high)) + if (!mca_intr_cfg) return; /* * Trust the value from hardware. * If there's a conflict, then setup_APIC_eilvt() will throw an error. */ - def_new = (low & MASK_DEF_LVTOFF) >> 4; - if (setup_APIC_eilvt(def_new, DEFERRED_ERROR_VECTOR, APIC_EILVT_MSG_FIX, 0)) + dfr_offset = FIELD_GET(INTR_CFG_DFR_LVT_OFFSET, mca_intr_cfg); + if (setup_APIC_eilvt(dfr_offset, DEFERRED_ERROR_VECTOR, APIC_EILVT_MSG_FIX, 0)) return; deferred_error_int_vector = amd_deferred_error_interrupt; - if (!mce_flags.smca) - low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC; + if (mce_flags.smca) + return; + + mca_intr_cfg &= ~INTR_CFG_LEGACY_DFR_INTR_TYPE; + mca_intr_cfg |= FIELD_PREP(INTR_CFG_LEGACY_DFR_INTR_TYPE, INTR_TYPE_APIC); - wrmsr(MSR_CU_DEF_ERR, low, high); + wrmsrl(MSR_MCA_INTR_CFG, mca_intr_cfg); } static u32 smca_get_block_address(unsigned int bank, unsigned int block, @@ -757,14 +757,28 @@ static void disable_err_thresholding(struct cpuinfo_x86 *c, unsigned int bank) wrmsrl(MSR_K7_HWCR, hwcr); } +static u64 get_mca_intr_cfg(void) +{ + u64 mca_intr_cfg; + + if (!mce_flags.succor && !mce_flags.smca) + return 0; + + if (rdmsrl_safe(MSR_MCA_INTR_CFG, &mca_intr_cfg)) + return 0; + + return mca_intr_cfg; +} + /* cpu init entry point, called from mce.c with preempt off */ void mce_amd_feature_init(struct cpuinfo_x86 *c) { unsigned int bank, block, cpu = smp_processor_id(); + u64 mca_intr_cfg = get_mca_intr_cfg(); u32 low = 0, high = 0, address = 0; int offset = -1; - enable_deferred_error_interrupt(); + enable_deferred_error_interrupt(mca_intr_cfg); for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) { if (mce_flags.smca) From patchwork Sat Nov 18 19:32:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 13460261 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="gRVr3wzb" Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2076.outbound.protection.outlook.com [40.107.93.76]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6F92A1A1; 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Sat, 18 Nov 2023 19:33:10 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BL6PEPF0001AB4A.mail.protection.outlook.com (10.167.242.68) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7025.12 via Frontend Transport; Sat, 18 Nov 2023 19:33:10 +0000 Received: from quartz-7b1chost.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Sat, 18 Nov 2023 13:33:07 -0600 From: Yazen Ghannam To: CC: , , , , , , , "Yazen Ghannam" Subject: [PATCH 13/20] x86/mce: Unify AMD THR handler with MCA Polling Date: Sat, 18 Nov 2023 13:32:41 -0600 Message-ID: <20231118193248.1296798-14-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231118193248.1296798-1-yazen.ghannam@amd.com> References: <20231118193248.1296798-1-yazen.ghannam@amd.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB4A:EE_|IA0PR12MB8716:EE_ X-MS-Office365-Filtering-Correlation-Id: c4ffbd18-ed28-40d3-c237-08dbe86d32e4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Nov 2023 19:33:10.5676 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c4ffbd18-ed28-40d3-c237-08dbe86d32e4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB4A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8716 AMD systems optionally support an MCA Thresholding interrupt. The interrupt should be used as another signal to trigger MCA polling. This is similar to how the Intel Corrected Machine Check interrupt (CMCI) is handled. AMD MCA Thresholding is managed using the MCA_MISC registers within an MCA bank. The OS will need to modify the hardware error count field in order to reset the threshold limit and rearm the interrupt. Management of the MCA_MISC register should be done as a follow up to the basic MCA polling flow. It should not be the main focus of the interrupt handler. Furthermore, future systems will have the ability to send an MCA Thresholding interrupt to the OS even when the OS does not manage the feature, i.e. MCA_MISC registers are Read-as-Zero/Locked. Call the common MCA polling function when handling the MCA Thresholding interrupt. This will allow the OS to find any valid errors whether or not the MCA Thresholding feature is OS-managed. Also, this allows the common MCA polling options and kernel parameters to apply to AMD systems. Add a callback to the MCA polling function to handle vendor-specific operations. Start by handling the AMD MCA Thresholding "block reset" flow. Signed-off-by: Yazen Ghannam --- arch/x86/kernel/cpu/mce/amd.c | 57 ++++++++++++++---------------- arch/x86/kernel/cpu/mce/core.c | 8 +++++ arch/x86/kernel/cpu/mce/internal.h | 2 ++ 3 files changed, 37 insertions(+), 30 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 83fdbf42a472..8735a8b9b7cc 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -981,12 +981,7 @@ static void amd_deferred_error_interrupt(void) log_error_deferred(bank); } -static void log_error_thresholding(unsigned int bank, u64 misc) -{ - _log_error_deferred(bank, misc); -} - -static void log_and_reset_block(struct threshold_block *block) +static void reset_block(struct threshold_block *block) { struct thresh_restart tr; u32 low = 0, high = 0; @@ -1000,49 +995,51 @@ static void log_and_reset_block(struct threshold_block *block) if (!(high & MASK_OVERFLOW_HI)) return; - /* Log the MCE which caused the threshold event. */ - log_error_thresholding(block->bank, ((u64)high << 32) | low); - /* Reset threshold block after logging error. */ memset(&tr, 0, sizeof(tr)); tr.b = block; threshold_restart_bank(&tr); } -/* - * Threshold interrupt handler will service THRESHOLD_APIC_VECTOR. The interrupt - * goes off when error_count reaches threshold_limit. - */ -static void amd_threshold_interrupt(void) +static void reset_thr_blocks(unsigned int bank) { struct threshold_block *first_block = NULL, *block = NULL, *tmp = NULL; struct threshold_bank **bp = this_cpu_read(threshold_banks); - unsigned int bank, cpu = smp_processor_id(); /* * Validate that the threshold bank has been initialized already. The * handler is installed at boot time, but on a hotplug event the * interrupt might fire before the data has been initialized. */ - if (!bp) + if (!bp || !bp[bank]) return; - for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) { - if (!(per_cpu(bank_map, cpu) & BIT_ULL(bank))) - continue; + first_block = bp[bank]->blocks; + if (!first_block) + return; - first_block = bp[bank]->blocks; - if (!first_block) - continue; + /* + * The first block is also the head of the list. Check it first + * before iterating over the rest. + */ + reset_block(first_block); + list_for_each_entry_safe(block, tmp, &first_block->miscj, miscj) + reset_block(block); +} - /* - * The first block is also the head of the list. Check it first - * before iterating over the rest. - */ - log_and_reset_block(first_block); - list_for_each_entry_safe(block, tmp, &first_block->miscj, miscj) - log_and_reset_block(block); - } +/* + * Threshold interrupt handler will service THRESHOLD_APIC_VECTOR. The interrupt + * goes off when error_count reaches threshold_limit. + */ +static void amd_threshold_interrupt(void) +{ + /* Check all banks for now. This could be optimized in the future. */ + machine_check_poll(MCP_TIMESTAMP, this_cpu_ptr(&mce_poll_banks)); +} + +void amd_handle_error(struct mce *m) +{ + reset_thr_blocks(m->bank); } /* diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 7e86086aa19c..040dc226c6a5 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -655,6 +655,12 @@ static noinstr void mce_read_aux(struct mce *m, int i) } } +static void vendor_handle_error(struct mce *m) +{ + if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) + return amd_handle_error(m); +} + DEFINE_PER_CPU(unsigned, mce_poll_count); /* @@ -760,6 +766,8 @@ bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b) mce_log(&m); clear_it: + vendor_handle_error(&m); + /* * Clear state for this bank. */ diff --git a/arch/x86/kernel/cpu/mce/internal.h b/arch/x86/kernel/cpu/mce/internal.h index 424c7461dcf9..8ed1035f013b 100644 --- a/arch/x86/kernel/cpu/mce/internal.h +++ b/arch/x86/kernel/cpu/mce/internal.h @@ -215,6 +215,7 @@ void mce_setup_per_cpu(struct mce *m); #ifdef CONFIG_X86_MCE_AMD extern bool amd_filter_mce(struct mce *m); bool amd_mce_usable_address(struct mce *m); +void amd_handle_error(struct mce *m); /* * If MCA_CONFIG[McaLsbInStatusSupported] is set, extract ErrAddr in bits @@ -243,6 +244,7 @@ static __always_inline void smca_extract_err_addr(struct mce *m) #else static inline bool amd_filter_mce(struct mce *m) { return false; } static inline bool amd_mce_usable_address(struct mce *m) { return false; } +static inline void amd_handle_error(struct mce *m) { } static inline void smca_extract_err_addr(struct mce *m) { } #endif From patchwork Sat Nov 18 19:32:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 13460264 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="vLm/8TBn" Received: from NAM04-BN8-obe.outbound.protection.outlook.com (mail-bn8nam04on2072.outbound.protection.outlook.com [40.107.100.72]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B4A25D56; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Nov 2023 19:33:10.5585 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8c0d46f6-284e-4d7e-5d80-08dbe86d32e3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB4E.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6123 AMD systems optionally support a Deferred error interrupt. The interrupt should be used as another signal to trigger MCA polling. This is similar to how other MCA interrupts are handled. Deferred errors do not require any special handling related to the interrupt, e.g. resetting or rearming the interrupt, etc. However, Scalable MCA systems include a pair of registers, MCA_DESTAT and MCA_DEADDR, that should be checked for valid errors. This check should be done whenever MCA registers are polled. Currently, the Deferred error interrupt does this check, but the MCA polling function does not. Call the MCA polling function when handling the Deferred error interrupt. This keeps all "polling" cases in a common function. Add a "SMCA DFR handler" for Deferred errors to the AMD vendor-specific error handler callback. This will do the same status check, register clearing, and logging that the interrupt handler has done. And it extends the common polling flow to find AMD Deferred errors. Give a common name for the AMD MCA interrupts handler now that both interrupt sources are handled in a unified function. Remove old code whose functionality is already covered in the common MCA code. Signed-off-by: Yazen Ghannam --- arch/x86/kernel/cpu/mce/amd.c | 122 +++++++++------------------------ arch/x86/kernel/cpu/mce/core.c | 16 ++++- 2 files changed, 48 insertions(+), 90 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 8735a8b9b7cc..b45ee297cde2 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -325,8 +325,7 @@ static DEFINE_PER_CPU(u64, bank_map); /* Map of banks that have more than MCA_MISC0 available. */ static DEFINE_PER_CPU(u64, smca_misc_banks_map); -static void amd_threshold_interrupt(void); -static void amd_deferred_error_interrupt(void); +static void amd_mca_interrupt(void); static void default_deferred_error_interrupt(void) { @@ -595,7 +594,7 @@ static void enable_deferred_error_interrupt(u64 mca_intr_cfg) if (setup_APIC_eilvt(dfr_offset, DEFERRED_ERROR_VECTOR, APIC_EILVT_MSG_FIX, 0)) return; - deferred_error_int_vector = amd_deferred_error_interrupt; + deferred_error_int_vector = amd_mca_interrupt; if (mce_flags.smca) return; @@ -874,33 +873,6 @@ bool amd_mce_usable_address(struct mce *m) return false; } -static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc) -{ - struct mce m; - - mce_setup(&m); - - m.status = status; - m.misc = misc; - m.bank = bank; - m.tsc = rdtsc(); - - if (m.status & MCI_STATUS_ADDRV) { - m.addr = addr; - - smca_extract_err_addr(&m); - } - - if (mce_flags.smca) { - rdmsrl(MSR_AMD64_SMCA_MCx_IPID(bank), m.ipid); - - if (m.status & MCI_STATUS_SYNDV) - rdmsrl(MSR_AMD64_SMCA_MCx_SYND(bank), m.synd); - } - - mce_log(&m); -} - DEFINE_IDTENTRY_SYSVEC(sysvec_deferred_error) { trace_deferred_error_apic_entry(DEFERRED_ERROR_VECTOR); @@ -910,75 +882,46 @@ DEFINE_IDTENTRY_SYSVEC(sysvec_deferred_error) apic_eoi(); } -/* - * Returns true if the logged error is deferred. False, otherwise. - */ -static inline bool -_log_error_bank(unsigned int bank, u32 msr_stat, u32 msr_addr, u64 misc) -{ - u64 status, addr = 0; - - rdmsrl(msr_stat, status); - if (!(status & MCI_STATUS_VAL)) - return false; - - if (status & MCI_STATUS_ADDRV) - rdmsrl(msr_addr, addr); - - __log_error(bank, status, addr, misc); - - wrmsrl(msr_stat, 0); - - return status & MCI_STATUS_DEFERRED; -} - -static bool _log_error_deferred(unsigned int bank, u32 misc) -{ - if (!_log_error_bank(bank, mca_msr_reg(bank, MCA_STATUS), - mca_msr_reg(bank, MCA_ADDR), misc)) - return false; - - /* - * Non-SMCA systems don't have MCA_DESTAT/MCA_DEADDR registers. - * Return true here to avoid accessing these registers. - */ - if (!mce_flags.smca) - return true; - - /* Clear MCA_DESTAT if the deferred error was logged from MCA_STATUS. */ - wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(bank), 0); - return true; -} - /* * We have three scenarios for checking for Deferred errors: * * 1) Non-SMCA systems check MCA_STATUS and log error if found. + * This is already handled in machine_check_poll(). * 2) SMCA systems check MCA_STATUS. If error is found then log it and also * clear MCA_DESTAT. * 3) SMCA systems check MCA_DESTAT, if error was not found in MCA_STATUS, and * log it. */ -static void log_error_deferred(unsigned int bank) +static void handle_smca_dfr_error(struct mce *m) { - if (_log_error_deferred(bank, 0)) + struct mce m_dfr; + u64 mca_destat; + + /* Non-SMCA systems don't have MCA_DESTAT/MCA_DEADDR registers. */ + if (!mce_flags.smca) return; - /* - * Only deferred errors are logged in MCA_DE{STAT,ADDR} so just check - * for a valid error. - */ - _log_error_bank(bank, MSR_AMD64_SMCA_MCx_DESTAT(bank), - MSR_AMD64_SMCA_MCx_DEADDR(bank), 0); -} + /* Clear MCA_DESTAT if the deferred error was logged from MCA_STATUS. */ + if (m->status & MCI_STATUS_DEFERRED) + goto out; -/* APIC interrupt handler for deferred errors */ -static void amd_deferred_error_interrupt(void) -{ - unsigned int bank; + /* MCA_STATUS didn't have a deferred error, so check MCA_DESTAT for one. */ + mca_destat = mce_rdmsrl(MSR_AMD64_SMCA_MCx_DESTAT(m->bank)); - for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) - log_error_deferred(bank); + if (!(mca_destat & MCI_STATUS_VAL)) + return; + + /* Reuse the same data collected from machine_check_poll(). */ + memcpy(&m_dfr, m, sizeof(m_dfr)); + + /* Save the MCA_DE{STAT,ADDR} values. */ + m_dfr.status = mca_destat; + m_dfr.addr = mce_rdmsrl(MSR_AMD64_SMCA_MCx_DEADDR(m_dfr.bank)); + + mce_log(&m_dfr); + +out: + wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(m->bank), 0); } static void reset_block(struct threshold_block *block) @@ -1028,10 +971,10 @@ static void reset_thr_blocks(unsigned int bank) } /* - * Threshold interrupt handler will service THRESHOLD_APIC_VECTOR. The interrupt - * goes off when error_count reaches threshold_limit. + * The same procedure should be used when checking MCA banks in non-urgent + * situations, e.g. polling and interrupts. */ -static void amd_threshold_interrupt(void) +static void amd_mca_interrupt(void) { /* Check all banks for now. This could be optimized in the future. */ machine_check_poll(MCP_TIMESTAMP, this_cpu_ptr(&mce_poll_banks)); @@ -1040,6 +983,7 @@ static void amd_threshold_interrupt(void) void amd_handle_error(struct mce *m) { reset_thr_blocks(m->bank); + handle_smca_dfr_error(m); } /* @@ -1514,6 +1458,6 @@ int mce_threshold_create_device(unsigned int cpu) this_cpu_write(threshold_banks, bp); if (thresholding_irq_en) - mce_threshold_vector = amd_threshold_interrupt; + mce_threshold_vector = amd_mca_interrupt; return 0; } diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 040dc226c6a5..a81c0df217e2 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -663,6 +663,14 @@ static void vendor_handle_error(struct mce *m) DEFINE_PER_CPU(unsigned, mce_poll_count); +static bool smca_destat_is_valid(unsigned int bank) +{ + if (!mce_flags.smca) + return false; + + return mce_rdmsrl(MSR_AMD64_SMCA_MCx_DESTAT(bank)) & MCI_STATUS_VAL; +} + /* * Poll for corrected events or events that happened before reset. * Those are just logged through /dev/mcelog. @@ -704,8 +712,14 @@ bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b) m.status = mce_rdmsrl(mca_msr_reg(i, MCA_STATUS)); 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BL6PEPF0001AB4A.mail.protection.outlook.com (10.167.242.68) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7025.12 via Frontend Transport; Sat, 18 Nov 2023 19:33:10 +0000 Received: from quartz-7b1chost.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Sat, 18 Nov 2023 13:33:08 -0600 From: Yazen Ghannam To: CC: , , , , , , , "Yazen Ghannam" Subject: [PATCH 15/20] x86/mce: Skip AMD threshold init if no threshold banks found Date: Sat, 18 Nov 2023 13:32:43 -0600 Message-ID: <20231118193248.1296798-16-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231118193248.1296798-1-yazen.ghannam@amd.com> References: <20231118193248.1296798-1-yazen.ghannam@amd.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB4A:EE_|IA0PR12MB8254:EE_ X-MS-Office365-Filtering-Correlation-Id: be7bb09a-1a85-4696-acad-08dbe86d330f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Nov 2023 19:33:10.8489 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: be7bb09a-1a85-4696-acad-08dbe86d330f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB4A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8254 AMD systems optionally support MCA Thresholding. This feature is discovered by checking capability bits in the MCA_MISC* registers. Currently, MCA Thresholding is set up in two passes. The first is during CPU init where available banks are detected, and the "bank_map" variable is updated. The second is during sysfs/device init when the thresholding data structures are allocated and hardware is fully configured. During device init, the "threshold_banks" array is allocated even if no available banks were discovered. Furthermore, the thresholding reset flow checks if the top-level "threshold_banks" array is non-NULL, but it doesn't check if individual "threshold_bank" structures are non-NULL. This is avoided because the hardware interrupt is not enabled in this case. But this issue becomes present if enabling the interrupt when the thresholding data structures are not initialized. Check "bank_map" to determine if the thresholding structures should be allocated and initialized. Also, remove "mce_flags.amd_threshold" which is redundant when checking "bank_map". Signed-off-by: Yazen Ghannam --- arch/x86/kernel/cpu/mce/amd.c | 2 +- arch/x86/kernel/cpu/mce/core.c | 1 - arch/x86/kernel/cpu/mce/internal.h | 3 --- 3 files changed, 1 insertion(+), 5 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index b45ee297cde2..462ba9ff997b 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -1434,7 +1434,7 @@ int mce_threshold_create_device(unsigned int cpu) struct threshold_bank **bp; int err; - if (!mce_flags.amd_threshold) + if (!this_cpu_read(bank_map)) return 0; bp = this_cpu_read(threshold_banks); diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index a81c0df217e2..bdbc32f10a9a 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -2004,7 +2004,6 @@ static void __mcheck_cpu_init_early(struct cpuinfo_x86 *c) mce_flags.overflow_recov = !!cpu_has(c, X86_FEATURE_OVERFLOW_RECOV); mce_flags.succor = !!cpu_has(c, X86_FEATURE_SUCCOR); mce_flags.smca = !!cpu_has(c, X86_FEATURE_SMCA); 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Sat, 18 Nov 2023 19:33:11 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BL6PEPF0001AB4E.mail.protection.outlook.com (10.167.242.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7025.12 via Frontend Transport; Sat, 18 Nov 2023 19:33:11 +0000 Received: from quartz-7b1chost.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Sat, 18 Nov 2023 13:33:09 -0600 From: Yazen Ghannam To: CC: , , , , , , , "Yazen Ghannam" Subject: [PATCH 16/20] x86/mce/amd: Support SMCA Corrected Error Interrupt Date: Sat, 18 Nov 2023 13:32:44 -0600 Message-ID: <20231118193248.1296798-17-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231118193248.1296798-1-yazen.ghannam@amd.com> References: <20231118193248.1296798-1-yazen.ghannam@amd.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB4E:EE_|BY5PR12MB4084:EE_ X-MS-Office365-Filtering-Correlation-Id: 4feae167-044e-44c1-e2af-08dbe86d3349 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Nov 2023 19:33:11.2147 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4feae167-044e-44c1-e2af-08dbe86d3349 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB4E.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4084 AMD systems optionally support MCA Thresholding which provides the ability for hardware to send an interrupt when a set error threshold is reached. This feature counts errors of all severities, but it is commonly used to report correctable errors with an interrupt rather than polling. Scalable MCA systems allow the Platform to take control of this feature. In this case, the OS will not see the feature configuration and control bits in the MCA_MISC* registers. The OS will not receive the MCA Thresholding interrupt, and it will need to poll for correctable errors. A "corrected error interrupt" will be available on Scalable MCA systems. This will be used in the same configuration where the Platform controls MCA Thresholding. However, the Platform will now be able to send the MCA Thresholding interrupt to the OS. Check for the feature bit in the MCA_CONFIG register and attempt to set up the MCA Thresholding interrupt handler. If successful, set the feature enable bit in the MCA_CONFIG register to indicate to the Platform that the OS is ready for the interrupt. Signed-off-by: Yazen Ghannam --- arch/x86/kernel/cpu/mce/amd.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 462ba9ff997b..9292096787ad 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -47,6 +47,7 @@ /* MCA Interrupt Configuration register, one per CPU */ #define MSR_CU_DEF_ERR 0xC0000410 #define MSR_MCA_INTR_CFG 0xC0000410 +#define INTR_CFG_THR_LVT_OFFSET GENMASK_ULL(15, 12) #define INTR_CFG_DFR_LVT_OFFSET GENMASK_ULL(7, 4) #define INTR_CFG_LEGACY_DFR_INTR_TYPE GENMASK_ULL(2, 1) #define INTR_TYPE_APIC 0x1 @@ -54,8 +55,10 @@ /* Scalable MCA: */ /* MCA_CONFIG register, one per MCA bank */ +#define CFG_CE_INT_EN BIT_ULL(40) #define CFG_DFR_INT_TYPE GENMASK_ULL(38, 37) #define CFG_MCAX_EN BIT_ULL(32) +#define CFG_CE_INT_PRESENT BIT_ULL(10) #define CFG_LSB_IN_STATUS BIT_ULL(8) #define CFG_DFR_INT_SUPP BIT_ULL(5) @@ -355,8 +358,19 @@ static void smca_set_misc_banks_map(unsigned int bank, unsigned int cpu) } +static bool smca_thr_handler_enabled(u64 mca_intr_cfg) +{ + u8 offset = FIELD_GET(INTR_CFG_THR_LVT_OFFSET, mca_intr_cfg); + + if (setup_APIC_eilvt(offset, THRESHOLD_APIC_VECTOR, APIC_EILVT_MSG_FIX, 0)) + return false; + + mce_threshold_vector = amd_mca_interrupt; + return true; +} + /* Set appropriate bits in MCA_CONFIG. */ -static void configure_smca(unsigned int bank) +static void configure_smca(unsigned int bank, u64 mca_intr_cfg) { u64 mca_config; @@ -391,6 +405,9 @@ static void configure_smca(unsigned int bank) if (FIELD_GET(CFG_LSB_IN_STATUS, mca_config)) this_cpu_ptr(mce_banks_array)[bank].lsb_in_status = true; + if (FIELD_GET(CFG_CE_INT_PRESENT, mca_config) && smca_thr_handler_enabled(mca_intr_cfg)) + mca_config |= FIELD_PREP(CFG_CE_INT_EN, 0x1); + wrmsrl(MSR_AMD64_SMCA_MCx_CONFIG(bank), mca_config); } @@ -783,7 +800,7 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c) if (mce_flags.smca) smca_configure_old(bank, cpu); - configure_smca(bank); + configure_smca(bank, mca_intr_cfg); disable_err_thresholding(c, bank); for (block = 0; block < NR_BLOCKS; ++block) { From patchwork Sat Nov 18 19:32:45 2023 Content-Type: text/plain; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BL6PEPF0001AB4A.mail.protection.outlook.com (10.167.242.68) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7025.12 via Frontend Transport; Sat, 18 Nov 2023 19:33:11 +0000 Received: from quartz-7b1chost.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Sat, 18 Nov 2023 13:33:09 -0600 From: Yazen Ghannam To: CC: , , , , , , , "Yazen Ghannam" Subject: [PATCH 17/20] x86/mce: Add wrapper for struct mce to export vendor specific info Date: Sat, 18 Nov 2023 13:32:45 -0600 Message-ID: <20231118193248.1296798-18-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231118193248.1296798-1-yazen.ghannam@amd.com> References: <20231118193248.1296798-1-yazen.ghannam@amd.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB4A:EE_|DS7PR12MB5911:EE_ X-MS-Office365-Filtering-Correlation-Id: 2b772cc5-dedc-4501-0c28-08dbe86d3350 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Nov 2023 19:33:11.2707 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2b772cc5-dedc-4501-0c28-08dbe86d3350 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB4A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB5911 From: Avadhut Naik Currently, exporting new additional machine check error information involves adding new fields for the same at the end of the struct mce. This additional information can then be consumed through mcelog or tracepoint. However, as new MSRs are being added (and will be added in the future) by CPU vendors on their newer CPUs with additional machine check error information to be exported, the size of struct mce will balloon on some CPUs, unnecessarily, since those fields are vendor-specific. Moreover, different CPU vendors may export the additional information in varying sizes. The problem particularly intensifies since struct mce is exposed to userspace as part of UAPI. It's bloating through vendor-specific data should be avoided to limit the information being sent out to userspace. Add a new structure mce_hw_err to wrap the existing struct mce. The same will prevent its ballooning since vendor-specifc data, if any, can now be exported through a union within the wrapper structure and through __dynamic_array in mce_record tracepoint. Furthermore, new internal kernel fields can be added to the wrapper struct without impacting the user space API. Note: Some Checkpatch checks have been ignored to maintain coding style. [Yazen: Add last commit message paragraph. Rebase on other MCA updates.] Suggested-by: Borislav Petkov (AMD) Signed-off-by: Avadhut Naik Signed-off-by: Yazen Ghannam --- arch/x86/include/asm/mce.h | 6 +- arch/x86/kernel/cpu/mce/amd.c | 24 ++-- arch/x86/kernel/cpu/mce/apei.c | 48 ++++---- arch/x86/kernel/cpu/mce/core.c | 174 ++++++++++++++++------------- arch/x86/kernel/cpu/mce/genpool.c | 20 ++-- arch/x86/kernel/cpu/mce/inject.c | 4 +- arch/x86/kernel/cpu/mce/internal.h | 8 +- include/trace/events/mce.h | 38 +++---- 8 files changed, 178 insertions(+), 144 deletions(-) diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index 9441b89afee3..99eb72dd7d05 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -187,6 +187,10 @@ enum mce_notifier_prios { MCE_PRIO_HIGHEST = MCE_PRIO_CEC }; +struct mce_hw_err { + struct mce m; +}; + struct notifier_block; extern void mce_register_decode_chain(struct notifier_block *nb); extern void mce_unregister_decode_chain(struct notifier_block *nb); @@ -222,7 +226,7 @@ static inline int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info, #endif void mce_setup(struct mce *m); -void mce_log(struct mce *m); +void mce_log(struct mce_hw_err *err); DECLARE_PER_CPU(struct device *, mce_device); /* Maximum number of MCA banks per CPU. */ diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 9292096787ad..cd86da38463b 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -909,9 +909,9 @@ DEFINE_IDTENTRY_SYSVEC(sysvec_deferred_error) * 3) SMCA systems check MCA_DESTAT, if error was not found in MCA_STATUS, and * log it. */ -static void handle_smca_dfr_error(struct mce *m) +static void handle_smca_dfr_error(struct mce_hw_err *err) { - struct mce m_dfr; + struct mce_hw_err err_dfr; u64 mca_destat; /* Non-SMCA systems don't have MCA_DESTAT/MCA_DEADDR registers. */ @@ -919,26 +919,26 @@ static void handle_smca_dfr_error(struct mce *m) return; /* Clear MCA_DESTAT if the deferred error was logged from MCA_STATUS. */ - if (m->status & MCI_STATUS_DEFERRED) + if (err->m.status & MCI_STATUS_DEFERRED) goto out; /* MCA_STATUS didn't have a deferred error, so check MCA_DESTAT for one. */ - mca_destat = mce_rdmsrl(MSR_AMD64_SMCA_MCx_DESTAT(m->bank)); + mca_destat = mce_rdmsrl(MSR_AMD64_SMCA_MCx_DESTAT(err->m.bank)); if (!(mca_destat & MCI_STATUS_VAL)) return; /* Reuse the same data collected from machine_check_poll(). */ - memcpy(&m_dfr, m, sizeof(m_dfr)); + memcpy(&err_dfr, err, sizeof(err_dfr)); /* Save the MCA_DE{STAT,ADDR} values. */ - m_dfr.status = mca_destat; - m_dfr.addr = mce_rdmsrl(MSR_AMD64_SMCA_MCx_DEADDR(m_dfr.bank)); + err_dfr.m.status = mca_destat; + err_dfr.m.addr = mce_rdmsrl(MSR_AMD64_SMCA_MCx_DEADDR(err_dfr.m.bank)); - mce_log(&m_dfr); + mce_log(&err_dfr); out: - wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(m->bank), 0); + wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(err->m.bank), 0); } static void reset_block(struct threshold_block *block) @@ -997,10 +997,10 @@ static void amd_mca_interrupt(void) machine_check_poll(MCP_TIMESTAMP, this_cpu_ptr(&mce_poll_banks)); } -void amd_handle_error(struct mce *m) +void amd_handle_error(struct mce_hw_err *err) { - reset_thr_blocks(m->bank); - handle_smca_dfr_error(m); + reset_thr_blocks(err->m.bank); + handle_smca_dfr_error(err); } /* diff --git a/arch/x86/kernel/cpu/mce/apei.c b/arch/x86/kernel/cpu/mce/apei.c index 33cefe6157eb..4820f8677460 100644 --- a/arch/x86/kernel/cpu/mce/apei.c +++ b/arch/x86/kernel/cpu/mce/apei.c @@ -28,9 +28,12 @@ void apei_mce_report_mem_error(int severity, struct cper_sec_mem_err *mem_err) { - struct mce m; + struct mce_hw_err err; + struct mce *m = &err.m; int lsb; + memset(&err, 0, sizeof(struct mce_hw_err)); + if (!(mem_err->validation_bits & CPER_MEM_VALID_PA)) return; @@ -44,30 +47,33 @@ void apei_mce_report_mem_error(int severity, struct cper_sec_mem_err *mem_err) else lsb = PAGE_SHIFT; - mce_setup(&m); - m.bank = -1; + mce_setup(m); + m->bank = -1; /* Fake a memory read error with unknown channel */ - m.status = MCI_STATUS_VAL | MCI_STATUS_EN | MCI_STATUS_ADDRV | MCI_STATUS_MISCV | 0x9f; - m.misc = (MCI_MISC_ADDR_PHYS << 6) | lsb; + m->status = MCI_STATUS_VAL | MCI_STATUS_EN | MCI_STATUS_ADDRV | MCI_STATUS_MISCV | 0x9f; + m->misc = (MCI_MISC_ADDR_PHYS << 6) | lsb; if (severity >= GHES_SEV_RECOVERABLE) - m.status |= MCI_STATUS_UC; + m->status |= MCI_STATUS_UC; if (severity >= GHES_SEV_PANIC) { - m.status |= MCI_STATUS_PCC; - m.tsc = rdtsc(); + m->status |= MCI_STATUS_PCC; + m->tsc = rdtsc(); } - m.addr = mem_err->physical_addr; - mce_log(&m); + m->addr = mem_err->physical_addr; + mce_log(&err); } EXPORT_SYMBOL_GPL(apei_mce_report_mem_error); int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info, u64 lapic_id) { const u64 *i_mce = ((const u64 *) (ctx_info + 1)); + struct mce_hw_err err; + struct mce *m = &err.m; unsigned int cpu; - struct mce m; + + memset(&err, 0, sizeof(struct mce_hw_err)); if (!boot_cpu_has(X86_FEATURE_SMCA)) return -EINVAL; @@ -105,19 +111,19 @@ int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info, u64 lapic_id) if (!cpu_possible(cpu)) return -EINVAL; - mce_setup_global(&m); - m.cpu = m.extcpu = cpu; - mce_setup_per_cpu(&m); + mce_setup_global(m); + m->cpu = m->extcpu = cpu; + mce_setup_per_cpu(m); - m.bank = (ctx_info->msr_addr >> 4) & 0xFF; - m.status = *i_mce; - m.addr = *(i_mce + 1); - m.misc = *(i_mce + 2); + m->bank = (ctx_info->msr_addr >> 4) & 0xFF; + m->status = *i_mce; + m->addr = *(i_mce + 1); + m->misc = *(i_mce + 2); /* Skipping MCA_CONFIG */ - m.ipid = *(i_mce + 4); - m.synd = *(i_mce + 5); + m->ipid = *(i_mce + 4); + m->synd = *(i_mce + 5); - mce_log(&m); + mce_log(&err); return 0; } diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index bdbc32f10a9a..8db8ed34b200 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -86,7 +86,7 @@ struct mca_config mca_cfg __read_mostly = { .monarch_timeout = -1 }; -static DEFINE_PER_CPU(struct mce, mces_seen); +static DEFINE_PER_CPU(struct mce_hw_err, hw_errs_seen); static unsigned long mce_need_notify; /* @@ -145,9 +145,9 @@ void mce_setup(struct mce *m) DEFINE_PER_CPU(struct mce, injectm); EXPORT_PER_CPU_SYMBOL_GPL(injectm); -void mce_log(struct mce *m) +void mce_log(struct mce_hw_err *err) { - if (!mce_gen_pool_add(m)) + if (!mce_gen_pool_add(err)) irq_work_queue(&mce_irq_work); } EXPORT_SYMBOL_GPL(mce_log); @@ -168,8 +168,10 @@ void mce_unregister_decode_chain(struct notifier_block *nb) } EXPORT_SYMBOL_GPL(mce_unregister_decode_chain); -static void __print_mce(struct mce *m) +static void __print_mce(struct mce_hw_err *err) { + struct mce *m = &err->m; + pr_emerg(HW_ERR "CPU %d: Machine Check%s: %Lx Bank %d: %016Lx\n", m->extcpu, (m->mcgstatus & MCG_STATUS_MCIP ? " Exception" : ""), @@ -211,9 +213,11 @@ static void __print_mce(struct mce *m) m->microcode); } -static void print_mce(struct mce *m) +static void print_mce(struct mce_hw_err *err) { - __print_mce(m); + struct mce *m = &err->m; + + __print_mce(err); if (m->cpuvendor != X86_VENDOR_AMD && m->cpuvendor != X86_VENDOR_HYGON) pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n"); @@ -240,7 +244,7 @@ static void wait_for_panic(void) panic("Panicing machine check CPU died"); } -static noinstr void mce_panic(const char *msg, struct mce *final, char *exp) +static noinstr void mce_panic(const char *msg, struct mce_hw_err *final, char *exp) { struct llist_node *pending; struct mce_evt_llist *l; @@ -271,20 +275,22 @@ static noinstr void mce_panic(const char *msg, struct mce *final, char *exp) pending = mce_gen_pool_prepare_records(); /* First print corrected ones that are still unlogged */ llist_for_each_entry(l, pending, llnode) { - struct mce *m = &l->mce; + struct mce_hw_err *err = &l->err; + struct mce *m = &err->m; if (!(m->status & MCI_STATUS_UC)) { - print_mce(m); + print_mce(err); if (!apei_err) apei_err = apei_write_mce(m); } } /* Now print uncorrected but with the final one last */ llist_for_each_entry(l, pending, llnode) { - struct mce *m = &l->mce; + struct mce_hw_err *err = &l->err; + struct mce *m = &err->m; if (!(m->status & MCI_STATUS_UC)) continue; - if (!final || mce_cmp(m, final)) { - print_mce(m); + if (!final || mce_cmp(m, &final->m)) { + print_mce(err); if (!apei_err) apei_err = apei_write_mce(m); } @@ -292,7 +298,7 @@ static noinstr void mce_panic(const char *msg, struct mce *final, char *exp) if (final) { print_mce(final); if (!apei_err) - apei_err = apei_write_mce(final); + apei_err = apei_write_mce(&final->m); } if (exp) pr_emerg(HW_ERR "Machine check: %s\n", exp); @@ -307,8 +313,8 @@ static noinstr void mce_panic(const char *msg, struct mce *final, char *exp) * panic. */ if (kexec_crash_loaded()) { - if (final && (final->status & MCI_STATUS_ADDRV)) { - p = pfn_to_online_page(final->addr >> PAGE_SHIFT); + if (final && (final->m.status & MCI_STATUS_ADDRV)) { + p = pfn_to_online_page(final->m.addr >> PAGE_SHIFT); if (p) SetPageHWPoison(p); } @@ -557,13 +563,13 @@ EXPORT_SYMBOL_GPL(mce_is_correctable); static int mce_early_notifier(struct notifier_block *nb, unsigned long val, void *data) { - struct mce *m = (struct mce *)data; + struct mce_hw_err *err = (struct mce_hw_err *)data; - if (!m) + if (!err) return NOTIFY_DONE; /* Emit the trace record: */ - trace_mce_record(m); + trace_mce_record(err); set_bit(0, &mce_need_notify); @@ -607,13 +613,13 @@ static struct notifier_block mce_uc_nb = { static int mce_default_notifier(struct notifier_block *nb, unsigned long val, void *data) { - struct mce *m = (struct mce *)data; + struct mce_hw_err *err = (struct mce_hw_err *)data; - if (!m) + if (!err) return NOTIFY_DONE; - if (mca_cfg.print_all || !m->kflags) - __print_mce(m); + if (mca_cfg.print_all || !(err->m.kflags)) + __print_mce(err); return NOTIFY_DONE; } @@ -655,10 +661,10 @@ static noinstr void mce_read_aux(struct mce *m, int i) } } -static void vendor_handle_error(struct mce *m) +static void vendor_handle_error(struct mce_hw_err *err) { if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) - return amd_handle_error(m); + return amd_handle_error(err); } DEFINE_PER_CPU(unsigned, mce_poll_count); @@ -690,31 +696,34 @@ bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b) { struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); bool error_seen = false; - struct mce m; + struct mce_hw_err err; + struct mce *m = &err.m; int i; + memset(&err, 0, sizeof(struct mce_hw_err)); + this_cpu_inc(mce_poll_count); - mce_gather_info(&m, NULL); + mce_gather_info(m, NULL); if (flags & MCP_TIMESTAMP) - m.tsc = rdtsc(); + m->tsc = rdtsc(); for (i = 0; i < this_cpu_read(mce_num_banks); i++) { if (!mce_banks[i].ctl || !test_bit(i, *b)) continue; - m.misc = 0; - m.addr = 0; - m.bank = i; + m->misc = 0; + m->addr = 0; + m->bank = i; barrier(); - m.status = mce_rdmsrl(mca_msr_reg(i, MCA_STATUS)); + m->status = mce_rdmsrl(mca_msr_reg(i, MCA_STATUS)); /* If this entry is not valid, ignore it */ - if (!(m.status & MCI_STATUS_VAL)) { + if (!(m->status & MCI_STATUS_VAL)) { if (smca_destat_is_valid(i)) { - mce_read_aux(&m, i); + mce_read_aux(m, i); goto clear_it; } @@ -725,7 +734,7 @@ bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b) * If we are logging everything (at CPU online) or this * is a corrected error, then we must log it. */ - if ((flags & MCP_UC) || !(m.status & MCI_STATUS_UC)) + if ((flags & MCP_UC) || !(m->status & MCI_STATUS_UC)) goto log_it; /* @@ -735,20 +744,20 @@ bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b) * everything else. */ if (!mca_cfg.ser) { - if (m.status & MCI_STATUS_UC) + if (m->status & MCI_STATUS_UC) continue; goto log_it; } /* Log "not enabled" (speculative) errors */ - if (!(m.status & MCI_STATUS_EN)) + if (!(m->status & MCI_STATUS_EN)) goto log_it; /* * Log UCNA (SDM: 15.6.3 "UCR Error Classification") * UC == 1 && PCC == 0 && S == 0 */ - if (!(m.status & MCI_STATUS_PCC) && !(m.status & MCI_STATUS_S)) + if (!(m->status & MCI_STATUS_PCC) && !(m->status & MCI_STATUS_S)) goto log_it; /* @@ -764,23 +773,24 @@ bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b) if (flags & MCP_DONTLOG) goto clear_it; - mce_read_aux(&m, i); - m.severity = mce_severity(&m, NULL, NULL, false); + mce_read_aux(m, i); + m->severity = mce_severity(m, NULL, NULL, false); + /* * Don't get the IP here because it's unlikely to * have anything to do with the actual error location. */ - if (mca_cfg.dont_log_ce && !mce_usable_address(&m)) + if (mca_cfg.dont_log_ce && !mce_usable_address(m)) goto clear_it; if (flags & MCP_QUEUE_LOG) - mce_gen_pool_add(&m); + mce_gen_pool_add(&err); else - mce_log(&m); + mce_log(&err); clear_it: - vendor_handle_error(&m); + vendor_handle_error(&err); /* * Clear state for this bank. @@ -1017,6 +1027,7 @@ static noinstr int mce_timed_out(u64 *t, const char *msg) static void mce_reign(void) { int cpu; + struct mce_hw_err *err = NULL; struct mce *m = NULL; int global_worst = 0; char *msg = NULL; @@ -1027,11 +1038,13 @@ static void mce_reign(void) * Grade the severity of the errors of all the CPUs. */ for_each_possible_cpu(cpu) { - struct mce *mtmp = &per_cpu(mces_seen, cpu); + struct mce_hw_err *etmp = &per_cpu(hw_errs_seen, cpu); + struct mce *mtmp = &etmp->m; if (mtmp->severity > global_worst) { global_worst = mtmp->severity; - m = &per_cpu(mces_seen, cpu); + err = &per_cpu(hw_errs_seen, cpu); + m = &err->m; } } @@ -1043,7 +1056,7 @@ static void mce_reign(void) if (m && global_worst >= MCE_PANIC_SEVERITY) { /* call mce_severity() to get "msg" for panic */ mce_severity(m, NULL, &msg, true); - mce_panic("Fatal machine check", m, msg); + mce_panic("Fatal machine check", err, msg); } /* @@ -1060,11 +1073,11 @@ static void mce_reign(void) mce_panic("Fatal machine check from unknown source", NULL, NULL); /* - * Now clear all the mces_seen so that they don't reappear on + * Now clear all the hw_errs_seen so that they don't reappear on * the next mce. */ for_each_possible_cpu(cpu) - memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce)); + memset(&per_cpu(hw_errs_seen, cpu), 0, sizeof(struct mce_hw_err)); } static atomic_t global_nwo; @@ -1268,12 +1281,13 @@ static noinstr bool mce_check_crashing_cpu(void) } static __always_inline int -__mc_scan_banks(struct mce *m, struct pt_regs *regs, struct mce *final, +__mc_scan_banks(struct mce_hw_err *err, struct pt_regs *regs, struct mce *final, unsigned long *toclear, unsigned long *valid_banks, int no_way_out, int *worst) { struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); struct mca_config *cfg = &mca_cfg; + struct mce *m = &err->m; int severity, i, taint = 0; for (i = 0; i < this_cpu_read(mce_num_banks); i++) { @@ -1329,7 +1343,7 @@ __mc_scan_banks(struct mce *m, struct pt_regs *regs, struct mce *final, * done in #MC context, where instrumentation is disabled. */ instrumentation_begin(); - mce_log(m); + mce_log(err); instrumentation_end(); if (severity > *worst) { @@ -1399,8 +1413,9 @@ static void kill_me_never(struct callback_head *cb) set_mce_nospec(pfn); } -static void queue_task_work(struct mce *m, char *msg, void (*func)(struct callback_head *)) +static void queue_task_work(struct mce_hw_err *err, char *msg, void (*func)(struct callback_head *)) { + struct mce *m = &err->m; int count = ++current->mce_count; /* First call, save all the details */ @@ -1414,11 +1429,12 @@ static void queue_task_work(struct mce *m, char *msg, void (*func)(struct callba /* Ten is likely overkill. Don't expect more than two faults before task_work() */ if (count > 10) - mce_panic("Too many consecutive machine checks while accessing user data", m, msg); + mce_panic("Too many consecutive machine checks while accessing user data", + err, msg); /* Second or later call, make sure page address matches the one from first call */ if (count > 1 && (current->mce_addr >> PAGE_SHIFT) != (m->addr >> PAGE_SHIFT)) - mce_panic("Consecutive machine checks to different user pages", m, msg); + mce_panic("Consecutive machine checks to different user pages", err, msg); /* Do not call task_work_add() more than once */ if (count > 1) @@ -1467,8 +1483,14 @@ noinstr void do_machine_check(struct pt_regs *regs) int worst = 0, order, no_way_out, kill_current_task, lmce, taint = 0; DECLARE_BITMAP(valid_banks, MAX_NR_BANKS) = { 0 }; DECLARE_BITMAP(toclear, MAX_NR_BANKS) = { 0 }; - struct mce m, *final; + struct mce_hw_err *final; + struct mce_hw_err err; char *msg = NULL; + struct mce *m; + + memset(&err, 0, sizeof(struct mce_hw_err)); + + m = &err.m; if (unlikely(mce_flags.p5)) return pentium_machine_check(regs); @@ -1506,13 +1528,13 @@ noinstr void do_machine_check(struct pt_regs *regs) this_cpu_inc(mce_exception_count); - mce_gather_info(&m, regs); - m.tsc = rdtsc(); + mce_gather_info(m, regs); + m->tsc = rdtsc(); - final = this_cpu_ptr(&mces_seen); - *final = m; + final = this_cpu_ptr(&hw_errs_seen); + final->m = *m; - no_way_out = mce_no_way_out(&m, &msg, valid_banks, regs); + no_way_out = mce_no_way_out(m, &msg, valid_banks, regs); barrier(); @@ -1521,15 +1543,15 @@ noinstr void do_machine_check(struct pt_regs *regs) * Assume the worst for now, but if we find the * severity is MCE_AR_SEVERITY we have other options. */ - if (!(m.mcgstatus & MCG_STATUS_RIPV)) + if (!(m->mcgstatus & MCG_STATUS_RIPV)) kill_current_task = 1; /* * Check if this MCE is signaled to only this logical processor, * on Intel, Zhaoxin only. */ - if (m.cpuvendor == X86_VENDOR_INTEL || - m.cpuvendor == X86_VENDOR_ZHAOXIN) - lmce = m.mcgstatus & MCG_STATUS_LMCES; + if (m->cpuvendor == X86_VENDOR_INTEL || + m->cpuvendor == X86_VENDOR_ZHAOXIN) + lmce = m->mcgstatus & MCG_STATUS_LMCES; /* * Local machine check may already know that we have to panic. @@ -1540,12 +1562,12 @@ noinstr void do_machine_check(struct pt_regs *regs) */ if (lmce) { if (no_way_out) - mce_panic("Fatal local machine check", &m, msg); + mce_panic("Fatal local machine check", &err, msg); } else { order = mce_start(&no_way_out); } - taint = __mc_scan_banks(&m, regs, final, toclear, valid_banks, no_way_out, &worst); + taint = __mc_scan_banks(&err, regs, &final->m, toclear, valid_banks, no_way_out, &worst); if (!no_way_out) mce_clear_state(toclear); @@ -1560,7 +1582,7 @@ noinstr void do_machine_check(struct pt_regs *regs) no_way_out = worst >= MCE_PANIC_SEVERITY; if (no_way_out) - mce_panic("Fatal machine check on current CPU", &m, msg); + mce_panic("Fatal machine check on current CPU", &err, msg); } } else { /* @@ -1572,8 +1594,8 @@ noinstr void do_machine_check(struct pt_regs *regs) * make sure we have the right "msg". */ if (worst >= MCE_PANIC_SEVERITY) { - mce_severity(&m, regs, &msg, true); - mce_panic("Local fatal machine check!", &m, msg); + mce_severity(m, regs, &msg, true); + mce_panic("Local fatal machine check!", &err, msg); } } @@ -1591,14 +1613,14 @@ noinstr void do_machine_check(struct pt_regs *regs) goto out; /* Fault was in user mode and we need to take some action */ - if ((m.cs & 3) == 3) { + if ((m->cs & 3) == 3) { /* If this triggers there is no way to recover. Die hard. */ BUG_ON(!on_thread_stack() || !user_mode(regs)); - if (!mce_usable_address(&m)) - queue_task_work(&m, msg, kill_me_now); + if (!mce_usable_address(m)) + queue_task_work(&err, msg, kill_me_now); else - queue_task_work(&m, msg, kill_me_maybe); + queue_task_work(&err, msg, kill_me_maybe); } else { /* @@ -1610,13 +1632,13 @@ noinstr void do_machine_check(struct pt_regs *regs) * corresponding exception handler which would do that is the * proper one. */ - if (m.kflags & MCE_IN_KERNEL_RECOV) { + if (m->kflags & MCE_IN_KERNEL_RECOV) { if (!fixup_exception(regs, X86_TRAP_MC, 0, 0)) - mce_panic("Failed kernel mode recovery", &m, msg); + mce_panic("Failed kernel mode recovery", &err, msg); } - if (m.kflags & MCE_IN_KERNEL_COPYIN) - queue_task_work(&m, msg, kill_me_never); + if (m->kflags & MCE_IN_KERNEL_COPYIN) + queue_task_work(&err, msg, kill_me_never); } out: diff --git a/arch/x86/kernel/cpu/mce/genpool.c b/arch/x86/kernel/cpu/mce/genpool.c index fbe8b61c3413..9a497234ad22 100644 --- a/arch/x86/kernel/cpu/mce/genpool.c +++ b/arch/x86/kernel/cpu/mce/genpool.c @@ -31,15 +31,15 @@ static char gen_pool_buf[MCE_POOLSZ]; */ static bool is_duplicate_mce_record(struct mce_evt_llist *t, struct mce_evt_llist *l) { + struct mce_hw_err *err1, *err2; struct mce_evt_llist *node; - struct mce *m1, *m2; - m1 = &t->mce; + err1 = &t->err; llist_for_each_entry(node, &l->llnode, llnode) { - m2 = &node->mce; + err2 = &node->err; - if (!mce_cmp(m1, m2)) + if (!mce_cmp(&err1->m, &err2->m)) return true; } return false; @@ -73,9 +73,9 @@ struct llist_node *mce_gen_pool_prepare_records(void) void mce_gen_pool_process(struct work_struct *__unused) { + struct mce_hw_err *err; struct llist_node *head; struct mce_evt_llist *node, *tmp; - struct mce *mce; head = llist_del_all(&mce_event_llist); if (!head) @@ -83,8 +83,8 @@ void mce_gen_pool_process(struct work_struct *__unused) head = llist_reverse_order(head); llist_for_each_entry_safe(node, tmp, head, llnode) { - mce = &node->mce; - blocking_notifier_call_chain(&x86_mce_decoder_chain, 0, mce); + err = &node->err; + blocking_notifier_call_chain(&x86_mce_decoder_chain, 0, err); gen_pool_free(mce_evt_pool, (unsigned long)node, sizeof(*node)); } } @@ -94,11 +94,11 @@ bool mce_gen_pool_empty(void) return llist_empty(&mce_event_llist); } -int mce_gen_pool_add(struct mce *mce) +int mce_gen_pool_add(struct mce_hw_err *err) { struct mce_evt_llist *node; - if (filter_mce(mce)) + if (filter_mce(&err->m)) return -EINVAL; if (!mce_evt_pool) @@ -110,7 +110,7 @@ int mce_gen_pool_add(struct mce *mce) return -ENOMEM; } - memcpy(&node->mce, mce, sizeof(*mce)); + memcpy(&node->err, err, sizeof(*err)); llist_add(&node->llnode, &mce_event_llist); return 0; diff --git a/arch/x86/kernel/cpu/mce/inject.c b/arch/x86/kernel/cpu/mce/inject.c index 72f0695c3dc1..3b064a2bb247 100644 --- a/arch/x86/kernel/cpu/mce/inject.c +++ b/arch/x86/kernel/cpu/mce/inject.c @@ -500,6 +500,7 @@ static void prepare_msrs(void *info) static void do_inject(void) { + struct mce_hw_err err; u64 mcg_status = 0; unsigned int cpu = i_mce.extcpu; u8 b = i_mce.bank; @@ -515,7 +516,8 @@ static void do_inject(void) i_mce.status |= MCI_STATUS_SYNDV; if (inj_type == SW_INJ) { - mce_log(&i_mce); + err.m = i_mce; + mce_log(&err); return; } diff --git a/arch/x86/kernel/cpu/mce/internal.h b/arch/x86/kernel/cpu/mce/internal.h index fca7499e1bf4..e74e142d4703 100644 --- a/arch/x86/kernel/cpu/mce/internal.h +++ b/arch/x86/kernel/cpu/mce/internal.h @@ -26,12 +26,12 @@ extern struct blocking_notifier_head x86_mce_decoder_chain; struct mce_evt_llist { struct llist_node llnode; - struct mce mce; + struct mce_hw_err err; }; void mce_gen_pool_process(struct work_struct *__unused); bool mce_gen_pool_empty(void); -int mce_gen_pool_add(struct mce *mce); +int mce_gen_pool_add(struct mce_hw_err *err); int mce_gen_pool_init(void); struct llist_node *mce_gen_pool_prepare_records(void); @@ -212,7 +212,7 @@ void mce_setup_per_cpu(struct mce *m); #ifdef CONFIG_X86_MCE_AMD extern bool amd_filter_mce(struct mce *m); bool amd_mce_usable_address(struct mce *m); -void amd_handle_error(struct mce *m); +void amd_handle_error(struct mce_hw_err *err); /* * If MCA_CONFIG[McaLsbInStatusSupported] is set, extract ErrAddr in bits @@ -241,7 +241,7 @@ static __always_inline void smca_extract_err_addr(struct mce *m) #else static inline bool amd_filter_mce(struct mce *m) { return false; } static inline bool amd_mce_usable_address(struct mce *m) { return false; } -static inline void amd_handle_error(struct mce *m) { } +static inline void amd_handle_error(struct mce_hw_err *err) { } static inline void smca_extract_err_addr(struct mce *m) { } #endif diff --git a/include/trace/events/mce.h b/include/trace/events/mce.h index 1391ada0da3b..b093cb28f6dd 100644 --- a/include/trace/events/mce.h +++ b/include/trace/events/mce.h @@ -11,9 +11,9 @@ TRACE_EVENT(mce_record, - TP_PROTO(struct mce *m), + TP_PROTO(struct mce_hw_err *err), - TP_ARGS(m), + TP_ARGS(err), TP_STRUCT__entry( __field( u64, mcgcap ) @@ -36,23 +36,23 @@ TRACE_EVENT(mce_record, ), TP_fast_assign( - __entry->mcgcap = m->mcgcap; - __entry->mcgstatus = m->mcgstatus; - __entry->status = m->status; - __entry->addr = m->addr; - __entry->misc = m->misc; - __entry->synd = m->synd; - __entry->ipid = m->ipid; - __entry->ip = m->ip; - __entry->tsc = m->tsc; - __entry->walltime = m->time; - __entry->cpu = m->extcpu; - __entry->cpuid = m->cpuid; - __entry->apicid = m->apicid; - __entry->socketid = m->socketid; - __entry->cs = m->cs; - __entry->bank = m->bank; - __entry->cpuvendor = m->cpuvendor; + __entry->mcgcap = err->m.mcgcap; + __entry->mcgstatus = err->m.mcgstatus; + __entry->status = err->m.status; + __entry->addr = err->m.addr; + __entry->misc = err->m.misc; + __entry->synd = err->m.synd; + __entry->ipid = err->m.ipid; + __entry->ip = err->m.ip; + __entry->tsc = err->m.tsc; + __entry->walltime = err->m.time; + __entry->cpu = err->m.extcpu; + __entry->cpuid = err->m.cpuid; + __entry->apicid = err->m.apicid; + __entry->socketid = err->m.socketid; + __entry->cs = err->m.cs; + __entry->bank = err->m.bank; + __entry->cpuvendor = err->m.cpuvendor; ), TP_printk("CPU: %d, MCGc/s: %llx/%llx, MC%d: %016Lx, IPID: %016Lx, ADDR/MISC/SYND: %016Lx/%016Lx/%016Lx, RIP: %02x:<%016Lx>, TSC: %llx, PROCESSOR: %u:%x, TIME: %llu, SOCKET: %u, APIC: %x", From patchwork Sat Nov 18 19:32:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 13460267 Authentication-Results: smtp.subspace.kernel.org; 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Sat, 18 Nov 2023 13:33:10 -0600 From: Yazen Ghannam To: CC: , , , , , , , "Yazen Ghannam" Subject: [PATCH 18/20] x86/mce, EDAC/mce_amd: Add support for new MCA_SYND{1,2} registers Date: Sat, 18 Nov 2023 13:32:46 -0600 Message-ID: <20231118193248.1296798-19-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231118193248.1296798-1-yazen.ghannam@amd.com> References: <20231118193248.1296798-1-yazen.ghannam@amd.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB4A:EE_|SA0PR12MB4526:EE_ X-MS-Office365-Filtering-Correlation-Id: 96ddd959-26a4-41cd-914f-08dbe86d33b6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: rmZethfCO+3wCn/T5nhVbyxxmL52baJFqTTkph1T1tg/m4R/OdWnGbaTpotCuqiHvIULi6gPydWt+XAzeTqQUX9iMJFoDYP3XQAERq2wTT3qw1OXFz1ZCYBL72gj+SGEV34yGmQCbd+pXg5D4CchNAhGHadGDRDGD9r7a4gDh48NMF3wYwfumXuzwNwlpYf/yeKUQ7lZHRjced6MwdSnrGdptmQ8Bx7W8s13C9PBuWEsnQLC5mzj9BdnpHoEBiU7NFBEoBrsZhYYjiye5PN8fSgSbtmmZsZxaUHKhTTSupu3/XNaZ5etyd40fjzWkjMmuIh+BglzIjj8RUZoC/ZYhZV1NcHuqthzqAC5RtshWx3Oe5lo1UKDOqrebQ6M5WWt/S21OCDJKYLwz3oMXUO+UgSqhhYdFgCFETSpsw6NS484MsIGdvpnciMBiDaXlWPUiH8NzZ0GS8wMaJzRkoJUDJps/eFfqBgrbRyQSZruGLMLINOTUWLrWQm5iNPPIK/zeIN7gfscgxM1K4qxkdAAuVtJLZIV6nGVOgayQz97YwRvS36R/qNddj856YUXZk73j1N+IS6t7Q+PC4gU0phnIwdEeS6QCHq3pH+i4MvwyFMMA54ihgSpyk83knmrDBMxNGGMAh+PXCwdqssXywSDu4Yxp+DY4pVAFimcIF0khLUS18D7CujQuX7oM+SWekdgfSDpaffHsuez/3nJ1RYNU4a0YfxuRBT4GRpvITMxp6ZfiBiJYINsHfQyJEWtRqv0mfOXhzVqxLh02aQpNxEMPn7OUX7pDEBAs8lRkmAnUJCm8OiKBzHTzVM5OlN99OEu X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(396003)(39860400002)(136003)(376002)(346002)(230173577357003)(230922051799003)(230273577357003)(451199024)(64100799003)(186009)(1800799012)(82310400011)(36840700001)(46966006)(40470700004)(40460700003)(70206006)(70586007)(54906003)(6916009)(316002)(36860700001)(36756003)(6666004)(7696005)(426003)(336012)(2616005)(26005)(16526019)(1076003)(478600001)(82740400003)(81166007)(356005)(83380400001)(86362001)(47076005)(44832011)(40480700001)(2906002)(5660300002)(4326008)(8676002)(8936002)(41300700001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Nov 2023 19:33:11.9426 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 96ddd959-26a4-41cd-914f-08dbe86d33b6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB4A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4526 From: Avadhut Naik AMD's Scalable MCA systems viz. Genoa will include two new registers: MCA_SYND1 and MCA_SYND2. These registers will include supplemental error information in addition to the existing MCA_SYND register. The data within the registers is considered valid if MCA_STATUS[SyndV] is set. Add fields for these registers as vendor-specific error information in struct mce_hw_err. Save and print these registers wherever MCA_STATUS[SyndV]/MCA_SYND is currently used. Also, modify the mce_record tracepoint to export these new registers through __dynamic_array. While the sizeof() operator has been used to determine the size of this __dynamic_array, the same, if needed in the future can be substituted by caching the size of vendor-specific error information as part of struct mce_hw_err. Note: Checkpatch warnings/errors are ignored to maintain coding style. [Yazen: Drop Yazen's Co-developed-by tag and moved SoB tag.] [Yazen: Change %Lx to %llx in TP_printk().] Signed-off-by: Avadhut Naik Signed-off-by: Yazen Ghannam --- arch/x86/include/asm/mce.h | 12 ++++++++++++ arch/x86/kernel/cpu/mce/core.c | 26 ++++++++++++++++++-------- drivers/edac/mce_amd.c | 10 +++++++--- include/trace/events/mce.h | 9 +++++++-- 4 files changed, 44 insertions(+), 13 deletions(-) diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index 99eb72dd7d05..1bd3f1e41dbb 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -122,6 +122,9 @@ #define MSR_AMD64_SMCA_MC0_DESTAT 0xc0002008 #define MSR_AMD64_SMCA_MC0_DEADDR 0xc0002009 #define MSR_AMD64_SMCA_MC0_MISC1 0xc000200a +/* Registers MISC2 to MISC4 are at offsets B to D. */ +#define MSR_AMD64_SMCA_MC0_SYND1 0xc000200e +#define MSR_AMD64_SMCA_MC0_SYND2 0xc000200f #define MSR_AMD64_SMCA_MCx_CTL(x) (MSR_AMD64_SMCA_MC0_CTL + 0x10*(x)) #define MSR_AMD64_SMCA_MCx_STATUS(x) (MSR_AMD64_SMCA_MC0_STATUS + 0x10*(x)) #define MSR_AMD64_SMCA_MCx_ADDR(x) (MSR_AMD64_SMCA_MC0_ADDR + 0x10*(x)) @@ -132,6 +135,8 @@ #define MSR_AMD64_SMCA_MCx_DESTAT(x) (MSR_AMD64_SMCA_MC0_DESTAT + 0x10*(x)) #define MSR_AMD64_SMCA_MCx_DEADDR(x) (MSR_AMD64_SMCA_MC0_DEADDR + 0x10*(x)) #define MSR_AMD64_SMCA_MCx_MISCy(x, y) ((MSR_AMD64_SMCA_MC0_MISC1 + y) + (0x10*(x))) +#define MSR_AMD64_SMCA_MCx_SYND1(x) (MSR_AMD64_SMCA_MC0_SYND1 + 0x10*(x)) +#define MSR_AMD64_SMCA_MCx_SYND2(x) (MSR_AMD64_SMCA_MC0_SYND2 + 0x10*(x)) #define XEC(x, mask) (((x) >> 16) & mask) @@ -189,6 +194,13 @@ enum mce_notifier_prios { struct mce_hw_err { struct mce m; + + union vendor_info { + struct { + u64 synd1; + u64 synd2; + } amd; + } vi; }; struct notifier_block; diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 8db8ed34b200..e153a21bdb1b 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -198,6 +198,10 @@ static void __print_mce(struct mce_hw_err *err) if (mce_flags.smca) { if (m->synd) pr_cont("SYND %llx ", m->synd); + if (err->vi.amd.synd1) + pr_cont("SYND1 %llx ", err->vi.amd.synd1); + if (err->vi.amd.synd2) + pr_cont("SYND2 %llx ", err->vi.amd.synd2); if (m->ipid) pr_cont("IPID %llx ", m->ipid); } @@ -633,8 +637,10 @@ static struct notifier_block mce_default_nb = { /* * Read ADDR and MISC registers. */ -static noinstr void mce_read_aux(struct mce *m, int i) +static noinstr void mce_read_aux(struct mce_hw_err *err, int i) { + struct mce *m = &err->m; + if (m->status & MCI_STATUS_MISCV) m->misc = mce_rdmsrl(mca_msr_reg(i, MCA_MISC)); @@ -656,8 +662,11 @@ static noinstr void mce_read_aux(struct mce *m, int i) if (mce_flags.smca) { m->ipid = mce_rdmsrl(MSR_AMD64_SMCA_MCx_IPID(i)); - if (m->status & MCI_STATUS_SYNDV) + if (m->status & MCI_STATUS_SYNDV) { m->synd = mce_rdmsrl(MSR_AMD64_SMCA_MCx_SYND(i)); + err->vi.amd.synd1 = mce_rdmsrl(MSR_AMD64_SMCA_MCx_SYND1(i)); + err->vi.amd.synd2 = mce_rdmsrl(MSR_AMD64_SMCA_MCx_SYND2(i)); + } } } @@ -723,7 +732,7 @@ bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b) /* If this entry is not valid, ignore it */ if (!(m->status & MCI_STATUS_VAL)) { if (smca_destat_is_valid(i)) { - mce_read_aux(m, i); + mce_read_aux(&err, i); goto clear_it; } @@ -773,7 +782,7 @@ bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b) if (flags & MCP_DONTLOG) goto clear_it; - mce_read_aux(m, i); + mce_read_aux(&err, i); m->severity = mce_severity(m, NULL, NULL, false); /* @@ -915,9 +924,10 @@ static __always_inline void quirk_zen_ifu(int bank, struct mce *m, struct pt_reg * Do a quick check if any of the events requires a panic. * This decides if we keep the events around or clear them. */ -static __always_inline int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp, +static __always_inline int mce_no_way_out(struct mce_hw_err *err, char **msg, unsigned long *validp, struct pt_regs *regs) { + struct mce *m = &err->m; char *tmp = *msg; int i; @@ -935,7 +945,7 @@ static __always_inline int mce_no_way_out(struct mce *m, char **msg, unsigned lo m->bank = i; if (mce_severity(m, regs, &tmp, true) >= MCE_PANIC_SEVERITY) { - mce_read_aux(m, i); + mce_read_aux(err, i); *msg = tmp; return 1; } @@ -1333,7 +1343,7 @@ __mc_scan_banks(struct mce_hw_err *err, struct pt_regs *regs, struct mce *final, if (severity == MCE_NO_SEVERITY) continue; - mce_read_aux(m, i); + mce_read_aux(err, i); /* assuming valid severity level != 0 */ m->severity = severity; @@ -1534,7 +1544,7 @@ noinstr void do_machine_check(struct pt_regs *regs) final = this_cpu_ptr(&hw_errs_seen); final->m = *m; - no_way_out = mce_no_way_out(m, &msg, valid_banks, regs); + no_way_out = mce_no_way_out(&err, &msg, valid_banks, regs); barrier(); diff --git a/drivers/edac/mce_amd.c b/drivers/edac/mce_amd.c index 701bc9556414..4d2929770620 100644 --- a/drivers/edac/mce_amd.c +++ b/drivers/edac/mce_amd.c @@ -1275,7 +1275,8 @@ static const char *decode_error_status(struct mce *m) static int amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data) { - struct mce *m = (struct mce *)data; + struct mce_hw_err *err = (struct mce_hw_err *)data; + struct mce *m = &err->m; unsigned int fam = x86_family(m->cpuid); int ecc; @@ -1333,8 +1334,11 @@ amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data) if (boot_cpu_has(X86_FEATURE_SMCA)) { pr_emerg(HW_ERR "IPID: 0x%016llx", m->ipid); - if (m->status & MCI_STATUS_SYNDV) - pr_cont(", Syndrome: 0x%016llx", m->synd); + if (m->status & MCI_STATUS_SYNDV) { + pr_cont(", Syndrome: 0x%016llx\n", m->synd); + pr_emerg(HW_ERR "Syndrome1: 0x%016llx, Syndrome2: 0x%016llx", + err->vi.amd.synd1, err->vi.amd.synd2); + } pr_cont("\n"); diff --git a/include/trace/events/mce.h b/include/trace/events/mce.h index b093cb28f6dd..29d079961aac 100644 --- a/include/trace/events/mce.h +++ b/include/trace/events/mce.h @@ -33,6 +33,8 @@ TRACE_EVENT(mce_record, __field( u8, cs ) __field( u8, bank ) __field( u8, cpuvendor ) + __field( u8, len ) + __dynamic_array(u8, v_data, sizeof(err->vi)) ), TP_fast_assign( @@ -53,9 +55,11 @@ TRACE_EVENT(mce_record, __entry->cs = err->m.cs; __entry->bank = err->m.bank; __entry->cpuvendor = err->m.cpuvendor; + __entry->len = sizeof(err->vi); + memcpy(__get_dynamic_array(v_data), &err->vi, sizeof(err->vi)); ), - TP_printk("CPU: %d, MCGc/s: %llx/%llx, MC%d: %016Lx, IPID: %016Lx, ADDR/MISC/SYND: %016Lx/%016Lx/%016Lx, RIP: %02x:<%016Lx>, TSC: %llx, PROCESSOR: %u:%x, TIME: %llu, SOCKET: %u, APIC: %x", + TP_printk("CPU: %d, MCGc/s: %llx/%llx, MC%d: %016llx, IPID: %016llx, ADDR/MISC/SYND: %016llx/%016llx/%016llx, RIP: %02x:<%016llx>, TSC: %llx, PROCESSOR: %u:%x, TIME: %llu, SOCKET: %u, APIC: %x, Vendor Data: %s", __entry->cpu, __entry->mcgcap, __entry->mcgstatus, __entry->bank, __entry->status, @@ -66,7 +70,8 @@ TRACE_EVENT(mce_record, __entry->cpuvendor, __entry->cpuid, __entry->walltime, __entry->socketid, - __entry->apicid) + __entry->apicid, + __print_array(__get_dynamic_array(v_data), __entry->len / 8, 8)) ); #endif /* _TRACE_MCE_H */ From patchwork Sat Nov 18 19:32:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 13460269 Authentication-Results: smtp.subspace.kernel.org; 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Sat, 18 Nov 2023 13:33:11 -0600 From: Yazen Ghannam To: CC: , , , , , , , "Yazen Ghannam" Subject: [PATCH 19/20] x86/mce/apei: Handle variable register array size Date: Sat, 18 Nov 2023 13:32:47 -0600 Message-ID: <20231118193248.1296798-20-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231118193248.1296798-1-yazen.ghannam@amd.com> References: <20231118193248.1296798-1-yazen.ghannam@amd.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB4E:EE_|DS0PR12MB6486:EE_ X-MS-Office365-Filtering-Correlation-Id: 745ad4b5-edd4-477c-793e-08dbe86d33e2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: BXeLLThDd1yupZa6DwH2y6z9f/kI7aRtDon5XChOTeYaLA2scmlIVvsEUTYgNueKP/9YSChzF4SLptgN0xVk5jKOetsk3ptuOcsDm8YBWTuEHQYzPqlbiV/j8DaIlhuhxU9d1kNfiB8i8WEiChW0Jp8wWQ17KTtBg/ozT7rYA4Kmsy5rpKkZfABywyzDLDgiAu9Q39ul5BvDtwLCi1AiBoqU098sneM88eoAORCChheGSJOneFp/ogx6505ZtGSQ5symnxQvxSt5bg6g+UvIrqjEL28F2OXn/tQMg6KGIOh9Kvx7EzorL6kE/HJzkLcmvtAcg3ebhsyGNqc+YT9VA9z/nIhf5u0CZk6yULdiyXc43M5SJ0kxEHxg7GKR8HZX0Kv3whRfWwQJAqnGgu1b/CnU/xWcevkrX7Y58xL+3idTYyaV3Aq+Emm1nrAk2Cp+LHoOzECAlC6dwIv0lchK89LaxDLlUmb5ZAcCUnB+y2TGlReFRMcWsbXd5oTgrO4ye/3Wh5bqPI608NTcyZYlEJuyLxWfru0zj2TZhoxJByyMX8m09bM1sRM6ij+mlQElf00AjfmdbYaIPUbK5WPyF7O8s1ppNEwQkfGpNkteeZFp6i4eGXJQ+YdZIiHvdJDumZsj6U/rDCY3ZGB2QsrUlTSficjcOxDMPryycH61uRPqNV34JdVyta+JYWsSHlVF0LiyfC9f5qcByW2cVA+r/hBbt+pohfbH7IYKcUapg5vcHKzcxApEDjCxXeKjD5eusYkodSQJ2o5Aof3PBo8Q7g== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(39860400002)(136003)(396003)(346002)(376002)(230922051799003)(451199024)(82310400011)(64100799003)(186009)(1800799012)(46966006)(36840700001)(40470700004)(40460700003)(5660300002)(44832011)(2906002)(356005)(81166007)(82740400003)(86362001)(36756003)(336012)(426003)(83380400001)(1076003)(26005)(16526019)(2616005)(7696005)(36860700001)(478600001)(6666004)(47076005)(41300700001)(8676002)(8936002)(4326008)(70586007)(70206006)(316002)(6916009)(54906003)(40480700001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Nov 2023 19:33:12.2147 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 745ad4b5-edd4-477c-793e-08dbe86d33e2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB4E.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB6486 ACPI Boot Error Record Table (BERT) is being used by the kernel to report errors that occurred in a previous boot. On some modern AMD systems, these very errors within the BERT are reported through the x86 Common Platform Error Record (CPER) format which consists of one or more Processor Context Information Structures. These context structures provide a starting address and represent an x86 MSR range in which the data constitutes a contiguous set of MSRs starting from, and including the starting address. It's common, for AMD systems that implement this behavior, that the MSR range represents the MCAX register space used for the Scalable MCA feature. The apei_smca_report_x86_error() function decodes and passes this information through the MCE notifier chain. However, this function assumes a fixed register size based on the original HW/FW implementation. This assumption breaks with the addition of two new MCAX registers viz. MCA_SYND1 and MCA_SYND2. These registers are added at the end of the MCAX register space, so they won't be included when decoding the CPER data. Rework apei_smca_report_x86_error() to support a variable register array size. This covers any case where the MSR context information starts at the MCAX address for MCA_STATUS and ends at any other register within the MCAX register space. Add code comments indicating the MCAX register at each offset. [Yazen: Add Avadhut as co-developer for wrapper changes.] Co-developed-by: Avadhut Naik Signed-off-by: Avadhut Naik Signed-off-by: Yazen Ghannam --- arch/x86/kernel/cpu/mce/apei.c | 73 +++++++++++++++++++++++++++------- 1 file changed, 59 insertions(+), 14 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/apei.c b/arch/x86/kernel/cpu/mce/apei.c index 4820f8677460..d01c9b272e2f 100644 --- a/arch/x86/kernel/cpu/mce/apei.c +++ b/arch/x86/kernel/cpu/mce/apei.c @@ -69,9 +69,9 @@ EXPORT_SYMBOL_GPL(apei_mce_report_mem_error); int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info, u64 lapic_id) { const u64 *i_mce = ((const u64 *) (ctx_info + 1)); + unsigned int cpu, num_registers; struct mce_hw_err err; struct mce *m = &err.m; - unsigned int cpu; memset(&err, 0, sizeof(struct mce_hw_err)); @@ -91,16 +91,12 @@ int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info, u64 lapic_id) return -EINVAL; /* - * The register array size must be large enough to include all the - * SMCA registers which need to be extracted. - * * The number of registers in the register array is determined by * Register Array Size/8 as defined in UEFI spec v2.8, sec N.2.4.2.2. - * The register layout is fixed and currently the raw data in the - * register array includes 6 SMCA registers which the kernel can - * extract. + * Ensure that the array size includes at least 1 register. */ - if (ctx_info->reg_arr_size < 48) + num_registers = ctx_info->reg_arr_size >> 3; + if (!num_registers) return -EINVAL; for_each_possible_cpu(cpu) { @@ -116,12 +112,61 @@ int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info, u64 lapic_id) mce_setup_per_cpu(m); m->bank = (ctx_info->msr_addr >> 4) & 0xFF; - m->status = *i_mce; - m->addr = *(i_mce + 1); - m->misc = *(i_mce + 2); - /* Skipping MCA_CONFIG */ - m->ipid = *(i_mce + 4); - m->synd = *(i_mce + 5); + + /* + * The SMCA register layout is fixed and includes 16 registers. + * The end of the array may be variable, but the beginning is known. + * Switch on the number of registers. Cap the number of registers to + * expected max (15). + */ + if (num_registers > 15) + num_registers = 15; + + switch (num_registers) { + /* MCA_SYND2 */ + case 15: + err.vi.amd.synd2 = *(i_mce + 14); + fallthrough; + /* MCA_SYND1 */ + case 14: + err.vi.amd.synd1 = *(i_mce + 13); + fallthrough; + /* MCA_MISC4 */ + case 13: + /* MCA_MISC3 */ + case 12: + /* MCA_MISC2 */ + case 11: + /* MCA_MISC1 */ + case 10: + /* MCA_DEADDR */ + case 9: + /* MCA_DESTAT */ + case 8: + /* reserved */ + case 7: + /* MCA_SYND */ + case 6: + m->synd = *(i_mce + 5); + fallthrough; + /* MCA_IPID */ + case 5: + m->ipid = *(i_mce + 4); + fallthrough; + /* MCA_CONFIG */ + case 4: + /* MCA_MISC0 */ + case 3: + m->misc = *(i_mce + 2); + fallthrough; + /* MCA_ADDR */ + case 2: + m->addr = *(i_mce + 1); + fallthrough; + /* MCA_STATUS */ + case 1: + m->status = *i_mce; + } mce_log(&err); From patchwork Sat Nov 18 19:32:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 13460268 Authentication-Results: smtp.subspace.kernel.org; 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Sat, 18 Nov 2023 13:33:11 -0600 From: Yazen Ghannam To: CC: , , , , , , , "Yazen Ghannam" Subject: [PATCH 20/20] EDAC/mce_amd: Add support for FRU Text in MCA Date: Sat, 18 Nov 2023 13:32:48 -0600 Message-ID: <20231118193248.1296798-21-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231118193248.1296798-1-yazen.ghannam@amd.com> References: <20231118193248.1296798-1-yazen.ghannam@amd.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB4E:EE_|LV2PR12MB5895:EE_ X-MS-Office365-Filtering-Correlation-Id: e159d9d2-14ea-4c17-4f41-08dbe86d3419 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 7fFQPBD/cpnZIiwtbYIsa1KOZ4JahrumpknEqmlYjESdjFe0ak7kC+VGmlJCIuyIQz58AIVAVSiQSg+htlxHRvEnxtPs9F+mDmWpyMPVKt04n2mWqYMBf4PV0jEhjarTxi/sLle8UUbnKO/MdcC7YAHH9x4kbFwD2kMStrgAskqEux8ycHbv/V2IXFbXzXzbNnap54O6AaR2pEcT1EnhjOOJjvgZcQrmTeyn8iLJjpuYxFJobHvzw1fk6L3o87LcQxxLt2E7sJ2UyiCJFdhoWt7EaHf1Ii5fjdC9ONsceLyEmdO3Y09RnmwWcmMPRC9ATO7iSWYDR7N8vhlHp6sYbiZxdlub8QoGVGs3ZiP3dAxuyIxN9DSEwOxAWvw7y5BIGPixhGuAyzUJvacty+1gXI6kimU3/OH9CCWZs/Zyq7jh5oc73SxPy0/IT3cQNP/mOTjJ4Yi+ie3uZmEvng5QRgU62WuYF11tATqdgQ+lJoy03ypnWe1+dGrQIML7dsLxS5Pv9CiJgIB+YBNsyZeGlgswC9HfVqbTAc/LtJsZCLxTks/wtpx4fHXCzEO57sfOTlaxyL01CbstLY+Z5qf2EhMqIXh20O5tnBS9IfMNTPT3K6dbEHV3n1nhDHDrszEVt8/GbfiKcCej2Y+VuHXYoniF7WxDqoyL3AuryRSgizUs3N9LBFmABhPuKzeT2+qPt8JhrgSv9z6HZKhvxN9F58r0D6kbHk+brFU9n//NKgy7/UdyhnPivELjvtwq8UrQoDbMZQqTEMjxG+xdvs93VIHmyEM6N0REtVdsNNvY9rU= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(396003)(136003)(39860400002)(346002)(376002)(230922051799003)(230173577357003)(230273577357003)(451199024)(1800799012)(186009)(82310400011)(64100799003)(46966006)(36840700001)(478600001)(36756003)(26005)(336012)(426003)(7696005)(41300700001)(2616005)(6666004)(81166007)(356005)(16526019)(36860700001)(86362001)(47076005)(82740400003)(83380400001)(1076003)(2906002)(4326008)(8676002)(8936002)(70206006)(70586007)(54906003)(44832011)(316002)(6916009)(40480700001)(5660300002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Nov 2023 19:33:12.5741 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e159d9d2-14ea-4c17-4f41-08dbe86d3419 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB4E.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5895 A new "FRU Text in MCA" feature is defined where the Field Replaceable Unit (FRU) Text for a device is represented by a string in the new MCA_SYND1 and MCA_SYND2 registers. This feature is supported per MCA bank, and it is advertised by the McaFruTextInMca bit (MCA_CONFIG[9]). The FRU Text is populated dynamically for each individual error state (MCA_STATUS, MCA_ADDR, et al.). This handles the case where an MCA bank covers multiple devices, for example, a Unified Memory Controller (UMC) bank that manages two DIMMs. Print the FRU Text string, if available, when decoding an MCA error. Also, add field for MCA_CONFIG MSR in struct mce_hw_err as vendor specific error information and save the value of the MSR. The very value can then be exported through tracepoint for userspace tools like rasdaemon to print FRU Text, if available. Note: Checkpatch checks/warnings are ignored to maintain coding style. [Yazen: Add Avadhut as co-developer for wrapper changes. ] Co-developed-by: Avadhut Naik Signed-off-by: Avadhut Naik Signed-off-by: Yazen Ghannam --- arch/x86/include/asm/mce.h | 2 ++ arch/x86/kernel/cpu/mce/apei.c | 2 ++ arch/x86/kernel/cpu/mce/core.c | 3 +++ drivers/edac/mce_amd.c | 21 ++++++++++++++------- 4 files changed, 21 insertions(+), 7 deletions(-) diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index 1bd3f1e41dbb..7e2a3dba0cf3 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -59,6 +59,7 @@ * - TCC bit is present in MCx_STATUS. */ #define MCI_CONFIG_MCAX 0x1 +#define MCI_CONFIG_FRUTEXT BIT_ULL(9) #define MCI_IPID_MCATYPE_OLD 0xFFFF0000 #define MCI_IPID_HWID_OLD 0xFFF #define MCI_IPID_MCATYPE GENMASK_ULL(63, 48) @@ -199,6 +200,7 @@ struct mce_hw_err { struct { u64 synd1; u64 synd2; + u64 config; } amd; } vi; }; diff --git a/arch/x86/kernel/cpu/mce/apei.c b/arch/x86/kernel/cpu/mce/apei.c index d01c9b272e2f..c8312e160117 100644 --- a/arch/x86/kernel/cpu/mce/apei.c +++ b/arch/x86/kernel/cpu/mce/apei.c @@ -155,6 +155,8 @@ int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info, u64 lapic_id) fallthrough; /* MCA_CONFIG */ case 4: + err.vi.amd.config = *(i_mce + 3); + fallthrough; /* MCA_MISC0 */ case 3: m->misc = *(i_mce + 2); diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index e153a21bdb1b..b9da1cd0fb88 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -204,6 +204,8 @@ static void __print_mce(struct mce_hw_err *err) pr_cont("SYND2 %llx ", err->vi.amd.synd2); if (m->ipid) pr_cont("IPID %llx ", m->ipid); + if (err->vi.amd.config) + pr_cont("CONFIG %llx ", err->vi.amd.config); } pr_cont("\n"); @@ -661,6 +663,7 @@ static noinstr void mce_read_aux(struct mce_hw_err *err, int i) if (mce_flags.smca) { m->ipid = mce_rdmsrl(MSR_AMD64_SMCA_MCx_IPID(i)); + err->vi.amd.config = mce_rdmsrl(MSR_AMD64_SMCA_MCx_CONFIG(i)); if (m->status & MCI_STATUS_SYNDV) { m->synd = mce_rdmsrl(MSR_AMD64_SMCA_MCx_SYND(i)); diff --git a/drivers/edac/mce_amd.c b/drivers/edac/mce_amd.c index 4d2929770620..2b738bd7889b 100644 --- a/drivers/edac/mce_amd.c +++ b/drivers/edac/mce_amd.c @@ -1278,6 +1278,7 @@ amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data) struct mce_hw_err *err = (struct mce_hw_err *)data; struct mce *m = &err->m; unsigned int fam = x86_family(m->cpuid); + u64 mca_config = err->vi.amd.config; int ecc; if (m->kflags & MCE_HANDLED_CEC) @@ -1297,11 +1298,7 @@ amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data) ((m->status & MCI_STATUS_PCC) ? "PCC" : "-")); if (boot_cpu_has(X86_FEATURE_SMCA)) { - u32 low, high; - u32 addr = MSR_AMD64_SMCA_MCx_CONFIG(m->bank); - - if (!rdmsr_safe(addr, &low, &high) && - (low & MCI_CONFIG_MCAX)) + if (mca_config & MCI_CONFIG_MCAX) pr_cont("|%s", ((m->status & MCI_STATUS_TCC) ? "TCC" : "-")); pr_cont("|%s", ((m->status & MCI_STATUS_SYNDV) ? "SyndV" : "-")); @@ -1336,8 +1333,18 @@ amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data) if (m->status & MCI_STATUS_SYNDV) { pr_cont(", Syndrome: 0x%016llx\n", m->synd); - pr_emerg(HW_ERR "Syndrome1: 0x%016llx, Syndrome2: 0x%016llx", - err->vi.amd.synd1, err->vi.amd.synd2); + if (mca_config & MCI_CONFIG_FRUTEXT) { + char frutext[17]; + + memset(frutext, 0, sizeof(frutext)); + memcpy(&frutext[0], &err->vi.amd.synd1, 8); + memcpy(&frutext[8], &err->vi.amd.synd2, 8); + + pr_emerg(HW_ERR "FRU Text: %s", frutext); + } else { + pr_emerg(HW_ERR "Syndrome1: 0x%016llx, Syndrome2: 0x%016llx", + err->vi.amd.synd1, err->vi.amd.synd2); + } } pr_cont("\n");