From patchwork Mon Nov 20 11:18:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13461071 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="Wd8lqIVa" Received: from mail-wm1-x336.google.com (mail-wm1-x336.google.com [IPv6:2a00:1450:4864:20::336]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 72AC310D2 for ; Mon, 20 Nov 2023 03:18:32 -0800 (PST) Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-40853c639abso15051885e9.0 for ; Mon, 20 Nov 2023 03:18:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1700479111; x=1701083911; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=C3zrIDT5N9p6eJitAm1oJTITcoW+HOP0VmG8nkt3FV0=; b=Wd8lqIVaCz4zOdau+zWarXenNTr0tUgyzonJJQ849gD475OpVKsomkngmvhBQuCN+Z ZL6CvCaK50rKULg6/fJwMU0vxQ/VzI5lEykagt7oCSfdpi9KxyOVZThKK0tITcp/WYkH 7RpFQqqZZ2NK1KQTkVljw6v6nX1NUOKryPZmg8XQJ2vVAiD0vQxLZTP11b2itz9o0CN4 gJwlYQ/PFGPHO3M/L14hCvDszgDeGkh3CD8JLrUpTqNwr8KV2XYN4MyIdMHPzBbWxdb1 L6MB9fYoMWn4doMIBAa7/9axCfCcZADr0FQXIr9d5RvjZepveFk3yjMpccU6WNiMckyO IYgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700479111; x=1701083911; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=C3zrIDT5N9p6eJitAm1oJTITcoW+HOP0VmG8nkt3FV0=; b=PnfFLYme0bwTm+xIZD8CA2JdJOFEFswigwgmrwGFj5cRfrCWjYVKnC6pRNRLYwjgnM mF8VIhI26mwwYHAtjf0G2zZa0i4/4JIbKRyrm36oyJOtBc6rCXCOG25iiX5BbPg7Pj7R rar2LxOJdch34ZqcCQGt4fWM4lm7hWVdzGzLrDOiLcmtBUtYSh2lqSvgW/w0tH0d96BD 7N2pVvphiDpcPTYE8v9ve1BUv+S739rqRq6o+4y0k3Afvhy6mFv6oLVzWoqt1KFL7C4M QFkKKL8B/JG0UZBSzZvIrcX3oHr8OYSUpjMGzCidyupe5sWK96NXfm4u1PNiKX70acdg e66g== X-Gm-Message-State: AOJu0Yxh0s3gIhcCrTa6g1yPEuL3JctQ/kzdWSgpKIBIEkLpc4PTUFUV rs4r4o5p3xvE4JHFjd3JXzAFRi6IqmlWNX0Iyuc= X-Google-Smtp-Source: AGHT+IG7MVqf/6hNKYkRXglolSsIpyxst5mObigjMOwk+LzWWRY5k4ezPeeB8D9kioAMd9xaHO5xCw== X-Received: by 2002:a05:600c:510d:b0:408:3bbd:4a82 with SMTP id o13-20020a05600c510d00b004083bbd4a82mr4666391wms.15.1700479110864; Mon, 20 Nov 2023 03:18:30 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.183]) by smtp.gmail.com with ESMTPSA id g6-20020a05600c310600b0040651505684sm13142676wmo.29.2023.11.20.03.18.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Nov 2023 03:18:30 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: tglx@linutronix.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, prabhakar.mahadev-lad.rj@bp.renesas.com Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Claudiu Beznea Subject: [PATCH v3 1/9] clk: renesas: r9a08g045: Add IA55 pclk and its reset Date: Mon, 20 Nov 2023 13:18:12 +0200 Message-Id: <20231120111820.87398-2-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231120111820.87398-1-claudiu.beznea.uj@bp.renesas.com> References: <20231120111820.87398-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea IA55 interrupt controller is available on RZ/G3S SoC. Add IA55 pclk and its reset. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- drivers/clk/renesas/r9a08g045-cpg.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/renesas/r9a08g045-cpg.c b/drivers/clk/renesas/r9a08g045-cpg.c index 4394cb241d99..ea3beca8b4e0 100644 --- a/drivers/clk/renesas/r9a08g045-cpg.c +++ b/drivers/clk/renesas/r9a08g045-cpg.c @@ -188,6 +188,7 @@ static const struct cpg_core_clk r9a08g045_core_clks[] __initconst = { static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = { DEF_MOD("gic_gicclk", R9A08G045_GIC600_GICCLK, R9A08G045_CLK_P1, 0x514, 0), + DEF_MOD("ia55_pclk", R9A08G045_IA55_PCLK, R9A08G045_CLK_P2, 0x518, 0), DEF_MOD("ia55_clk", R9A08G045_IA55_CLK, R9A08G045_CLK_P1, 0x518, 1), DEF_MOD("dmac_aclk", R9A08G045_DMAC_ACLK, R9A08G045_CLK_P3, 0x52c, 0), DEF_MOD("sdhi0_imclk", R9A08G045_SDHI0_IMCLK, CLK_SD0_DIV4, 0x554, 0), @@ -209,6 +210,7 @@ static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = { static const struct rzg2l_reset r9a08g045_resets[] = { DEF_RST(R9A08G045_GIC600_GICRESET_N, 0x814, 0), DEF_RST(R9A08G045_GIC600_DBG_GICRESET_N, 0x814, 1), + DEF_RST(R9A08G045_IA55_RESETN, 0x818, 0), DEF_RST(R9A08G045_SDHI0_IXRST, 0x854, 0), DEF_RST(R9A08G045_SDHI1_IXRST, 0x854, 1), DEF_RST(R9A08G045_SDHI2_IXRST, 0x854, 2), @@ -220,6 +222,7 @@ static const struct rzg2l_reset r9a08g045_resets[] = { static const unsigned int r9a08g045_crit_mod_clks[] __initconst = { MOD_CLK_BASE + R9A08G045_GIC600_GICCLK, + MOD_CLK_BASE + R9A08G045_IA55_PCLK, MOD_CLK_BASE + R9A08G045_IA55_CLK, MOD_CLK_BASE + R9A08G045_DMAC_ACLK, }; From patchwork Mon Nov 20 11:18:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13461072 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="dGPEuAMd" Received: from mail-wm1-x335.google.com (mail-wm1-x335.google.com [IPv6:2a00:1450:4864:20::335]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C17E310DB for ; Mon, 20 Nov 2023 03:18:33 -0800 (PST) Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-4083ac51d8aso15053775e9.2 for ; Mon, 20 Nov 2023 03:18:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1700479112; x=1701083912; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Gc8Hzq3Ts2nxCQ0omkudOSRnL/wtmp/FWmIm+F9jowA=; b=dGPEuAMdFCV9NlctN9B0xXm/HSlHxfFOfN0H/zW3UBjkyNKFCvhJToet097rFn4HLL z8jDAHwbWzJQJuyZA4euL5LrYl/R54C4NuBOdMzxLEG+3cFiZWLB5GihrHuSPA8yUThF 5spNYyVzf7NnjYLa2CvjqdEVDZnDy07WZ5CM8cEWQhpB/+c13zm/McKXC2GFXoLqJau5 7o+2SkudWUXZVxQfXaH0vMn7zYDLeZ4F2dD9jaK0vp5TOu8m+A9SYTb10fgqF2ttwq/f NkBYu4wv3s7SV02UDS4plxGcDnucAh5HFOvu0/XH5H//Zkfdd3Pmft1m3hcDtSftv1dh cEQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700479112; x=1701083912; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Gc8Hzq3Ts2nxCQ0omkudOSRnL/wtmp/FWmIm+F9jowA=; b=dvkaAP5ZMTbjcyxm1Nm695KUT9zptoTza9oQJINIidpcfH6X4CCyvNVg46OV+8m0s9 Rms6tUc/Tlm31TUmHD/jFUF1Q7hCl6/rT6aVikKLyRu8SwnNsVDOsxzrAIiUg3529qEH 1VUjDTbpg3bb5bPnck0pvmIOoAsCUIbZ6bgPHCnB6hmKCvbtY3aeoUhFz1z5YPv+kXUR pRzsU4bVwURgHNMNcKRliwwkyZLEZv69WaEsd/MHpP34z1X9KLMZaAmJVmynFxvVFCmS b2nMDNehgW8EYVIsXZyhQEENhOQeDWo+NPuxmlBM7mrvrhadSRMKpKIw2k5MEUcVke7M uVGQ== X-Gm-Message-State: AOJu0YxqnDD0/oBTVLN99nl53XXjT3LhWm8Kp5g+w1x57FP4AbVx9Upm DaDxjF96jevKn7ulv6K2ZIs5mg== X-Google-Smtp-Source: AGHT+IGR4NGMGQuVNYATIPlT42I33gdkgFm4f8WvykH8Sea8phFSl9bGFJL8tFMSI4OQOpZND0ITug== X-Received: by 2002:a05:600c:1c96:b0:405:336b:8307 with SMTP id k22-20020a05600c1c9600b00405336b8307mr5941605wms.7.1700479112208; Mon, 20 Nov 2023 03:18:32 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.183]) by smtp.gmail.com with ESMTPSA id g6-20020a05600c310600b0040651505684sm13142676wmo.29.2023.11.20.03.18.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Nov 2023 03:18:31 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: tglx@linutronix.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, prabhakar.mahadev-lad.rj@bp.renesas.com Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Claudiu Beznea Subject: [PATCH v3 2/9] irqchip/renesas-rzg2l: Use tabs instead of spaces Date: Mon, 20 Nov 2023 13:18:13 +0200 Message-Id: <20231120111820.87398-3-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231120111820.87398-1-claudiu.beznea.uj@bp.renesas.com> References: <20231120111820.87398-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Use tabs instead of spaces in definition of TINT_EXTRACT_HWIRQ() and TINT_EXTRACT_GPIOINT() macros to align with coding style requirements described in Documentation/process/coding-style.rst, "Indentation" chapter. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- drivers/irqchip/irq-renesas-rzg2l.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c index fe8d516f3614..cc42cbd05762 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -53,8 +53,8 @@ #define IITSR_IITSEL_EDGE_BOTH 3 #define IITSR_IITSEL_MASK(n) IITSR_IITSEL((n), 3) -#define TINT_EXTRACT_HWIRQ(x) FIELD_GET(GENMASK(15, 0), (x)) -#define TINT_EXTRACT_GPIOINT(x) FIELD_GET(GENMASK(31, 16), (x)) +#define TINT_EXTRACT_HWIRQ(x) FIELD_GET(GENMASK(15, 0), (x)) +#define TINT_EXTRACT_GPIOINT(x) FIELD_GET(GENMASK(31, 16), (x)) struct rzg2l_irqc_priv { void __iomem *base; From patchwork Mon Nov 20 11:18:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13461073 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="FFiMjGl9" Received: from mail-wm1-x330.google.com (mail-wm1-x330.google.com [IPv6:2a00:1450:4864:20::330]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2C666D5D for ; Mon, 20 Nov 2023 03:18:35 -0800 (PST) Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-4084b0223ccso14923815e9.2 for ; Mon, 20 Nov 2023 03:18:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1700479113; x=1701083913; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fqTdxNbR3DIWsz90mETj0syANj+j4DLCa1dx7/EKSLU=; b=FFiMjGl9DXP9ZUo53s3400ANiQ+OJGY3XLbwLiILiFV9AbFMt6wCcVYc4BoohCzbf4 Z+60P10VHsScbMoV/s1DShDHhGQmD8rLou4CSKpJysI3/Ie7AA6H3KQaJ3V0Wk9vD9HU GoJ9rASMn+Sad3cl9vXzHHvW2bhSzHBP+jplDpgxFixsQKFkWv4T2Z7lthd18fdUZ0U+ cZpMMeYHmKpXU9tM1VJ+UOwjAdRqwNKUJpOjJQcU78yAaZtxg8Cg/yjGePfalkN/lZRg V5P0m+rBn9WP0/etgRYPZz6sj0nFA+ibtjR9GCJNJchfIK1K2e9dGuWj8v95Mb32E36O ruJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700479113; x=1701083913; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fqTdxNbR3DIWsz90mETj0syANj+j4DLCa1dx7/EKSLU=; b=BkuNwkTmS3HeeplZaNcO5V45INaJ3wRJ4RpztZXM0G+r/JBWHjU7musNO5T2+AsduF k4iSK+0Ir3pBnuJ0pj51KvQ4cgw8jsIV5tKi91nqBJcEJ8yA/4i9uRdlKU9V+fu9zzY0 xNBBNCL/TY7J4thmwif/7pbKbtCKpIZgXXVktUNSK4LQ1YdlMr1yKotJgOKO/jPxZuHZ F6O5aUrvhCdE6mgrirgfS57vCCdStkmoM6t2OiVX7lQm7QT6hYk6tCLMGcMHsqKjlbyB 3lm6b/2HQmNUbV8DHYU3suUG6FivTSXodOzjMUTrlPgo2FrEOUyEkyrKt2Uw3YJWERwT 9Y3A== X-Gm-Message-State: AOJu0YxewQwh7pY8NTlePtfkzkcFyVs1x/O9bQrUaiNsDbQs88MLaaO3 PD5CXwXaad+E72m5BqSZg9V+Xw== X-Google-Smtp-Source: AGHT+IHgzpzdAPQRoTygB2X9zpY2EXIcjHCka24fPfFIsh88xrSV88jkI8f1ygKOgzJkWwOk1S4GeA== X-Received: by 2002:a05:600c:4752:b0:406:52f1:7e6f with SMTP id w18-20020a05600c475200b0040652f17e6fmr5869517wmo.12.1700479113644; Mon, 20 Nov 2023 03:18:33 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.183]) by smtp.gmail.com with ESMTPSA id g6-20020a05600c310600b0040651505684sm13142676wmo.29.2023.11.20.03.18.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Nov 2023 03:18:33 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: tglx@linutronix.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, prabhakar.mahadev-lad.rj@bp.renesas.com Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Claudiu Beznea Subject: [PATCH v3 3/9] irqchip/renesas-rzg2l: Align struct member names to tabs Date: Mon, 20 Nov 2023 13:18:14 +0200 Message-Id: <20231120111820.87398-4-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231120111820.87398-1-claudiu.beznea.uj@bp.renesas.com> References: <20231120111820.87398-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Align struct member names to tabs to follow the requirements from maintainer-tip file. 3 tabs were used at the moment as the next commits will add a new member which requires 3 tabs for a better view. Link: https://www.kernel.org/doc/html/latest/process/maintainer-tip.html#struct-declarations-and-initializers Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- drivers/irqchip/irq-renesas-rzg2l.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c index cc42cbd05762..90971ab06f0c 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -57,9 +57,9 @@ #define TINT_EXTRACT_GPIOINT(x) FIELD_GET(GENMASK(31, 16), (x)) struct rzg2l_irqc_priv { - void __iomem *base; - struct irq_fwspec fwspec[IRQC_NUM_IRQ]; - raw_spinlock_t lock; + void __iomem *base; + struct irq_fwspec fwspec[IRQC_NUM_IRQ]; + raw_spinlock_t lock; }; static struct rzg2l_irqc_priv *irq_data_to_priv(struct irq_data *data) From patchwork Mon Nov 20 11:18:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13461074 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="gi15J+Hc" Received: from mail-wm1-x335.google.com (mail-wm1-x335.google.com [IPv6:2a00:1450:4864:20::335]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8FDE510F6 for ; Mon, 20 Nov 2023 03:18:36 -0800 (PST) Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-4083740f92dso14876195e9.3 for ; Mon, 20 Nov 2023 03:18:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1700479115; x=1701083915; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AqGjAGh4CKyy6nggCnS+RNoaOYdNw7jP+033IkTDbaA=; b=gi15J+HcQvbepVqOCaFZsE+HwH8glyFd9oupueA1mn1Oq+vRSjqaa1uv/XdhRMrPyT fN0L6T034H5pcGa0mc8NVYS6fOrayE5w4h6ctbHa8CRWWICl1nAPHDOTwWT4jAKdzy5i 1oUbXpyj1lTuQTdT2Xk2yVetjhn2Vmn09ZELJqhqMJ8lMHW0pxmDPlYYLahRyxntNtkE bawYDs2jLD6yju1VdiGVQK3XeHIp7qxzZa2jvz8PHagrPUZ6X0T4riIhGqNgOkS6Z0+w M/M7U1b1A8hhN3ii9lSvobE+CADxbbAhWabaTu3OyZL0Ms0Jc5ZJAVw0RK0fogfFQupW 9CBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700479115; x=1701083915; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AqGjAGh4CKyy6nggCnS+RNoaOYdNw7jP+033IkTDbaA=; b=PjGF18TgI4JvPTtQ6gb9T+B1xf3bWyfGjzgpvKkIklUqfdgwEfs98ZJOW1S39GY9Vw 2EX22ZWsJyuIO7ToJd4XwUGXSeje2yCUcWU4AX0KB4SX2/bb+8/nOv9P02rAOl9PpouY M2Fo4kxpGcbP7Kju1cx5XZ33WiaQzOwuoDqM5RdcADlt6/rqaO0d7AYIE7n1TInqRZB6 2SevxYrIMONDLmYlr7s/SqE9P5WSZ9H3RbXyBPz0cSGDm6PCcIlA8/NGfTNVRUX4dtrN EHqLdnDPFFwCLZZo/L9BdeXiY8WxToOamf/cjQ8Ng62a2do97VCR4E6Ylfr9hr9IXFUo 7ksg== X-Gm-Message-State: AOJu0YwrYDJvfU0bGj8lEbQfjXe1vRVvsJJdGOwJA1Vbcfn9MEr8qhaP /Mx6U+hXUf7ax6DQggbh+yeyLg== X-Google-Smtp-Source: AGHT+IFwee0RbxTWFSj/lIhD5S5cVpFwg/mR026a7EYJzWpnZC1lfGCpTao9S2IGVkR3x0ZZ2BBNHg== X-Received: by 2002:a05:600c:3555:b0:401:b204:3b97 with SMTP id i21-20020a05600c355500b00401b2043b97mr5468250wmq.4.1700479115107; Mon, 20 Nov 2023 03:18:35 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.183]) by smtp.gmail.com with ESMTPSA id g6-20020a05600c310600b0040651505684sm13142676wmo.29.2023.11.20.03.18.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Nov 2023 03:18:34 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: tglx@linutronix.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, prabhakar.mahadev-lad.rj@bp.renesas.com Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Claudiu Beznea Subject: [PATCH v3 4/9] irqchip/renesas-rzg2l: Document structure members Date: Mon, 20 Nov 2023 13:18:15 +0200 Message-Id: <20231120111820.87398-5-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231120111820.87398-1-claudiu.beznea.uj@bp.renesas.com> References: <20231120111820.87398-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Document structure members to follow the requirements specified in maintainer-tip, section 4.3.7. Struct declarations and initializers. Link: https://www.kernel.org/doc/html/latest/process/maintainer-tip.html#struct-declarations-and-initializers Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- drivers/irqchip/irq-renesas-rzg2l.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c index 90971ab06f0c..d666912adc74 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -56,6 +56,12 @@ #define TINT_EXTRACT_HWIRQ(x) FIELD_GET(GENMASK(15, 0), (x)) #define TINT_EXTRACT_GPIOINT(x) FIELD_GET(GENMASK(31, 16), (x)) +/** + * struct rzg2l_irqc_priv - IRQ controller private data structure + * @base: controller's base address + * @fwspec: IRQ firmware specific data + * @lock: lock to protect concurrent access to hardware registers + */ struct rzg2l_irqc_priv { void __iomem *base; struct irq_fwspec fwspec[IRQC_NUM_IRQ]; From patchwork Mon Nov 20 11:18:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13461075 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="A5lX2Xkt" Received: from mail-wm1-x32b.google.com (mail-wm1-x32b.google.com [IPv6:2a00:1450:4864:20::32b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7A5641709 for ; Mon, 20 Nov 2023 03:18:38 -0800 (PST) Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-40a4d04af5cso12286975e9.0 for ; Mon, 20 Nov 2023 03:18:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1700479116; x=1701083916; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Mx4aN/zGGPbPx5wuHBwZqoZnjcfUFGnzIbzLn9y7CFM=; b=A5lX2XkttnakvOALBo9HgEMO/99tfIMdnWeKfg0aarUCsl1vg4QtB/K3GXZ4Eihxbs FJEEZGHTGECduu3sL63UqbAZ33Gp88XgBzSLa4N3WpFSmtKeUX72NTISinjAPnF/pOCx bRc5nlxZJ9lZKkipMFdLzo8vfSrmeYcNBbmbqD261Xfa3+k7+kS93Eoum3QHH1YOSIza DcSwgdqTXhRfGE+yh8ksTGujHQKs3LfYomnVU2+HQiWc2RUX80siP6PPRd+4auzIpLFF U8Y4wC9lsmP5fgCglaAc/kBVdL1P6m07pbiVVUZO4N/y8XfZGpv3NnxIxSzu65xLxWcp LhnQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700479116; x=1701083916; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Mx4aN/zGGPbPx5wuHBwZqoZnjcfUFGnzIbzLn9y7CFM=; b=YDLBgtP/YQrUWP3dxhNCztYOqe/lYXwjmDY+dg2EgJBAgRUGz3oKjwsyWeBmiw/Ff4 i7e55ucdu7w4qvm0Hjy9vPdbicfsGMIRtPp0TDnEHheiRRFTSUHgdMceKRAg/YxZqdNI IymWDIj1DWyfZVE1xBoKksd4Jg3j0nZZdVWomWZrTuUio1mqVpIIGeLoAZon7ilTtdDW 4YmzHs4FIpCGXf6366G2u5Hp70RCA6UHnJ1LVmBpJub+O2BebYu83TBHC0BB7e1l4CbI 3GFzisEFcF7JQ8LFqceAy3CN/9b5LP/CzIQP92N1iYvDktehUa+rEPyy6YFCwotyxJ2y C4Qw== X-Gm-Message-State: AOJu0YzDDuRYcNYi5Vm1dknEoZCIpc/KsxiVgceaHU3pEkk8ZQk4vr0/ Z+oVLZVML9QOZYDI+6qqWaCrMw== X-Google-Smtp-Source: AGHT+IG4q9+CFKWWh1PtV4CMYsm0ublGYiA2GT1Ip89ZJtr+DG+TrKWQY2HA9TpUNmUJDiG8Qb2AvQ== X-Received: by 2002:a05:600c:a07:b0:409:703c:b9b1 with SMTP id z7-20020a05600c0a0700b00409703cb9b1mr6455336wmp.40.1700479116562; Mon, 20 Nov 2023 03:18:36 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.183]) by smtp.gmail.com with ESMTPSA id g6-20020a05600c310600b0040651505684sm13142676wmo.29.2023.11.20.03.18.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Nov 2023 03:18:36 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: tglx@linutronix.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, prabhakar.mahadev-lad.rj@bp.renesas.com Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Claudiu Beznea Subject: [PATCH v3 5/9] irqchip/renesas-rzg2l: Implement restriction when writing ISCR register Date: Mon, 20 Nov 2023 13:18:16 +0200 Message-Id: <20231120111820.87398-6-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231120111820.87398-1-claudiu.beznea.uj@bp.renesas.com> References: <20231120111820.87398-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea The RZ/G2L manual (chapter "IRQ Status Control Register (ISCR)") describes the operation to clear interrupts through the ISCR register as follows: [Write operation] When "Falling-edge detection", "Rising-edge detection" or "Falling/Rising-edge detection" is set in IITSR: - In case ISTAT is 1 0: IRQn interrupt detection status is cleared. 1: Invalid to write. - In case ISTAT is 0 Invalid to write. When “Low-level detection” is set in IITSR.: Invalid to write. Take the interrupt type into account when clearing interrupts through the ISCR register to avoid writing the ISCR when interrupt type is level. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- drivers/irqchip/irq-renesas-rzg2l.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c index d666912adc74..a77ac6e1606f 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -78,11 +78,17 @@ static void rzg2l_irq_eoi(struct irq_data *d) unsigned int hw_irq = irqd_to_hwirq(d) - IRQC_IRQ_START; struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); u32 bit = BIT(hw_irq); - u32 reg; + u32 iitsr, iscr; - reg = readl_relaxed(priv->base + ISCR); - if (reg & bit) - writel_relaxed(reg & ~bit, priv->base + ISCR); + iscr = readl_relaxed(priv->base + ISCR); + iitsr = readl_relaxed(priv->base + IITSR); + + /* + * ISCR can only be cleared if the type is falling-edge, rising-edge or + * falling/rising-edge. + */ + if ((iscr & bit) && (iitsr & IITSR_IITSEL_MASK(hw_irq))) + writel_relaxed(iscr & ~bit, priv->base + ISCR); } static void rzg2l_tint_eoi(struct irq_data *d) From patchwork Mon Nov 20 11:18:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13461076 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="hux3o7Dx" Received: from mail-lj1-x234.google.com (mail-lj1-x234.google.com [IPv6:2a00:1450:4864:20::234]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 10BED1984 for ; Mon, 20 Nov 2023 03:18:40 -0800 (PST) Received: by mail-lj1-x234.google.com with SMTP id 38308e7fff4ca-2c87903d314so17808101fa.1 for ; Mon, 20 Nov 2023 03:18:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1700479118; x=1701083918; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LV9ajd1Vn5neabgAa2TZQ+P/1Gh4jYJqAFrZemb2qP0=; b=hux3o7DxjrSRfQTe46yFrhg0OqyhEEKbHEMxnFPN3DPhRAoSTyjI0Ry19qTas6fJZ9 lwaWEKtRxUrjCeo2HmWg7JY4dxPWvDhMkDCtNmoYLKpkG9F219qimmZwI3slnJqWehvM RjmfTI3/8tqVeGi3/I9DPQrGi8h0+8kq7XXJWaUqMbK8Db73tflU3I2Fnd+MgdNURBSc xv71sirvepTkneNsB3xHjsn17Xasn9VPMqY3lnKyAV5KRB9siHJvQBv+PDPmmfHoMewt ddAvqNQ+P88AHXwlM0CRQbfnVo2kqoabNhTPDxWeAC2ekN4+4sj6bj9rYEnkT7Ovs+gK k/Vg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700479118; x=1701083918; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LV9ajd1Vn5neabgAa2TZQ+P/1Gh4jYJqAFrZemb2qP0=; b=jGA5H07OzhrAYsSEJj6euLkwXr01PCKjtya5XQaPYnmpcEBhqlZEb8d0efovsRqu4c XplFDpmbDOL1t7HSi+FG9o0KQxT5893r8YDoGVLK5kNktV7cFMvju9/lJTu71WNlO7Jh O8Mg9iX994cIKhjXwShCBUj28DoJKZAgm2hMid0RWytXTYbuxhnX4YCP0mwHxp6fmOgH fqp/AWoGk4q33/hz/8zj4MCXe+e4EnIfKYUn2GCEVomG6bE6asw3Oq5xNTHHo9AQVThj 8t4fmRwJc2/ygZZTC7ONc8TiKzZbXerh2RBd6Ky4GQ1dqE3dVQhQ2eaS6mzrlDOpFllA 9qdg== X-Gm-Message-State: AOJu0YzwEZn4ZlQIQCxXw9Y+Rja+7n4UNe/lbE0x7uoG+rVKJRDQoHOn UE+MVdJd0xV4Y5qn6qnrEOFB/Q== X-Google-Smtp-Source: AGHT+IEiQKWoeAHflWfxsYGxW57vdmsVdNEpIhaVkUYjrztJ40uvkrK4CIk91VUscIDSWi9q/5RInA== X-Received: by 2002:a2e:9b95:0:b0:2c1:9a8b:f67 with SMTP id z21-20020a2e9b95000000b002c19a8b0f67mr3867505lji.1.1700479118250; Mon, 20 Nov 2023 03:18:38 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.183]) by smtp.gmail.com with ESMTPSA id g6-20020a05600c310600b0040651505684sm13142676wmo.29.2023.11.20.03.18.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Nov 2023 03:18:37 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: tglx@linutronix.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, prabhakar.mahadev-lad.rj@bp.renesas.com Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Claudiu Beznea Subject: [PATCH v3 6/9] irqchip/renesas-rzg2l: Add macro to retrieve TITSR register offset based on register's index Date: Mon, 20 Nov 2023 13:18:17 +0200 Message-Id: <20231120111820.87398-7-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231120111820.87398-1-claudiu.beznea.uj@bp.renesas.com> References: <20231120111820.87398-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea There are 2 TITSR registers available on IA55 interrupt controller. A single macro could be used to access both of them. Add a macro that retrieves TITSR register offset based on it's index. This macro is useful in commit that adds suspend/resume support to access both TITSR registers in a for loop. Signed-off-by: Claudiu Beznea --- drivers/irqchip/irq-renesas-rzg2l.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c index a77ac6e1606f..45b696db220f 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -28,8 +28,7 @@ #define ISCR 0x10 #define IITSR 0x14 #define TSCR 0x20 -#define TITSR0 0x24 -#define TITSR1 0x28 +#define TITSR(n) (0x24 + (n) * 4) #define TITSR0_MAX_INT 16 #define TITSEL_WIDTH 0x2 #define TSSR(n) (0x30 + ((n) * 4)) @@ -200,8 +199,7 @@ static int rzg2l_tint_set_edge(struct irq_data *d, unsigned int type) struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); unsigned int hwirq = irqd_to_hwirq(d); u32 titseln = hwirq - IRQC_TINT_START; - u32 offset; - u8 sense; + u8 index, sense; u32 reg; switch (type & IRQ_TYPE_SENSE_MASK) { @@ -217,17 +215,17 @@ static int rzg2l_tint_set_edge(struct irq_data *d, unsigned int type) return -EINVAL; } - offset = TITSR0; + index = 0; if (titseln >= TITSR0_MAX_INT) { titseln -= TITSR0_MAX_INT; - offset = TITSR1; + index = 1; } raw_spin_lock(&priv->lock); - reg = readl_relaxed(priv->base + offset); + reg = readl_relaxed(priv->base + TITSR(index)); reg &= ~(IRQ_MASK << (titseln * TITSEL_WIDTH)); reg |= sense << (titseln * TITSEL_WIDTH); - writel_relaxed(reg, priv->base + offset); + writel_relaxed(reg, priv->base + TITSR(index)); raw_spin_unlock(&priv->lock); return 0; From patchwork Mon Nov 20 11:18:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13461077 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="eN/7mUF9" Received: from mail-wm1-x334.google.com (mail-wm1-x334.google.com [IPv6:2a00:1450:4864:20::334]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3F2FE198E for ; Mon, 20 Nov 2023 03:18:41 -0800 (PST) Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-40b23aeb9d9so4776775e9.3 for ; Mon, 20 Nov 2023 03:18:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1700479119; x=1701083919; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zt28BEamGK9GJg+uoPutTMJWsmRnLkQhTTMvCGxCklI=; b=eN/7mUF9Z1s5Bj2gQFa6OUrgXsBXuEikuqF/3Uidrppv5vLTgr/ghaTslm395EchUr mZceJve9uDRMP7atFMZhlMXBZp6LX3nBrhs0+RwWOT3OAsTPiCwLk8neHE2Y6wboImnp dombQrcLIU0PVMyVM6LDWfzYJ4Nxw89Pr04n8Rh9g0mGLrObSYqUfSnjFK4LgJV1fhZs IbvKgX6YUqtQiUQDh8WCWs3Hhiy5+jpR9et8+R4C1zsWBo+2sRSzUPcT2OYOvOA8YHH1 TYfcnSXxNvJTLc/smeW4NidiQk6agpc+2F9omDvFCEQ+EMFK7vQ/KYwEH+zxSVKFI1aN SFQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700479119; x=1701083919; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zt28BEamGK9GJg+uoPutTMJWsmRnLkQhTTMvCGxCklI=; b=N3JlohAlDH6Cglrz9huxo2EkKitHbtTMoO3hTKgI0grqS10zKPdkiPrjVdSG03ewSm TzvwyTHll665G84VYxCeYSLE5M9CNIw3piGzxL17yviszaVLXnk5y5wzyNoYdNUrvYZK WO/bOfeaIOsaB2SUvjwe6PQCVx7pZ3ncAlP3kWf5wbbyVxBpUGv23rn2sKUCdt59AY5h ShWdmVhq/7j2RTc0YcO5weDaTmpQk8JWqkSf2+cZTM4kRoHsl/vxxoFE6nt1+n91G2Qk V65xeLQ1n4jACLEhRzRSLg75q8k318auTbDZCsJFEJ54nandskl1dhQSTmL3nsCkOGFO Xl1Q== X-Gm-Message-State: AOJu0YwNRJ8tc93NsC+cwMQS/bFyOweVEbaKwqSrHTw/LJPmSsl6bRD7 u6w/xaLCPmJstgL4bpsDLyKa3A== X-Google-Smtp-Source: AGHT+IFULmbUM8eR4HVE5mvSY9mHpDxkW8t2l5mdI05BAFDfMEVwZdiXch6T49nMwu1EITfl3yaVyw== X-Received: by 2002:a05:600c:5102:b0:40a:206a:578d with SMTP id o2-20020a05600c510200b0040a206a578dmr5673551wms.31.1700479119621; Mon, 20 Nov 2023 03:18:39 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.183]) by smtp.gmail.com with ESMTPSA id g6-20020a05600c310600b0040651505684sm13142676wmo.29.2023.11.20.03.18.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Nov 2023 03:18:39 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: tglx@linutronix.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, prabhakar.mahadev-lad.rj@bp.renesas.com Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Claudiu Beznea Subject: [PATCH v3 7/9] irqchip/renesas-rzg2l: Add support for suspend to RAM Date: Mon, 20 Nov 2023 13:18:18 +0200 Message-Id: <20231120111820.87398-8-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231120111820.87398-1-claudiu.beznea.uj@bp.renesas.com> References: <20231120111820.87398-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea irqchip-renesas-rzg2l driver is used on RZ/G3S SoC. RZ/G3S could go to deep sleep states where power to different SoC's parts are cut off and RAM is switched to self-refresh. The resume from these states is done with the help of bootloader. IA55 IRQ controller needs to be reconfigured when resuming from deep sleep state. For this the IA55 registers are cached in suspend and restored in resume. The IA55 IRQ controller is connected to GPIO controller and GIC as follows: ┌──────────┐ ┌──────────┐ │ │ SPIX │ │ │ ├─────────►│ │ │ │ │ │ │ │ │ │ ┌────────┐IRQ0-7 │ IA55 │ │ GIC │ Pin0 ───────►│ ├─────────────►│ │ │ │ │ │ │ │ PPIY │ │ ... │ GPIO │ │ ├─────────►│ │ │ │GPIOINT0-127 │ │ │ │ PinN ───────►│ ├─────────────►│ │ │ │ └────────┘ └──────────┘ └──────────┘ where: - Pin0 is the first GPIO controller pin - PinN is the last GPIO controller pin - SPIX is the SPI interrupt with identifier X - PPIY is the PPI interrupt with identifier Y Suspend/resume functionality was implemented with syscore_ops to be able to cache/restore the registers after/before GPIO controller suspend/resume was called. As suspend/resume function members of syscore_ops doesn't take any argument, to be able to access the cache data structure and controller's base address from within suspend/resume functions, the driver private data structure was declared as static in file, named rzg2l_irqc_data and driver has been adjusted accordingly for this. Because IA55 IRQC is resumed before GPIO controller and different GPIO pins could be in unwanted state for IA55 IRQC (e.g. HiZ) when IA55 reconfiguration is done on resume path, to avoid spurious interrupts the IA55 resume configures only interrupt type on resume. The interrupt enable operation will be done at the end of GPIO controller resume. The interrupt type reconfiguration was kept in IA55 driver to minimize the number of subsystems interactions on suspend/resume b/w GPIO and IA55 drivers (as the IRQ reconfiguration from GPIO driver is done with IRQ specific APIs). Signed-off-by: Claudiu Beznea --- drivers/irqchip/irq-renesas-rzg2l.c | 68 ++++++++++++++++++++++++----- 1 file changed, 57 insertions(+), 11 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c index 45b696db220f..3c179ff0b2f0 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -18,6 +18,7 @@ #include #include #include +#include #define IRQC_IRQ_START 1 #define IRQC_IRQ_COUNT 8 @@ -55,17 +56,29 @@ #define TINT_EXTRACT_HWIRQ(x) FIELD_GET(GENMASK(15, 0), (x)) #define TINT_EXTRACT_GPIOINT(x) FIELD_GET(GENMASK(31, 16), (x)) +/** + * struct rzg2l_irqc_reg_cache - registers cache (necessary for suspend/resume) + * @iitsr: IITSR register + * @titsr: TITSR registers + */ +struct rzg2l_irqc_reg_cache { + u32 iitsr; + u32 titsr[2]; +}; + /** * struct rzg2l_irqc_priv - IRQ controller private data structure * @base: controller's base address * @fwspec: IRQ firmware specific data * @lock: lock to protect concurrent access to hardware registers + * @cache: registers cache (necessary for suspend/resume) */ -struct rzg2l_irqc_priv { +static struct rzg2l_irqc_priv { void __iomem *base; struct irq_fwspec fwspec[IRQC_NUM_IRQ]; raw_spinlock_t lock; -}; + struct rzg2l_irqc_reg_cache cache; +} *rzg2l_irqc_data; static struct rzg2l_irqc_priv *irq_data_to_priv(struct irq_data *data) { @@ -246,6 +259,38 @@ static int rzg2l_irqc_set_type(struct irq_data *d, unsigned int type) return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH); } +static int rzg2l_irqc_irq_suspend(void) +{ + struct rzg2l_irqc_reg_cache *cache = &rzg2l_irqc_data->cache; + void __iomem *base = rzg2l_irqc_data->base; + + cache->iitsr = readl_relaxed(base + IITSR); + for (u8 i = 0; i < 2; i++) + cache->titsr[i] = readl_relaxed(base + TITSR(i)); + + return 0; +} + +static void rzg2l_irqc_irq_resume(void) +{ + struct rzg2l_irqc_reg_cache *cache = &rzg2l_irqc_data->cache; + void __iomem *base = rzg2l_irqc_data->base; + + /* + * Restore only interrupt type. TSSRx will be restored at the + * request of pin controller to avoid spurious interrupts due + * to invalid PIN states. + */ + for (u8 i = 0; i < 2; i++) + writel_relaxed(cache->titsr[i], base + TITSR(i)); + writel_relaxed(cache->iitsr, base + IITSR); +} + +static struct syscore_ops rzg2l_irqc_syscore_ops = { + .suspend = rzg2l_irqc_irq_suspend, + .resume = rzg2l_irqc_irq_resume, +}; + static const struct irq_chip irqc_chip = { .name = "rzg2l-irqc", .irq_eoi = rzg2l_irqc_eoi, @@ -331,7 +376,6 @@ static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent) struct irq_domain *irq_domain, *parent_domain; struct platform_device *pdev; struct reset_control *resetn; - struct rzg2l_irqc_priv *priv; int ret; pdev = of_find_device_by_node(node); @@ -344,15 +388,15 @@ static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent) return -ENODEV; } - priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); - if (!priv) + rzg2l_irqc_data = devm_kzalloc(&pdev->dev, sizeof(*rzg2l_irqc_data), GFP_KERNEL); + if (!rzg2l_irqc_data) return -ENOMEM; - priv->base = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL); - if (IS_ERR(priv->base)) - return PTR_ERR(priv->base); + rzg2l_irqc_data->base = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL); + if (IS_ERR(rzg2l_irqc_data->base)) + return PTR_ERR(rzg2l_irqc_data->base); - ret = rzg2l_irqc_parse_interrupts(priv, node); + ret = rzg2l_irqc_parse_interrupts(rzg2l_irqc_data, node); if (ret) { dev_err(&pdev->dev, "cannot parse interrupts: %d\n", ret); return ret; @@ -375,17 +419,19 @@ static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent) goto pm_disable; } - raw_spin_lock_init(&priv->lock); + raw_spin_lock_init(&rzg2l_irqc_data->lock); irq_domain = irq_domain_add_hierarchy(parent_domain, 0, IRQC_NUM_IRQ, node, &rzg2l_irqc_domain_ops, - priv); + rzg2l_irqc_data); if (!irq_domain) { dev_err(&pdev->dev, "failed to add irq domain\n"); ret = -ENOMEM; goto pm_put; } + register_syscore_ops(&rzg2l_irqc_syscore_ops); + return 0; pm_put: From patchwork Mon Nov 20 11:18:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13461078 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="OJhASzGg" Received: from mail-wm1-x336.google.com (mail-wm1-x336.google.com [IPv6:2a00:1450:4864:20::336]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BF54E1707 for ; Mon, 20 Nov 2023 03:18:42 -0800 (PST) Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-40b23aeb9d9so4776965e9.3 for ; Mon, 20 Nov 2023 03:18:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1700479121; x=1701083921; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ptQiN1S6gJwg7uT81xFHroZyIQZNKxY8fT8PJ58AJo4=; b=OJhASzGg2XqGKK19Hd0sGp45Vs86iL1W8HjaiUwfGV8P/Vka4DSYgt1r1AOmkn4DlO gI+wWkkOzjP6cUOmw5wNY3/08b/UzRV9Aou/ykcZc4rBDjsvUoKHpPXNRESKnVQx9vOf ehrIZPLU0mdkwU2JpGpGsSg1LZ12OglTfB/aWkG29ysw4lF9rxHyhLv9g1aSgiZIYob7 eBXE01zzMrxySZjZooUTFh/fCjetlJlz1YA8mAZrJs7N26BSC15bZ3V8Elxy/4y4W0NZ /5cWKPa4u7brO30VG92uGSEiMUZdImAQw8DhlWNrQemLXxnzCOs6XUIjtmrA0PGOPpjC IeRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700479121; x=1701083921; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ptQiN1S6gJwg7uT81xFHroZyIQZNKxY8fT8PJ58AJo4=; b=JbqQHn+whpQVla4vdX1kKKmrbtNWxivQxx8ySbv6OhCEHGKwswnoVbWjxY3ip+rUKY EXHsm09KAhMQQIiWtNmOK4EJf4nN/Rr35e1nYEiW06WT+GN7ocBPxT8XSBL8e3Ls5Hzy fWgqpCMW8J0aRjjd0pKeX0Z1yW4yJb0zynf5pATTf4oupAEfDJUvPkru6e6Qr18KQao5 0TLa08Yzp42DkapdXb7j4qd44qnTKIp+GeVYt27WZZOsaPwcoms6i/ZFLC7nMeba9kta rld9v+SBuHtpi2PSaO0MpMmyYtXZlLN2p1MPIqLL5ai5c4bQT2Q/heWPry4j9xTcpIF0 WGQg== X-Gm-Message-State: AOJu0YzJC1/0ChNVPZ6f1i1BbW7MQ5n1lH5DmvEYlctNfUBH5FssHeAT SmPh3M+mS5LYHTGyc1Gxcugfdw== X-Google-Smtp-Source: AGHT+IFU8rlbSjXZPP5nvJmH/WWhnefTiuKeGPD0GA72G9qNeDNZ4oQXOndWcr4wW3agcRaLHHpDYg== X-Received: by 2002:a05:600c:4f56:b0:402:8c7e:3fc4 with SMTP id m22-20020a05600c4f5600b004028c7e3fc4mr5606755wmq.30.1700479121095; Mon, 20 Nov 2023 03:18:41 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.183]) by smtp.gmail.com with ESMTPSA id g6-20020a05600c310600b0040651505684sm13142676wmo.29.2023.11.20.03.18.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Nov 2023 03:18:40 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: tglx@linutronix.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, prabhakar.mahadev-lad.rj@bp.renesas.com Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Claudiu Beznea , Conor Dooley Subject: [PATCH v3 8/9] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G3S Date: Mon, 20 Nov 2023 13:18:19 +0200 Message-Id: <20231120111820.87398-9-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231120111820.87398-1-claudiu.beznea.uj@bp.renesas.com> References: <20231120111820.87398-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Document RZ/G3S (R9108G045) interrupt controller. This has few extra functionalities compared with RZ/G2UL but the already existing driver could still be used. Acked-by: Conor Dooley Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- .../bindings/interrupt-controller/renesas,rzg2l-irqc.yaml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml index 2ef3081eaaf3..d3b5aec0a3f7 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml @@ -26,6 +26,7 @@ properties: - renesas,r9a07g043u-irqc # RZ/G2UL - renesas,r9a07g044-irqc # RZ/G2{L,LC} - renesas,r9a07g054-irqc # RZ/V2L + - renesas,r9a08g045-irqc # RZ/G3S - const: renesas,rzg2l-irqc '#interrupt-cells': @@ -167,7 +168,9 @@ allOf: properties: compatible: contains: - const: renesas,r9a07g043u-irqc + enum: + - renesas,r9a07g043u-irqc + - renesas,r9a08g045-irqc then: properties: interrupts: From patchwork Mon Nov 20 11:18:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: claudiu beznea X-Patchwork-Id: 13461079 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="pOOKuEFp" Received: from mail-wm1-x330.google.com (mail-wm1-x330.google.com [IPv6:2a00:1450:4864:20::330]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0676010F7 for ; Mon, 20 Nov 2023 03:18:44 -0800 (PST) Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-40839807e82so9670795e9.0 for ; Mon, 20 Nov 2023 03:18:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1700479122; x=1701083922; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bGvXvdztvnU1Noz3qGE9zeJXlVtwjcExrfXoSufIG6g=; b=pOOKuEFpUEgBmFpMI7RSjFsYDT8AECq+ge4189kqw49264Pci3accNK65X1Yf3aS/g I4nxjk57NyAcOHvIE6fYwJZJdH8OYdnqhwhoDssmwhb9ZGhW54/HSRkY2pI2WIC7ODg9 2iMl2yVWw84bPANMe9c/KmT7g+QLk6fuTPKvQ8Z3V5vW78ia38oQB4mzk4UMx4jq/JyK bj2LMa/CIff+KipplMElmGK6yz9cy5X2mAe6hhcQFzDwBmYoDPlQVi8+6VHyYVL8F0TX lp6AfpK9LyGIXT2cRMe6vmLpw/ulYQ4xLuiygh1aKMC8Z8FiIS043M/6mtsd1c0zisbu +I4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700479122; x=1701083922; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bGvXvdztvnU1Noz3qGE9zeJXlVtwjcExrfXoSufIG6g=; b=UEW6ABc80GK2vQg3eY6ck/C1NUP/Iyu61rkRQcf8i+ytxWvhRse5Sj1la9KJWUUO2J BRfuf+WC+H4IO06EcmMdoqLpAhVTVugI5EtU/4ju2XpF0NaS0v6+DjiMX5kr9qb7CdZ+ JveO1bM7e4JOImsWUPD3gOy6W25OSp6gxNSCEPg4NIwAEQ7jwtsAdZDGALkbAxnO8pSM 5hcFGHDa2bHAZo5pofgQyomyzNhMoXonyTk7EEjTTOQ80jfi1Kth+nQkv7XjBmd9g5u/ XSRStKuJcn7GLbuJbm8hiQORp6ZzKTJBEGrssvnzTjvDfjTcvleqA8+uyG6+T1/u618U lXsg== X-Gm-Message-State: AOJu0YwhzloeNxH7EOf1M4rT7KIMSMzVp7z5JClQzo5EY7HZJviqD6v2 ldPQneuELPmFGMT9e2kAKYO1dw== X-Google-Smtp-Source: AGHT+IFiqC0hAoROkF8bGe1DWe/xZ03qtfGR9V52jRRdovggVx9Iq3wYl/7ufgUAj6kVUgCoo0FR1g== X-Received: by 2002:a05:600c:358e:b0:409:6e0e:e95a with SMTP id p14-20020a05600c358e00b004096e0ee95amr5778715wmq.19.1700479122593; Mon, 20 Nov 2023 03:18:42 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.183]) by smtp.gmail.com with ESMTPSA id g6-20020a05600c310600b0040651505684sm13142676wmo.29.2023.11.20.03.18.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Nov 2023 03:18:42 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: tglx@linutronix.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, prabhakar.mahadev-lad.rj@bp.renesas.com Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Claudiu Beznea Subject: [PATCH v3 9/9] arm64: dts: renesas: r9108g045: Add IA55 interrupt controller node Date: Mon, 20 Nov 2023 13:18:20 +0200 Message-Id: <20231120111820.87398-10-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231120111820.87398-1-claudiu.beznea.uj@bp.renesas.com> References: <20231120111820.87398-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Add IA55 interrupt controller node and set it as interrupt parent for pin controller. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 68 ++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index 02a5dc9a0a3e..793512c4b31c 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -101,6 +101,7 @@ pinctrl: pinctrl@11030000 { #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + interrupt-parent = <&irqc>; gpio-ranges = <&pinctrl 0 0 152>; clocks = <&cpg CPG_MOD R9A08G045_GPIO_HCLK>; power-domains = <&cpg>; @@ -109,6 +110,73 @@ pinctrl: pinctrl@11030000 { <&cpg R9A08G045_GPIO_SPARE_RESETN>; }; + irqc: interrupt-controller@11050000 { + compatible = "renesas,r9a08g045-irqc", "renesas,rzg2l-irqc"; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0x11050000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "nmi", + "irq0", "irq1", "irq2", "irq3", + "irq4", "irq5", "irq6", "irq7", + "tint0", "tint1", "tint2", "tint3", + "tint4", "tint5", "tint6", "tint7", + "tint8", "tint9", "tint10", "tint11", + "tint12", "tint13", "tint14", "tint15", + "tint16", "tint17", "tint18", "tint19", + "tint20", "tint21", "tint22", "tint23", + "tint24", "tint25", "tint26", "tint27", + "tint28", "tint29", "tint30", "tint31", + "bus-err"; + clocks = <&cpg CPG_MOD R9A08G045_IA55_CLK>, + <&cpg CPG_MOD R9A08G045_IA55_PCLK>; + clock-names = "clk", "pclk"; + power-domains = <&cpg>; + resets = <&cpg R9A08G045_IA55_RESETN>; + }; + sdhi0: mmc@11c00000 { compatible = "renesas,sdhi-r9a08g045", "renesas,rcar-gen3-sdhi"; reg = <0x0 0x11c00000 0 0x10000>;