From patchwork Mon Nov 20 13:50:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 13461339 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="HmIofVy0" Received: from mail-wm1-x331.google.com (mail-wm1-x331.google.com [IPv6:2a00:1450:4864:20::331]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B08EC11A; Mon, 20 Nov 2023 05:51:14 -0800 (PST) Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-40842752c6eso16249175e9.1; Mon, 20 Nov 2023 05:51:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1700488273; x=1701093073; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=170V99bF9fbfKYiUs+utHt6sltSk5a5hRXsRWfq9j/0=; b=HmIofVy08rNlatvNMXCD1zP9m32NF/HRYHJPkmME4lW12R6gx5PEUZUBS241lu5nUy RzWaI9KiGaLqyzJI64PvQ5QJbJ+FENq34VvjfbA85INHniRuOWKEarLY0uE/vA7zUHIq nE6UFB8LkVnL1IiUaPva7nKrYLzOKlGlGaOci3AfrB7GkWozQNV+aLgspMLzZ40geFyM V0+qQ4zgb92UPCNwxPcT96Zg1WNCt+ea/Nxcl8aZwY4qDmSpd8Gc1irT378+8gIFBMjU 8YF0Fb6WXm3AXgIMhUnCMZwhKHS+Wn1n/4KoYSsYNxBu43abStCifCSkqW68JaIMIaJ8 vGdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700488273; x=1701093073; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=170V99bF9fbfKYiUs+utHt6sltSk5a5hRXsRWfq9j/0=; b=RPw9qwxO4FTGwRxizaPfELUWdEJvXv/5Z4bnynsyAH4p+lEb4N5Op8iI6j7aqdbkmz uNfMsuEn8BNCIuDViUuNh9zuHNss7KvOHhsTZDMNn8oVIkeh+/D9Y/NGcP4FoJQQeHYu x8EimvLVLESSYUMoCH/doQWehn5dpcnE37FMTtG3vRNZamL29I0lZk5Q5heJ/QK2OR2o DINqZcZs8RFCKWmEdpvg5nULn5ZmGMzTtYEtjfRk3Jk/cIZK4EGwiGUYSLvYckrk/jHz qvRT9/I62dZ3/E6e0VLSwct2W7NHE4GeQ5idvYsRttu9SfsL9iBcmsLqeYYLG2nNJb4r xWVw== X-Gm-Message-State: AOJu0Yw3YHiO7Zov6UN43ckVkQppZ6FacvWRtsMynGotejUWzH2/BM82 815Qgm6sEIVUmE2ZrBCgirE= X-Google-Smtp-Source: AGHT+IFTkDfxMNb1b6FZQ9MepE/DjOHpjkTOnj3b3hIBgk5iYkgdd79aYf85OFwnUYWEh7hwYf5COA== X-Received: by 2002:a05:600c:4445:b0:407:8e85:899f with SMTP id v5-20020a05600c444500b004078e85899fmr6518168wmn.16.1700488272715; Mon, 20 Nov 2023 05:51:12 -0800 (PST) Received: from localhost.localdomain (93-34-89-13.ip49.fastwebnet.it. [93.34.89.13]) by smtp.googlemail.com with ESMTPSA id j33-20020a05600c1c2100b0040772934b12sm18205846wms.7.2023.11.20.05.51.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Nov 2023 05:51:12 -0800 (PST) From: Christian Marangi To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Andrew Lunn , Heiner Kallweit , Russell King , Florian Fainelli , Broadcom internal kernel review list , Daniel Golle , Qingfang Deng , SkyLake Huang , Matthias Brugger , AngeloGioacchino Del Regno , David Epping , Vladimir Oltean , Christian Marangi , "Russell King (Oracle)" , Harini Katakam , Simon Horman , Robert Marko , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [net-next RFC PATCH 01/14] net: phy: extend PHY package API to support multiple global address Date: Mon, 20 Nov 2023 14:50:28 +0100 Message-Id: <20231120135041.15259-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231120135041.15259-1-ansuelsmth@gmail.com> References: <20231120135041.15259-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Current API for PHY package are limited to single address to configure global settings for the PHY package. It was found that some PHY package (for example the qca807x, a PHY package that is shipped with a bundle of 5 PHY) require multiple PHY address to configure global settings. An example scenario is a PHY that have a dedicated PHY for PSGMII/serdes calibrarion and have a specific PHY in the package where the global PHY mode is set and affects every other PHY in the package. Change the API in the following way: - Make phy_package_join() require a list of address to be passed and the number of address in the list - On shared data init, each address is the list is checked and added to the shared struct. - Make __/phy_package_write/read() require an additional arg that select what global PHY address to use in the provided list. Each user of this API is updated to follow this new implementation following a pattern where an enum is defined to declare the index of the addr and the addr list is passed. Signed-off-by: Christian Marangi --- drivers/net/phy/bcm54140.c | 23 +++++++-- drivers/net/phy/mediatek-ge-soc.c | 11 +++- drivers/net/phy/micrel.c | 13 +++-- drivers/net/phy/mscc/mscc.h | 7 +++ drivers/net/phy/mscc/mscc_main.c | 16 ++++-- drivers/net/phy/phy_device.c | 85 ++++++++++++++++++++----------- include/linux/phy.h | 51 +++++++++++++------ 7 files changed, 147 insertions(+), 59 deletions(-) diff --git a/drivers/net/phy/bcm54140.c b/drivers/net/phy/bcm54140.c index d43076592f81..89c735b386d3 100644 --- a/drivers/net/phy/bcm54140.c +++ b/drivers/net/phy/bcm54140.c @@ -128,6 +128,12 @@ #define BCM54140_DEFAULT_DOWNSHIFT 5 #define BCM54140_MAX_DOWNSHIFT 9 +enum bcm54140_global_phy { + BCM54140_BASE_ADDR = 0, + + __BCM54140_GLOBAL_PHY_MAX, +}; + struct bcm54140_priv { int port; int base_addr; @@ -429,11 +435,13 @@ static int bcm54140_base_read_rdb(struct phy_device *phydev, u16 rdb) int ret; phy_lock_mdio_bus(phydev); - ret = __phy_package_write(phydev, MII_BCM54XX_RDB_ADDR, rdb); + ret = __phy_package_write(phydev, BCM54140_BASE_ADDR, + MII_BCM54XX_RDB_ADDR, rdb); if (ret < 0) goto out; - ret = __phy_package_read(phydev, MII_BCM54XX_RDB_DATA); + ret = __phy_package_read(phydev, BCM54140_BASE_ADDR, + MII_BCM54XX_RDB_DATA); out: phy_unlock_mdio_bus(phydev); @@ -446,11 +454,13 @@ static int bcm54140_base_write_rdb(struct phy_device *phydev, int ret; phy_lock_mdio_bus(phydev); - ret = __phy_package_write(phydev, MII_BCM54XX_RDB_ADDR, rdb); + ret = __phy_package_write(phydev, BCM54140_BASE_ADDR, + MII_BCM54XX_RDB_ADDR, rdb); if (ret < 0) goto out; - ret = __phy_package_write(phydev, MII_BCM54XX_RDB_DATA, val); + ret = __phy_package_write(phydev, BCM54140_BASE_ADDR, + MII_BCM54XX_RDB_DATA, val); out: phy_unlock_mdio_bus(phydev); @@ -570,6 +580,7 @@ static int bcm54140_get_base_addr_and_port(struct phy_device *phydev) static int bcm54140_probe(struct phy_device *phydev) { + int addrs[__BCM54140_GLOBAL_PHY_MAX]; struct bcm54140_priv *priv; int ret; @@ -583,7 +594,9 @@ static int bcm54140_probe(struct phy_device *phydev) if (ret) return ret; - devm_phy_package_join(&phydev->mdio.dev, phydev, priv->base_addr, 0); + addrs[BCM54140_BASE_ADDR] = priv->base_addr; + devm_phy_package_join(&phydev->mdio.dev, phydev, addrs, + ARRAY_SIZE(addrs), 0); #if IS_ENABLED(CONFIG_HWMON) mutex_init(&priv->alarm_lock); diff --git a/drivers/net/phy/mediatek-ge-soc.c b/drivers/net/phy/mediatek-ge-soc.c index 8a20d9889f10..3f2043fe05ed 100644 --- a/drivers/net/phy/mediatek-ge-soc.c +++ b/drivers/net/phy/mediatek-ge-soc.c @@ -298,6 +298,12 @@ struct mtk_socphy_priv { unsigned long led_state; }; +enum mtk_global_phy { + MTK_BASE_ADDR = 0, + + __MTK_GLOBAL_PHY_MAX +}; + struct mtk_socphy_shared { u32 boottrap; struct mtk_socphy_priv priv[4]; @@ -1431,13 +1437,16 @@ static void mt798x_phy_leds_state_init(struct phy_device *phydev) static int mt7988_phy_probe(struct phy_device *phydev) { struct mtk_socphy_shared *shared; + int addrs[__MTK_GLOBAL_PHY_MAX]; struct mtk_socphy_priv *priv; int err; if (phydev->mdio.addr > 3) return -EINVAL; - err = devm_phy_package_join(&phydev->mdio.dev, phydev, 0, + addrs[MTK_BASE_ADDR] = 0; + err = devm_phy_package_join(&phydev->mdio.dev, phydev, + addrs, ARRAY_SIZE(addrs), sizeof(struct mtk_socphy_shared)); if (err) return err; diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c index 08e3915001c3..94a4c7d9ae9c 100644 --- a/drivers/net/phy/micrel.c +++ b/drivers/net/phy/micrel.c @@ -328,6 +328,12 @@ struct kszphy_ptp_priv { spinlock_t seconds_lock; }; +enum ksz_global_phy { + KSZ_BASE_ADDR = 0, + + __KZS_GLOBAL_PHY_MAX, +}; + struct kszphy_priv { struct kszphy_ptp_priv ptp_priv; const struct kszphy_type *type; @@ -3274,8 +3280,8 @@ static int lan8814_release_coma_mode(struct phy_device *phydev) static int lan8814_probe(struct phy_device *phydev) { const struct kszphy_type *type = phydev->drv->driver_data; + int addrs[__KZS_GLOBAL_PHY_MAX]; struct kszphy_priv *priv; - u16 addr; int err; priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); @@ -3291,9 +3297,10 @@ static int lan8814_probe(struct phy_device *phydev) /* Strap-in value for PHY address, below register read gives starting * phy address value */ - addr = lanphy_read_page_reg(phydev, 4, 0) & 0x1F; + addrs[KSZ_BASE_ADDR] = lanphy_read_page_reg(phydev, 4, 0) & 0x1F; devm_phy_package_join(&phydev->mdio.dev, phydev, - addr, sizeof(struct lan8814_shared_priv)); + addrs, ARRAY_SIZE(addrs), + sizeof(struct lan8814_shared_priv)); if (phy_package_init_once(phydev)) { err = lan8814_release_coma_mode(phydev); diff --git a/drivers/net/phy/mscc/mscc.h b/drivers/net/phy/mscc/mscc.h index 7a962050a4d4..88da8eca2b94 100644 --- a/drivers/net/phy/mscc/mscc.h +++ b/drivers/net/phy/mscc/mscc.h @@ -416,6 +416,13 @@ struct vsc8531_private { * gpio_lock: used for PHC operations. Common for all PHYs as the load/save GPIO * is shared. */ + +enum vsc85xx_global_phy { + VSC88XX_BASE_ADDR = 0, + + __VSC8XX_GLOBAL_PHY_MAX, +}; + struct vsc85xx_shared_private { struct mutex gpio_lock; }; diff --git a/drivers/net/phy/mscc/mscc_main.c b/drivers/net/phy/mscc/mscc_main.c index 4171f01d34e5..749d4a6be60c 100644 --- a/drivers/net/phy/mscc/mscc_main.c +++ b/drivers/net/phy/mscc/mscc_main.c @@ -711,7 +711,7 @@ int phy_base_write(struct phy_device *phydev, u32 regnum, u16 val) dump_stack(); } - return __phy_package_write(phydev, regnum, val); + return __phy_package_write(phydev, VSC88XX_BASE_ADDR, regnum, val); } /* phydev->bus->mdio_lock should be locked when using this function */ @@ -722,7 +722,7 @@ int phy_base_read(struct phy_device *phydev, u32 regnum) dump_stack(); } - return __phy_package_read(phydev, regnum); + return __phy_package_read(phydev, VSC88XX_BASE_ADDR, regnum); } u32 vsc85xx_csr_read(struct phy_device *phydev, @@ -2204,6 +2204,7 @@ static int vsc85xx_read_status(struct phy_device *phydev) static int vsc8514_probe(struct phy_device *phydev) { + int addrs[__VSC8XX_GLOBAL_PHY_MAX]; struct vsc8531_private *vsc8531; u32 default_mode[4] = {VSC8531_LINK_1000_ACTIVITY, VSC8531_LINK_100_ACTIVITY, VSC8531_LINK_ACTIVITY, @@ -2216,8 +2217,9 @@ static int vsc8514_probe(struct phy_device *phydev) phydev->priv = vsc8531; vsc8584_get_base_addr(phydev); + addrs[VSC88XX_BASE_ADDR] = vsc8531->base_addr; devm_phy_package_join(&phydev->mdio.dev, phydev, - vsc8531->base_addr, 0); + addrs, ARRAY_SIZE(addrs), 0); vsc8531->nleds = 4; vsc8531->supp_led_modes = VSC85XX_SUPP_LED_MODES; @@ -2233,6 +2235,7 @@ static int vsc8514_probe(struct phy_device *phydev) static int vsc8574_probe(struct phy_device *phydev) { + int addrs[__VSC8XX_GLOBAL_PHY_MAX]; struct vsc8531_private *vsc8531; u32 default_mode[4] = {VSC8531_LINK_1000_ACTIVITY, VSC8531_LINK_100_ACTIVITY, VSC8531_LINK_ACTIVITY, @@ -2245,8 +2248,9 @@ static int vsc8574_probe(struct phy_device *phydev) phydev->priv = vsc8531; vsc8584_get_base_addr(phydev); + addrs[VSC88XX_BASE_ADDR] = vsc8531->base_addr; devm_phy_package_join(&phydev->mdio.dev, phydev, - vsc8531->base_addr, 0); + addrs, ARRAY_SIZE(addrs), 0); vsc8531->nleds = 4; vsc8531->supp_led_modes = VSC8584_SUPP_LED_MODES; @@ -2262,6 +2266,7 @@ static int vsc8574_probe(struct phy_device *phydev) static int vsc8584_probe(struct phy_device *phydev) { + int addrs[__VSC8XX_GLOBAL_PHY_MAX]; struct vsc8531_private *vsc8531; u32 default_mode[4] = {VSC8531_LINK_1000_ACTIVITY, VSC8531_LINK_100_ACTIVITY, VSC8531_LINK_ACTIVITY, @@ -2280,7 +2285,8 @@ static int vsc8584_probe(struct phy_device *phydev) phydev->priv = vsc8531; vsc8584_get_base_addr(phydev); - devm_phy_package_join(&phydev->mdio.dev, phydev, vsc8531->base_addr, + addrs[VSC88XX_BASE_ADDR] = vsc8531->base_addr; + devm_phy_package_join(&phydev->mdio.dev, phydev, addrs, ARRAY_SIZE(addrs), sizeof(struct vsc85xx_shared_private)); vsc8531->nleds = 4; diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c index 478126f6b5bc..e016dbfb0d27 100644 --- a/drivers/net/phy/phy_device.c +++ b/drivers/net/phy/phy_device.c @@ -1648,59 +1648,80 @@ EXPORT_SYMBOL_GPL(phy_driver_is_genphy_10g); /** * phy_package_join - join a common PHY group * @phydev: target phy_device struct - * @addr: cookie and PHY address for global register access + * @addrs: list of cookies and PHY addresses for global register access + * @addrs_num: num of cookies and PHY address in addrs list * @priv_size: if non-zero allocate this amount of bytes for private data * * This joins a PHY group and provides a shared storage for all phydevs in * this group. This is intended to be used for packages which contain * more than one PHY, for example a quad PHY transceiver. * - * The addr parameter serves as a cookie which has to have the same value + * The addrs parameters serves as cookies which has to have the same values * for all members of one group and as a PHY address to access generic * registers of a PHY package. Usually, one of the PHY addresses of the * different PHYs in the package provides access to these global registers. - * The address which is given here, will be used in the phy_package_read() + * The addresses which is given here, will be used in the phy_package_read() * and phy_package_write() convenience functions. If your PHY doesn't have * global registers you can just pick any of the PHY addresses. + * In some special PHY package, multiple PHY are used for global init of + * the entire PHY package. In the scenario, multiple address are defined. + * phy_package_read() and phy_package_write() requires an index to be passed + * to communicate which PHY to use for global init on read/write. * * This will set the shared pointer of the phydev to the shared storage. * If this is the first call for a this cookie the shared storage will be * allocated. If priv_size is non-zero, the given amount of bytes are * allocated for the priv member. + * A list is allocated based on the addrs_num value and the passed list in + * addrs is copied to the just allocated list. * * Returns < 1 on error, 0 on success. Esp. calling phy_package_join() * with the same cookie but a different priv_size is an error. */ -int phy_package_join(struct phy_device *phydev, int addr, size_t priv_size) +int phy_package_join(struct phy_device *phydev, int *addrs, size_t addrs_num, + size_t priv_size) { struct mii_bus *bus = phydev->mdio.bus; struct phy_package_shared *shared; - int ret; + int *shared_addrs; + int i, addr, ret; - if (addr < 0 || addr >= PHY_MAX_ADDR) + if (!addrs || !addrs_num) return -EINVAL; + for (i = 0; i < addrs_num; i++) + if (addrs[i] < 0 || addrs[i] >= PHY_MAX_ADDR) + return -EINVAL; + mutex_lock(&bus->shared_lock); - shared = bus->shared[addr]; - if (!shared) { - ret = -ENOMEM; - shared = kzalloc(sizeof(*shared), GFP_KERNEL); - if (!shared) - goto err_unlock; - if (priv_size) { - shared->priv = kzalloc(priv_size, GFP_KERNEL); - if (!shared->priv) - goto err_free; - shared->priv_size = priv_size; + for (i = 0; i < addrs_num; i++) { + addr = addrs[i]; + shared = bus->shared[addr]; + if (!shared) { + ret = -ENOMEM; + shared = kzalloc(sizeof(*shared), GFP_KERNEL); + if (!shared) + goto err_unlock; + if (priv_size) { + shared->priv = kzalloc(priv_size, GFP_KERNEL); + if (!shared->priv) + goto err_free; + shared->priv_size = priv_size; + } + shared_addrs = kmalloc_array(addrs_num, sizeof(*addrs), GFP_KERNEL); + if (!shared_addrs) + goto err_free_priv; + memcpy(shared_addrs, addrs, sizeof(*addrs) * addrs_num); + shared->addrs = shared_addrs; + shared->addrs_num = addrs_num; + refcount_set(&shared->refcnt, 1); + bus->shared[addr] = shared; + } else { + ret = -EINVAL; + if (priv_size && priv_size != shared->priv_size) + goto err_unlock; + refcount_inc(&shared->refcnt); } - shared->addr = addr; - refcount_set(&shared->refcnt, 1); - bus->shared[addr] = shared; - } else { - ret = -EINVAL; - if (priv_size && priv_size != shared->priv_size) - goto err_unlock; - refcount_inc(&shared->refcnt); } mutex_unlock(&bus->shared_lock); @@ -1708,6 +1729,8 @@ int phy_package_join(struct phy_device *phydev, int addr, size_t priv_size) return 0; +err_free_priv: + kfree(shared->priv); err_free: kfree(shared); err_unlock: @@ -1728,13 +1751,16 @@ void phy_package_leave(struct phy_device *phydev) { struct phy_package_shared *shared = phydev->shared; struct mii_bus *bus = phydev->mdio.bus; + int i; if (!shared) return; if (refcount_dec_and_mutex_lock(&shared->refcnt, &bus->shared_lock)) { - bus->shared[shared->addr] = NULL; + for (i = 0; i < shared->addrs_num; i++) + bus->shared[shared->addrs[i]] = NULL; mutex_unlock(&bus->shared_lock); + kfree(shared->addrs); kfree(shared->priv); kfree(shared); } @@ -1752,7 +1778,8 @@ static void devm_phy_package_leave(struct device *dev, void *res) * devm_phy_package_join - resource managed phy_package_join() * @dev: device that is registering this PHY package * @phydev: target phy_device struct - * @addr: cookie and PHY address for global register access + * @addrs: list of cookies and PHY addresses for global register access + * @addrs_num: num of cookies and PHY address in addrs list * @priv_size: if non-zero allocate this amount of bytes for private data * * Managed phy_package_join(). Shared storage fetched by this function, @@ -1760,7 +1787,7 @@ static void devm_phy_package_leave(struct device *dev, void *res) * phy_package_join() for more information. */ int devm_phy_package_join(struct device *dev, struct phy_device *phydev, - int addr, size_t priv_size) + int *addrs, size_t addrs_num, size_t priv_size) { struct phy_device **ptr; int ret; @@ -1770,7 +1797,7 @@ int devm_phy_package_join(struct device *dev, struct phy_device *phydev, if (!ptr) return -ENOMEM; - ret = phy_package_join(phydev, addr, priv_size); + ret = phy_package_join(phydev, addrs, addrs_num, priv_size); if (!ret) { *ptr = phydev; diff --git a/include/linux/phy.h b/include/linux/phy.h index 3cc52826f18e..c2bb3f0b9dda 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -327,7 +327,8 @@ struct mdio_bus_stats { /** * struct phy_package_shared - Shared information in PHY packages - * @addr: Common PHY address used to combine PHYs in one package + * @addrs: List of common PHY addresses used to combine PHYs in one package + * @addrs_num: Number of common PHY addresses in addrs list * @refcnt: Number of PHYs connected to this shared data * @flags: Initialization of PHY package * @priv_size: Size of the shared private data @priv @@ -338,7 +339,14 @@ struct mdio_bus_stats { * phy_package_leave(). */ struct phy_package_shared { - int addr; + /* addrs list pointer */ + /* note that this pointer is shared between different phydevs. + * It is allocated and freed automatically by phy_package_join() and + * phy_package_leave(), the list passed to phy_package_join() is copied + * to the new allocated list. + */ + int *addrs; + size_t addrs_num; refcount_t refcnt; unsigned long flags; size_t priv_size; @@ -1970,10 +1978,11 @@ int phy_ethtool_get_link_ksettings(struct net_device *ndev, int phy_ethtool_set_link_ksettings(struct net_device *ndev, const struct ethtool_link_ksettings *cmd); int phy_ethtool_nway_reset(struct net_device *ndev); -int phy_package_join(struct phy_device *phydev, int addr, size_t priv_size); +int phy_package_join(struct phy_device *phydev, int *addrs, size_t addrs_num, + size_t priv_size); void phy_package_leave(struct phy_device *phydev); int devm_phy_package_join(struct device *dev, struct phy_device *phydev, - int addr, size_t priv_size); + int *addrs, size_t addrs_num, size_t priv_size); int __init mdio_bus_init(void); void mdio_bus_exit(void); @@ -1996,46 +2005,56 @@ int __phy_hwtstamp_set(struct phy_device *phydev, struct kernel_hwtstamp_config *config, struct netlink_ext_ack *extack); -static inline int phy_package_read(struct phy_device *phydev, u32 regnum) +static inline int phy_package_read(struct phy_device *phydev, + int global_phy_index, u32 regnum) { struct phy_package_shared *shared = phydev->shared; + int addr; - if (!shared) + if (!shared || global_phy_index > shared->addrs_num - 1) return -EIO; - return mdiobus_read(phydev->mdio.bus, shared->addr, regnum); + addr = shared->addrs[global_phy_index]; + return mdiobus_read(phydev->mdio.bus, addr, regnum); } -static inline int __phy_package_read(struct phy_device *phydev, u32 regnum) +static inline int __phy_package_read(struct phy_device *phydev, + int global_phy_index, u32 regnum) { struct phy_package_shared *shared = phydev->shared; + int addr; - if (!shared) + if (!shared || global_phy_index > shared->addrs_num - 1) return -EIO; - return __mdiobus_read(phydev->mdio.bus, shared->addr, regnum); + addr = shared->addrs[global_phy_index]; + return __mdiobus_read(phydev->mdio.bus, addr, regnum); } static inline int phy_package_write(struct phy_device *phydev, - u32 regnum, u16 val) + int global_phy_index, u32 regnum, u16 val) { struct phy_package_shared *shared = phydev->shared; + int addr; - if (!shared) + if (!shared || global_phy_index > shared->addrs_num - 1) return -EIO; - return mdiobus_write(phydev->mdio.bus, shared->addr, regnum, val); + addr = shared->addrs[global_phy_index]; + return mdiobus_write(phydev->mdio.bus, addr, regnum, val); } static inline int __phy_package_write(struct phy_device *phydev, - u32 regnum, u16 val) + int global_phy_index, u32 regnum, u16 val) { struct phy_package_shared *shared = phydev->shared; + int addr; - if (!shared) + if (!shared || global_phy_index > shared->addrs_num - 1) return -EIO; - return __mdiobus_write(phydev->mdio.bus, shared->addr, regnum, val); + addr = shared->addrs[global_phy_index]; + return __mdiobus_write(phydev->mdio.bus, addr, regnum, val); } static inline bool __phy_package_set_once(struct phy_device *phydev, From patchwork Mon Nov 20 13:50:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 13461338 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="G9XHnbFt" Received: from mail-wm1-x32b.google.com (mail-wm1-x32b.google.com [IPv6:2a00:1450:4864:20::32b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4BCEA116; Mon, 20 Nov 2023 05:51:16 -0800 (PST) Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-4084de32db5so19083985e9.0; Mon, 20 Nov 2023 05:51:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1700488275; x=1701093075; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=mDe+pQVEhH3Sr9b4984YEcBYZXzy8ixz3G1rWEEdZm8=; b=G9XHnbFtyXO/Q9ohweCu+fSUhIFx9cm7Ka51CQ21tkCLQwZl//z0nhWiaYaQmPwkBm TpjQJB/fSOO+shR7YHd7qyWdgcLfRc3PDUYQtjW8T2u9CapDnKje552Xc/xfBP82jmCP a4oOLWlfpTDCGTj91bhakUjy8DO22Spc8arm9j5xdfPThEmxZRCtAJzklGJvOS/hbbXg 6B+v/MyKLz16RBcpw0HlK32w9MddlGDvzsIyCtlyKzoy8bZlkkNI+idefexwcLBhunjN UCf/i8Upbd4S7hrV8pgS/A8veQt3MCxm+0mjdOmdF03Jzz4GRUIMLWVIHd9ua4DP+Sdz SZUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700488275; x=1701093075; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mDe+pQVEhH3Sr9b4984YEcBYZXzy8ixz3G1rWEEdZm8=; b=BOAx2JpRIXlZJe6Siujm0q9rA5+cK8fcb0oebvrSsNgAHQI6AMeqxaE3vCJsrPPkXu tGBcLvmxGv3wlvdt45PcUA3W2wZHMClXyK5qK3KQHKuIEH+E6iUGAZusiUuI1rf37OBi W/7uTRIqSRjsDVHBK8gQ8k39RVnrmlxW3jpC4rI4ppIyB7Bd2gzW7aV9YHoUxDM12Oil CzemwA3a1E1dZD/XCQ1JYkPPFaK3769GLvNcOLoIQvCDZxOppphmLtf6lrfksVxGFd5c Z5jc5GCGaMa5Oi7ckEOnhnDWB51YOhjbGzKewa9S3nl2DSAgu/C3Geqdak+Zwy35X8MK YD3Q== X-Gm-Message-State: AOJu0YxREjsbdmwv4FWLZ+oxwIiKgmd9m79sYhKKYdlRY3F/zgRZuRTJ V5DQW/HR7zr03mpGtvMW7pE= X-Google-Smtp-Source: AGHT+IHVHnzgf8EEZJbwbHrD1fJrQtGhYDQUh/AnVfNHdAOlAXGB/wAsBqejt0p1a7rxHshO7e2S9w== X-Received: by 2002:a05:600c:5248:b0:408:3ab3:a029 with SMTP id fc8-20020a05600c524800b004083ab3a029mr6210181wmb.38.1700488274368; Mon, 20 Nov 2023 05:51:14 -0800 (PST) Received: from localhost.localdomain (93-34-89-13.ip49.fastwebnet.it. [93.34.89.13]) by smtp.googlemail.com with ESMTPSA id j33-20020a05600c1c2100b0040772934b12sm18205846wms.7.2023.11.20.05.51.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Nov 2023 05:51:14 -0800 (PST) From: Christian Marangi To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Andrew Lunn , Heiner Kallweit , Russell King , Florian Fainelli , Broadcom internal kernel review list , Daniel Golle , Qingfang Deng , SkyLake Huang , Matthias Brugger , AngeloGioacchino Del Regno , David Epping , Vladimir Oltean , Christian Marangi , "Russell King (Oracle)" , Harini Katakam , Simon Horman , Robert Marko , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [net-next RFC PATCH 02/14] dt-bindings: net: move PHY modes to common PHY mode types definition Date: Mon, 20 Nov 2023 14:50:29 +0100 Message-Id: <20231120135041.15259-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231120135041.15259-1-ansuelsmth@gmail.com> References: <20231120135041.15259-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Move PHY modes from ethernet-controller schema to dedicated common PHY mode types definition. This is needed to have a centralized place to define PHY interface mode and permit usage and reference of these modes in other schemas. Signed-off-by: Christian Marangi --- .../bindings/net/ethernet-controller.yaml | 47 +------ .../bindings/net/ethernet-phy-mode-types.yaml | 132 ++++++++++++++++++ 2 files changed, 133 insertions(+), 46 deletions(-) create mode 100644 Documentation/devicetree/bindings/net/ethernet-phy-mode-types.yaml diff --git a/Documentation/devicetree/bindings/net/ethernet-controller.yaml b/Documentation/devicetree/bindings/net/ethernet-controller.yaml index 9f6a5ccbcefe..40c1daff2a48 100644 --- a/Documentation/devicetree/bindings/net/ethernet-controller.yaml +++ b/Documentation/devicetree/bindings/net/ethernet-controller.yaml @@ -55,55 +55,10 @@ properties: const: mac-address phy-connection-type: + $ref: /schemas/net/ethernet-phy-mode-types.yaml#definitions/phy-connection-type description: Specifies interface type between the Ethernet device and a physical layer (PHY) device. - enum: - # There is not a standard bus between the MAC and the PHY, - # something proprietary is being used to embed the PHY in the - # MAC. - - internal - - mii - - gmii - - sgmii - - psgmii - - qsgmii - - qusgmii - - tbi - - rev-mii - - rmii - - rev-rmii - - moca - - # RX and TX delays are added by the MAC when required - - rgmii - - # RGMII with internal RX and TX delays provided by the PHY, - # the MAC should not add the RX or TX delays in this case - - rgmii-id - - # RGMII with internal RX delay provided by the PHY, the MAC - # should not add an RX delay in this case - - rgmii-rxid - - # RGMII with internal TX delay provided by the PHY, the MAC - # should not add an TX delay in this case - - rgmii-txid - - rtbi - - smii - - xgmii - - trgmii - - 1000base-x - - 2500base-x - - 5gbase-r - - rxaui - - xaui - - # 10GBASE-KR, XFI, SFI - - 10gbase-kr - - usxgmii - - 10gbase-r - - 25gbase-r phy-mode: $ref: "#/properties/phy-connection-type" diff --git a/Documentation/devicetree/bindings/net/ethernet-phy-mode-types.yaml b/Documentation/devicetree/bindings/net/ethernet-phy-mode-types.yaml new file mode 100644 index 000000000000..6d15743b4ffa --- /dev/null +++ b/Documentation/devicetree/bindings/net/ethernet-phy-mode-types.yaml @@ -0,0 +1,132 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/ethernet-phy-mode-types.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ethernet PHY Common Mode Types + +maintainers: + - David S. Miller + +definitions: + phy-connection-type: + # const: "internal" + allOf: + - $ref: /schemas/types.yaml#/definitions/string + - oneOf: + # There is not a standard bus between the MAC and the PHY, + # something proprietary is being used to embed the PHY in the + # MAC. + - items: + - type: string + const: internal + - items: + - type: string + const: mii + - items: + - type: string + const: gmii + - items: + - type: string + const: sgmii + - items: + - type: string + const: psgmii + - items: + - type: string + const: qsgmii + - items: + - type: string + const: qusgmii + - items: + - type: string + const: tbi + - items: + - type: string + const: rev-mii + - items: + - type: string + const: rmii + - items: + - type: string + const: rev-rmii + - items: + - type: string + const: moca + + # RX and TX delays are added by the MAC when required + - items: + - type: string + const: rgmii + + # RGMII with internal RX and TX delays provided by the PHY, + # the MAC should not add the RX or TX delays in this case + - items: + - type: string + const: rgmii-id + + # RGMII with internal RX delay provided by the PHY, the MAC + # should not add an RX delay in this case + - items: + - type: string + const: rgmii-rxid + + # RGMII with internal TX delay provided by the PHY, the MAC + # should not add an TX delay in this case + - items: + - type: string + const: rgmii-txid + + - items: + - type: string + const: rtbi + + - items: + - type: string + const: smii + + - items: + - type: string + const: xgmii + + - items: + - type: string + const: trgmii + + - items: + - type: string + const: 1000base-x + + - items: + - type: string + const: 2500base-x + + - items: + - type: string + const: 5gbase-r + + - items: + - type: string + const: rxaui + + - items: + - type: string + const: xaui + + # 10GBASE-KR, XFI, SFI + - items: + - type: string + const: 10gbase-kr + + - items: + - type: string + const: usxgmii + + - items: + - type: string + const: 10gbase-r + + - items: + - type: string + const: 25gbase-r From patchwork Mon Nov 20 13:50:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 13461340 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="dIAJDECF" Received: from mail-lj1-x22a.google.com (mail-lj1-x22a.google.com [IPv6:2a00:1450:4864:20::22a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1D05E126; Mon, 20 Nov 2023 05:51:18 -0800 (PST) Received: by mail-lj1-x22a.google.com with SMTP id 38308e7fff4ca-2c5b7764016so53079351fa.1; Mon, 20 Nov 2023 05:51:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1700488276; x=1701093076; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=mSkXFy8s0m4FAo3hSta1RKyG8KAPqujjDp76lrQjrQM=; b=dIAJDECFtovM/SqF68vyMyKsts4M+lf79QkH/pCP22SLdmmmGHLLZ1eJ7qC2dEAzI/ kjgf6qiq8UVTe3qjqohF1ukPaB5fKv19SJcupSZxU8zvAtWAFWExY4M48cQdsG7MJ/Qe zlNN6WHPjbmR5Ya1X6mGNKgnswouIoA7SRx7o+gCPtuP+E0S4OMHewkK+xYnJER0gj0i ny8/IxRggIVSBLnE/gcD0MJ7QrtEdw++k0+U2buDeP8N7RpROXej3aslqlJcDWS3U1N6 cldVDOvRj1L7WD6KNLRT/SrEb4uyx5Jb2tOb9BFXGtLtzRH5pEJTB0ihOTBFNhFIgoCe WK8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700488276; x=1701093076; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mSkXFy8s0m4FAo3hSta1RKyG8KAPqujjDp76lrQjrQM=; b=eIeqSH555xEJ5PiHh+TI0F8nGGQ9n1zABnFgDFb+r5kTLB5Xj4jKzqJzipuL8xCgbP OYRi/MHDZ5jFu2uIVLBgGs+HpT1WCeFP6r5FBxf0SEfNitnUFV0O2ndwigMCfGvqPSRf 8m4wxtNQyce6Rniq/AxTNLhYoU3BN6kxUA+jbknzReXvBjDzUmbyQC3AZMiEiKK3WvEC 1pvubN/t+ZVkYlpSyHwZz7uZG06sh9kyPE/rEkOqtZt6OlDoNM3tQKUTCRT4j9+4kghB /uu2+ihTKcCOWdtbJ9UrLghQWRhQp0yCLFJiwRVQPjuWnWvMNWMxgCxf851p9qUot/4Z sNlw== X-Gm-Message-State: AOJu0YzVOIppXrVzxjXmaqQsV/twC7bzZ9EHXQoZR3aavxPsVSVOSO4M YAZIj882jsE20wyqSEMGfV0= X-Google-Smtp-Source: AGHT+IGRWPskxjGA2rJREXkXtdcG94gsGR4fcmJx18lPkb4K8zHD6Ut0hUV6FgYsk/XQHGBG6tApZg== X-Received: by 2002:a2e:9192:0:b0:2c5:2eaa:5398 with SMTP id f18-20020a2e9192000000b002c52eaa5398mr4967418ljg.25.1700488276123; Mon, 20 Nov 2023 05:51:16 -0800 (PST) Received: from localhost.localdomain (93-34-89-13.ip49.fastwebnet.it. [93.34.89.13]) by smtp.googlemail.com with ESMTPSA id j33-20020a05600c1c2100b0040772934b12sm18205846wms.7.2023.11.20.05.51.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Nov 2023 05:51:15 -0800 (PST) From: Christian Marangi To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Andrew Lunn , Heiner Kallweit , Russell King , Florian Fainelli , Broadcom internal kernel review list , Daniel Golle , Qingfang Deng , SkyLake Huang , Matthias Brugger , AngeloGioacchino Del Regno , David Epping , Vladimir Oltean , Christian Marangi , "Russell King (Oracle)" , Harini Katakam , Simon Horman , Robert Marko , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [net-next RFC PATCH 03/14] dt-bindings: net: document ethernet PHY package nodes Date: Mon, 20 Nov 2023 14:50:30 +0100 Message-Id: <20231120135041.15259-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231120135041.15259-1-ansuelsmth@gmail.com> References: <20231120135041.15259-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Document ethernet PHY package nodes used to describe PHY shipped in bundle of 4-5 PHY. These particular PHY require specific PHY in the package for global onfiguration of the PHY package. Example are PHY package that have some regs only in one PHY of the package and will affect every other PHY in the package, for example related to PHY interface mode calibration or global PHY mode selection. The PHY package node should use the global-phys property and the global-phy-names to define PHY in the package required by the PHY driver for global configuration. It's also possible to specify the property phy-mode to specify that the PHY package sets a global PHY interface mode and every PHY of the package requires to have the same PHY interface mode. Signed-off-by: Christian Marangi --- .../bindings/net/ethernet-phy-package.yaml | 86 +++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/ethernet-phy-package.yaml diff --git a/Documentation/devicetree/bindings/net/ethernet-phy-package.yaml b/Documentation/devicetree/bindings/net/ethernet-phy-package.yaml new file mode 100644 index 000000000000..2aa109e155d9 --- /dev/null +++ b/Documentation/devicetree/bindings/net/ethernet-phy-package.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/ethernet-phy-package.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ethernet PHY Package Common Properties + +maintainers: + - Christian Marangi ; + #size-cells = <0>; + + ethernet-phy-package { + compatible = "ethernet-phy-package"; + #address-cells = <1>; + #size-cells = <0>; + + global-phys = <&phy4>; + global-phy-names = "base"; + + ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + + phy4: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <4>; + }; + }; + }; From patchwork Mon Nov 20 13:50:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 13461341 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="lyHTT3wF" Received: from mail-lj1-x22c.google.com (mail-lj1-x22c.google.com [IPv6:2a00:1450:4864:20::22c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2EB2F194; Mon, 20 Nov 2023 05:51:20 -0800 (PST) Received: by mail-lj1-x22c.google.com with SMTP id 38308e7fff4ca-2c83d37a492so54327121fa.3; Mon, 20 Nov 2023 05:51:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1700488278; x=1701093078; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=FX7V7trfh1DXAxYTuLbIm4MQGMj2UzdEIFOOsY5wQzg=; b=lyHTT3wFdsGJoTupp+QiKLHg+uOcbcxvHOSvnwxIvEgut1SJj/02QQxV2VPuWVtV2K MJ6XLk9rPtDX/w/nqHM3FCyQGzrj3VCw1d2Sihfypb3eq09M9jb65UVStXYs6tJFYlz3 ZwiVPMOZfBhOIRcIMEhFEtIls8+SSVQGTnmpwL8iiRHvjeC+nENHdD96i9oHS5yLQpF0 4mOlwGxAg+NKCwJqIxg3CWq2K/0smWcn7vLQLAbzvEKB2RB5ALaaGXxCW1sMmCjg47Sb F73UCLIxArDYw7scr3L3C4WzBGgGz59TUX7ZbkAEwA7cBJA/js0N8e9dOhZ6IQydnMhv WBZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700488278; x=1701093078; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FX7V7trfh1DXAxYTuLbIm4MQGMj2UzdEIFOOsY5wQzg=; b=TiBOW+Mkc5po0nuMI8RGIpECp9qXBpdoTrGVlAWHaQ0mujTK3P4bmXQLr+uuchOX5b hlL6BmTIk9t6heZaKl+A9DfSiz63hstDn3mK7P++2na8UuWAYSWykK4eXITlcZXDRUGy hIqAu87p0y0Hag1EeKLFe9fAyxiTEYnUrFiPOWFaAyDzJY9swNO4qQxZahLTBI6DcOMc OhQQTTwU/AYxGr+moVftNS0dBle733M+48N15xIOBSg/fdr+BIOXDfM6R5HMtw7PQyYm dS6LvxuuBDOa/3An8uuRQeyp3peGBhWVtXE+DY+KZWmmmqv6RvsqbpR2v82n62R//Rtj 8fqw== X-Gm-Message-State: AOJu0YwL23iZBH2xwOo9nxVBNuyzn/y617+FZwlHZ+ixejjUzRKVrg5o jlscb/Csn/3qHg23O2xNWig= X-Google-Smtp-Source: AGHT+IF4ycEz6nEuh7H0LHPJzm7S6F42GA5GwMWhCXVp35tpWzh2Uz1UI71fbUqJe1Q0eWODeWR8WQ== X-Received: by 2002:a2e:81d8:0:b0:2c6:f625:cc61 with SMTP id s24-20020a2e81d8000000b002c6f625cc61mr4805116ljg.31.1700488278078; Mon, 20 Nov 2023 05:51:18 -0800 (PST) Received: from localhost.localdomain (93-34-89-13.ip49.fastwebnet.it. [93.34.89.13]) by smtp.googlemail.com with ESMTPSA id j33-20020a05600c1c2100b0040772934b12sm18205846wms.7.2023.11.20.05.51.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Nov 2023 05:51:17 -0800 (PST) From: Christian Marangi To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Andrew Lunn , Heiner Kallweit , Russell King , Florian Fainelli , Broadcom internal kernel review list , Daniel Golle , Qingfang Deng , SkyLake Huang , Matthias Brugger , AngeloGioacchino Del Regno , David Epping , Vladimir Oltean , Christian Marangi , "Russell King (Oracle)" , Harini Katakam , Simon Horman , Robert Marko , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [net-next RFC PATCH 04/14] net: phy: add initial support for PHY package in DT Date: Mon, 20 Nov 2023 14:50:31 +0100 Message-Id: <20231120135041.15259-5-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231120135041.15259-1-ansuelsmth@gmail.com> References: <20231120135041.15259-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add initial support for PHY package in DT. Make it easier to define PHY package and describe the global PHY directly in DT by refereincing them by phandles instead of custom functions in each PHY driver. Each PHY in a package needs to be defined in a dedicated node in the mdio node. This dedicated node needs to have the compatible set to "ethernet-phy-package" and define "global-phys" and "#global-phy-cells" respectively to a list of phandle to the global phy to define for the PHY package and 0 for cells as the phandle won't take any args. With this defined, the generic PHY probe will join each PHY in this dedicated node to the package. PHY driver MUST set the required global PHY count in .phy_package_global_phy_num to correctly verify that DT define the correct number of phandle to the required global PHY. mdio_bus.c and of_mdio.c is updated to now support and parse also PHY package subnote that have the compatible "phy-package". Signed-off-by: Christian Marangi --- drivers/net/mdio/of_mdio.c | 60 ++++++++++++++++++++++----------- drivers/net/phy/mdio_bus.c | 33 ++++++++++++++----- drivers/net/phy/phy_device.c | 64 ++++++++++++++++++++++++++++++++++++ include/linux/phy.h | 5 +++ 4 files changed, 135 insertions(+), 27 deletions(-) diff --git a/drivers/net/mdio/of_mdio.c b/drivers/net/mdio/of_mdio.c index 64ebcb6d235c..bb910651118f 100644 --- a/drivers/net/mdio/of_mdio.c +++ b/drivers/net/mdio/of_mdio.c @@ -139,6 +139,44 @@ bool of_mdiobus_child_is_phy(struct device_node *child) } EXPORT_SYMBOL(of_mdiobus_child_is_phy); +static int __of_mdiobus_parse_phys(struct mii_bus *mdio, struct device_node *np, + bool *scanphys) +{ + struct device_node *child; + int addr, rc; + + /* Loop over the child nodes and register a phy_device for each phy */ + for_each_available_child_of_node(np, child) { + if (of_device_is_compatible(child, "ethernet-phy-package")) { + rc = __of_mdiobus_parse_phys(mdio, child, scanphys); + if (rc && rc != -ENODEV) + return rc; + + continue; + } + + addr = of_mdio_parse_addr(&mdio->dev, child); + if (addr < 0) { + *scanphys = true; + continue; + } + + if (of_mdiobus_child_is_phy(child)) + rc = of_mdiobus_register_phy(mdio, child, addr); + else + rc = of_mdiobus_register_device(mdio, child, addr); + + if (rc == -ENODEV) + dev_err(&mdio->dev, + "MDIO device at address %d is missing.\n", + addr); + else if (rc) + return rc; + } + + return 0; +} + /** * __of_mdiobus_register - Register mii_bus and create PHYs from the device tree * @mdio: pointer to mii_bus structure @@ -180,25 +218,9 @@ int __of_mdiobus_register(struct mii_bus *mdio, struct device_node *np, return rc; /* Loop over the child nodes and register a phy_device for each phy */ - for_each_available_child_of_node(np, child) { - addr = of_mdio_parse_addr(&mdio->dev, child); - if (addr < 0) { - scanphys = true; - continue; - } - - if (of_mdiobus_child_is_phy(child)) - rc = of_mdiobus_register_phy(mdio, child, addr); - else - rc = of_mdiobus_register_device(mdio, child, addr); - - if (rc == -ENODEV) - dev_err(&mdio->dev, - "MDIO device at address %d is missing.\n", - addr); - else if (rc) - goto unregister; - } + rc = __of_mdiobus_parse_phys(mdio, np, &scanphys); + if (rc) + goto unregister; if (!scanphys) return 0; diff --git a/drivers/net/phy/mdio_bus.c b/drivers/net/phy/mdio_bus.c index 25dcaa49ab8b..ecec20fd3fd3 100644 --- a/drivers/net/phy/mdio_bus.c +++ b/drivers/net/phy/mdio_bus.c @@ -455,19 +455,23 @@ EXPORT_SYMBOL(of_mdio_find_bus); * found, set the of_node pointer for the mdio device. This allows * auto-probed phy devices to be supplied with information passed in * via DT. + * If a PHY package is found, PHY is searched also there. */ -static void of_mdiobus_link_mdiodev(struct mii_bus *bus, - struct mdio_device *mdiodev) +static int of_mdiobus_find_phy(struct device *dev, struct mdio_device *mdiodev, + struct device_node *np) { - struct device *dev = &mdiodev->dev; struct device_node *child; - if (dev->of_node || !bus->dev.of_node) - return; - - for_each_available_child_of_node(bus->dev.of_node, child) { + for_each_available_child_of_node(np, child) { int addr; + if (of_device_is_compatible(child, "ethernet-phy-package")) { + if (!of_mdiobus_find_phy(dev, mdiodev, child)) + return 0; + + continue; + } + addr = of_mdio_parse_addr(dev, child); if (addr < 0) continue; @@ -477,9 +481,22 @@ static void of_mdiobus_link_mdiodev(struct mii_bus *bus, /* The refcount on "child" is passed to the mdio * device. Do _not_ use of_node_put(child) here. */ - return; + return 0; } } + + return -ENODEV; +} + +static void of_mdiobus_link_mdiodev(struct mii_bus *bus, + struct mdio_device *mdiodev) +{ + struct device *dev = &mdiodev->dev; + + if (dev->of_node || !bus->dev.of_node) + return; + + of_mdiobus_find_phy(dev, mdiodev, bus->dev.of_node); } #else /* !IS_ENABLED(CONFIG_OF_MDIO) */ static inline void of_mdiobus_link_mdiodev(struct mii_bus *mdio, diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c index e016dbfb0d27..9ff76d84dca0 100644 --- a/drivers/net/phy/phy_device.c +++ b/drivers/net/phy/phy_device.c @@ -3193,6 +3193,65 @@ static int of_phy_leds(struct phy_device *phydev) return 0; } +static int of_phy_package(struct phy_device *phydev) +{ + struct device_node *node = phydev->mdio.dev.of_node; + struct of_phandle_args phy_phandle; + struct device_node *package_node; + int i, global_phys_num, ret; + int *global_phy_addrs; + + if (!node) + return 0; + + package_node = of_get_parent(node); + if (!package_node) + return 0; + + if (!of_device_is_compatible(package_node, "ethernet-phy-package")) + return 0; + + ret = of_count_phandle_with_args(package_node, "global-phys", NULL); + if (ret < 0) + return 0; + global_phys_num = ret; + + if (global_phys_num != phydev->drv->phy_package_global_phy_num) + return -EINVAL; + + global_phy_addrs = kmalloc_array(global_phys_num, sizeof(*global_phy_addrs), + GFP_KERNEL); + if (!global_phy_addrs) + return -ENOMEM; + + for (i = 0; i < global_phys_num; i++) { + int addr; + + ret = of_parse_phandle_with_args(package_node, "global-phys", + NULL, i, &phy_phandle); + if (ret) + goto exit; + + ret = of_property_read_u32(phy_phandle.np, "reg", &addr); + if (ret) + goto exit; + + global_phy_addrs[i] = addr; + } + + ret = devm_phy_package_join(&phydev->mdio.dev, phydev, global_phy_addrs, + global_phys_num, 0); + if (ret) + goto exit; + + phydev->shared->np = package_node; + +exit: + kfree(global_phy_addrs); + + return ret; +} + /** * fwnode_mdio_find_device - Given a fwnode, find the mdio_device * @fwnode: pointer to the mdio_device's fwnode @@ -3301,6 +3360,11 @@ static int phy_probe(struct device *dev) if (phydrv->flags & PHY_IS_INTERNAL) phydev->is_internal = true; + /* Parse DT to detect PHY package and join them */ + err = of_phy_package(phydev); + if (err) + goto out; + /* Deassert the reset signal */ phy_device_reset(phydev, 0); diff --git a/include/linux/phy.h b/include/linux/phy.h index c2bb3f0b9dda..5bf90c49e5bd 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -339,6 +339,8 @@ struct mdio_bus_stats { * phy_package_leave(). */ struct phy_package_shared { + /* With PHY package defined in DT this points to the PHY package node */ + struct device_node *np; /* addrs list pointer */ /* note that this pointer is shared between different phydevs. * It is allocated and freed automatically by phy_package_join() and @@ -888,6 +890,8 @@ struct phy_led { * @flags: A bitfield defining certain other features this PHY * supports (like interrupts) * @driver_data: Static driver data + * @phy_package_global_phy_num: Num of the required global phy + * for PHY package global configuration. * * All functions are optional. If config_aneg or read_status * are not implemented, the phy core uses the genphy versions. @@ -905,6 +909,7 @@ struct phy_driver { const unsigned long * const features; u32 flags; const void *driver_data; + unsigned int phy_package_global_phy_num; /** * @soft_reset: Called to issue a PHY software reset From patchwork Mon Nov 20 13:50:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 13461342 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="lR9zlysf" Received: from mail-wm1-x334.google.com (mail-wm1-x334.google.com [IPv6:2a00:1450:4864:20::334]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 77F2CD4C; Mon, 20 Nov 2023 05:51:21 -0800 (PST) Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-40806e4106dso10789515e9.1; Mon, 20 Nov 2023 05:51:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1700488280; x=1701093080; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=TooJwdKX/NbwarJe/arvXU+/yWQ/ijJnXp3t5io/O14=; b=lR9zlysfLiOA/JebJWYcU0QaVOVjrPpSRo6Qf8eYzGzQ3QV1H2l8+KKsTCzo5mvkP4 +mDS7PF5tBX0ywO+zPxZLAedhZ5eobXFISp9tCLsqLg9nWBmA1AnkByU3XxdhXsW9orj b39TqSZOVh1ZVR/t1ZkEv0m9N5WGBRPUlvHGNzNm26RxLc3E+nmiA6StHBDh9TI+MA0d WSG+go6FLtN1UADyF7fdif3jD+gmrZwiyBrHT36WHHFwWR51SoKbrIkL7M6jqTnba6B9 9n/t2RtBVLtLOHYwPObFwAk/6NREnRqYrwplxutMb/N4M/LiOiUWVSU8VAhZZCNpT2Lg mWcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700488280; x=1701093080; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TooJwdKX/NbwarJe/arvXU+/yWQ/ijJnXp3t5io/O14=; b=AK8IF78/6+OHrIod9k0D65JltuecX99PDWGdlHsE7MJb+21X+y9PwnG6zr3/zF9KW1 t4X6Kk/YQus02r1AIi6TAjAnchdEc8OMsMdbU+ORSi8UnOlullotfWRt0dm7BFlfCrKd IUjQHTpuE434JkDF/UNRfo73w4tdP9MKUhNkcL9mOjxq/Wdo5vtRqauC/HUwsWsmcW09 0Dv8efPtZnrCaoZy8jd/g9Oj4vZIXgYpVDiUKOZVdGnrodY5uF6OPzIue64xna1ICNBU HDKhPjhO4zBCRSlHLwsz9ylt2GBRKfXGcd+n4LfcwdUrTApOdqn5g53pBkgsUtmRJq2/ 8iiw== X-Gm-Message-State: AOJu0YxuJYVWtinj20vzWfz9Uly+K1VlgY8Il5zZ/B4ajPj3mtNKaqdC QtlDuZPUK6FsYuMC5i16pZo= X-Google-Smtp-Source: AGHT+IGbR/jLe62wvESEe8CFVjFJBQOHE36zG4blKfXpV72kg2YCPBmafC4MW5hggXNjObGvZiPqSQ== X-Received: by 2002:a05:600c:1c22:b0:40a:4c6c:c87a with SMTP id j34-20020a05600c1c2200b0040a4c6cc87amr6787606wms.3.1700488279771; Mon, 20 Nov 2023 05:51:19 -0800 (PST) Received: from localhost.localdomain (93-34-89-13.ip49.fastwebnet.it. [93.34.89.13]) by smtp.googlemail.com with ESMTPSA id j33-20020a05600c1c2100b0040772934b12sm18205846wms.7.2023.11.20.05.51.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Nov 2023 05:51:19 -0800 (PST) From: Christian Marangi To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Andrew Lunn , Heiner Kallweit , Russell King , Florian Fainelli , Broadcom internal kernel review list , Daniel Golle , Qingfang Deng , SkyLake Huang , Matthias Brugger , AngeloGioacchino Del Regno , David Epping , Vladimir Oltean , Christian Marangi , "Russell King (Oracle)" , Harini Katakam , Simon Horman , Robert Marko , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [net-next RFC PATCH 05/14] net: phy: add support for named global PHY in DT PHY package Date: Mon, 20 Nov 2023 14:50:32 +0100 Message-Id: <20231120135041.15259-6-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231120135041.15259-1-ansuelsmth@gmail.com> References: <20231120135041.15259-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add support for named global PHY in DT PHY package definition. A phy-package node can provide the property "global-phy-names" to provide named global PHY to correctly reference the phandle defined in the global-phys list. Each PHY driver has to define the .phy_package_global_phy_names list to verify correct order of named PHY phandle defined in DT with the expected order in the PHY driver. If the list is not defined or "global-phy-names" is not defined in DT, global phy addresses are insered in order defined in the "global-phys" property. Signed-off-by: Christian Marangi --- drivers/net/phy/phy_device.c | 13 +++++++++++++ include/linux/phy.h | 6 +++++- 2 files changed, 18 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c index 9ff76d84dca0..452fd69e8924 100644 --- a/drivers/net/phy/phy_device.c +++ b/drivers/net/phy/phy_device.c @@ -3198,6 +3198,7 @@ static int of_phy_package(struct phy_device *phydev) struct device_node *node = phydev->mdio.dev.of_node; struct of_phandle_args phy_phandle; struct device_node *package_node; + const char *global_phy_name; int i, global_phys_num, ret; int *global_phy_addrs; @@ -3236,6 +3237,18 @@ static int of_phy_package(struct phy_device *phydev) if (ret) goto exit; + ret = of_property_read_string_index(package_node, "global-phy-names", + i, &global_phy_name); + if (!ret && phydev->drv->phy_package_global_phy_names) { + const char *name; + + name = phydev->drv->phy_package_global_phy_names[i]; + if (strcmp(global_phy_name, name)) { + ret = -EINVAL; + goto exit; + } + } + global_phy_addrs[i] = addr; } diff --git a/include/linux/phy.h b/include/linux/phy.h index 5bf90c49e5bd..5e595a0a43b6 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -892,6 +892,10 @@ struct phy_led { * @driver_data: Static driver data * @phy_package_global_phy_num: Num of the required global phy * for PHY package global configuration. + * @phy_package_global_phy_names: List of global PHY names used + * for PHY package global init. If defined, list is compared + * with DT values to match correct PHY phandle order. List + * last element MUST BE an empty string. * * All functions are optional. If config_aneg or read_status * are not implemented, the phy core uses the genphy versions. @@ -910,6 +914,7 @@ struct phy_driver { u32 flags; const void *driver_data; unsigned int phy_package_global_phy_num; + const char * const *phy_package_global_phy_names; /** * @soft_reset: Called to issue a PHY software reset @@ -1154,7 +1159,6 @@ struct phy_driver { */ int (*led_hw_control_get)(struct phy_device *dev, u8 index, unsigned long *rules); - }; #define to_phy_driver(d) container_of(to_mdio_common_driver(d), \ struct phy_driver, mdiodrv) From patchwork Mon Nov 20 13:50:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 13461343 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="mAzqogHA" Received: from mail-wm1-x32a.google.com (mail-wm1-x32a.google.com [IPv6:2a00:1450:4864:20::32a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 217CED5D; Mon, 20 Nov 2023 05:51:23 -0800 (PST) Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-40842752c6eso16250665e9.1; Mon, 20 Nov 2023 05:51:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1700488281; x=1701093081; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=qB4fi/eCMZ5pGZWSsqUWAAl8tjVSzuSGp4YLf0Eq9M0=; b=mAzqogHAf1D7ONAHYaBcvRLY8y8kp/v0Pmr+NA15XISsQ68WKVxe+MPI62RYMcTuqX T/wDomRuB61Ycq5TaUsjptkKJ0ngs0NU3Co6kMI7zZKfrOVhYYptixAyRo39SJwuKtE4 S9YNa+UmbAg0+mq+EW8GXRqq+ZfMOagqG+ADHss4ZYr2DIrEJb8y/Uvhns/7wKIbNwjI EteutBXF/bTkPeADtYfyvPZAlXUe7RRGYVyCd7qallSSewVHbwPtzu72daTsrCL3U95z iYDjRvK2naegCoteX4a7w+pweSOj6ZL+FiB1XvvXNxrcUU5F4GJPFhQ5LTCiqzE7qa/D U46g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700488281; x=1701093081; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qB4fi/eCMZ5pGZWSsqUWAAl8tjVSzuSGp4YLf0Eq9M0=; b=nEkkqFiShc7tRFlYqoR40AlK0l9CgzgbKoevTdb6hbYHTD4r1ObpwwRpM4WPFmDAqX cSK2U3sX86uKUlG85uxhq0s9BcnAutttimY3jL2jelN+VS4H8gxWaUJVgH05OhPVe1O+ +vT/DAWPbvMhSrCYFMGrk3SIpJvhVys6LbEYwRmUFWd/bMWSeQRnnY0DG92lqq4dC1FV WzL/uU4W7YToEvFicHtRtwQ/i0a8/twt0+WO2QyhMWEac2xQKdN2OcUzEqVkDwEQqiPQ grv7yxHv7qfqaqFKELPR0XNuR75PL6tClYUJdoHGqJr5tF0wwZVu2zyWCG7GteFmn6A3 4XzQ== X-Gm-Message-State: AOJu0YyLvP+ZNK4htVM3VkBq9ld5Mqix24jp4BQRUq0f3+PYM3ssSoRf ytGnyl2S/VLMfygibhmzvmw= X-Google-Smtp-Source: AGHT+IFcMey6TnOXOu5MSlLdoD6XtZU3LWDsq7B13n3sOVMBzRaLsi3NtlxaruTsT9S5irAnnjq1Bg== X-Received: by 2002:a05:600c:1914:b0:409:7d0:d20b with SMTP id j20-20020a05600c191400b0040907d0d20bmr5623787wmq.24.1700488281411; Mon, 20 Nov 2023 05:51:21 -0800 (PST) Received: from localhost.localdomain (93-34-89-13.ip49.fastwebnet.it. [93.34.89.13]) by smtp.googlemail.com with ESMTPSA id j33-20020a05600c1c2100b0040772934b12sm18205846wms.7.2023.11.20.05.51.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Nov 2023 05:51:21 -0800 (PST) From: Christian Marangi To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Andrew Lunn , Heiner Kallweit , Russell King , Florian Fainelli , Broadcom internal kernel review list , Daniel Golle , Qingfang Deng , SkyLake Huang , Matthias Brugger , AngeloGioacchino Del Regno , David Epping , Vladimir Oltean , Christian Marangi , "Russell King (Oracle)" , Harini Katakam , Simon Horman , Robert Marko , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [net-next RFC PATCH 06/14] net: phy: add support for shared priv data size for PHY package in DT Date: Mon, 20 Nov 2023 14:50:33 +0100 Message-Id: <20231120135041.15259-7-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231120135041.15259-1-ansuelsmth@gmail.com> References: <20231120135041.15259-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add support for defining shared data size for PHY package defined in DT. A PHY driver has to define the value .phy_package_priv_data_size to make the generic OF PHY package function alloc priv data in the shared struct for the PHY package. Signed-off-by: Christian Marangi --- drivers/net/phy/phy_device.c | 7 ++++++- include/linux/phy.h | 3 +++ 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c index 452fd69e8924..91d17129b774 100644 --- a/drivers/net/phy/phy_device.c +++ b/drivers/net/phy/phy_device.c @@ -3200,6 +3200,7 @@ static int of_phy_package(struct phy_device *phydev) struct device_node *package_node; const char *global_phy_name; int i, global_phys_num, ret; + int shared_priv_data_size; int *global_phy_addrs; if (!node) @@ -3252,8 +3253,12 @@ static int of_phy_package(struct phy_device *phydev) global_phy_addrs[i] = addr; } + shared_priv_data_size = 0; + if (phydev->drv->phy_package_priv_data_size) + shared_priv_data_size = phydev->drv->phy_package_priv_data_size; + ret = devm_phy_package_join(&phydev->mdio.dev, phydev, global_phy_addrs, - global_phys_num, 0); + global_phys_num, shared_priv_data_size); if (ret) goto exit; diff --git a/include/linux/phy.h b/include/linux/phy.h index 5e595a0a43b6..7c47c12cffa0 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -896,6 +896,8 @@ struct phy_led { * for PHY package global init. If defined, list is compared * with DT values to match correct PHY phandle order. List * last element MUST BE an empty string. + * @phy_package_priv_data_size: Size of the priv data to alloc + * for shared struct of PHY package. * * All functions are optional. If config_aneg or read_status * are not implemented, the phy core uses the genphy versions. @@ -915,6 +917,7 @@ struct phy_driver { const void *driver_data; unsigned int phy_package_global_phy_num; const char * const *phy_package_global_phy_names; + unsigned int phy_package_priv_data_size; /** * @soft_reset: Called to issue a PHY software reset From patchwork Mon Nov 20 13:50:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 13461344 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="J1+btUUb" Received: from mail-wm1-x32f.google.com (mail-wm1-x32f.google.com [IPv6:2a00:1450:4864:20::32f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 23D24D65; Mon, 20 Nov 2023 05:51:25 -0800 (PST) Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-4083dbc43cfso13342015e9.3; Mon, 20 Nov 2023 05:51:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1700488283; x=1701093083; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=BkZZkQ+fhxkG3W91GuOjhKRxuNJAr/jVw9bM/JNE+9s=; b=J1+btUUb5WrurF6QYxTmgcKDcBACAHe7JecqQG9TaU/nGjgjop+jVcw2UQwd8WD/zT qTDGlnckUUg5WW/j0+38PGul3U7gP3YxWTG4fJFwPAsepM5vFu8wwc35hdWldFSFAqRW tX+HHQLCDRv47891OnVmT+Oc424B+olrIast+XdLvX2LmnCL1baWlGZoXc9yzhoAD9zO FWk/zGq3Ukfx7NKJw4Jmq2m3OFAdixqvSAGP4I75A2V9kSverqRZSeB7W34XpF7ogD3l f8M94ws1diEFoAeFvq2i49Gk7/NQF4aK+TnTnvP5zrzdxKBVfQceY1GKCukfSvx4Ku40 psIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700488283; x=1701093083; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BkZZkQ+fhxkG3W91GuOjhKRxuNJAr/jVw9bM/JNE+9s=; b=stdnmm8qSa9QElTAyfvX67b42xAa5++eTyBcrTR316hCI3MILRXebDCZ6sq/YKghFo xde2+fUnECCJHqMfeY+My2PmgjRVFnvxDlDR/HX8GjvGwyIGyUBbiO4o4DJTUJwqNSy5 Kap7h8jMBRc8wTogYTDB+/sETDg0LhGbBW2SG9H7x0wNXfxJY/oqiRXupxLhttoypcUe fZb+DADfK8SSEujFu4bP6lBrJvnnP2yW0KIvhbDZ+wptQHV+FUvm/lvbPnkX3ePAb/xb zoxhjX0t/sL2mVrVqsiDoWzyOeWiA4kLN8gsabpxZHnpHLPzuJF5M6j8cdhcJjPynWyG kPzQ== X-Gm-Message-State: AOJu0YzlDcGdYhlStmYAG2xt6J0BmumwSdCd/pWc0lbI48J/cNZO0QQP vSnepkRDCKGWOf/wkRWm128= X-Google-Smtp-Source: AGHT+IHHHmLbo0ls+ZfdjXnfQDFKRg9UMz3ucecEJfw4iq5blHC0EFBdWzjf+AlCouNSkFhaXzhm/Q== X-Received: by 2002:a05:600c:3b8c:b0:407:5b54:bb10 with SMTP id n12-20020a05600c3b8c00b004075b54bb10mr5935396wms.8.1700488283168; Mon, 20 Nov 2023 05:51:23 -0800 (PST) Received: from localhost.localdomain (93-34-89-13.ip49.fastwebnet.it. [93.34.89.13]) by smtp.googlemail.com with ESMTPSA id j33-20020a05600c1c2100b0040772934b12sm18205846wms.7.2023.11.20.05.51.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Nov 2023 05:51:22 -0800 (PST) From: Christian Marangi To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Andrew Lunn , Heiner Kallweit , Russell King , Florian Fainelli , Broadcom internal kernel review list , Daniel Golle , Qingfang Deng , SkyLake Huang , Matthias Brugger , AngeloGioacchino Del Regno , David Epping , Vladimir Oltean , Christian Marangi , "Russell King (Oracle)" , Harini Katakam , Simon Horman , Robert Marko , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [net-next RFC PATCH 07/14] net: phy: add support for driver specific PHY package probe/config Date: Mon, 20 Nov 2023 14:50:34 +0100 Message-Id: <20231120135041.15259-8-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231120135041.15259-1-ansuelsmth@gmail.com> References: <20231120135041.15259-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add PHY driver specific function to probe and configure PHY package. These function are run only once before the PHY probe and config_init. They are used in conjunction with DT PHY package define for basic PHY package implementation to setup and probe PHY package with simple functions directly defined in the PHY driver struct. Signed-off-by: Christian Marangi --- drivers/net/phy/phy_device.c | 14 ++++++++++++++ include/linux/phy.h | 21 +++++++++++++++++++++ 2 files changed, 35 insertions(+) diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c index 91d17129b774..0b7ba6995929 100644 --- a/drivers/net/phy/phy_device.c +++ b/drivers/net/phy/phy_device.c @@ -1246,6 +1246,13 @@ int phy_init_hw(struct phy_device *phydev) if (ret < 0) return ret; + if (phydev->drv->phy_package_config_init_once && + phy_package_init_once(phydev)) { + ret = phydev->drv->phy_package_config_init_once(phydev); + if (ret < 0) + return ret; + } + if (phydev->drv->config_init) { ret = phydev->drv->config_init(phydev); if (ret < 0) @@ -3386,6 +3393,13 @@ static int phy_probe(struct device *dev) /* Deassert the reset signal */ phy_device_reset(phydev, 0); + if (phydev->drv->phy_package_probe_once && + phy_package_probe_once(phydev)) { + err = phydev->drv->phy_package_probe_once(phydev); + if (err) + goto out; + } + if (phydev->drv->probe) { err = phydev->drv->probe(phydev); if (err) diff --git a/include/linux/phy.h b/include/linux/phy.h index 7c47c12cffa0..1849fc637196 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -924,12 +924,33 @@ struct phy_driver { */ int (*soft_reset)(struct phy_device *phydev); + /** + * @phy_package_config_init_once: Driver specific PHY package + * config init call + * @def: PHY device to use to probe PHY package + * + * Called to initialize the PHY package, including after + * a reset. + * Called BEFORE PHY config_init. + */ + int (*phy_package_config_init_once)(struct phy_device *dev); + /** * @config_init: Called to initialize the PHY, * including after a reset */ int (*config_init)(struct phy_device *phydev); + /** + * @phy_package_probe_once: Driver specific PHY package probe + * @def: PHY device to use to probe PHY package + * + * Called during discovery once per PHY package. Used to set + * up device-specific PHY package structures, if any. + * Called BEFORE PHY probe. + */ + int (*phy_package_probe_once)(struct phy_device *dev); + /** * @probe: Called during discovery. Used to set * up device-specific structures, if any From patchwork Mon Nov 20 13:50:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 13461345 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="lNI38QJY" Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AFC00D78; Mon, 20 Nov 2023 05:51:26 -0800 (PST) Received: by mail-lf1-x136.google.com with SMTP id 2adb3069b0e04-50aab0ca90aso1754615e87.0; Mon, 20 Nov 2023 05:51:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1700488285; x=1701093085; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=RJJcNZQjoxDpL64YJUPbX5zAdxkULtiEGewpt5HLNRQ=; b=lNI38QJY+hLhb05yxNU8aMXdbP1ccm/A0KKezhus2NmfKLnTP4uHCMNTI6LLwd7DSp nn5rlkvXOjpv/CXXgEb66R0q2leOEKyYbOa46FQUPzt3PCgPy9hdQf9RqPlrl+NEKATz o6N9Vetc2vlV3NLSNZv8nTdQAZKRo40kKIcHjuTjU2WOG3mBFf171uDNFSppiSilg7Uw 62c/gg+Qje3XFS5+euq2MScISJff7hfxVum1pVEcQ7dgH6ix+LekQ085hs6KiOmEZxmN nMtjN2dcVNekncsvx69VxkfEjz+LE+3l0ci67Wn+AbcUZbinAhBXSqmG0+dWqMU9vzS9 pQww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700488285; x=1701093085; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RJJcNZQjoxDpL64YJUPbX5zAdxkULtiEGewpt5HLNRQ=; b=lEf3HYlrB5hMDVRormqdUBwGzfCuAbV8zOwui9bPvUyuJpRuczIW9dhgQjtJo4m7Ca L8HE6rc5K6wa/BXF1DEMo4nGtqlY+ppez1GQO1vJkuFrtCP/OifWMIIVCiqzxNM0VK3e zo1Pkmj0AjLe1DcagFzGf0X2rcnHb4rw9JWAzYNZGMB9WqEiXhRf1Y0OPjJrwa1RNGNf u9AZ4ltiOygEb+EWooBDH7MkaaugkV1N/BHCSGH3y0oXOWplJfC+iWW/2IP/6UNetqr0 kfk978w+4ujgPHo7Xj5n37D9TjwtpZvwgvOMl+P4dJRzCIdr5dgAx3EiWgzN8M2F5EGD VhmA== X-Gm-Message-State: AOJu0Yw8zyQpUBc/5bg1DpHUFE8JYLn47eZ5qvLQKy7Gp/JaiorfiNz+ AiLeCqHpO9FQOJaD33+N/Zo= X-Google-Smtp-Source: AGHT+IHEV5yAbedHXZPHvi496M5AnmqBvoItl/mLTRfObKuQHz0eqFU2KUnKLxPwW2KQ8CFk9bb54A== X-Received: by 2002:a2e:7302:0:b0:2c5:ee7:b322 with SMTP id o2-20020a2e7302000000b002c50ee7b322mr6395660ljc.18.1700488284849; Mon, 20 Nov 2023 05:51:24 -0800 (PST) Received: from localhost.localdomain (93-34-89-13.ip49.fastwebnet.it. [93.34.89.13]) by smtp.googlemail.com with ESMTPSA id j33-20020a05600c1c2100b0040772934b12sm18205846wms.7.2023.11.20.05.51.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Nov 2023 05:51:24 -0800 (PST) From: Christian Marangi To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Andrew Lunn , Heiner Kallweit , Russell King , Florian Fainelli , Broadcom internal kernel review list , Daniel Golle , Qingfang Deng , SkyLake Huang , Matthias Brugger , AngeloGioacchino Del Regno , David Epping , Vladimir Oltean , Christian Marangi , "Russell King (Oracle)" , Harini Katakam , Simon Horman , Robert Marko , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [net-next RFC PATCH 08/14] net: phy: add support for PHY package interface mode Date: Mon, 20 Nov 2023 14:50:35 +0100 Message-Id: <20231120135041.15259-9-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231120135041.15259-1-ansuelsmth@gmail.com> References: <20231120135041.15259-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Some PHY in PHY package supports running only at a specific mode for each PHY in the package. Add support for enforcing this special thing a verify consistency with the requested mode to prevent misconfiguration. To set the PHY package mode, simply set "phy-mode" in the phy-package node. Each PHY on init will verify if the requested mode match the one set for the PHY package and will return -EINVAL if this is not true. If PHY package doesn't specify any mode, it's assumed that PHY in the package doesn't have such limitation. Signed-off-by: Christian Marangi --- drivers/net/phy/phy_device.c | 37 ++++++++++++++++++++++++++++++++++++ include/linux/phy.h | 6 ++++++ 2 files changed, 43 insertions(+) diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c index 0b7ba6995929..73af4197a7af 100644 --- a/drivers/net/phy/phy_device.c +++ b/drivers/net/phy/phy_device.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include #include @@ -1225,8 +1226,17 @@ static int phy_poll_reset(struct phy_device *phydev) int phy_init_hw(struct phy_device *phydev) { + phy_interface_t package_interface; int ret = 0; + /* Validate we are requesting consistent mode if we + * are in a PHY package and the PHY package requires a + * specific mode. + */ + ret = phy_package_get_mode(phydev, &package_interface); + if (!ret && phydev->interface != package_interface) + return -EINVAL; + /* Deassert the reset signal */ phy_device_reset(phydev, 0); @@ -1776,6 +1786,32 @@ void phy_package_leave(struct phy_device *phydev) } EXPORT_SYMBOL_GPL(phy_package_leave); +/** + * phy_package_get_mode - get PHY interface mode for PHY package + * @phydev: target phy_device struct + * @interface: phy_interface_t pointer where to save the PHY package mode + * + * Gets PHY interface mode for the shared data of the PHY package. + * Returns 0 and updates @interface with the PHY package value, or -ENODEV + * if PHY is not in PHY package or -EINVAL if a PHY package interface mode + * is not set. + */ +int phy_package_get_mode(struct phy_device *phydev, phy_interface_t *interface) +{ + struct phy_package_shared *shared = phydev->shared; + + if (!shared) + return -ENODEV; + + if (shared->package_interface == PHY_INTERFACE_MODE_NA) + return -EINVAL; + + *interface = shared->package_interface; + + return 0; +} +EXPORT_SYMBOL_GPL(phy_package_get_mode); + static void devm_phy_package_leave(struct device *dev, void *res) { phy_package_leave(*(struct phy_device **)res); @@ -3270,6 +3306,7 @@ static int of_phy_package(struct phy_device *phydev) goto exit; phydev->shared->np = package_node; + of_get_phy_mode(package_node, &phydev->shared->package_interface); exit: kfree(global_phy_addrs); diff --git a/include/linux/phy.h b/include/linux/phy.h index 1849fc637196..8af0a8a72b88 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -341,6 +341,11 @@ struct mdio_bus_stats { struct phy_package_shared { /* With PHY package defined in DT this points to the PHY package node */ struct device_node *np; + /* PHY package interface + * If defined, each PHY of the package MUST have the interface + * set to the PHY package. + */ + phy_interface_t package_interface; /* addrs list pointer */ /* note that this pointer is shared between different phydevs. * It is allocated and freed automatically by phy_package_join() and @@ -2014,6 +2019,7 @@ int phy_ethtool_nway_reset(struct net_device *ndev); int phy_package_join(struct phy_device *phydev, int *addrs, size_t addrs_num, size_t priv_size); void phy_package_leave(struct phy_device *phydev); +int phy_package_get_mode(struct phy_device *phydev, phy_interface_t *interface); int devm_phy_package_join(struct device *dev, struct phy_device *phydev, int *addrs, size_t addrs_num, size_t priv_size); From patchwork Mon Nov 20 13:50:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 13461346 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="mz+Mv7wx" Received: from mail-wm1-x32f.google.com (mail-wm1-x32f.google.com [IPv6:2a00:1450:4864:20::32f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2FA7610C0; Mon, 20 Nov 2023 05:51:28 -0800 (PST) Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-4083f613272so19033615e9.1; Mon, 20 Nov 2023 05:51:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1700488286; x=1701093086; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=aMjjq9qLyKnXGA+eO91BLzIpEsWi8EWdg29zu6S5n/U=; b=mz+Mv7wx085TBN6rp/PGnQRCgBjfhDqDbQ4jGkavcfhFCno4iA1ibrWKK17O4lXHaC ShBGUkDARpSuj4iifEf2FywsjDVLdOswNTTz7j+KV37zDomUN0S0sjSLWtM4JfvRwups VkC8BHJX9iCxbV/GUSQ6dCRWcRne2amgxkaWIkGjaGRsUQSYCrMxQeLQjn0quEJKgeLY fXdifrhnFndEP387lljtsTc5mj4INsVH+HAsRuDC310pq3d2H4upeeuLL8LFxKfvk7in Ys5XjeMRlYxDQxpIfhnCOHMxHHNYbd6RD1AD6/B5ezUAwm6Oz3DmKU1er9osXZ6bNfXA fC/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700488286; x=1701093086; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aMjjq9qLyKnXGA+eO91BLzIpEsWi8EWdg29zu6S5n/U=; b=LvQ9/VUuXIubFGsirVrSNvDEN4oiFqSQxBimPPkigMEohI2boAGTnGxs9t/WvhXctx Cf00kJ8xacXGCmQv604cy30FVmt+zyEhW/plk676hL9wQZ6OFOZy5B6elgTjpUCjaUdN uRr93qE67f7OX+JaRVsm6Sl6rvWI78W6MN10h/lQneSgCoxnP74LC8IaIHm9mqutc8ve jKHCutMg/PzeAYoBnfdC1HYn91V7RDFka0bOELMNMqXNS9YEOjBLT0V4KVAxa6/ehCAX W2S5uzyn0yR0+Mnuzj1cQtchEYyYfZc0e6HcozV02o09S4Sc0TvCMoo8nNOjOTlXik3n Jj8w== X-Gm-Message-State: AOJu0YwCClhedLnv6gteV3p18DfgcM+Irf8bfYvwlDPgPP/Klx6RwrUg xykzJo3gBODHJRkteQU01mM= X-Google-Smtp-Source: AGHT+IELaaTlk2hOemekBls41C7RViCTII0CDMoPho0KjrhB6Lc/w0Sv0fdqN6PCiINS6TOvzE03Tg== X-Received: by 2002:a05:600c:1d1a:b0:40a:49bc:fa9d with SMTP id l26-20020a05600c1d1a00b0040a49bcfa9dmr6576777wms.26.1700488286520; Mon, 20 Nov 2023 05:51:26 -0800 (PST) Received: from localhost.localdomain (93-34-89-13.ip49.fastwebnet.it. [93.34.89.13]) by smtp.googlemail.com with ESMTPSA id j33-20020a05600c1c2100b0040772934b12sm18205846wms.7.2023.11.20.05.51.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Nov 2023 05:51:26 -0800 (PST) From: Christian Marangi To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Andrew Lunn , Heiner Kallweit , Russell King , Florian Fainelli , Broadcom internal kernel review list , Daniel Golle , Qingfang Deng , SkyLake Huang , Matthias Brugger , AngeloGioacchino Del Regno , David Epping , Vladimir Oltean , Christian Marangi , "Russell King (Oracle)" , Harini Katakam , Simon Horman , Robert Marko , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [net-next RFC PATCH 09/14] net: phy: move mmd_phy_indirect to generic header Date: Mon, 20 Nov 2023 14:50:36 +0100 Message-Id: <20231120135041.15259-10-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231120135041.15259-1-ansuelsmth@gmail.com> References: <20231120135041.15259-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Move mmd_phy_indirect function from phy-core to generic phy.h to permit future usage for PHY package read/write_mmd. Signed-off-by: Christian Marangi --- drivers/net/phy/phy-core.c | 14 -------------- include/linux/phy.h | 14 ++++++++++++++ 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/net/phy/phy-core.c b/drivers/net/phy/phy-core.c index 966c93cbe616..b4f80847eefd 100644 --- a/drivers/net/phy/phy-core.c +++ b/drivers/net/phy/phy-core.c @@ -526,20 +526,6 @@ int phy_speed_down_core(struct phy_device *phydev) return 0; } -static void mmd_phy_indirect(struct mii_bus *bus, int phy_addr, int devad, - u16 regnum) -{ - /* Write the desired MMD Devad */ - __mdiobus_write(bus, phy_addr, MII_MMD_CTRL, devad); - - /* Write the desired MMD register address */ - __mdiobus_write(bus, phy_addr, MII_MMD_DATA, regnum); - - /* Select the Function : DATA with no post increment */ - __mdiobus_write(bus, phy_addr, MII_MMD_CTRL, - devad | MII_MMD_CTRL_NOINCR); -} - /** * __phy_read_mmd - Convenience function for reading a register * from an MMD on a given PHY. diff --git a/include/linux/phy.h b/include/linux/phy.h index 8af0a8a72b88..dd2381652dd1 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -1361,6 +1361,20 @@ static inline int __phy_modify_changed(struct phy_device *phydev, u32 regnum, regnum, mask, set); } +static inline void mmd_phy_indirect(struct mii_bus *bus, int phy_addr, int devad, + u16 regnum) +{ + /* Write the desired MMD Devad */ + __mdiobus_write(bus, phy_addr, MII_MMD_CTRL, devad); + + /* Write the desired MMD register address */ + __mdiobus_write(bus, phy_addr, MII_MMD_DATA, regnum); + + /* Select the Function : DATA with no post increment */ + __mdiobus_write(bus, phy_addr, MII_MMD_CTRL, + devad | MII_MMD_CTRL_NOINCR); +} + /* * phy_read_mmd - Convenience function for reading a register * from an MMD on a given PHY. From patchwork Mon Nov 20 13:50:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 13461347 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="DzOWvVfr" Received: from mail-wm1-x336.google.com (mail-wm1-x336.google.com [IPv6:2a00:1450:4864:20::336]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C25C510D1; Mon, 20 Nov 2023 05:51:29 -0800 (PST) Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-4083740f92dso16080325e9.3; Mon, 20 Nov 2023 05:51:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1700488288; x=1701093088; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=7KlciZ6HGUzRiM58ultDgzciNJogKhU8Km072RfwAf4=; b=DzOWvVfrm178CDzV/mmSwdpTxeWYfjw4xLSRh4/7NcSxsrsTEMdLtDxUwYB4H4K14c VHt7GejI75AwRzQLlkUD8oprRaoW2JN20GX3QP272DTZg4oNtnjo5K9kJbBCuL4V8Ivu m2XUwRMbvoSrYNbIEFeSIo0zTMstFtVlO7Ln85DAFlndy3lQlU9KL9VTrjOTuHC9Pj2O Y3AmooLD7HRhaJm3p7JU7b6eRQlkxJ3DM+0qmW7FI90aohrFLuJ6DZmHKgBdfXeGV12G sQcMxhAPay8f/sn7nNnesotJNvxV/vrjqOCuTyHZDU8l4YzGYJp/qLaXH31zizVPPlTL j4Jw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700488288; x=1701093088; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7KlciZ6HGUzRiM58ultDgzciNJogKhU8Km072RfwAf4=; b=g7XDxOj66xPyly01UZ9P773JGpiwwdYByCmt5EnswTarDR450T9hg579tapTVY3yWd Tm4wRs/WsJp+OrNZg5/jx6gknf0l/cYKcbjL8GdE9Bcbldq/DO/G5iKxgc/ZR9jVo+KC jkM0XPDW6zI67k+TptjM6rgJfCWZnLEMLJB8CquCz+AKhpwqpHDPs/2B2Xz6v2ml8U6T e3tR6iQxNaiFy+FXgMD6WgKRE/bcModXY0Wt38tH1rvklYQzdh3Q+6uSFc5+bxDu1A5D EfZQk44MomjjneYdpxiNpRnTY+CdqQPBDROApPcrAo5HVbSGbZjY3uyME0l2qq/a+uaF xU+w== X-Gm-Message-State: AOJu0YxjcsSSW6dhOKZPCo9e0vaxbCkzU2+ZVF5PyWKmwcerfxs/rnX/ 1Jxr6v5N/2YOCjEuRN0jfZw= X-Google-Smtp-Source: AGHT+IEgMWdVSmBqk/Db3v8YVKpL/4mMmUM+K0FYzCeo2AsDXwgh5SY0EbCSMcmSejPYpR8JOj4Fqg== X-Received: by 2002:a05:600c:3113:b0:408:e441:1697 with SMTP id g19-20020a05600c311300b00408e4411697mr5904786wmo.39.1700488288141; Mon, 20 Nov 2023 05:51:28 -0800 (PST) Received: from localhost.localdomain (93-34-89-13.ip49.fastwebnet.it. [93.34.89.13]) by smtp.googlemail.com with ESMTPSA id j33-20020a05600c1c2100b0040772934b12sm18205846wms.7.2023.11.20.05.51.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Nov 2023 05:51:27 -0800 (PST) From: Christian Marangi To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Andrew Lunn , Heiner Kallweit , Russell King , Florian Fainelli , Broadcom internal kernel review list , Daniel Golle , Qingfang Deng , SkyLake Huang , Matthias Brugger , AngeloGioacchino Del Regno , David Epping , Vladimir Oltean , Christian Marangi , "Russell King (Oracle)" , Harini Katakam , Simon Horman , Robert Marko , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [net-next RFC PATCH 10/14] net: phy: add support for PHY package MMD read/write Date: Mon, 20 Nov 2023 14:50:37 +0100 Message-Id: <20231120135041.15259-11-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231120135041.15259-1-ansuelsmth@gmail.com> References: <20231120135041.15259-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Some PHY in PHY package may require to read/write MMD regs to correctly configure the PHY package. Add support for these additional required function in both lock and no lock variant. Signed-off-by: Christian Marangi --- include/linux/phy.h | 72 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/include/linux/phy.h b/include/linux/phy.h index dd2381652dd1..90bfaa36689f 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -2110,6 +2110,78 @@ static inline int __phy_package_write(struct phy_device *phydev, return __mdiobus_write(phydev->mdio.bus, addr, regnum, val); } +static inline int phy_package_read_mmd(struct phy_device *phydev, + int global_phy_index, int devad, u32 regnum) +{ + struct phy_package_shared *shared = phydev->shared; + struct mii_bus *bus = phydev->mdio.bus; + int addr, val; + + if (!shared || global_phy_index > shared->addrs_num - 1) + return -EIO; + + addr = shared->addrs[global_phy_index]; + + phy_lock_mdio_bus(phydev); + mmd_phy_indirect(bus, addr, devad, regnum); + val = __mdiobus_read(bus, addr, MII_MMD_DATA); + phy_unlock_mdio_bus(phydev); + + return val; +} + +static inline int __phy_package_read_mmd(struct phy_device *phydev, + int global_phy_index, int devad, u32 regnum) +{ + struct phy_package_shared *shared = phydev->shared; + struct mii_bus *bus = phydev->mdio.bus; + int addr; + + if (!shared || global_phy_index > shared->addrs_num - 1) + return -EIO; + + addr = shared->addrs[global_phy_index]; + mmd_phy_indirect(bus, addr, devad, regnum); + return __mdiobus_read(bus, addr, MII_MMD_DATA); +} + +static inline int phy_package_write_mmd(struct phy_device *phydev, + int global_phy_index, int devad, + u32 regnum, u16 val) +{ + struct phy_package_shared *shared = phydev->shared; + struct mii_bus *bus = phydev->mdio.bus; + int addr, ret; + + if (!shared || global_phy_index > shared->addrs_num - 1) + return -EIO; + + addr = shared->addrs[global_phy_index]; + + phy_lock_mdio_bus(phydev); + mmd_phy_indirect(bus, addr, devad, regnum); + ret = __mdiobus_write(bus, addr, MII_MMD_DATA, val); + phy_unlock_mdio_bus(phydev); + + return ret; +} + +static inline int __phy_package_write_mmd(struct phy_device *phydev, + int global_phy_index, int devad, + u32 regnum, u16 val) +{ + struct phy_package_shared *shared = phydev->shared; + struct mii_bus *bus = phydev->mdio.bus; + int addr; + + if (!shared || global_phy_index > shared->addrs_num - 1) + return -EIO; + + addr = shared->addrs[global_phy_index]; + mmd_phy_indirect(bus, addr, devad, regnum); + return __mdiobus_write(bus, addr, MII_MMD_DATA, val); +} + static inline bool __phy_package_set_once(struct phy_device *phydev, unsigned int b) { From patchwork Mon Nov 20 13:50:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 13461364 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="HeWb+XlZ" Received: from mail-wr1-x42e.google.com (mail-wr1-x42e.google.com [IPv6:2a00:1450:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7A9F810E4; Mon, 20 Nov 2023 05:51:31 -0800 (PST) Received: by mail-wr1-x42e.google.com with SMTP id ffacd0b85a97d-3316d3d11e1so1603694f8f.0; Mon, 20 Nov 2023 05:51:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1700488290; x=1701093090; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=+bK4gHzJ+y3tePc89TtX9q7l+Za/0YYi8syFPOCy8lg=; b=HeWb+XlZCqLF+KUgMKMDI142PLxAvEzhH679iJOPRQav8kONDKqe0ksdNf7O4EOy6s 1G53YHkVQ7mQd2rxAVkuTK2fj99PyHXAyWDGtmZgqR/yObCxvqUCoQdZ36HNLWzeGNYe YnJQQnFuO08xFuA6PMnEBdETs6T0ZPVcbyqX5nWvwFCrj3dx+x4puWT6meqXgXwwILB5 8nhHg1Ts8ncTHRAy+g9b93slJWnwUEXZKgfZZLe3d+9SKp8xVFwViuzgbhekF/NDTDZi TdTeotSovBcYBpQgnMhkYfrdtknFk7YDkfeEQPBnaVGlj5DRutk4nv/zNwyLFrzx8bN5 2W2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700488290; x=1701093090; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+bK4gHzJ+y3tePc89TtX9q7l+Za/0YYi8syFPOCy8lg=; b=vVU7nWnQDbtL6gK3cZnt1vlYxRZpUkq6KvpbKTIBYMJgGy2cn7jKylS6EhGJ8Wrmev cESEjWVy3mJyVEDrPT+uoBi/EYJZsKjcEEyUIj3OIjd8PAkxmUuoPUTxRM/HHoFzryoW zx5M0EwJNKaQB1az2ySRVPoee16KRic2oRLFY4JjhI7JqknSFTf6WllK9E29a5NNMlt9 yqcpmT4RyhMDR0aFfjYjF/KR4UVj0XU8f/84t5OntC5dafEpyV85RmfWW7oK7ZLI0Pmt 4mtTdnFmLO6SkVqs0PDOJDc7fiXBfa3I4E70wz78pkuo3PIWd6zcDZ03Jp3s2YulVqd0 5jCg== X-Gm-Message-State: AOJu0YwrXezaYAQirMZDDJYoXsVdGsePfRgUMgqnh5VygBSMSmXeZ7YW dnb7GP8v9Y6cTQSxV5NmkOc= X-Google-Smtp-Source: AGHT+IGQpqPZK+oPA2rWRqOtnSOKMxcGuZz5hDx228kkb7ZrMwBDn5rbRsE/t5rqE8I++LpS4paQag== X-Received: by 2002:a05:6000:1445:b0:332:cb0e:73b6 with SMTP id v5-20020a056000144500b00332cb0e73b6mr1341263wrx.2.1700488289753; Mon, 20 Nov 2023 05:51:29 -0800 (PST) Received: from localhost.localdomain (93-34-89-13.ip49.fastwebnet.it. [93.34.89.13]) by smtp.googlemail.com with ESMTPSA id j33-20020a05600c1c2100b0040772934b12sm18205846wms.7.2023.11.20.05.51.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Nov 2023 05:51:29 -0800 (PST) From: Christian Marangi To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Andrew Lunn , Heiner Kallweit , Russell King , Florian Fainelli , Broadcom internal kernel review list , Daniel Golle , Qingfang Deng , SkyLake Huang , Matthias Brugger , AngeloGioacchino Del Regno , David Epping , Vladimir Oltean , Christian Marangi , "Russell King (Oracle)" , Harini Katakam , Simon Horman , Robert Marko , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [net-next RFC PATCH 11/14] dt-bindings: net: add QCA807x PHY defines Date: Mon, 20 Nov 2023 14:50:38 +0100 Message-Id: <20231120135041.15259-12-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231120135041.15259-1-ansuelsmth@gmail.com> References: <20231120135041.15259-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Robert Marko Add DT bindings defined for Qualcomm QCA807x PHY series related to calibration and DAC settings. Signed-off-by: Robert Marko Signed-off-by: Christian Marangi --- include/dt-bindings/net/qcom-qca807x.h | 45 ++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 include/dt-bindings/net/qcom-qca807x.h diff --git a/include/dt-bindings/net/qcom-qca807x.h b/include/dt-bindings/net/qcom-qca807x.h new file mode 100644 index 000000000000..42c45c7d5210 --- /dev/null +++ b/include/dt-bindings/net/qcom-qca807x.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ +/* + * Device Tree constants for the Qualcomm QCA807X PHYs + */ + +#ifndef _DT_BINDINGS_QCOM_QCA807X_H +#define _DT_BINDINGS_QCOM_QCA807X_H + +#define PSGMII_QSGMII_TX_DRIVER_140MV 0 +#define PSGMII_QSGMII_TX_DRIVER_160MV 1 +#define PSGMII_QSGMII_TX_DRIVER_180MV 2 +#define PSGMII_QSGMII_TX_DRIVER_200MV 3 +#define PSGMII_QSGMII_TX_DRIVER_220MV 4 +#define PSGMII_QSGMII_TX_DRIVER_240MV 5 +#define PSGMII_QSGMII_TX_DRIVER_260MV 6 +#define PSGMII_QSGMII_TX_DRIVER_280MV 7 +#define PSGMII_QSGMII_TX_DRIVER_300MV 8 +#define PSGMII_QSGMII_TX_DRIVER_320MV 9 +#define PSGMII_QSGMII_TX_DRIVER_400MV 10 +#define PSGMII_QSGMII_TX_DRIVER_500MV 11 +/* Default value */ +#define PSGMII_QSGMII_TX_DRIVER_600MV 12 + +/* Full amplitude, full bias current */ +#define QCA807X_CONTROL_DAC_FULL_VOLT_BIAS 0 +/* Amplitude follow DSP (amplitude is adjusted based on cable length), half bias current */ +#define QCA807X_CONTROL_DAC_DSP_VOLT_HALF_BIAS 1 +/* Full amplitude, bias current follow DSP (bias current is adjusted based on cable length) */ +#define QCA807X_CONTROL_DAC_FULL_VOLT_DSP_BIAS 2 +/* Both amplitude and bias current follow DSP */ +#define QCA807X_CONTROL_DAC_DSP_VOLT_BIAS 3 +/* Full amplitude, half bias current */ +#define QCA807X_CONTROL_DAC_FULL_VOLT_HALF_BIAS 4 +/* Amplitude follow DSP setting; 1/4 bias current when cable<10m, + * otherwise half bias current + */ +#define QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS 5 +/* Full amplitude; same bias current setting with “010” and “011”, + * but half more bias is reduced when cable <10m + */ +#define QCA807X_CONTROL_DAC_FULL_VOLT_HALF_BIAS_SHORT 6 +/* Amplitude follow DSP; same bias current setting with “110”, default value */ +#define QCA807X_CONTROL_DAC_DSP_VOLT_HALF_BIAS_SHORT 7 + +#endif From patchwork Mon Nov 20 13:50:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 13461365 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="CzzUKVvm" Received: from mail-wm1-x32d.google.com (mail-wm1-x32d.google.com [IPv6:2a00:1450:4864:20::32d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 42EB010F2; Mon, 20 Nov 2023 05:51:33 -0800 (PST) Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-4083f613275so17334675e9.2; Mon, 20 Nov 2023 05:51:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1700488291; x=1701093091; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=4oWbW7U8hDbK7k3dW8cQqnctME3Rpq10CqBR82g551s=; b=CzzUKVvmkp5BfeDYesxJl1FL4w+Ld41Uvsk5nB2hPADF7Ge85QruVFbx1twhJmSgeX QSInIKpAo5xdDnnhWz3ey5LgYginkJvC6sNiGxGXlwjYYMHun2WOp4fwUo/f34CgIA7q orcaIzGoeF9brek8CDaWlWI5G+B+hVwmM0lK5waaZd4gts+EvslyHP06BD23fdAM9I4S 3cmnikIEUZ19yu7ldoZ0xMmwVhtKlv3APVx1/FVdp17bD7R1eImu0K7Kzk58gMq89Sn3 kEkLw9jYLilD5oAf+pfBPSm1b/hWdmJqHDvFQ6saTrzrecp0PRNeUlwwQG65bfdocf/P b6Pw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700488291; x=1701093091; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4oWbW7U8hDbK7k3dW8cQqnctME3Rpq10CqBR82g551s=; b=tFOPECHW6aRuwCFNl7KZJhQewIfJwz+heV3+Awyw6JIhnpee0MSCXwo/pPzb0XxXgo w+RXZvciMkcPAjVSmPDNLpnVwV6PlJlLn/LivIjm0gAQiEBuXs/sXITDv4ClmwBLpUC9 evPElXSNvUnQeYJ5T0zpM1L8VxC1nnECvtcGJ60KK/efbGbZLWUg0Y7SqIQ252dwBi4h IviD/hmf5eKSd5eZaRoAVx1qZ/FDs08zagDl3MlrsrLL1DcDr9IzJeqM7sTjQH2TSz7g pf6E6GLskaKz1pvawh104luIzawf3TjcEQLtXjJ8vEpjG2iH1rLof4Wd77uxNj7SUIdx 824g== X-Gm-Message-State: AOJu0YzCpiMFh7mNJZEty3AhohMmwrwh7PuXx6sAUYapHcTYL0OCtpnM Bc3meee2qjGCJ3eJpbLluPo= X-Google-Smtp-Source: AGHT+IGXDhVPZ/LrxiUSncChlDmbdW69CX3+FivEfcaF6fIFK68I+CV58V07sZTeNeA90QyJl9UMSg== X-Received: by 2002:a05:600c:4ed2:b0:405:4a78:a890 with SMTP id g18-20020a05600c4ed200b004054a78a890mr5843086wmq.8.1700488291376; Mon, 20 Nov 2023 05:51:31 -0800 (PST) Received: from localhost.localdomain (93-34-89-13.ip49.fastwebnet.it. [93.34.89.13]) by smtp.googlemail.com with ESMTPSA id j33-20020a05600c1c2100b0040772934b12sm18205846wms.7.2023.11.20.05.51.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Nov 2023 05:51:31 -0800 (PST) From: Christian Marangi To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Andrew Lunn , Heiner Kallweit , Russell King , Florian Fainelli , Broadcom internal kernel review list , Daniel Golle , Qingfang Deng , SkyLake Huang , Matthias Brugger , AngeloGioacchino Del Regno , David Epping , Vladimir Oltean , Christian Marangi , "Russell King (Oracle)" , Harini Katakam , Simon Horman , Robert Marko , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [net-next RFC PATCH 12/14] dt-bindings: net: Document Qcom QCA807x PHY package Date: Mon, 20 Nov 2023 14:50:39 +0100 Message-Id: <20231120135041.15259-13-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231120135041.15259-1-ansuelsmth@gmail.com> References: <20231120135041.15259-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Document Qcom QCA807x PHY package. Qualcomm QCA807X Ethernet PHY is PHY package of 2 or 5 IEEE 802.3 clause 22 compliant 10BASE-Te, 100BASE-TX and 1000BASE-T PHY-s. Document the required property to make the PHY package correctly configure and work. Signed-off-by: Christian Marangi --- .../devicetree/bindings/net/qcom,qca807x.yaml | 143 ++++++++++++++++++ 1 file changed, 143 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/qcom,qca807x.yaml diff --git a/Documentation/devicetree/bindings/net/qcom,qca807x.yaml b/Documentation/devicetree/bindings/net/qcom,qca807x.yaml new file mode 100644 index 000000000000..c2d59068d015 --- /dev/null +++ b/Documentation/devicetree/bindings/net/qcom,qca807x.yaml @@ -0,0 +1,143 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/qcom,qca807x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm QCA807X Ethernet PHY + +maintainers: + - Christian Marangi + - Robert Marko + +description: | + Qualcomm QCA807X Ethernet PHY is PHY package of 2 or 5 + IEEE 802.3 clause 22 compliant 10BASE-Te, 100BASE-TX and + 1000BASE-T PHY-s. + + They feature 2 SerDes, one for PSGMII or QSGMII connection with + MAC, while second one is SGMII for connection to MAC or fiber. + + Both models have a combo port that supports 1000BASE-X and + 100BASE-FX fiber. + + Each PHY inside of QCA807x series has 4 digitally controlled + output only pins that natively drive LED-s for up to 2 attached + LEDs. Some vendor also use these 4 output for GPIO usage without + attaching LEDs. + + Note that output pins can be set to drive LEDs OR GPIO, mixed + definition are not accepted. + +allOf: + - $ref: ethernet-phy-package.yaml# + +select: + properties: + compatible: + contains: + const: ethernet-phy-package + patternProperties: + ^ethernet-phy(@[a-f0-9]+)?$: + properties: + compatible: + contains: + enum: + - ethernet-phy-id004d.d0b2 + - ethernet-phy-id004d.d0b1 + required: + - compatible + +properties: + global-phys: + maxItems: 2 + + global-phy-names: + items: + - const: combo + - const: pqsgmii + + phy-connection-type: + enum: + - qsgmii + - psgmii + +patternProperties: + ^ethernet-phy(@[a-f0-9]+)?$: + $ref: /schemas/net/ethernet-phy.yaml# + + properties: + gpio-controller: + description: set the output lines as GPIO instead of LEDs + type: boolean + + '#gpio-cells': + description: number of GPIO cells for the PHY + const: 2 + + dependencies: + gpio-controller: ['#gpio-cells'] + + unevaluatedProperties: false + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + #include + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy-package { + compatible = "ethernet-phy-package"; + #address-cells = <1>; + #size-cells = <0>; + + global-phys = <&qca8075_4>, <&qca8075_psgmii>; + global-phy-names = "combo", "pqsgmii"; + + qca8075_1: ethernet-phy@1 { + compatible = "ethernet-phy-id004d.d0b2"; + reg = <1>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + }; + }; + + qca8075_2: ethernet-phy@2 { + compatible = "ethernet-phy-id004d.d0b2"; + reg = <2>; + + gpio-controller; + #gpio-cells = <2>; + }; + + qca8075_3: ethernet-phy@3 { + compatible = "ethernet-phy-id004d.d0b2"; + reg = <3>; + }; + + qca8075_4: ethernet-phy@4 { + compatible = "ethernet-phy-id004d.d0b2"; + reg = <4>; + }; + + qca8075_pqsgmii: ethernet-phy@5 { + reg = <5>; + }; + }; + }; From patchwork Mon Nov 20 13:50:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 13461367 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ji14EHQo" Received: from mail-wm1-x32b.google.com (mail-wm1-x32b.google.com [IPv6:2a00:1450:4864:20::32b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EF7A71AA; Mon, 20 Nov 2023 05:51:34 -0800 (PST) Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-40859c466efso16144705e9.3; Mon, 20 Nov 2023 05:51:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1700488293; x=1701093093; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=lwOqpq8wMuGFvFAyqjc9ntVImZ49seWbU3wj+Y9SX8M=; b=ji14EHQov7fyk/OvaaNMrxT4AlYBd7e84GmAu/3P3XbrJNjvZnZnw9qT4Cn1gW7yY2 hhpRBTTOYvlaXj4drASFQeIyenzoy9NPfZ0iIgW1KZLOjGC0IKJnuWwnTlaxB2bliByh ns+L4bUOfC3OcuV7qF6Bz3FffWvRGziXimoJmjJzhpdZ9bwCF5ItiLWuRj9k40+MqHnq sw40E7ljIWQAinKedUTAdODIJAnQUslaLW7/j+dRETZ+mRqb4EBvXSW1eXVBNt8pEN3j T4SzK87oLKotiRwmrXcqFb3Ea5/tGwzXNxdbpaN9y60OotVmjt18ypvvih2Qp3+RW+y1 rlgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700488293; x=1701093093; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lwOqpq8wMuGFvFAyqjc9ntVImZ49seWbU3wj+Y9SX8M=; b=vbX7pB3bDIE6PUmuY1o44ITYNtzQ1ejE5TLfsTvNwKzMvf0hO7Nx6wf8WI8ACABufd AlpLb9s+SKu8AI22r73s7vC4Pmd9ZET0Jd6Ld1E2sVxZF5te93g4O8RjpwIApX5HXrnH 0Vb3AFew3V+jvHFXKeT2dBoR/bY+Us6/fGXHnWBXapLMnEO0wgDxLA1JVRauG7alDZNE aEBuUalKrIQiuCT6HynkRyRZxMEra+DOYRVEKXXs9YOsNR37qHWxscj+yOEkzjDB57Px H/j7cTZ9QlFVySMchX5tLGhBxB4xnuWjZv2WXyTyGyhA7vFKJxHKmye2YmGYgyKbEddY Bahw== X-Gm-Message-State: AOJu0YxSvpwWT3gB8ZrIBeT7veiI8mR/BAhdY0YFDQGCBr5f9I/m5puE zrcTS6V9UtF+p2ZIIhux0K4= X-Google-Smtp-Source: AGHT+IFmg+IDN1S5hiDX/OCJuB0kKVd53gCz/3x1PpP8nqnLbxDFU7dX760HGV1Bk2uTz15Nrzm28w== X-Received: by 2002:a05:600c:4f55:b0:406:411f:742e with SMTP id m21-20020a05600c4f5500b00406411f742emr6269618wmq.34.1700488293121; Mon, 20 Nov 2023 05:51:33 -0800 (PST) Received: from localhost.localdomain (93-34-89-13.ip49.fastwebnet.it. [93.34.89.13]) by smtp.googlemail.com with ESMTPSA id j33-20020a05600c1c2100b0040772934b12sm18205846wms.7.2023.11.20.05.51.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Nov 2023 05:51:32 -0800 (PST) From: Christian Marangi To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Andrew Lunn , Heiner Kallweit , Russell King , Florian Fainelli , Broadcom internal kernel review list , Daniel Golle , Qingfang Deng , SkyLake Huang , Matthias Brugger , AngeloGioacchino Del Regno , David Epping , Vladimir Oltean , Christian Marangi , "Russell King (Oracle)" , Harini Katakam , Simon Horman , Robert Marko , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [net-next RFC PATCH 13/14] net: phy: add Qualcom QCA807x driver Date: Mon, 20 Nov 2023 14:50:40 +0100 Message-Id: <20231120135041.15259-14-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231120135041.15259-1-ansuelsmth@gmail.com> References: <20231120135041.15259-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Robert Marko This adds driver for the Qualcomm QCA8072 and QCA8075 PHY-s. They are 2 or 5 port IEEE 802.3 clause 22 compliant 10BASE-Te, 100BASE-TX and 1000BASE-T PHY-s. They feature 2 SerDes, one for PSGMII or QSGMII connection with MAC, while second one is SGMII for connection to MAC or fiber. Both models have a combo port that supports 1000BASE-X and 100BASE-FX fiber. Each PHY inside of QCA807x series has 4 digitally controlled output only pins that natively drive LED-s. But some vendors used these to driver generic LED-s controlled by userspace, so lets enable registering each PHY as GPIO controller and add driver for it. These are commonly used in Qualcomm IPQ40xx, IPQ60xx and IPQ807x boards. Co-developed-by: Christian Marangi Signed-off-by: Robert Marko Signed-off-by: Christian Marangi --- drivers/net/phy/Kconfig | 7 + drivers/net/phy/Makefile | 1 + drivers/net/phy/qca807x.c | 864 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 872 insertions(+) create mode 100644 drivers/net/phy/qca807x.c diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 25cfc5ded1da..5ad85bd978a0 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -325,6 +325,13 @@ config AT803X_PHY Currently supports the AR8030, AR8031, AR8033, AR8035 and internal QCA8337(Internal qca8k PHY) model +config QCA807X_PHY + tristate "Qualcomm QCA807x PHYs" + depends on OF_MDIO + help + Currently supports the Qualcomm QCA8072, QCA8075 and the PSGMII + control PHY. + config QSEMI_PHY tristate "Quality Semiconductor PHYs" help diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index f65e85c91fc1..a4da4f127b23 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -82,6 +82,7 @@ obj-$(CONFIG_NCN26000_PHY) += ncn26000.o obj-$(CONFIG_NXP_C45_TJA11XX_PHY) += nxp-c45-tja11xx.o obj-$(CONFIG_NXP_CBTX_PHY) += nxp-cbtx.o obj-$(CONFIG_NXP_TJA11XX_PHY) += nxp-tja11xx.o +obj-$(CONFIG_QCA807X_PHY) += qca807x.o obj-$(CONFIG_QSEMI_PHY) += qsemi.o obj-$(CONFIG_REALTEK_PHY) += realtek.o obj-$(CONFIG_RENESAS_PHY) += uPD60620.o diff --git a/drivers/net/phy/qca807x.c b/drivers/net/phy/qca807x.c new file mode 100644 index 000000000000..5b82af52778a --- /dev/null +++ b/drivers/net/phy/qca807x.c @@ -0,0 +1,864 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2023 Sartura Ltd. + * + * Author: Robert Marko + * Christian Marangi + * + * Qualcomm QCA8072 and QCA8075 PHY driver + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define PHY_ID_QCA8072 0x004dd0b2 +#define PHY_ID_QCA8075 0x004dd0b1 + +/* Downshift */ +#define QCA807X_SMARTSPEED_EN BIT(5) +#define QCA807X_SMARTSPEED_RETRY_LIMIT_MASK GENMASK(4, 2) +#define QCA807X_SMARTSPEED_RETRY_LIMIT_DEFAULT 5 +#define QCA807X_SMARTSPEED_RETRY_LIMIT_MIN 2 +#define QCA807X_SMARTSPEED_RETRY_LIMIT_MAX 9 + +/* Cable diagnostic test (CDT) */ +#define QCA807X_CDT 0x16 +#define QCA807X_CDT_ENABLE BIT(15) +#define QCA807X_CDT_ENABLE_INTER_PAIR_SHORT BIT(13) +#define QCA807X_CDT_STATUS BIT(11) +#define QCA807X_CDT_MMD3_STATUS 0x8064 +#define QCA807X_CDT_MDI0_STATUS_MASK GENMASK(15, 12) +#define QCA807X_CDT_MDI1_STATUS_MASK GENMASK(11, 8) +#define QCA807X_CDT_MDI2_STATUS_MASK GENMASK(7, 4) +#define QCA807X_CDT_MDI3_STATUS_MASK GENMASK(3, 0) +#define QCA807X_CDT_RESULTS_INVALID 0x0 +#define QCA807X_CDT_RESULTS_OK 0x1 +#define QCA807X_CDT_RESULTS_OPEN 0x2 +#define QCA807X_CDT_RESULTS_SAME_SHORT 0x3 +#define QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI1_SAME_OK 0x4 +#define QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI2_SAME_OK 0x8 +#define QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI3_SAME_OK 0xc +#define QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI1_SAME_OPEN 0x6 +#define QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI2_SAME_OPEN 0xa +#define QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI3_SAME_OPEN 0xe +#define QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI1_SAME_SHORT 0x7 +#define QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI2_SAME_SHORT 0xb +#define QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI3_SAME_SHORT 0xf +#define QCA807X_CDT_RESULTS_BUSY 0x9 +#define QCA807X_CDT_MMD3_MDI0_LENGTH 0x8065 +#define QCA807X_CDT_MMD3_MDI1_LENGTH 0x8066 +#define QCA807X_CDT_MMD3_MDI2_LENGTH 0x8067 +#define QCA807X_CDT_MMD3_MDI3_LENGTH 0x8068 +#define QCA807X_CDT_SAME_SHORT_LENGTH_MASK GENMASK(15, 8) +#define QCA807X_CDT_CROSS_SHORT_LENGTH_MASK GENMASK(7, 0) + +#define QCA807X_CHIP_CONFIGURATION 0x1f +#define QCA807X_BT_BX_REG_SEL BIT(15) +#define QCA807X_BT_BX_REG_SEL_FIBER 0 +#define QCA807X_BT_BX_REG_SEL_COPPER 1 +#define QCA807X_CHIP_CONFIGURATION_MODE_CFG_MASK GENMASK(3, 0) +#define QCA807X_CHIP_CONFIGURATION_MODE_QSGMII_SGMII 4 +#define QCA807X_CHIP_CONFIGURATION_MODE_PSGMII_FIBER 3 +#define QCA807X_CHIP_CONFIGURATION_MODE_PSGMII_ALL_COPPER 0 + +#define QCA807X_MEDIA_SELECT_STATUS 0x1a +#define QCA807X_MEDIA_DETECTED_COPPER BIT(5) +#define QCA807X_MEDIA_DETECTED_1000_BASE_X BIT(4) +#define QCA807X_MEDIA_DETECTED_100_BASE_FX BIT(3) + +#define QCA807X_MMD7_FIBER_MODE_AUTO_DETECTION 0x807e +#define QCA807X_MMD7_FIBER_MODE_AUTO_DETECTION_EN BIT(0) + +#define QCA807X_MMD7_1000BASE_T_POWER_SAVE_PER_CABLE_LENGTH 0x801a +#define QCA807X_CONTROL_DAC_MASK GENMASK(2, 0) + +#define QCA807X_MMD7_LED_100N_1 0x8074 +#define QCA807X_MMD7_LED_100N_2 0x8075 +#define QCA807X_MMD7_LED_1000N_1 0x8076 +#define QCA807X_MMD7_LED_1000N_2 0x8077 +#define QCA807X_LED_TXACT_BLK_EN_2 BIT(10) +#define QCA807X_LED_RXACT_BLK_EN_2 BIT(9) +#define QCA807X_LED_GT_ON_EN_2 BIT(6) +#define QCA807X_LED_HT_ON_EN_2 BIT(5) +#define QCA807X_LED_BT_ON_EN_2 BIT(4) +#define QCA807X_GPIO_FORCE_EN BIT(15) +#define QCA807X_GPIO_FORCE_MODE_MASK GENMASK(14, 13) + +#define QCA807X_INTR_ENABLE 0x12 +#define QCA807X_INTR_STATUS 0x13 +#define QCA807X_INTR_ENABLE_AUTONEG_ERR BIT(15) +#define QCA807X_INTR_ENABLE_SPEED_CHANGED BIT(14) +#define QCA807X_INTR_ENABLE_DUPLEX_CHANGED BIT(13) +#define QCA807X_INTR_ENABLE_LINK_FAIL BIT(11) +#define QCA807X_INTR_ENABLE_LINK_SUCCESS BIT(10) + +#define QCA807X_FUNCTION_CONTROL 0x10 +#define QCA807X_FC_MDI_CROSSOVER_MODE_MASK GENMASK(6, 5) +#define QCA807X_FC_MDI_CROSSOVER_AUTO 3 +#define QCA807X_FC_MDI_CROSSOVER_MANUAL_MDIX 1 +#define QCA807X_FC_MDI_CROSSOVER_MANUAL_MDI 0 + +#define QCA807X_PHY_SPECIFIC_STATUS 0x11 +#define QCA807X_SS_SPEED_AND_DUPLEX_RESOLVED BIT(11) +#define QCA807X_SS_SPEED_MASK GENMASK(15, 14) +#define QCA807X_SS_SPEED_1000 2 +#define QCA807X_SS_SPEED_100 1 +#define QCA807X_SS_SPEED_10 0 +#define QCA807X_SS_DUPLEX BIT(13) +#define QCA807X_SS_MDIX BIT(6) + +/* PQSGMII Analog PHY specific */ +#define PQSGMII_CTRL_REG 0x0 +#define PQSGMII_ANALOG_SW_RESET BIT(6) +#define PQSGMII_DRIVE_CONTROL_1 0xb +#define PQSGMII_TX_DRIVER_MASK GENMASK(7, 4) +#define PQSGMII_MODE_CTRL 0x6d +#define PQSGMII_MODE_CTRL_AZ_WORKAROUND_MASK BIT(0) +#define PQSGMII_MMD3_SERDES_CONTROL 0x805a + +#define SERDES_RESET_SLEEP 100 + +enum qca807x_global_phy { + QCA807X_COMBO_ADDR = 0, + QCA807X_PQSGMII_ADDR, + + __QCA807X_GLOBAL_PHY_MAX, +}; + +const char * const qca807x_global_phy_names[] = { + [QCA807X_COMBO_ADDR] = "combo", + [QCA807X_PQSGMII_ADDR] = "pqsgmii", +}; + +struct qca807x_gpio_priv { + struct phy_device *phy; +}; + +static int qca807x_get_downshift(struct phy_device *phydev, u8 *data) +{ + int val, cnt, enable; + + val = phy_read(phydev, MII_NWAYTEST); + if (val < 0) + return val; + + enable = FIELD_GET(QCA807X_SMARTSPEED_EN, val); + cnt = FIELD_GET(QCA807X_SMARTSPEED_RETRY_LIMIT_MASK, val) + 2; + + *data = enable ? cnt : DOWNSHIFT_DEV_DISABLE; + + return 0; +} + +static int qca807x_set_downshift(struct phy_device *phydev, u8 cnt) +{ + int ret, val; + + if (cnt > QCA807X_SMARTSPEED_RETRY_LIMIT_MAX || + (cnt < QCA807X_SMARTSPEED_RETRY_LIMIT_MIN && cnt != DOWNSHIFT_DEV_DISABLE)) + return -EINVAL; + + if (!cnt) { + ret = phy_clear_bits(phydev, MII_NWAYTEST, QCA807X_SMARTSPEED_EN); + } else { + val = QCA807X_SMARTSPEED_EN; + val |= FIELD_PREP(QCA807X_SMARTSPEED_RETRY_LIMIT_MASK, cnt - 2); + + phy_modify(phydev, MII_NWAYTEST, + QCA807X_SMARTSPEED_EN | + QCA807X_SMARTSPEED_RETRY_LIMIT_MASK, + val); + } + + ret = genphy_soft_reset(phydev); + + return ret; +} + +static int qca807x_get_tunable(struct phy_device *phydev, + struct ethtool_tunable *tuna, void *data) +{ + switch (tuna->id) { + case ETHTOOL_PHY_DOWNSHIFT: + return qca807x_get_downshift(phydev, data); + default: + return -EOPNOTSUPP; + } +} + +static int qca807x_set_tunable(struct phy_device *phydev, + struct ethtool_tunable *tuna, const void *data) +{ + switch (tuna->id) { + case ETHTOOL_PHY_DOWNSHIFT: + return qca807x_set_downshift(phydev, *(const u8 *)data); + default: + return -EOPNOTSUPP; + } +} + +static bool qca807x_distance_valid(int result) +{ + switch (result) { + case QCA807X_CDT_RESULTS_OPEN: + case QCA807X_CDT_RESULTS_SAME_SHORT: + case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI1_SAME_OK: + case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI2_SAME_OK: + case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI3_SAME_OK: + case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI1_SAME_OPEN: + case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI2_SAME_OPEN: + case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI3_SAME_OPEN: + case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI1_SAME_SHORT: + case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI2_SAME_SHORT: + case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI3_SAME_SHORT: + return true; + } + return false; +} + +static int qca807x_report_length(struct phy_device *phydev, + int pair, int result) +{ + int length; + int ret; + + ret = phy_read_mmd(phydev, MDIO_MMD_PCS, QCA807X_CDT_MMD3_MDI0_LENGTH + pair); + if (ret < 0) + return ret; + + switch (result) { + case ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT: + length = (FIELD_GET(QCA807X_CDT_SAME_SHORT_LENGTH_MASK, ret) * 800) / 10; + break; + case ETHTOOL_A_CABLE_RESULT_CODE_OPEN: + case ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT: + length = (FIELD_GET(QCA807X_CDT_CROSS_SHORT_LENGTH_MASK, ret) * 800) / 10; + break; + } + + ethnl_cable_test_fault_length(phydev, pair, length); + + return 0; +} + +static int qca807x_cable_test_report_trans(int result) +{ + switch (result) { + case QCA807X_CDT_RESULTS_OK: + return ETHTOOL_A_CABLE_RESULT_CODE_OK; + case QCA807X_CDT_RESULTS_OPEN: + return ETHTOOL_A_CABLE_RESULT_CODE_OPEN; + case QCA807X_CDT_RESULTS_SAME_SHORT: + return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT; + case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI1_SAME_OK: + case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI2_SAME_OK: + case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI3_SAME_OK: + case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI1_SAME_OPEN: + case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI2_SAME_OPEN: + case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI3_SAME_OPEN: + case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI1_SAME_SHORT: + case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI2_SAME_SHORT: + case QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI3_SAME_SHORT: + return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT; + default: + return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC; + } +} + +static int qca807x_cable_test_report(struct phy_device *phydev) +{ + int pair0, pair1, pair2, pair3; + int ret; + + ret = phy_read_mmd(phydev, MDIO_MMD_PCS, QCA807X_CDT_MMD3_STATUS); + if (ret < 0) + return ret; + + pair0 = FIELD_GET(QCA807X_CDT_MDI0_STATUS_MASK, ret); + pair1 = FIELD_GET(QCA807X_CDT_MDI1_STATUS_MASK, ret); + pair2 = FIELD_GET(QCA807X_CDT_MDI2_STATUS_MASK, ret); + pair3 = FIELD_GET(QCA807X_CDT_MDI3_STATUS_MASK, ret); + + ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A, + qca807x_cable_test_report_trans(pair0)); + ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_B, + qca807x_cable_test_report_trans(pair1)); + ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_C, + qca807x_cable_test_report_trans(pair2)); + ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_D, + qca807x_cable_test_report_trans(pair3)); + + if (qca807x_distance_valid(pair0)) + qca807x_report_length(phydev, 0, qca807x_cable_test_report_trans(pair0)); + if (qca807x_distance_valid(pair1)) + qca807x_report_length(phydev, 1, qca807x_cable_test_report_trans(pair1)); + if (qca807x_distance_valid(pair2)) + qca807x_report_length(phydev, 2, qca807x_cable_test_report_trans(pair2)); + if (qca807x_distance_valid(pair3)) + qca807x_report_length(phydev, 3, qca807x_cable_test_report_trans(pair3)); + + return 0; +} + +static int qca807x_cable_test_get_status(struct phy_device *phydev, + bool *finished) +{ + int val; + + *finished = false; + + val = phy_read(phydev, QCA807X_CDT); + if (!((val & QCA807X_CDT_ENABLE) && (val & QCA807X_CDT_STATUS))) { + *finished = true; + + return qca807x_cable_test_report(phydev); + } + + return 0; +} + +static int qca807x_cable_test_start(struct phy_device *phydev) +{ + int val, ret; + + val = phy_read(phydev, QCA807X_CDT); + /* Enable inter-pair short check as well */ + val &= ~QCA807X_CDT_ENABLE_INTER_PAIR_SHORT; + val |= QCA807X_CDT_ENABLE; + ret = phy_write(phydev, QCA807X_CDT, val); + + return ret; +} + +#ifdef CONFIG_GPIOLIB +static int qca807x_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) +{ + return GPIO_LINE_DIRECTION_OUT; +} + +static int qca807x_gpio_get_reg(unsigned int offset) +{ + return QCA807X_MMD7_LED_100N_2 + (offset % 2) * 2; +} + +static int qca807x_gpio_get(struct gpio_chip *gc, unsigned int offset) +{ + struct qca807x_gpio_priv *priv = gpiochip_get_data(gc); + int val; + + val = phy_read_mmd(priv->phy, MDIO_MMD_AN, qca807x_gpio_get_reg(offset)); + + return FIELD_GET(QCA807X_GPIO_FORCE_MODE_MASK, val); +} + +static void qca807x_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) +{ + struct qca807x_gpio_priv *priv = gpiochip_get_data(gc); + int val; + + val = phy_read_mmd(priv->phy, MDIO_MMD_AN, qca807x_gpio_get_reg(offset)); + val &= ~QCA807X_GPIO_FORCE_MODE_MASK; + val |= QCA807X_GPIO_FORCE_EN; + val |= FIELD_PREP(QCA807X_GPIO_FORCE_MODE_MASK, value); + + phy_write_mmd(priv->phy, MDIO_MMD_AN, qca807x_gpio_get_reg(offset), val); +} + +static int qca807x_gpio_dir_out(struct gpio_chip *gc, unsigned int offset, int value) +{ + qca807x_gpio_set(gc, offset, value); + + return 0; +} + +static int qca807x_gpio(struct phy_device *phydev) +{ + struct device *dev = &phydev->mdio.dev; + struct qca807x_gpio_priv *priv; + struct gpio_chip *gc; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->phy = phydev; + + gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL); + if (!gc) + return -ENOMEM; + + gc->label = dev_name(dev); + gc->base = -1; + gc->ngpio = 2; + gc->parent = dev; + gc->owner = THIS_MODULE; + gc->can_sleep = true; + gc->get_direction = qca807x_gpio_get_direction; + gc->direction_output = qca807x_gpio_dir_out; + gc->get = qca807x_gpio_get; + gc->set = qca807x_gpio_set; + + return devm_gpiochip_add_data(dev, gc, priv); +} +#endif + +static int qca807x_read_copper_status(struct phy_device *phydev) +{ + int ss, err, old_link = phydev->link; + + /* Update the link, but return if there was an error */ + err = genphy_update_link(phydev); + if (err) + return err; + + /* why bother the PHY if nothing can have changed */ + if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link) + return 0; + + phydev->speed = SPEED_UNKNOWN; + phydev->duplex = DUPLEX_UNKNOWN; + phydev->pause = 0; + phydev->asym_pause = 0; + + err = genphy_read_lpa(phydev); + if (err < 0) + return err; + + /* Read the QCA807x PHY-Specific Status register copper page, + * which indicates the speed and duplex that the PHY is actually + * using, irrespective of whether we are in autoneg mode or not. + */ + ss = phy_read(phydev, QCA807X_PHY_SPECIFIC_STATUS); + if (ss < 0) + return ss; + + if (ss & QCA807X_SS_SPEED_AND_DUPLEX_RESOLVED) { + int sfc; + + sfc = phy_read(phydev, QCA807X_FUNCTION_CONTROL); + if (sfc < 0) + return sfc; + + switch (FIELD_GET(QCA807X_SS_SPEED_MASK, ss)) { + case QCA807X_SS_SPEED_10: + phydev->speed = SPEED_10; + break; + case QCA807X_SS_SPEED_100: + phydev->speed = SPEED_100; + break; + case QCA807X_SS_SPEED_1000: + phydev->speed = SPEED_1000; + break; + } + if (ss & QCA807X_SS_DUPLEX) + phydev->duplex = DUPLEX_FULL; + else + phydev->duplex = DUPLEX_HALF; + + if (ss & QCA807X_SS_MDIX) + phydev->mdix = ETH_TP_MDI_X; + else + phydev->mdix = ETH_TP_MDI; + + switch (FIELD_GET(QCA807X_FC_MDI_CROSSOVER_MODE_MASK, sfc)) { + case QCA807X_FC_MDI_CROSSOVER_MANUAL_MDI: + phydev->mdix_ctrl = ETH_TP_MDI; + break; + case QCA807X_FC_MDI_CROSSOVER_MANUAL_MDIX: + phydev->mdix_ctrl = ETH_TP_MDI_X; + break; + case QCA807X_FC_MDI_CROSSOVER_AUTO: + phydev->mdix_ctrl = ETH_TP_MDI_AUTO; + break; + } + } + + if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) + phy_resolve_aneg_pause(phydev); + + return 0; +} + +static int qca807x_read_fiber_status(struct phy_device *phydev) +{ + int ss, err, lpa, old_link = phydev->link; + + /* Update the link, but return if there was an error */ + err = genphy_update_link(phydev); + if (err) + return err; + + /* why bother the PHY if nothing can have changed */ + if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link) + return 0; + + phydev->speed = SPEED_UNKNOWN; + phydev->duplex = DUPLEX_UNKNOWN; + phydev->pause = 0; + phydev->asym_pause = 0; + + if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) { + lpa = phy_read(phydev, MII_LPA); + if (lpa < 0) + return lpa; + + linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, + phydev->lp_advertising, lpa & LPA_LPACK); + linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, + phydev->lp_advertising, lpa & LPA_1000XFULL); + linkmode_mod_bit(ETHTOOL_LINK_MODE_Pause_BIT, + phydev->lp_advertising, lpa & LPA_1000XPAUSE); + linkmode_mod_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, + phydev->lp_advertising, + lpa & LPA_1000XPAUSE_ASYM); + + phy_resolve_aneg_linkmode(phydev); + } + + /* Read the QCA807x PHY-Specific Status register fiber page, + * which indicates the speed and duplex that the PHY is actually + * using, irrespective of whether we are in autoneg mode or not. + */ + ss = phy_read(phydev, QCA807X_PHY_SPECIFIC_STATUS); + if (ss < 0) + return ss; + + if (ss & QCA807X_SS_SPEED_AND_DUPLEX_RESOLVED) { + switch (FIELD_GET(QCA807X_SS_SPEED_MASK, ss)) { + case QCA807X_SS_SPEED_100: + phydev->speed = SPEED_100; + break; + case QCA807X_SS_SPEED_1000: + phydev->speed = SPEED_1000; + break; + } + + if (ss & QCA807X_SS_DUPLEX) + phydev->duplex = DUPLEX_FULL; + else + phydev->duplex = DUPLEX_HALF; + } + + return 0; +} + +static int qca807x_read_status(struct phy_device *phydev) +{ + if (linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, phydev->supported)) { + switch (phydev->port) { + case PORT_FIBRE: + return qca807x_read_fiber_status(phydev); + case PORT_TP: + return qca807x_read_copper_status(phydev); + default: + return -EINVAL; + } + } + + return qca807x_read_copper_status(phydev); +} + +static int qca807x_config_intr(struct phy_device *phydev) +{ + int ret, val; + + val = phy_read(phydev, QCA807X_INTR_ENABLE); + + if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { + /* Check for combo port as it has fewer interrupts */ + if (phy_read(phydev, QCA807X_CHIP_CONFIGURATION)) { + val |= QCA807X_INTR_ENABLE_SPEED_CHANGED; + val |= QCA807X_INTR_ENABLE_LINK_FAIL; + val |= QCA807X_INTR_ENABLE_LINK_SUCCESS; + } else { + val |= QCA807X_INTR_ENABLE_AUTONEG_ERR; + val |= QCA807X_INTR_ENABLE_SPEED_CHANGED; + val |= QCA807X_INTR_ENABLE_DUPLEX_CHANGED; + val |= QCA807X_INTR_ENABLE_LINK_FAIL; + val |= QCA807X_INTR_ENABLE_LINK_SUCCESS; + } + ret = phy_write(phydev, QCA807X_INTR_ENABLE, val); + } else { + ret = phy_write(phydev, QCA807X_INTR_ENABLE, 0); + } + + return ret; +} + +static irqreturn_t qca807x_handle_interrupt(struct phy_device *phydev) +{ + int irq_status, int_enabled; + + irq_status = phy_read(phydev, QCA807X_INTR_STATUS); + if (irq_status < 0) { + phy_error(phydev); + return IRQ_NONE; + } + + /* Read the current enabled interrupts */ + int_enabled = phy_read(phydev, QCA807X_INTR_ENABLE); + if (int_enabled < 0) { + phy_error(phydev); + return IRQ_NONE; + } + + /* See if this was one of our enabled interrupts */ + if (!(irq_status & int_enabled)) + return IRQ_NONE; + + phy_trigger_machine(phydev); + + return IRQ_HANDLED; +} + +static int qca807x_sfp_insert(void *upstream, const struct sfp_eeprom_id *id) +{ + struct phy_device *phydev = upstream; + __ETHTOOL_DECLARE_LINK_MODE_MASK(support) = { 0, }; + phy_interface_t iface; + int ret; + DECLARE_PHY_INTERFACE_MASK(interfaces); + + sfp_parse_support(phydev->sfp_bus, id, support, interfaces); + iface = sfp_select_interface(phydev->sfp_bus, support); + + dev_info(&phydev->mdio.dev, "%s SFP module inserted\n", phy_modes(iface)); + + switch (iface) { + case PHY_INTERFACE_MODE_1000BASEX: + case PHY_INTERFACE_MODE_100BASEX: + /* Set PHY mode to PSGMII combo (1/4 copper + combo ports) mode */ + ret = phy_modify(phydev, + QCA807X_CHIP_CONFIGURATION, + QCA807X_CHIP_CONFIGURATION_MODE_CFG_MASK, + QCA807X_CHIP_CONFIGURATION_MODE_PSGMII_FIBER); + /* Enable fiber mode autodection (1000Base-X or 100Base-FX) */ + ret = phy_set_bits_mmd(phydev, + MDIO_MMD_AN, + QCA807X_MMD7_FIBER_MODE_AUTO_DETECTION, + QCA807X_MMD7_FIBER_MODE_AUTO_DETECTION_EN); + /* Select fiber page */ + ret = phy_clear_bits(phydev, + QCA807X_CHIP_CONFIGURATION, + QCA807X_BT_BX_REG_SEL); + + phydev->port = PORT_FIBRE; + break; + default: + dev_err(&phydev->mdio.dev, "Incompatible SFP module inserted\n"); + return -EINVAL; + } + + return ret; +} + +static void qca807x_sfp_remove(void *upstream) +{ + struct phy_device *phydev = upstream; + + /* Select copper page */ + phy_set_bits(phydev, + QCA807X_CHIP_CONFIGURATION, + QCA807X_BT_BX_REG_SEL); + + phydev->port = PORT_TP; +} + +static const struct sfp_upstream_ops qca807x_sfp_ops = { + .attach = phy_sfp_attach, + .detach = phy_sfp_detach, + .module_insert = qca807x_sfp_insert, + .module_remove = qca807x_sfp_remove, +}; + +static int qca807x_config(struct phy_device *phydev) +{ + struct device_node *node = phydev->mdio.dev.of_node; + int control_dac, ret = 0; + u32 of_control_dac; + + if (of_property_read_u32(node, "qcom,control-dac", &of_control_dac)) + of_control_dac = QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS; + + control_dac = phy_read_mmd(phydev, MDIO_MMD_AN, + QCA807X_MMD7_1000BASE_T_POWER_SAVE_PER_CABLE_LENGTH); + control_dac &= ~QCA807X_CONTROL_DAC_MASK; + control_dac |= FIELD_PREP(QCA807X_CONTROL_DAC_MASK, of_control_dac); + ret = phy_write_mmd(phydev, MDIO_MMD_AN, + QCA807X_MMD7_1000BASE_T_POWER_SAVE_PER_CABLE_LENGTH, + control_dac); + + return ret; +} + +static int qca807x_probe(struct phy_device *phydev) +{ + struct device_node *node = phydev->mdio.dev.of_node; + int ret = 0; + + if (IS_ENABLED(CONFIG_GPIOLIB)) { + if (of_find_property(node, "leds") && + of_find_property(node, "gpio-controller")) { + phydev_err("Invalid property detected. LEDs and gpio-controller are mutually exclusive."); + return -EINVAL; + } + + /* Do not register a GPIO controller unless flagged for it */ + if (of_property_read_bool(node, "gpio-controller")) { + ret = qca807x_gpio(phydev); + if (ret) + return ret; + } + } + + /* Attach SFP bus on combo port*/ + if (phy_read(phydev, QCA807X_CHIP_CONFIGURATION)) { + ret = phy_sfp_probe(phydev, &qca807x_sfp_ops); + linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, phydev->supported); + linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, phydev->advertising); + } + + return ret; +} + +static int qca807x_phy_package_config_init_once(struct phy_device *phydev) +{ + phy_interface_t package_interface = PHY_INTERFACE_MODE_NA; + struct phy_package_shared *shared = phydev->shared; + u32 tx_driver_strength; + int val, ret; + + if (of_property_read_u32(shared->np, "qcom,tx-driver-strength", + &tx_driver_strength)) + tx_driver_strength = PSGMII_QSGMII_TX_DRIVER_600MV; + + phy_lock_mdio_bus(phydev); + + /* Set correct PHY package mode */ + phy_package_get_mode(phydev, &package_interface); + val = __phy_package_read(phydev, QCA807X_COMBO_ADDR, + QCA807X_CHIP_CONFIGURATION); + val &= ~QCA807X_CHIP_CONFIGURATION_MODE_CFG_MASK; + if (package_interface == PHY_INTERFACE_MODE_QSGMII) + val |= QCA807X_CHIP_CONFIGURATION_MODE_QSGMII_SGMII; + else if (package_interface == PHY_INTERFACE_MODE_PSGMII) + val |= QCA807X_CHIP_CONFIGURATION_MODE_PSGMII_ALL_COPPER; + ret = __phy_package_write(phydev, QCA807X_COMBO_ADDR, + QCA807X_CHIP_CONFIGURATION, val); + if (ret) + goto exit; + + /* After mode change Serdes reset is required */ + val = __phy_package_read(phydev, QCA807X_PQSGMII_ADDR, + PQSGMII_CTRL_REG); + val &= ~PQSGMII_ANALOG_SW_RESET; + ret = __phy_package_write(phydev, QCA807X_PQSGMII_ADDR, + PQSGMII_CTRL_REG, val); + if (ret) + goto exit; + + msleep(SERDES_RESET_SLEEP); + + val = __phy_package_read(phydev, QCA807X_PQSGMII_ADDR, + PQSGMII_CTRL_REG); + val |= PQSGMII_ANALOG_SW_RESET; + ret = __phy_package_write(phydev, QCA807X_PQSGMII_ADDR, + PQSGMII_CTRL_REG, val); + if (ret) + goto exit; + + /* Workaround to enable AZ transmitting ability */ + val = __phy_package_read_mmd(phydev, QCA807X_PQSGMII_ADDR, + MDIO_MMD_PMAPMD, PQSGMII_MODE_CTRL); + val &= ~PQSGMII_MODE_CTRL_AZ_WORKAROUND_MASK; + ret = __phy_package_write_mmd(phydev, QCA807X_PQSGMII_ADDR, + MDIO_MMD_PMAPMD, PQSGMII_MODE_CTRL, val); + if (ret) + goto exit; + + /* Set PQSGMII TX AMP strength */ + val = __phy_package_read(phydev, QCA807X_PQSGMII_ADDR, + PQSGMII_DRIVE_CONTROL_1); + val &= ~PQSGMII_TX_DRIVER_MASK; + val |= FIELD_PREP(PQSGMII_TX_DRIVER_MASK, tx_driver_strength); + ret = __phy_package_write(phydev, QCA807X_PQSGMII_ADDR, + PQSGMII_DRIVE_CONTROL_1, val); + if (ret) + goto exit; + + /* Prevent PSGMII going into hibernation via PSGMII self test */ + val = __phy_package_read_mmd(phydev, QCA807X_COMBO_ADDR, + MDIO_MMD_PCS, PQSGMII_MMD3_SERDES_CONTROL); + val &= ~BIT(1); + ret = __phy_package_write_mmd(phydev, QCA807X_COMBO_ADDR, + MDIO_MMD_PCS, PQSGMII_MMD3_SERDES_CONTROL, val); + +exit: + phy_unlock_mdio_bus(phydev); + + return ret; +} + +static struct phy_driver qca807x_drivers[] = { + { + PHY_ID_MATCH_EXACT(PHY_ID_QCA8072), + .name = "Qualcomm QCA8072", + .flags = PHY_POLL_CABLE_TEST, + /* PHY_GBIT_FEATURES */ + .probe = qca807x_probe, + .config_init = qca807x_config, + .read_status = qca807x_read_status, + .config_intr = qca807x_config_intr, + .handle_interrupt = qca807x_handle_interrupt, + .soft_reset = genphy_soft_reset, + .get_tunable = qca807x_get_tunable, + .set_tunable = qca807x_set_tunable, + .resume = genphy_resume, + .suspend = genphy_suspend, + .cable_test_start = qca807x_cable_test_start, + .cable_test_get_status = qca807x_cable_test_get_status, + }, + { + PHY_ID_MATCH_EXACT(PHY_ID_QCA8075), + .name = "Qualcomm QCA8075", + .flags = PHY_POLL_CABLE_TEST, + /* PHY_GBIT_FEATURES */ + .probe = qca807x_probe, + .config_init = qca807x_config, + .read_status = qca807x_read_status, + .config_intr = qca807x_config_intr, + .handle_interrupt = qca807x_handle_interrupt, + .soft_reset = genphy_soft_reset, + .get_tunable = qca807x_get_tunable, + .set_tunable = qca807x_set_tunable, + .resume = genphy_resume, + .suspend = genphy_suspend, + .cable_test_start = qca807x_cable_test_start, + .cable_test_get_status = qca807x_cable_test_get_status, + /* PHY package define */ + .phy_package_global_phy_num = ARRAY_SIZE(qca807x_global_phy_names), + .phy_package_global_phy_names = qca807x_global_phy_names, + .phy_package_config_init_once = qca807x_phy_package_config_init_once, + }, +}; +module_phy_driver(qca807x_drivers); + +static struct mdio_device_id __maybe_unused qca807x_tbl[] = { + { PHY_ID_MATCH_EXACT(PHY_ID_QCA8072) }, + { PHY_ID_MATCH_EXACT(PHY_ID_QCA8075) }, + { } +}; + +MODULE_AUTHOR("Robert Marko "); +MODULE_AUTHOR("Christian Marangi "); +MODULE_DESCRIPTION("Qualcomm QCA807x PHY driver"); +MODULE_DEVICE_TABLE(mdio, qca807x_tbl); +MODULE_LICENSE("GPL"); From patchwork Mon Nov 20 13:50:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 13461366 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="MIyUMT8P" Received: from mail-lj1-x22b.google.com (mail-lj1-x22b.google.com [IPv6:2a00:1450:4864:20::22b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CC186D4B; Mon, 20 Nov 2023 05:51:36 -0800 (PST) Received: by mail-lj1-x22b.google.com with SMTP id 38308e7fff4ca-2c87acba73bso17908651fa.1; Mon, 20 Nov 2023 05:51:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1700488295; x=1701093095; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=GIf/7OpP8VtEJNt4sR3DXzoJdNlezeJaMEZxH0YUM0o=; b=MIyUMT8PelQ67olLv87UXHhxjI/iyYzIpcE7MB8VsB89H20cJ2nFoNBO0NrzWb+5Yn YrIwlpYjZTyw1jtUxbdbo0KSVMyu1KsAwPobUaKyQhz8nyj8Ju0OeogEp/3SlE9adC86 odY5xKHtMdWL3CxbfF3xvaQQDi7CAQrJIP9kON0Zce6UD3JqwYRSfHvgr7tIPNjpknLc T/SsL7zp79atKX1wG3X/Ifbqcoxh+iZNy9yQj+DDXeLufplN5czqrcBE34yCkvr/boq5 Tb/vQojqATc5naYmUUwIKMkQvtfTP26aXRohigRPTHli/U9CeUo3aIGx8VE+W6vIa5Br VYVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700488295; x=1701093095; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GIf/7OpP8VtEJNt4sR3DXzoJdNlezeJaMEZxH0YUM0o=; b=ioYxNpExWLWtXJKbL/ioc3MV6MmaIiNMd2/xrGTEvaaAYG3D5XHyJdDIDMmN4Nhbbo JXeQcskfMyw9EuV5ndOP4mDJMe3nf3a3kxCIv71an7y2e4lAu+X0qy2m/o0VaehwwdGz Dww0EqnLPNQVLZogegRV8Fu2ZZSeqDUJRbVvsp3jZKHX9utap8IHauiPnuoQvcKfAhSs KRpNuQHKLbEJWoicZs9toTSoFiZWEPdjIpRwzn77sbV7oFwGI46+4xWu5qMhWEhyYFcH c5g2FAnlo5Psb+Nv2VlaqWcSm2QT/qKGSqlTGrzRPVf6h+sRTJi9WqqAz3kLi78vCjKn 9BJg== X-Gm-Message-State: AOJu0Yy6qGViDtMklo0SzR25DVitlv5jl9CzsS5+VmdQ1pxjXh8eXq1V mVLCo07NV3YP17DUnRP0q+F4JCvJ3ZQ= X-Google-Smtp-Source: AGHT+IGNG/CqatG35iNvkBw+BbCu3x+dR7FxjR/Rwbwjxh+7pqa/JRoV2sSvFgNdFxXPxvvTAa8z6A== X-Received: by 2002:a05:651c:311:b0:2c8:5b9b:397c with SMTP id a17-20020a05651c031100b002c85b9b397cmr4630573ljp.32.1700488294817; Mon, 20 Nov 2023 05:51:34 -0800 (PST) Received: from localhost.localdomain (93-34-89-13.ip49.fastwebnet.it. [93.34.89.13]) by smtp.googlemail.com with ESMTPSA id j33-20020a05600c1c2100b0040772934b12sm18205846wms.7.2023.11.20.05.51.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Nov 2023 05:51:34 -0800 (PST) From: Christian Marangi To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Andrew Lunn , Heiner Kallweit , Russell King , Florian Fainelli , Broadcom internal kernel review list , Daniel Golle , Qingfang Deng , SkyLake Huang , Matthias Brugger , AngeloGioacchino Del Regno , David Epping , Vladimir Oltean , Christian Marangi , "Russell King (Oracle)" , Harini Katakam , Simon Horman , Robert Marko , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [net-next RFC PATCH 14/14] net: phy: qca807x: Add support for configurable LED Date: Mon, 20 Nov 2023 14:50:41 +0100 Message-Id: <20231120135041.15259-15-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231120135041.15259-1-ansuelsmth@gmail.com> References: <20231120135041.15259-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 QCA8072/5 have up to 2 LEDs attached for PHY. LEDs can be configured to be ON/hw blink or be set to HW control. Hw blink mode is set to blink at 4Hz or 250ms. PHY can support both copper (TP) or fiber (FIBRE) kind and supports different HW control modes based on the port type. HW control modes supported for netdev trigger for copper ports are: - LINK_10 - LINK_100 - LINK_1000 - TX - RX - FULL_DUPLEX - HALF_DUPLEX HW control modes supported for netdev trigger for fiber ports are: - LINK_100 - LINK_1000 - TX - RX - FULL_DUPLEX - HALF_DUPLEX LED support conflicts with GPIO controller feature and must be disabled if gpio-controller is used for the PHY. Signed-off-by: Christian Marangi --- drivers/net/phy/qca807x.c | 382 +++++++++++++++++++++++++++++++++++++- 1 file changed, 375 insertions(+), 7 deletions(-) diff --git a/drivers/net/phy/qca807x.c b/drivers/net/phy/qca807x.c index 5b82af52778a..a0daf65d872d 100644 --- a/drivers/net/phy/qca807x.c +++ b/drivers/net/phy/qca807x.c @@ -80,17 +80,60 @@ #define QCA807X_MMD7_1000BASE_T_POWER_SAVE_PER_CABLE_LENGTH 0x801a #define QCA807X_CONTROL_DAC_MASK GENMASK(2, 0) +#define QCA807X_MMD7_LED_GLOBAL 0x8073 +#define QCA807X_LED_BLINK_1 GENMASK(11, 6) +#define QCA807X_LED_BLINK_2 GENMASK(5, 0) +/* Values are the same for both BLINK_1 and BLINK_2 */ +#define QCA807X_LED_BLINK_FREQ_MASK GENMASK(5, 3) +#define QCA807X_LED_BLINK_FREQ_2HZ FIELD_PREP(QCA807X_LED_BLINK_FREQ_MASK, 0x0) +#define QCA807X_LED_BLINK_FREQ_4HZ FIELD_PREP(QCA807X_LED_BLINK_FREQ_MASK, 0x1) +#define QCA807X_LED_BLINK_FREQ_8HZ FIELD_PREP(QCA807X_LED_BLINK_FREQ_MASK, 0x2) +#define QCA807X_LED_BLINK_FREQ_16HZ FIELD_PREP(QCA807X_LED_BLINK_FREQ_MASK, 0x3) +#define QCA807X_LED_BLINK_FREQ_32HZ FIELD_PREP(QCA807X_LED_BLINK_FREQ_MASK, 0x4) +#define QCA807X_LED_BLINK_FREQ_64HZ FIELD_PREP(QCA807X_LED_BLINK_FREQ_MASK, 0x5) +#define QCA807X_LED_BLINK_FREQ_128HZ FIELD_PREP(QCA807X_LED_BLINK_FREQ_MASK, 0x6) +#define QCA807X_LED_BLINK_FREQ_256HZ FIELD_PREP(QCA807X_LED_BLINK_FREQ_MASK, 0x7) +#define QCA807X_LED_BLINK_DUTY_MASK GENMASK(2, 0) +#define QCA807X_LED_BLINK_DUTY_50_50 FIELD_PREP(QCA807X_LED_BLINK_DUTY_MASK, 0x0) +#define QCA807X_LED_BLINK_DUTY_75_25 FIELD_PREP(QCA807X_LED_BLINK_DUTY_MASK, 0x1) +#define QCA807X_LED_BLINK_DUTY_25_75 FIELD_PREP(QCA807X_LED_BLINK_DUTY_MASK, 0x2) +#define QCA807X_LED_BLINK_DUTY_33_67 FIELD_PREP(QCA807X_LED_BLINK_DUTY_MASK, 0x3) +#define QCA807X_LED_BLINK_DUTY_67_33 FIELD_PREP(QCA807X_LED_BLINK_DUTY_MASK, 0x4) +#define QCA807X_LED_BLINK_DUTY_17_83 FIELD_PREP(QCA807X_LED_BLINK_DUTY_MASK, 0x5) +#define QCA807X_LED_BLINK_DUTY_83_17 FIELD_PREP(QCA807X_LED_BLINK_DUTY_MASK, 0x6) +#define QCA807X_LED_BLINK_DUTY_8_92 FIELD_PREP(QCA807X_LED_BLINK_DUTY_MASK, 0x7) #define QCA807X_MMD7_LED_100N_1 0x8074 #define QCA807X_MMD7_LED_100N_2 0x8075 #define QCA807X_MMD7_LED_1000N_1 0x8076 #define QCA807X_MMD7_LED_1000N_2 0x8077 -#define QCA807X_LED_TXACT_BLK_EN_2 BIT(10) -#define QCA807X_LED_RXACT_BLK_EN_2 BIT(9) -#define QCA807X_LED_GT_ON_EN_2 BIT(6) -#define QCA807X_LED_HT_ON_EN_2 BIT(5) -#define QCA807X_LED_BT_ON_EN_2 BIT(4) -#define QCA807X_GPIO_FORCE_EN BIT(15) -#define QCA807X_GPIO_FORCE_MODE_MASK GENMASK(14, 13) +/* Values are the same for LED1 and LED2 */ +/* Values for control 1 */ +#define QCA807X_LED_COPPER_ON_BLINK_MASK GENMASK(12, 0) +#define QCA807X_LED_FDX_ON_EN BIT(12) +#define QCA807X_LED_HDX_ON_EN BIT(11) +#define QCA807X_LED_TXACT_BLK_EN BIT(10) +#define QCA807X_LED_RXACT_BLK_EN BIT(9) +#define QCA807X_LED_GT_ON_EN BIT(6) +#define QCA807X_LED_HT_ON_EN BIT(5) +#define QCA807X_LED_BT_ON_EN BIT(4) +/* Values for control 2 */ +#define QCA807X_LED_FORCE_EN BIT(15) +#define QCA807X_LED_FORCE_MODE_MASK GENMASK(14, 13) +#define QCA807X_LED_FORCE_BLINK_1 FIELD_PREP(QCA807X_LED_FORCE_MODE_MASK, 0x3) +#define QCA807X_LED_FORCE_BLINK_2 FIELD_PREP(QCA807X_LED_FORCE_MODE_MASK, 0x2) +#define QCA807X_LED_FORCE_ON FIELD_PREP(QCA807X_LED_FORCE_MODE_MASK, 0x1) +#define QCA807X_LED_FORCE_OFF FIELD_PREP(QCA807X_LED_FORCE_MODE_MASK, 0x0) +#define QCA807X_LED_FIBER_ON_BLINK_MASK GENMASK(11, 1) +#define QCA807X_LED_FIBER_TXACT_BLK_EN BIT(10) +#define QCA807X_LED_FIBER_RXACT_BLK_EN BIT(9) +#define QCA807X_LED_FIBER_FDX_ON_EN BIT(6) +#define QCA807X_LED_FIBER_HDX_ON_EN BIT(5) +#define QCA807X_LED_FIBER_1000BX_ON_EN BIT(2) +#define QCA807X_LED_FIBER_100FX_ON_EN BIT(1) + +/* Some device repurpose the LED as GPIO out */ +#define QCA807X_GPIO_FORCE_EN QCA807X_LED_FORCE_EN +#define QCA807X_GPIO_FORCE_MODE_MASK QCA807X_LED_FORCE_MODE_MASK #define QCA807X_INTR_ENABLE 0x12 #define QCA807X_INTR_STATUS 0x13 @@ -338,6 +381,320 @@ static int qca807x_cable_test_start(struct phy_device *phydev) return ret; } +static int qca807x_led_parse_netdev(struct phy_device *phydev, unsigned long rules, + u16 *offload_trigger) +{ + /* Parsing specific to netdev trigger */ + switch (phydev->port) { + case PORT_TP: + if (test_bit(TRIGGER_NETDEV_TX, &rules)) + *offload_trigger |= QCA807X_LED_TXACT_BLK_EN; + if (test_bit(TRIGGER_NETDEV_RX, &rules)) + *offload_trigger |= QCA807X_LED_RXACT_BLK_EN; + if (test_bit(TRIGGER_NETDEV_LINK_10, &rules)) + *offload_trigger |= QCA807X_LED_BT_ON_EN; + if (test_bit(TRIGGER_NETDEV_LINK_100, &rules)) + *offload_trigger |= QCA807X_LED_HT_ON_EN; + if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules)) + *offload_trigger |= QCA807X_LED_GT_ON_EN; + if (test_bit(TRIGGER_NETDEV_HALF_DUPLEX, &rules)) + *offload_trigger |= QCA807X_LED_HDX_ON_EN; + if (test_bit(TRIGGER_NETDEV_FULL_DUPLEX, &rules)) + *offload_trigger |= QCA807X_LED_FDX_ON_EN; + break; + case PORT_FIBRE: + if (test_bit(TRIGGER_NETDEV_TX, &rules)) + *offload_trigger |= QCA807X_LED_FIBER_TXACT_BLK_EN; + if (test_bit(TRIGGER_NETDEV_RX, &rules)) + *offload_trigger |= QCA807X_LED_FIBER_RXACT_BLK_EN; + if (test_bit(TRIGGER_NETDEV_LINK_100, &rules)) + *offload_trigger |= QCA807X_LED_FIBER_100FX_ON_EN; + if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules)) + *offload_trigger |= QCA807X_LED_FIBER_1000BX_ON_EN; + if (test_bit(TRIGGER_NETDEV_HALF_DUPLEX, &rules)) + *offload_trigger |= QCA807X_LED_FIBER_HDX_ON_EN; + if (test_bit(TRIGGER_NETDEV_FULL_DUPLEX, &rules)) + *offload_trigger |= QCA807X_LED_FIBER_FDX_ON_EN; + break; + default: + return -EOPNOTSUPP; + } + + if (rules && !*offload_trigger) + return -EOPNOTSUPP; + + return 0; +} + +static int qca807x_led_hw_control_enable(struct phy_device *phydev, u8 index) +{ + int val, reg, ret; + + switch (index) { + case 0: + reg = QCA807X_MMD7_LED_100N_2; + break; + case 1: + reg = QCA807X_MMD7_LED_1000N_2; + break; + default: + return -EINVAL; + } + + val = phy_read_mmd(phydev, MDIO_MMD_AN, reg); + val &= ~QCA807X_LED_FORCE_EN; + ret = phy_write_mmd(phydev, MDIO_MMD_AN, reg, val); + + return ret; +} + +static int qca807x_led_hw_is_supported(struct phy_device *phydev, u8 index, + unsigned long rules) +{ + u16 offload_trigger = 0; + + if (index > 1) + return -EINVAL; + + return qca807x_led_parse_netdev(phydev, rules, &offload_trigger); +} + +static int qca807x_led_hw_control_set(struct phy_device *phydev, u8 index, + unsigned long rules) +{ + int val, ret, copper_reg, fibre_reg; + u16 offload_trigger = 0; + + switch (index) { + case 0: + copper_reg = QCA807X_MMD7_LED_100N_1; + fibre_reg = QCA807X_MMD7_LED_100N_2; + break; + case 1: + copper_reg = QCA807X_MMD7_LED_1000N_1; + fibre_reg = QCA807X_MMD7_LED_1000N_2; + break; + default: + return -EINVAL; + } + + ret = qca807x_led_parse_netdev(phydev, rules, &offload_trigger); + if (ret) + return ret; + + ret = qca807x_led_hw_control_enable(phydev, index); + if (ret) + return ret; + + switch (phydev->port) { + case PORT_TP: + val = phy_read_mmd(phydev, MDIO_MMD_AN, copper_reg); + val &= ~QCA807X_LED_COPPER_ON_BLINK_MASK; + val |= offload_trigger; + ret = phy_write_mmd(phydev, MDIO_MMD_AN, copper_reg, val); + break; + case PORT_FIBRE: + val = phy_read_mmd(phydev, MDIO_MMD_AN, fibre_reg); + val &= ~QCA807X_LED_FIBER_ON_BLINK_MASK; + val |= offload_trigger; + ret = phy_write_mmd(phydev, MDIO_MMD_AN, fibre_reg, val); + break; + default: + return -EINVAL; + } + + return ret; +} + +static bool qca807x_led_hw_control_status(struct phy_device *phydev, u8 index) +{ + int val, reg; + + switch (index) { + case 0: + reg = QCA807X_MMD7_LED_100N_2; + break; + case 1: + reg = QCA807X_MMD7_LED_1000N_2; + break; + default: + return false; + } + + val = phy_read_mmd(phydev, MDIO_MMD_AN, reg); + + return !(val & QCA807X_LED_FORCE_EN); +} + +static int qca807x_led_hw_control_get(struct phy_device *phydev, u8 index, + unsigned long *rules) +{ + int val, copper_reg, fibre_reg; + + switch (index) { + case 0: + copper_reg = QCA807X_MMD7_LED_100N_1; + fibre_reg = QCA807X_MMD7_LED_100N_2; + break; + case 1: + copper_reg = QCA807X_MMD7_LED_1000N_1; + fibre_reg = QCA807X_MMD7_LED_100N_2; + break; + default: + return -EINVAL; + } + + /* Check if we have hw control enabled */ + if (qca807x_led_hw_control_status(phydev, index)) + return -EINVAL; + + /* Parsing specific to netdev trigger */ + switch (phydev->port) { + case PORT_TP: + val = phy_read_mmd(phydev, MDIO_MMD_AN, copper_reg); + if (val & QCA807X_LED_TXACT_BLK_EN) + set_bit(TRIGGER_NETDEV_TX, rules); + if (val & QCA807X_LED_RXACT_BLK_EN) + set_bit(TRIGGER_NETDEV_RX, rules); + if (val & QCA807X_LED_BT_ON_EN) + set_bit(TRIGGER_NETDEV_LINK_10, rules); + if (val & QCA807X_LED_HT_ON_EN) + set_bit(TRIGGER_NETDEV_LINK_100, rules); + if (val & QCA807X_LED_GT_ON_EN) + set_bit(TRIGGER_NETDEV_LINK_1000, rules); + if (val & QCA807X_LED_HDX_ON_EN) + set_bit(TRIGGER_NETDEV_HALF_DUPLEX, rules); + if (val & QCA807X_LED_FDX_ON_EN) + set_bit(TRIGGER_NETDEV_FULL_DUPLEX, rules); + break; + case PORT_FIBRE: + val = phy_read_mmd(phydev, MDIO_MMD_AN, fibre_reg); + if (val & QCA807X_LED_FIBER_TXACT_BLK_EN) + set_bit(TRIGGER_NETDEV_TX, rules); + if (val & QCA807X_LED_FIBER_RXACT_BLK_EN) + set_bit(TRIGGER_NETDEV_RX, rules); + if (val & QCA807X_LED_FIBER_100FX_ON_EN) + set_bit(TRIGGER_NETDEV_LINK_100, rules); + if (val & QCA807X_LED_FIBER_1000BX_ON_EN) + set_bit(TRIGGER_NETDEV_LINK_1000, rules); + if (val & QCA807X_LED_FIBER_HDX_ON_EN) + set_bit(TRIGGER_NETDEV_HALF_DUPLEX, rules); + if (val & QCA807X_LED_FIBER_FDX_ON_EN) + set_bit(TRIGGER_NETDEV_FULL_DUPLEX, rules); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int qca807x_led_hw_control_reset(struct phy_device *phydev, u8 index) +{ + int val, copper_reg, fibre_reg, ret; + + switch (index) { + case 0: + copper_reg = QCA807X_MMD7_LED_100N_1; + fibre_reg = QCA807X_MMD7_LED_100N_2; + break; + case 1: + copper_reg = QCA807X_MMD7_LED_1000N_1; + fibre_reg = QCA807X_MMD7_LED_100N_2; + break; + default: + return -EINVAL; + } + + switch (phydev->port) { + case PORT_TP: + val = phy_read_mmd(phydev, MDIO_MMD_AN, copper_reg); + val &= ~QCA807X_LED_COPPER_ON_BLINK_MASK; + ret = phy_write_mmd(phydev, MDIO_MMD_AN, copper_reg, val); + break; + case PORT_FIBRE: + val = phy_read_mmd(phydev, MDIO_MMD_AN, fibre_reg); + val &= ~QCA807X_LED_FIBER_ON_BLINK_MASK; + ret = phy_write_mmd(phydev, MDIO_MMD_AN, fibre_reg, val); + break; + default: + return -EINVAL; + } + + return ret; +} + +static int qca807x_led_brightness_set(struct phy_device *phydev, + u8 index, enum led_brightness value) +{ + int val, ret; + u16 reg; + + switch (index) { + case 0: + reg = QCA807X_MMD7_LED_100N_2; + break; + case 1: + reg = QCA807X_MMD7_LED_1000N_2; + break; + default: + return -EINVAL; + } + + /* If we are setting off the LED reset any hw control rule */ + if (!value) { + ret = qca807x_led_hw_control_reset(phydev, index); + if (ret) + return ret; + } + + val = phy_read_mmd(phydev, MDIO_MMD_AN, reg); + val &= ~(QCA807X_LED_FORCE_EN | QCA807X_LED_FORCE_MODE_MASK); + val |= QCA807X_LED_FORCE_EN; + if (value) + val |= QCA807X_LED_FORCE_ON; + ret = phy_write_mmd(phydev, MDIO_MMD_AN, reg, val); + + return ret; +} + +static int qca807x_led_blink_set(struct phy_device *phydev, u8 index, + unsigned long *delay_on, + unsigned long *delay_off) +{ + int val, ret; + u16 reg; + + switch (index) { + case 0: + reg = QCA807X_MMD7_LED_100N_2; + break; + case 1: + reg = QCA807X_MMD7_LED_1000N_2; + break; + default: + return -EINVAL; + } + + /* Set blink to 50% off, 50% on at 4Hz by default */ + val = phy_read_mmd(phydev, MDIO_MMD_AN, QCA807X_MMD7_LED_GLOBAL); + val &= ~(QCA807X_LED_BLINK_FREQ_MASK | QCA807X_LED_BLINK_DUTY_MASK); + val |= QCA807X_LED_BLINK_FREQ_4HZ | QCA807X_LED_BLINK_DUTY_50_50; + ret = phy_write_mmd(phydev, MDIO_MMD_AN, QCA807X_MMD7_LED_GLOBAL, val); + + /* We use BLINK_1 for normal blinking */ + val = phy_read_mmd(phydev, MDIO_MMD_AN, reg); + val &= ~(QCA807X_LED_FORCE_EN | QCA807X_LED_FORCE_MODE_MASK); + val |= QCA807X_LED_FORCE_EN | QCA807X_LED_FORCE_BLINK_1; + ret = phy_write_mmd(phydev, MDIO_MMD_AN, reg, val); + + /* We set blink to 4Hz, aka 250ms */ + *delay_on = 250 / 2; + *delay_off = 250 / 2; + + return ret; +} + #ifdef CONFIG_GPIOLIB static int qca807x_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) { @@ -716,6 +1073,12 @@ static int qca807x_probe(struct phy_device *phydev) ret = qca807x_gpio(phydev); if (ret) return ret; + + phydev->drv->led_brightness_set = NULL; + phydev->drv->led_blink_set = NULL; + phydev->drv->led_hw_is_supported = NULL; + phydev->drv->led_hw_control_set = NULL; + phydev->drv->led_hw_control_get = NULL; } } @@ -843,6 +1206,11 @@ static struct phy_driver qca807x_drivers[] = { .suspend = genphy_suspend, .cable_test_start = qca807x_cable_test_start, .cable_test_get_status = qca807x_cable_test_get_status, + .led_brightness_set = qca807x_led_brightness_set, + .led_blink_set = qca807x_led_blink_set, + .led_hw_is_supported = qca807x_led_hw_is_supported, + .led_hw_control_set = qca807x_led_hw_control_set, + .led_hw_control_get = qca807x_led_hw_control_get, /* PHY package define */ .phy_package_global_phy_num = ARRAY_SIZE(qca807x_global_phy_names), .phy_package_global_phy_names = qca807x_global_phy_names,