From patchwork Mon Nov 20 14:10:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 13461392 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="P6c6bdC1" Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.100]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7D6C0CA; Mon, 20 Nov 2023 06:13:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1700489588; x=1732025588; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=TuRKMqc5s8ctrxhZQRN1hc+qrqht23N2CXc03YDUn4k=; b=P6c6bdC1IrSiP2WRgGJkAhfhsOD0jsZ2PIvM3mzyR6d8wWZrNYO0caZF 0bYJ+grMhjC6Io09S7Zig2tXYA3mSnbefJPPzd5xbQ4gvNuPr7HP/tqTD Jw3C4GpzwiaZWHgU2hywRaBuz3NEDO4rvpr8fJcMLce1Kx1fwi8A9/haU xeQK55TCfVrHxmpji1g5DZ3/YO2O8bzwxckHtJXkQez9oD6AoTKGrCCFK L5fFEgMJDaLAQ8f5HDZIZBCzOsEUNuaGAajEcNfprSB3cFr/KCGgSyiD8 ypeVCOczodczFcw602lpJVlEQIZ9zoT9YDMFflo26C+fM5xY8eJJExmuG g==; X-IronPort-AV: E=McAfee;i="6600,9927,10900"; a="458121759" X-IronPort-AV: E=Sophos;i="6.04,214,1695711600"; d="scan'208";a="458121759" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Nov 2023 06:12:37 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10900"; a="801184235" X-IronPort-AV: E=Sophos;i="6.04,214,1695711600"; d="scan'208";a="801184235" Received: from black.fi.intel.com ([10.237.72.28]) by orsmga001.jf.intel.com with ESMTP; 20 Nov 2023 06:12:34 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id 0C7092CA; Mon, 20 Nov 2023 16:12:32 +0200 (EET) From: Andy Shevchenko To: Andy Shevchenko , linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Tony Luck , Borislav Petkov , James Morse , Mauro Carvalho Chehab , Robert Richter , Qiuxu Zhuo Subject: [PATCH v2 1/4] EDAC, pnd2: Replace custom definition by one from sizes.h Date: Mon, 20 Nov 2023 16:10:45 +0200 Message-ID: <20231120141231.1638240-1-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.43.0.rc1.1.gbec44491f096 Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The sizes.h provides a set of common size definitions, use it. Reviewed-by: Qiuxu Zhuo Signed-off-by: Andy Shevchenko --- v2: added tag (Qiuxu) drivers/edac/pnd2_edac.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/edac/pnd2_edac.c b/drivers/edac/pnd2_edac.c index 2b306f2cc605..45e3c2913d51 100644 --- a/drivers/edac/pnd2_edac.c +++ b/drivers/edac/pnd2_edac.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -109,7 +110,6 @@ static struct mem_ctl_info *pnd2_mci; #define MOT_CHAN_INTLV_BIT_1SLC_2CH 12 #define MOT_CHAN_INTLV_BIT_2SLC_2CH 13 #define SELECTOR_DISABLED (-1) -#define _4GB (1ul << 32) #define PMI_ADDRESS_WIDTH 31 #define PND_MAX_PHYS_BIT 39 @@ -587,7 +587,7 @@ static int get_registers(void) /* Get a contiguous memory address (remove the MMIO gap) */ static u64 remove_mmio_gap(u64 sys) { - return (sys < _4GB) ? sys : sys - (_4GB - top_lm); + return (sys < SZ_4G) ? sys : sys - (SZ_4G - top_lm); } /* Squeeze out one address bit, shift upper part down to fill gap */ @@ -643,7 +643,7 @@ static int sys2pmi(const u64 addr, u32 *pmiidx, u64 *pmiaddr, char *msg) /* Give up if address is out of range, or in MMIO gap */ if (addr >= (1ul << PND_MAX_PHYS_BIT) || - (addr >= top_lm && addr < _4GB) || addr >= top_hm) { + (addr >= top_lm && addr < SZ_4G) || addr >= top_hm) { snprintf(msg, PND2_MSG_SIZE, "Error address 0x%llx is not DRAM", addr); return -EINVAL; } From patchwork Mon Nov 20 14:10:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 13461391 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="TxSBSO+9" Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.100]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 21CA3BA; Mon, 20 Nov 2023 06:13:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1700489588; x=1732025588; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=dcBH8dkNNXnKF0j8ud1kjx2WkqUBoV7nIP12in5A7ms=; b=TxSBSO+96S4nOTT7Yf2deTYfI8sCLlpIaN6Tlifb2d52DOIOrsHFDZ5o nKk+MscvvOE36MwYo3BbRNbWXsRe0Rld4Yn/nAPiJ8BzjZHHvSI3kHnUB 1kYvK7XlD2ewyuAZD8bU/wx90VuFpCRZFhqK3Emfg3LNEpMNWiCu9wmbG paMzndE/UobhONmQC79En+zvIK4pQZpYKc8/Vs8AZmhWB2JC+VOSVPFf/ mgb02HO81MIblsbjyv5dQiCsuoTGJ6pgzg94soNdjdL1xWZdIYwVV2cF+ +vA9Lo3/bnALAzcHfS41qvoB2zi51jM7b64xW4VtcnLK4PqNAhxL8O97Q Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10900"; a="458121751" X-IronPort-AV: E=Sophos;i="6.04,214,1695711600"; d="scan'208";a="458121751" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Nov 2023 06:12:37 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10900"; a="801184238" X-IronPort-AV: E=Sophos;i="6.04,214,1695711600"; d="scan'208";a="801184238" Received: from black.fi.intel.com ([10.237.72.28]) by orsmga001.jf.intel.com with ESMTP; 20 Nov 2023 06:12:34 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id 219BB24F; Mon, 20 Nov 2023 16:12:33 +0200 (EET) From: Andy Shevchenko To: Andy Shevchenko , linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Tony Luck , Borislav Petkov , James Morse , Mauro Carvalho Chehab , Robert Richter Subject: [PATCH v2 2/4] EDAC, pnd2: Apply bit macros and helpers where it makes sense Date: Mon, 20 Nov 2023 16:10:46 +0200 Message-ID: <20231120141231.1638240-2-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.43.0.rc1.1.gbec44491f096 In-Reply-To: <20231120141231.1638240-1-andriy.shevchenko@linux.intel.com> References: <20231120141231.1638240-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Apply bit macros (BIT()/BIT_ULL()/GENMASK()/etc) and helpers (for_each_set_bit()/etc) where it makes sense. Signed-off-by: Andy Shevchenko Reviewed-by: Qiuxu Zhuo --- v2: fixed uninitialized variable (lkp, Qiuxu), dropped mask check change (Qiuxu) drivers/edac/pnd2_edac.c | 32 ++++++++++++++------------------ 1 file changed, 14 insertions(+), 18 deletions(-) diff --git a/drivers/edac/pnd2_edac.c b/drivers/edac/pnd2_edac.c index 45e3c2913d51..ee7c9b024354 100644 --- a/drivers/edac/pnd2_edac.c +++ b/drivers/edac/pnd2_edac.c @@ -183,7 +183,7 @@ static int _apl_rd_reg(int port, int off, int op, u32 *data) } P2SB_READ(dword, P2SB_DATA_OFF, data); - ret = (status >> 1) & 0x3; + ret = (status >> 1) & GENMASK(1, 0); out: /* Hide the P2SB device, if it was hidden before */ if (hidden) @@ -307,7 +307,7 @@ static bool two_channels; /* Both PMI channels in one slice enabled */ static u8 sym_chan_mask; static u8 asym_chan_mask; -static u8 chan_mask; +static unsigned long chan_mask; static int slice_selector = -1; static int chan_selector = -1; @@ -598,7 +598,7 @@ static void remove_addr_bit(u64 *addr, int bitidx) if (bitidx == -1) return; - mask = (1ull << bitidx) - 1; + mask = BIT_ULL(bitidx) - 1; *addr = ((*addr >> 1) & ~mask) | (*addr & mask); } @@ -642,7 +642,7 @@ static int sys2pmi(const u64 addr, u32 *pmiidx, u64 *pmiaddr, char *msg) int sym_chan_shift = sym_channels >> 1; /* Give up if address is out of range, or in MMIO gap */ - if (addr >= (1ul << PND_MAX_PHYS_BIT) || + if (addr >= BIT(PND_MAX_PHYS_BIT) || (addr >= top_lm && addr < SZ_4G) || addr >= top_hm) { snprintf(msg, PND2_MSG_SIZE, "Error address 0x%llx is not DRAM", addr); return -EINVAL; @@ -727,10 +727,10 @@ static int sys2pmi(const u64 addr, u32 *pmiidx, u64 *pmiaddr, char *msg) } /* Translate PMI address to memory (rank, row, bank, column) */ -#define C(n) (0x10 | (n)) /* column */ -#define B(n) (0x20 | (n)) /* bank */ -#define R(n) (0x40 | (n)) /* row */ -#define RS (0x80) /* rank */ +#define C(n) (BIT(4) | (n)) /* column */ +#define B(n) (BIT(5) | (n)) /* bank */ +#define R(n) (BIT(6) | (n)) /* row */ +#define RS (BIT(7)) /* rank */ /* addrdec values */ #define AMAP_1KB 0 @@ -1064,9 +1064,9 @@ static int apl_check_ecc_active(void) int i, ret = 0; /* Check dramtype and ECC mode for each present DIMM */ - for (i = 0; i < APL_NUM_CHANNELS; i++) - if (chan_mask & BIT(i)) - ret += check_channel(i); + for_each_set_bit(i, &chan_mask, APL_NUM_CHANNELS) + ret += check_channel(i); + return ret ? -EINVAL : 0; } @@ -1205,10 +1205,7 @@ static void apl_get_dimm_config(struct mem_ctl_info *mci) u64 capacity; int i, g; - for (i = 0; i < APL_NUM_CHANNELS; i++) { - if (!(chan_mask & BIT(i))) - continue; - + for_each_set_bit(i, &chan_mask, APL_NUM_CHANNELS) { dimm = edac_get_dimm(mci, i, 0, 0); if (!dimm) { edac_dbg(0, "No allocated DIMM for channel %d\n", i); @@ -1228,8 +1225,7 @@ static void apl_get_dimm_config(struct mem_ctl_info *mci) } pvt->dimm_geom[i] = g; - capacity = (d->rken0 + d->rken1) * 8 * (1ul << dimms[g].rowbits) * - (1ul << dimms[g].colbits); + capacity = (d->rken0 + d->rken1) * 8 * BIT(dimms[g].rowbits + dimms[g].colbits); edac_dbg(0, "Channel %d: %lld MByte DIMM\n", i, capacity >> (20 - 3)); dimm->nr_pages = MiB_TO_PAGES(capacity >> (20 - 3)); dimm->grain = 32; @@ -1295,7 +1291,7 @@ static void dnv_get_dimm_config(struct mem_ctl_info *mci) continue; } - capacity = ranks_of_dimm[j] * banks * (1ul << rowbits) * (1ul << colbits); + capacity = ranks_of_dimm[j] * banks * BIT(rowbits + colbits); edac_dbg(0, "Channel %d DIMM %d: %lld MByte DIMM\n", i, j, capacity >> (20 - 3)); dimm->nr_pages = MiB_TO_PAGES(capacity >> (20 - 3)); dimm->grain = 32; From patchwork Mon Nov 20 14:10:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 13461389 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="js7MhCg2" Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.100]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5CB21BA; Mon, 20 Nov 2023 06:13:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1700489584; x=1732025584; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1DDuOJefk+3o6ygYL1H6D6JOyUtWSGokeA8lulBT4/o=; b=js7MhCg2iKZhxWkxlLu3Q4w5+PoKPgLwl5qDj1TQxAXUiHX9IF+UG9FP z0dKwd792mJbcjZop+9QAsd6jto6ApdG7S03c0TFPu2+M+em/5c0M5Xng 8Mn57W2wHU4NAPYTuqsjGA69e4gWEJuSJIHu6GQa11sc/lnNWEjSYvFAq 1Gl05nxV+cF9l0kRBrqWWr9wcL6HasOme8GB5dSkHcHWqXFY+jEvfPfnd KTO6n7D1ykrzvszKPoZbus/IcLsLODlNEEDlBqA9VTaElOMlFgcEGf6qD c3SGQexN4V+KxlKxpMmkTWx8dj8F72xb0e8CWNPmge8TMx/ek4P4NU5nw Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10900"; a="458121746" X-IronPort-AV: E=Sophos;i="6.04,214,1695711600"; d="scan'208";a="458121746" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Nov 2023 06:12:37 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10900"; a="801184237" X-IronPort-AV: E=Sophos;i="6.04,214,1695711600"; d="scan'208";a="801184237" Received: from black.fi.intel.com ([10.237.72.28]) by orsmga001.jf.intel.com with ESMTP; 20 Nov 2023 06:12:34 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id 2BDE72F0; Mon, 20 Nov 2023 16:12:33 +0200 (EET) From: Andy Shevchenko To: Andy Shevchenko , linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Tony Luck , Borislav Petkov , James Morse , Mauro Carvalho Chehab , Robert Richter , Qiuxu Zhuo Subject: [PATCH v2 3/4] EDAC, pnd2: Correct misleading error message in mk_region_mask() Date: Mon, 20 Nov 2023 16:10:47 +0200 Message-ID: <20231120141231.1638240-3-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.43.0.rc1.1.gbec44491f096 In-Reply-To: <20231120141231.1638240-1-andriy.shevchenko@linux.intel.com> References: <20231120141231.1638240-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The mask parameter is expected to be of a sequence of the set bits. It does not mean it must be power of two (only single bit set). Correct misleading error message. Suggested-by: Qiuxu Zhuo Signed-off-by: Andy Shevchenko --- v2: new patch as suggested (Qiuxu) drivers/edac/pnd2_edac.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/edac/pnd2_edac.c b/drivers/edac/pnd2_edac.c index ee7c9b024354..969fb2465edb 100644 --- a/drivers/edac/pnd2_edac.c +++ b/drivers/edac/pnd2_edac.c @@ -329,7 +329,7 @@ static void mk_region_mask(char *name, struct region *rp, u64 base, u64 mask) return; } if (mask != GENMASK_ULL(PND_MAX_PHYS_BIT, __ffs(mask))) { - pr_info(FW_BUG "MOT mask not power of two\n"); + pr_info(FW_BUG "MOT mask is invalid\n"); return; } if (base & ~mask) { From patchwork Mon Nov 20 14:10:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 13461390 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="iO19RStE" Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.100]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 90F9DA0; Mon, 20 Nov 2023 06:13:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1700489587; x=1732025587; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=XKZFQUi+U4ersNqM4YmQM70MnyE4Os/TQpc7j9Ab95o=; b=iO19RStEWjyQLAwIbTLZEi7AOOE4fHs1zJvBjy5sUCbH5AH+5KktXaSm Y7SJzDPSMDuC2qf0xiDtVR/Gq0AVUCv2wjEyN22RRB0nI2Cu5tlr92gBv bVL9HOjngVvrRsPGUwmyfQGFM0dbNsofAuN4rpOYbc+RKuWR0ge7S8UVi At3/LhgF238bvxXwQ1gcSGp4AR/YpNZTA3X8yLLmJ0kCKG0Gg5YYddUXU olmlHWz7ExltKUGiUNQKtxiE/tlrhGRm/p8BqSWyOJbl15YTbRDtjtVar QeQkM+w7sW0DTPPYV83TM+ZgVZrcXtw6OAPGeowQ6S0sATogxUJ32bOIf Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10900"; a="458121755" X-IronPort-AV: E=Sophos;i="6.04,214,1695711600"; d="scan'208";a="458121755" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Nov 2023 06:12:37 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10900"; a="801184239" X-IronPort-AV: E=Sophos;i="6.04,214,1695711600"; d="scan'208";a="801184239" Received: from black.fi.intel.com ([10.237.72.28]) by orsmga001.jf.intel.com with ESMTP; 20 Nov 2023 06:12:34 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id 3DA4E4F8; Mon, 20 Nov 2023 16:12:33 +0200 (EET) From: Andy Shevchenko To: Andy Shevchenko , linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Tony Luck , Borislav Petkov , James Morse , Mauro Carvalho Chehab , Robert Richter , Qiuxu Zhuo Subject: [PATCH v2 4/4] EDAC, pnd2: Sort headers alphabetically Date: Mon, 20 Nov 2023 16:10:48 +0200 Message-ID: <20231120141231.1638240-4-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.43.0.rc1.1.gbec44491f096 In-Reply-To: <20231120141231.1638240-1-andriy.shevchenko@linux.intel.com> References: <20231120141231.1638240-1-andriy.shevchenko@linux.intel.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Sort the headers in alphabetic order in order to ease the maintenance for this part. Reviewed-by: Qiuxu Zhuo Signed-off-by: Andy Shevchenko --- v2: added tag (Qiuxu) drivers/edac/pnd2_edac.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/drivers/edac/pnd2_edac.c b/drivers/edac/pnd2_edac.c index 969fb2465edb..2afcd148fcf8 100644 --- a/drivers/edac/pnd2_edac.c +++ b/drivers/edac/pnd2_edac.c @@ -16,19 +16,20 @@ * rank, bank, row and column using the appropriate "dunit_ops" functions/parameters. */ -#include -#include -#include -#include -#include +#include #include #include -#include -#include -#include -#include +#include #include +#include #include +#include +#include +#include +#include +#include +#include + #include #include