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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id u12-20020a170903124c00b001c0a4146961sm8923952plh.19.2023.11.21.21.38.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 21:38:14 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Palmer Dabbelt , Alistair Francis , Daniel Henrique Barboza Subject: [PULL 1/6] linux-user/riscv: Add Zicboz block size to hwprobe Date: Wed, 22 Nov 2023 15:37:55 +1000 Message-ID: <20231122053800.1531799-2-alistair.francis@wdc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231122053800.1531799-1-alistair.francis@wdc.com> References: <20231122053800.1531799-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=alistair23@gmail.com; helo=mail-pg1-x534.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Palmer Dabbelt Support for probing the Zicboz block size landed in Linux 6.6, which was released a few weeks ago. This provides the user-configured block size when Zicboz is enabled. Signed-off-by: Palmer Dabbelt Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Message-ID: <20231110173716.24423-1-palmer@rivosinc.com> Signed-off-by: Alistair Francis --- linux-user/syscall.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 16ca5ea7b6..e384e14248 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -8808,6 +8808,8 @@ static int do_getdents64(abi_long dirfd, abi_long arg2, abi_long count) #define RISCV_HWPROBE_MISALIGNED_UNSUPPORTED (4 << 0) #define RISCV_HWPROBE_MISALIGNED_MASK (7 << 0) +#define RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE 6 + struct riscv_hwprobe { abi_llong key; abi_ullong value; @@ -8860,6 +8862,10 @@ static void risc_hwprobe_fill_pairs(CPURISCVState *env, case RISCV_HWPROBE_KEY_CPUPERF_0: __put_user(RISCV_HWPROBE_MISALIGNED_FAST, &pair->value); break; + case RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE: + value = cfg->ext_zicboz ? cfg->cboz_blocksize : 0; + __put_user(value, &pair->value); + break; default: __put_user(-1, &pair->key); break; From patchwork Wed Nov 22 05:37:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13464001 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 04FD1C61D96 for ; Wed, 22 Nov 2023 05:39:37 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r5fwO-0002dX-E0; Wed, 22 Nov 2023 00:38:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r5fwM-0002dB-Vq for qemu-devel@nongnu.org; Wed, 22 Nov 2023 00:38:23 -0500 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r5fwL-00079c-00 for qemu-devel@nongnu.org; Wed, 22 Nov 2023 00:38:22 -0500 Received: by mail-pl1-x62b.google.com with SMTP id d9443c01a7336-1cf678043fdso19789655ad.2 for ; Tue, 21 Nov 2023 21:38:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1700631499; x=1701236299; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=O8CW4PWbEPru8lgh4qRFI+Ky/lG8EKD33qb1ErlTZ+Q=; b=LWNQ4WoMXgYivC05yepwbGEfMYRtxnJ4wYWVgFdZgiA8+BX7zFyzAr+FcoG3qXhva/ CwJQdCgRPxRN3d8cWcKT3mkcXrV5cOxchtoiX+m8dmXbGs68T34dy2jiq/dEkjr/zjD6 M9usNVXoNRYBqdazPc60cdqvVq0PQZt8J82/gVmYVfzmba3OnilDDOlCyYxEd4CMyirn ZpcdTXHChkd9qfmI3E1SfpGdUsnrZBmfVmvJ2pmwi/YWPk4KHx+/Hx83smfrJz0vT75q whPYQvbvZWU1knc5GiFr7zMzDr/yUGdVsrVMwAQf+TyxThJ/lVYWiIL6QJtr7dgh01lY PZqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700631499; x=1701236299; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=O8CW4PWbEPru8lgh4qRFI+Ky/lG8EKD33qb1ErlTZ+Q=; b=lkL4FC+8Yy94S2CjRePLhMvOUIiFaXBOj5ExVVoa3fG1A3wSSAmJYA2Sb4ggG35YFg L1vYFx1QVnDnnDHCUNRc8ViAr4duiY/TzdQgzHLloozhiTCgXClMEC86j5YpEgJ3Jwgs T2zH8cTWmV55teDXqk8DnfTaHFv9Spn1Tm67w/DORgnboC0mTEsWhVbukRZcECsCzYNi YuHuVLFM4RvqKfFePUlpnfXxcYu9m7uFyIQTafrQXRfoGcZ4j9a83cQU6/HLASG9F5EJ H1Ui50cVWNtr+5O8LcO9a3mH1e5+mz6DsBvkiRBEsL09U9VyeTTD7KYY+ByJpGrzt587 FWow== X-Gm-Message-State: AOJu0YxcIZibB7RvKzH7zn+HjW1Xzm2Hc5qDvILs6gAMY5YY7+EJQYYT 9ryQE5Sx1wBcxQDB9LnmF7gv17vy9tYKMQ== X-Google-Smtp-Source: AGHT+IFlCYdeKffbUpunpVWkHtv2++yS91HOTian/g2Gv6g7Qfq7WIHGAFYT3lNIGvla/LDmhgCoXw== X-Received: by 2002:a17:903:18f:b0:1cc:6e8f:c14e with SMTP id z15-20020a170903018f00b001cc6e8fc14emr1859363plg.15.1700631499251; Tue, 21 Nov 2023 21:38:19 -0800 (PST) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id u12-20020a170903124c00b001c0a4146961sm8923952plh.19.2023.11.21.21.38.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 21:38:18 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Alistair Francis Subject: [PULL 2/6] hw/riscv/virt.c: do create_fdt() earlier, add finalize_fdt() Date: Wed, 22 Nov 2023 15:37:56 +1000 Message-ID: <20231122053800.1531799-3-alistair.francis@wdc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231122053800.1531799-1-alistair.francis@wdc.com> References: <20231122053800.1531799-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62b.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Daniel Henrique Barboza Commit 49554856f0 fixed a problem, where TPM devices were not appearing in the FDT, by delaying the FDT creation up until virt_machine_done(). This create a side effect (see gitlab #1925) - devices that need access to the '/chosen' FDT node during realize() stopped working because, at that point, we don't have a FDT. This happens because our FDT creation is monolithic, but it doesn't need to be. We can add the needed FDT components for realize() time and, at the same time, do another FDT round where we account for dynamic sysbus devices. In other words, the problem fixed by 49554856f0 could also be fixed by postponing only create_fdt_sockets() and its dependencies, leaving everything else from create_fdt() to be done during init(). Split the FDT creation in two parts: - create_fdt(), now moved back to virt_machine_init(), will create FDT nodes that doesn't depend on additional (dynamic) devices from the sysbus; - a new finalize_fdt() step is added, where create_fdt_sockets() and friends is executed, accounting for the dynamic sysbus devices that were added during realize(). This will make both use cases happy: TPM devices are still working as intended, and devices such as 'guest-loader' have a FDT to work on during realize(). Fixes: 49554856f0 ("riscv: Generate devicetree only after machine initialization is complete") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1925 Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20231110172559.73209-1-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- hw/riscv/virt.c | 71 +++++++++++++++++++++++++++++-------------------- 1 file changed, 42 insertions(+), 29 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index c7fc97e273..d2eac24156 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -962,7 +962,6 @@ static void create_fdt_uart(RISCVVirtState *s, const MemMapEntry *memmap, qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", UART0_IRQ, 0x4); } - qemu_fdt_add_subnode(ms->fdt, "/chosen"); qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", name); g_free(name); } @@ -1023,11 +1022,29 @@ static void create_fdt_fw_cfg(RISCVVirtState *s, const MemMapEntry *memmap) g_free(nodename); } -static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap) +static void finalize_fdt(RISCVVirtState *s) { - MachineState *ms = MACHINE(s); uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1; uint32_t irq_pcie_phandle = 1, irq_virtio_phandle = 1; + + create_fdt_sockets(s, virt_memmap, &phandle, &irq_mmio_phandle, + &irq_pcie_phandle, &irq_virtio_phandle, + &msi_pcie_phandle); + + create_fdt_virtio(s, virt_memmap, irq_virtio_phandle); + + create_fdt_pcie(s, virt_memmap, irq_pcie_phandle, msi_pcie_phandle); + + create_fdt_reset(s, virt_memmap, &phandle); + + create_fdt_uart(s, virt_memmap, irq_mmio_phandle); + + create_fdt_rtc(s, virt_memmap, irq_mmio_phandle); +} + +static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap) +{ + MachineState *ms = MACHINE(s); uint8_t rng_seed[32]; ms->fdt = create_device_tree(&s->fdt_size); @@ -1047,28 +1064,16 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap) qemu_fdt_setprop_cell(ms->fdt, "/soc", "#size-cells", 0x2); qemu_fdt_setprop_cell(ms->fdt, "/soc", "#address-cells", 0x2); - create_fdt_sockets(s, memmap, &phandle, &irq_mmio_phandle, - &irq_pcie_phandle, &irq_virtio_phandle, - &msi_pcie_phandle); - - create_fdt_virtio(s, memmap, irq_virtio_phandle); - - create_fdt_pcie(s, memmap, irq_pcie_phandle, msi_pcie_phandle); - - create_fdt_reset(s, memmap, &phandle); - - create_fdt_uart(s, memmap, irq_mmio_phandle); - - create_fdt_rtc(s, memmap, irq_mmio_phandle); - - create_fdt_flash(s, memmap); - create_fdt_fw_cfg(s, memmap); - create_fdt_pmu(s); + qemu_fdt_add_subnode(ms->fdt, "/chosen"); /* Pass seed to RNG */ qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); qemu_fdt_setprop(ms->fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_seed)); + + create_fdt_flash(s, memmap); + create_fdt_fw_cfg(s, memmap); + create_fdt_pmu(s); } static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, @@ -1257,15 +1262,12 @@ static void virt_machine_done(Notifier *notifier, void *data) uint64_t kernel_entry = 0; BlockBackend *pflash_blk0; - /* load/create device tree */ - if (machine->dtb) { - machine->fdt = load_device_tree(machine->dtb, &s->fdt_size); - if (!machine->fdt) { - error_report("load_device_tree() failed"); - exit(1); - } - } else { - create_fdt(s, memmap); + /* + * An user provided dtb must include everything, including + * dynamic sysbus devices. Our FDT needs to be finalized. + */ + if (machine->dtb == NULL) { + finalize_fdt(s); } /* @@ -1541,6 +1543,17 @@ static void virt_machine_init(MachineState *machine) } virt_flash_map(s, system_memory); + /* load/create device tree */ + if (machine->dtb) { + machine->fdt = load_device_tree(machine->dtb, &s->fdt_size); + if (!machine->fdt) { + error_report("load_device_tree() failed"); + exit(1); + } + } else { + create_fdt(s, memmap); + } + s->machine_done.notify = virt_machine_done; qemu_add_machine_init_done_notifier(&s->machine_done); } From patchwork Wed Nov 22 05:37:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13463999 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9F95DC61D99 for ; Wed, 22 Nov 2023 05:39:21 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r5fwR-0002eD-QP; Wed, 22 Nov 2023 00:38:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r5fwQ-0002dw-55 for qemu-devel@nongnu.org; Wed, 22 Nov 2023 00:38:26 -0500 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r5fwO-00079t-Hw for qemu-devel@nongnu.org; Wed, 22 Nov 2023 00:38:25 -0500 Received: by mail-pl1-x630.google.com with SMTP id d9443c01a7336-1cf6a67e290so19933755ad.1 for ; Tue, 21 Nov 2023 21:38:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1700631503; x=1701236303; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ffQ3ckw80DQQK7pNtkarYFV8Ajwf2z94gxNCXOj01oQ=; b=MOjoVysPYNP7q+8sr/CzzSz4UAP27mVxKGplmzV0cwMSCtkXGBVIEDtWZJYm3TT2iu i2Kr+Swmtg8OrF5k8tNkcNXr3FewpKjOocYoVvFZ5mWtYjBbSJJuqdqKxGLaFYWiq181 uobFrFOMiBVX2clwOhqz/FmhWYSQFtnlzd3paZDGOq+GuujYs8ufoS5msChFwkViThtv ellMJWJemEX+QfIoLwhCWb06CQFN37X9YFpIl82XAwdLTbBUjpqelEV0EjxI9tBt+2SZ dlVY2Ni6PD2HHZEreLb35X4bcTvBhHoxwk2qa0CR4r5nsIGhBtUGrd9LnOrLOEWerZGm iRJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700631503; x=1701236303; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ffQ3ckw80DQQK7pNtkarYFV8Ajwf2z94gxNCXOj01oQ=; b=IgJ0O5kBNimFHjIT7VcpWlbbZv75sQQxusOawOsSAP01w5mdPjgchxO0bd4nOo8cj/ d1FbNxg5W5zUVlYN2CFgkd1DvvXdieH2xBCTNXr0mG3yN8cgCXCeD5vrOEPSGlu3rcPT HPj68TQBdSkYFt6541MZnAxcDoP461zeNot/4t2IKC4UGn3p2SD3vu9h4I0DgkmrLAR7 Cp8d4DtSZ2adz5UJji7JwBLiFZyEDYLHpkxAJ2sgSM3ZVt3lGeaKmTvWF0lDsk9tNx6A qBp3gYxn/uucFy+om8/TS0WqoZ9y7FjMlksKw9vwtLN00fwnhquWgaZLgzP8U41vyKlj /k3Q== X-Gm-Message-State: AOJu0YwwTLjE6Z6xm5zKoG8XKNWCcuUy+YepGjic1YOKHY6fp5tSDh1i gqOvDI79gumOivSA7yu6k4b7OSE+Q5jhlQ== X-Google-Smtp-Source: AGHT+IHHdsRRxy1IDfNse5GatBzPhuDVIrFMKJoWninIQCLj8CFwtHw/9Mq8ssT8qNlmZGyr53027A== X-Received: by 2002:a17:902:d2ca:b0:1cf:5629:a0c6 with SMTP id n10-20020a170902d2ca00b001cf5629a0c6mr1561205plc.13.1700631502818; Tue, 21 Nov 2023 21:38:22 -0800 (PST) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id u12-20020a170903124c00b001c0a4146961sm8923952plh.19.2023.11.21.21.38.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 21:38:22 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, =?utf-8?q?Cl=C3=A9ment_Chigot?= , Daniel Henrique Barboza , Alistair Francis Subject: [PULL 3/6] target/riscv: don't verify ISA compatibility for zicntr and zihpm Date: Wed, 22 Nov 2023 15:37:57 +1000 Message-ID: <20231122053800.1531799-4-alistair.francis@wdc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231122053800.1531799-1-alistair.francis@wdc.com> References: <20231122053800.1531799-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=alistair23@gmail.com; helo=mail-pl1-x630.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Clément Chigot The extensions zicntr and zihpm were officially added in the privilege instruction set specification 1.12. However, QEMU has been implemented them long before it and thus they are forced to be on during the cpu initialization to ensure compatibility (see riscv_cpu_init). riscv_cpu_disable_priv_spec_isa_exts was not updated when the above behavior was introduced, resulting in these extensions to be disabled after all. Signed-off-by: Clément Chigot Fixes: c004099330 ("target/riscv: add zicntr extension flag for TCG") Fixes: 0824121660 ("target/riscv: add zihpm extension flag for TCG") Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20231114123913.536194-1-chigot@adacore.com> Signed-off-by: Alistair Francis --- target/riscv/tcg/tcg-cpu.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 08adad304d..8a35683a34 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -250,6 +250,15 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) for (edata = isa_edata_arr; edata && edata->name; edata++) { if (isa_ext_is_enabled(cpu, edata->ext_enable_offset) && (env->priv_ver < edata->min_version)) { + /* + * These two extensions are always enabled as they were supported + * by QEMU before they were added as extensions in the ISA. + */ + if (!strcmp(edata->name, "zicntr") || + !strcmp(edata->name, "zihpm")) { + continue; + } + isa_ext_update_enabled(cpu, edata->ext_enable_offset, false); #ifndef CONFIG_USER_ONLY warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx From patchwork Wed Nov 22 05:37:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13463998 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C0A59C61D9A for ; Wed, 22 Nov 2023 05:39:21 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r5fwV-0002ex-Vq; Wed, 22 Nov 2023 00:38:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r5fwT-0002eW-Po for qemu-devel@nongnu.org; Wed, 22 Nov 2023 00:38:29 -0500 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r5fwS-0007A5-4W for qemu-devel@nongnu.org; Wed, 22 Nov 2023 00:38:29 -0500 Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-1cc0e78ec92so41715255ad.3 for ; Tue, 21 Nov 2023 21:38:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1700631506; x=1701236306; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lLbOAJzLWl9ZAwxrRE8Vm/IEKsPP3IN/EvETdsopNPM=; b=AzlYFhlN6rL7snbYvcyktuUHb+1KakSaICkcu6JKca7lc9oPQoB+PYCVafi4zgdbQ7 ZgxG+MZaBT1cWn2J2I3iufIhxB96NPolq3u5atGplvnodYl7LyoEPgT9OH7hPeNpSM/w DYWoFU4mSkaVpt2bPIJrOPbMkPikmvX3mDu7I1zCn+Y9vXn0vIjsjzYd78nPpi5qGp/h n9EdkxB2tWrYixY8ho2AdnpvM/cg4zDqvhp6WdBZMI8L6AtFRwBl+hKwghMbpGmqY//m OjZMHw4lGWgoY2KDi795oGMpDo9eki805wM4gcy0QnBkEnLrZfTzNL/Hboa7IouybUM9 mGhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700631506; x=1701236306; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lLbOAJzLWl9ZAwxrRE8Vm/IEKsPP3IN/EvETdsopNPM=; b=h0pJ/z1jCGkE3SvCc1xrTh+K8zHCxZumQM0yhfoJbyuJUDDj023iZGYW/3Gp22Kysb 64bzW9JluMJRN2T/AfZ5Mtr/VZnHPiPMPlu3Q9a+tM1TjZHobWrhmKRP12bocmwwTqVg zfxnzk5o7kBHWe4wtWSIFg7c+IxsqS3NOPsSjzf7lGJRyfEBT7xg+P5VGdb6zi+/O0tB v9KU2u1awlKFk1qxtiD7nJRAOgZl7AnhfoUAeZmBouOeN+1QgGj7npoK/r/o2cFf49Iw gYPLppo5YxGG6lJWQaQUkb61DT47S+UVWviJvS4TswrWm41oT0iADORrrE2mcK9Syozt 8Xvg== X-Gm-Message-State: AOJu0YxlSbSEdPu39GWechVuMrzbgcbMvV3W4rH2JVl1yFiAhTKq6JGk YwDFc9l7NaJyLarZkvYtm3GwSAERE0u9ig== X-Google-Smtp-Source: AGHT+IFnKbjPXvvOYxNGxrSSRvYkv990v8CTCH8ZBogx4CavNedlVP+zJZQMkgnDcyf8XS64y4C2yg== X-Received: by 2002:a17:903:32cb:b0:1c9:d0a0:ee88 with SMTP id i11-20020a17090332cb00b001c9d0a0ee88mr1413388plr.62.1700631506374; Tue, 21 Nov 2023 21:38:26 -0800 (PST) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id u12-20020a170903124c00b001c0a4146961sm8923952plh.19.2023.11.21.21.38.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 21:38:25 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, =?utf-8?q?Rom=C3=A1n_C=C3=A1rdenas?= , Alistair Francis , Daniel Henrique Barboza Subject: [PULL 4/6] riscv: Fix SiFive E CLINT clock frequency Date: Wed, 22 Nov 2023 15:37:58 +1000 Message-ID: <20231122053800.1531799-5-alistair.francis@wdc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231122053800.1531799-1-alistair.francis@wdc.com> References: <20231122053800.1531799-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=alistair23@gmail.com; helo=mail-pl1-x636.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Román Cárdenas If you check the manual of SiFive E310 (https://cdn.sparkfun.com/assets/7/f/0/2/7/fe310-g002-manual-v19p05.pdf), you can see in Figure 1 that the CLINT is connected to the real time clock, which also feeds the AON peripheral (they share the same clock). In page 43, the docs also say that the timer registers of the CLINT count ticks from the rtcclk. I am currently playing with bare metal applications both in QEMU and a physical SiFive E310 board and I confirm that the CLINT clock in the physical board runs at 32.768 kHz. In QEMU, the same app produces a completely different outcome, as sometimes a new CLINT interrupt is triggered before finishing other tasks. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1978 Signed-off-by: Rom\ufffd\ufffdn C\ufffd\ufffdrdenas Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Message-ID: <20231117082840.55705-1-rcardenas.rod@gmail.com> Signed-off-by: Alistair Francis --- hw/riscv/sifive_e.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 0d37adc542..87d9602383 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -225,7 +225,7 @@ static void sifive_e_soc_realize(DeviceState *dev, Error **errp) RISCV_ACLINT_SWI_SIZE, RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus, RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, - RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, false); + SIFIVE_E_LFCLK_DEFAULT_FREQ, false); sifive_e_prci_create(memmap[SIFIVE_E_DEV_PRCI].base); /* AON */ From patchwork Wed Nov 22 05:37:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13464000 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E0892C61D92 for ; Wed, 22 Nov 2023 05:39:34 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r5fwZ-0002fW-2N; Wed, 22 Nov 2023 00:38:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r5fwX-0002f8-DM for qemu-devel@nongnu.org; Wed, 22 Nov 2023 00:38:33 -0500 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r5fwV-0007AN-Rq for qemu-devel@nongnu.org; Wed, 22 Nov 2023 00:38:33 -0500 Received: by mail-pl1-x62c.google.com with SMTP id d9443c01a7336-1cc394f4cdfso47538345ad.0 for ; Tue, 21 Nov 2023 21:38:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1700631510; x=1701236310; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xiA82anXAb6GFv8v+4BJl2QNe9543bv58UGYFn8y2Jk=; b=Bciz533nJfIgOdaG8cXF9P4f8Ce/y9MoVyt26uHAqAh0LOz/TjLLSwRgGhqqWsauVy zTdRj1XxL4Je44qkw79KPmFiPeKLVHn+jv5lcZfW5dY526gIKWlXgMs/z4hDa7jPBLC5 kCDTPF4cXdwjhx9+DyjV18+CiF2dgUmBn65WarVYfrLpQMykPXK0pkq7ZK+mgIoQwwpC 2/ulEAZx/C9UyTjBscwP8Wx5JGouQEwoWRLiCUYzW/tbptmJfVAFN0eM8hHr4J5M1VLI pGfHwa3xELXlnMmDAWpowfAQiaP9Cqq6juQ+W9lOBI8jJbqsR+UjxHvuZyyD4D4iBY8I UDgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700631510; x=1701236310; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xiA82anXAb6GFv8v+4BJl2QNe9543bv58UGYFn8y2Jk=; b=OS8FOIMhmfyxOOu2i/XQiu1zvaK2MlKctdp2CpRKUgBf0vn3TS6iHT0hd0Nf1Uv8Fg qHwuevfijFIjmKg9QwXqAv74VlaRwTFa2RpNYlIvh8XN0dZCmKxPsaKoT9+SLlL1bDIF uaXtQ+S7geYJt70B2CCNRyrQzapQhwOLrW0kvVGhKGPfbMOZUYjXPjRTAcf6dJ2JKQaZ 6N/OjnBRUPt2eUrrBqBoTidpEZKb+N9dPAB9UHzVHhG7BlLx/Av88G9eScDqpG4o3Hi4 /qAN2E2vjuVRyC9WOkWiwwpr4AqTtACmpzj0EFBaCj7baqB40963T1LZyJpLO+ZjGTn4 0BXw== X-Gm-Message-State: AOJu0YxJgehBoMlXMXfw0MoAWZxqRyMSccAySioTx4C7OT3a0qrZ+VMn L7zDi9SaCnLWHrKLE2nOM/JEdQl+gNUdNg== X-Google-Smtp-Source: AGHT+IFk9skq27AH5cRDmyFKc+Ks94tA3ZOAN5bYWhBeu+U3nsDQEge4JCsNRiwMB/3aYtv6hwOv5w== X-Received: by 2002:a17:902:7002:b0:1cc:29ef:df81 with SMTP id y2-20020a170902700200b001cc29efdf81mr1134765plk.41.1700631510050; Tue, 21 Nov 2023 21:38:30 -0800 (PST) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id u12-20020a170903124c00b001c0a4146961sm8923952plh.19.2023.11.21.21.38.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 21:38:29 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Ivan Klokov , Alistair Francis , Daniel Henrique Barboza Subject: [PULL 5/6] target/riscv/cpu_helper.c: Invalid exception on MMU translation stage Date: Wed, 22 Nov 2023 15:37:59 +1000 Message-ID: <20231122053800.1531799-6-alistair.francis@wdc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231122053800.1531799-1-alistair.francis@wdc.com> References: <20231122053800.1531799-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62c.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Ivan Klokov According to RISCV privileged spec sect. 5.3.2 Virtual Address Translation Process access-fault exceptions may raise only after PMA/PMP check. Current implementation generates an access-fault for mbare mode even if there were no PMA/PMP errors. This patch removes the erroneous MMU mode check and generates an access-fault exception based on the pmp_violation flag only. Fixes: 1448689c7b ("target/riscv: Allow specifying MMU stage") Signed-off-by: Ivan Klokov Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Message-ID: <20231121071757.7178-2-ivan.klokov@syntacore.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 30 +++++++----------------------- 1 file changed, 7 insertions(+), 23 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index b7af69de53..9ff0952e46 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1143,47 +1143,31 @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address, bool two_stage_indirect) { CPUState *cs = env_cpu(env); - int page_fault_exceptions, vm; - uint64_t stap_mode; - - if (riscv_cpu_mxl(env) == MXL_RV32) { - stap_mode = SATP32_MODE; - } else { - stap_mode = SATP64_MODE; - } - - if (first_stage) { - vm = get_field(env->satp, stap_mode); - } else { - vm = get_field(env->hgatp, stap_mode); - } - - page_fault_exceptions = vm != VM_1_10_MBARE && !pmp_violation; switch (access_type) { case MMU_INST_FETCH: if (env->virt_enabled && !first_stage) { cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT; } else { - cs->exception_index = page_fault_exceptions ? - RISCV_EXCP_INST_PAGE_FAULT : RISCV_EXCP_INST_ACCESS_FAULT; + cs->exception_index = pmp_violation ? + RISCV_EXCP_INST_ACCESS_FAULT : RISCV_EXCP_INST_PAGE_FAULT; } break; case MMU_DATA_LOAD: if (two_stage && !first_stage) { cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT; } else { - cs->exception_index = page_fault_exceptions ? - RISCV_EXCP_LOAD_PAGE_FAULT : RISCV_EXCP_LOAD_ACCESS_FAULT; + cs->exception_index = pmp_violation ? + RISCV_EXCP_LOAD_ACCESS_FAULT : RISCV_EXCP_LOAD_PAGE_FAULT; } break; case MMU_DATA_STORE: if (two_stage && !first_stage) { cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT; } else { - cs->exception_index = page_fault_exceptions ? - RISCV_EXCP_STORE_PAGE_FAULT : - RISCV_EXCP_STORE_AMO_ACCESS_FAULT; + cs->exception_index = pmp_violation ? + RISCV_EXCP_STORE_AMO_ACCESS_FAULT : + RISCV_EXCP_STORE_PAGE_FAULT; } break; default: From patchwork Wed Nov 22 05:38:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 13463996 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 273A6C072A2 for ; Wed, 22 Nov 2023 05:39:21 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r5fwc-0002pN-L2; Wed, 22 Nov 2023 00:38:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r5fwb-0002iu-2X for qemu-devel@nongnu.org; Wed, 22 Nov 2023 00:38:37 -0500 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1r5fwZ-0007Ae-Bb for qemu-devel@nongnu.org; Wed, 22 Nov 2023 00:38:36 -0500 Received: by mail-pl1-x62e.google.com with SMTP id d9443c01a7336-1cc5fa0e4d5so53735245ad.0 for ; Tue, 21 Nov 2023 21:38:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1700631513; x=1701236313; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VfdNnE304ZcORy8+jKuKo1TUlW31ZX6mKgVvqcTL9E4=; b=WALXjzQ0Zf+zJLoJ0H5ZOlPFYGUZeEkC7YdcHAvWwu0aIyQN0zyeIgY3uPILke8ap7 XAGBLzAUzjU9ktKve6ZTjx3watp9QoJj5VVO1Yke0yPLV4V/gzA1Syth/lwxLZcSUNli oclHIwmd67u0BIHKjbPaRcoiPprucIZmeOnnJW3FnP7WXCkYq8cD/FECIUo4l45DhXb1 PVZytHiM7rE0UWxUjU2kTupLME1pq07vKQEnnX4i4oRFrRkCte03PGljKSI1BGAJCC7V nf+LE+uTJJeHbKbF5LclzW2treGr3fS/cd62IBd3olXc/qNoyFPPRdqZyb9J6hkNr0Si aF1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700631513; x=1701236313; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VfdNnE304ZcORy8+jKuKo1TUlW31ZX6mKgVvqcTL9E4=; b=G6hC79umBPQ+4oUF1+olLYDY73uS7U8XFvdkZpQYTLWQ/Q27vld+l2EVATXTLjFIlX Ucm43G3eDga6XTZm/eCTYk4TOT0y5hzDD+mjp/FqITo5a7T7fadA3WHnKS4MfFlrwR/V tSbv8fp4dUYkG+j91uPhl8yt0WsWAlHrwyGJg/XNSsLlcfNWxKAWMtZjMLlWen2RDwD5 UFR0P/Hp8vk5t4hOj1HNJ1ELBWbrMJ8gRbiczHq/pF6hJihg8VEY64beWkfzadKdBzIk cqPevmLrLcMALy8smDjAUDXpGaEpfbJYG0p7xTRfsucrCVSB7Sp4UT4oJ+ts0f0VXFME 3xPw== X-Gm-Message-State: AOJu0YyjQqRrstJo5xZjbf+i5uOB+64/QyEMdueOBLBuUlinCfuNNyRG uStQ4SkxIoZs9M0xM/fdszZxdNqUshSs3Q== X-Google-Smtp-Source: AGHT+IFlNip6xknP3Kv6zaxZtOJvecxWi7X2NxPfFrN0Z7C1N+m2qkvU4DjZ2SUDVaBN8sXDf1iDMw== X-Received: by 2002:a17:902:b784:b0:1cf:5670:243e with SMTP id e4-20020a170902b78400b001cf5670243emr1502648pls.13.1700631513602; Tue, 21 Nov 2023 21:38:33 -0800 (PST) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id u12-20020a170903124c00b001c0a4146961sm8923952plh.19.2023.11.21.21.38.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 21:38:32 -0800 (PST) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Ivan Klokov , Alistair Francis , Daniel Henrique Barboza Subject: [PULL 6/6] target/riscv/cpu_helper.c: Fix mxr bit behavior Date: Wed, 22 Nov 2023 15:38:00 +1000 Message-ID: <20231122053800.1531799-7-alistair.francis@wdc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231122053800.1531799-1-alistair.francis@wdc.com> References: <20231122053800.1531799-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Ivan Klokov According to RISCV Specification sect 9.5 on two stage translation when V=1 the vsstatus(mstatus in QEMU's terms) field MXR, which makes execute-only pages readable, only overrides VS-stage page protection. Setting MXR at HS-level(mstatus_hs), however, overrides both VS-stage and G-stage execute-only permissions. The hypervisor extension changes the behavior of MXR\MPV\MPRV bits. Due to RISCV Specification sect. 9.4.1 when MPRV=1, explicit memory accesses are translated and protected, and endianness is applied, as though the current virtualization mode were set to MPV and the current nominal privilege mode were set to MPP. vsstatus.MXR makes readable those pages marked executable at the VS translation stage. Fixes: 36a18664ba ("target/riscv: Implement second stage MMU") Signed-off-by: Ivan Klokov Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Message-ID: <20231121071757.7178-3-ivan.klokov@syntacore.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 9ff0952e46..e7e23b34f4 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1032,13 +1032,29 @@ restart: prot |= PAGE_WRITE; } if (pte & PTE_X) { - bool mxr; + bool mxr = false; - if (first_stage == true) { + /* + * Use mstatus for first stage or for the second stage without + * virt_enabled (MPRV+MPV) + */ + if (first_stage || !env->virt_enabled) { mxr = get_field(env->mstatus, MSTATUS_MXR); - } else { - mxr = get_field(env->vsstatus, MSTATUS_MXR); } + + /* MPRV+MPV case, check VSSTATUS */ + if (first_stage && two_stage && !env->virt_enabled) { + mxr |= get_field(env->vsstatus, MSTATUS_MXR); + } + + /* + * Setting MXR at HS-level overrides both VS-stage and G-stage + * execute-only permissions + */ + if (env->virt_enabled) { + mxr |= get_field(env->mstatus_hs, MSTATUS_MXR); + } + if (mxr) { prot |= PAGE_READ; }