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Fri, 24 Nov 2023 10:15:59 +0000 (GMT) Received: from smtpav03.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id E16D720077; Fri, 24 Nov 2023 10:15:57 +0000 (GMT) Received: from gfwr515.rchland.ibm.com (unknown [9.10.239.103]) by smtpav03.fra02v.mail.ibm.com (Postfix) with ESMTP; Fri, 24 Nov 2023 10:15:57 +0000 (GMT) From: Chalapathi V To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, fbarrat@linux.ibm.com, npiggin@gmail.com, clg@kaod.org, calebs@us.ibm.com, chalapathi.v@ibm.com, saif.abrar@linux.vnet.ibm.com Subject: [PATCH v5 1/3] hw/ppc: Add pnv pervasive common chiplet units Date: Fri, 24 Nov 2023 04:15:32 -0600 Message-Id: <20231124101534.19454-2-chalapathi.v@linux.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20231124101534.19454-1-chalapathi.v@linux.ibm.com> References: <20231124101534.19454-1-chalapathi.v@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: AU_k01m1oBqbjHR0g20JOnv8njlyGtPi X-Proofpoint-GUID: vSFkOCu_rwb6q-t2ncGDKyl-7PDhsM7X X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-23_15,2023-11-22_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 priorityscore=1501 mlxscore=0 lowpriorityscore=0 malwarescore=0 adultscore=0 spamscore=0 suspectscore=0 clxscore=1015 mlxlogscore=999 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311240080 Received-SPF: pass client-ip=148.163.156.1; envelope-from=chalapathi.v@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This part of the patchset creates a common pervasive chiplet model where it houses the common units of a chiplets. The chiplet control unit is common across chiplets and this commit implements the pervasive chiplet model with chiplet control registers. Signed-off-by: Chalapathi V --- include/hw/ppc/pnv_pervasive.h | 37 ++++++ include/hw/ppc/pnv_xscom.h | 3 + hw/ppc/pnv_pervasive.c | 217 +++++++++++++++++++++++++++++++++ hw/ppc/meson.build | 1 + 4 files changed, 258 insertions(+) create mode 100644 include/hw/ppc/pnv_pervasive.h create mode 100644 hw/ppc/pnv_pervasive.c diff --git a/include/hw/ppc/pnv_pervasive.h b/include/hw/ppc/pnv_pervasive.h new file mode 100644 index 0000000000..d83f86df7b --- /dev/null +++ b/include/hw/ppc/pnv_pervasive.h @@ -0,0 +1,37 @@ +/* + * QEMU PowerPC pervasive common chiplet model + * + * Copyright (c) 2023, IBM Corporation. + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * This code is licensed under the GPL version 2 or later. See the + * COPYING file in the top-level directory. + */ + +#ifndef PPC_PNV_PERVASIVE_H +#define PPC_PNV_PERVASIVE_H + +#define TYPE_PNV_PERV "pnv-pervasive-chiplet" +#define PNV_PERV(obj) OBJECT_CHECK(PnvPerv, (obj), TYPE_PNV_PERV) + +typedef struct PnvPervCtrlRegs { +#define CPLT_CTRL_SIZE 6 + uint64_t cplt_ctrl[CPLT_CTRL_SIZE]; + uint64_t cplt_cfg0; + uint64_t cplt_cfg1; + uint64_t cplt_stat0; + uint64_t cplt_mask0; + uint64_t ctrl_protect_mode; + uint64_t ctrl_atomic_lock; +} PnvPervCtrlRegs; + +typedef struct PnvPerv { + DeviceState parent; + char *parent_obj_name; + MemoryRegion xscom_perv_ctrl_regs; + PnvPervCtrlRegs control_regs; +} PnvPerv; + +void pnv_perv_dt(PnvPerv *perv, uint32_t base_addr, void *fdt, int offset); +#endif /*PPC_PNV_PERVASIVE_H */ diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h index f5becbab41..d09d10f32b 100644 --- a/include/hw/ppc/pnv_xscom.h +++ b/include/hw/ppc/pnv_xscom.h @@ -170,6 +170,9 @@ struct PnvXScomInterfaceClass { #define PNV10_XSCOM_XIVE2_BASE 0x2010800 #define PNV10_XSCOM_XIVE2_SIZE 0x400 +#define PNV10_XSCOM_NEST1_CTRL_CHIPLET_BASE 0x3000000 +#define PNV10_XSCOM_CTRL_CHIPLET_SIZE 0x400 + #define PNV10_XSCOM_PEC_NEST_BASE 0x3011800 /* index goes downwards ... */ #define PNV10_XSCOM_PEC_NEST_SIZE 0x100 diff --git a/hw/ppc/pnv_pervasive.c b/hw/ppc/pnv_pervasive.c new file mode 100644 index 0000000000..c925070798 --- /dev/null +++ b/hw/ppc/pnv_pervasive.c @@ -0,0 +1,217 @@ +/* + * QEMU PowerPC pervasive common chiplet model + * + * Copyright (c) 2023, IBM Corporation. + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * This code is licensed under the GPL version 2 or later. See the + * COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "hw/qdev-properties.h" +#include "hw/ppc/pnv.h" +#include "hw/ppc/pnv_xscom.h" +#include "hw/ppc/pnv_pervasive.h" +#include "hw/ppc/fdt.h" +#include + +#define CPLT_CONF0 0x08 +#define CPLT_CONF0_OR 0x18 +#define CPLT_CONF0_CLEAR 0x28 +#define CPLT_CONF1 0x09 +#define CPLT_CONF1_OR 0x19 +#define CPLT_CONF1_CLEAR 0x29 +#define CPLT_STAT0 0x100 +#define CPLT_MASK0 0x101 +#define CPLT_PROTECT_MODE 0x3FE +#define CPLT_ATOMIC_CLOCK 0x3FF + +static uint64_t pnv_chiplet_ctrl_read(void *opaque, hwaddr addr, unsigned size) +{ + PnvPerv *perv = PNV_PERV(opaque); + int reg = addr >> 3; + uint64_t val = ~0ull; + + /* CPLT_CTRL0 to CPLT_CTRL5 */ + for (int i = 0; i < CPLT_CTRL_SIZE; i++) { + if (reg == i) { + return perv->control_regs.cplt_ctrl[i]; + } else if ((reg == (i + 0x10)) || (reg == (i + 0x20))) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Write only register, ignoring " + "xscom read at 0x%" PRIx64 "\n", + __func__, (unsigned long)reg); + return val; + } + } + + switch (reg) { + case CPLT_CONF0: + val = perv->control_regs.cplt_cfg0; + break; + case CPLT_CONF0_OR: + case CPLT_CONF0_CLEAR: + qemu_log_mask(LOG_GUEST_ERROR, "%s: Write only register, ignoring " + "xscom read at 0x%" PRIx64 "\n", + __func__, (unsigned long)reg); + break; + case CPLT_CONF1: + val = perv->control_regs.cplt_cfg1; + break; + case CPLT_CONF1_OR: + case CPLT_CONF1_CLEAR: + qemu_log_mask(LOG_GUEST_ERROR, "%s: Write only register, ignoring " + "xscom read at 0x%" PRIx64 "\n", + __func__, (unsigned long)reg); + break; + case CPLT_STAT0: + val = perv->control_regs.cplt_stat0; + break; + case CPLT_MASK0: + val = perv->control_regs.cplt_mask0; + break; + case CPLT_PROTECT_MODE: + val = perv->control_regs.ctrl_protect_mode; + break; + case CPLT_ATOMIC_CLOCK: + val = perv->control_regs.ctrl_atomic_lock; + break; + default: + qemu_log_mask(LOG_UNIMP, "%s: Chiplet_control_regs: Invalid xscom " + "read at 0x%" PRIx64 "\n", __func__, (unsigned long)reg); + } + return val; +} + +static void pnv_chiplet_ctrl_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) +{ + PnvPerv *perv = PNV_PERV(opaque); + int reg = addr >> 3; + + /* CPLT_CTRL0 to CPLT_CTRL5 */ + for (int i = 0; i < CPLT_CTRL_SIZE; i++) { + if (reg == i) { + perv->control_regs.cplt_ctrl[i] = val; + return; + } else if (reg == (i + 0x10)) { + perv->control_regs.cplt_ctrl[i] |= val; + return; + } else if (reg == (i + 0x20)) { + perv->control_regs.cplt_ctrl[i] &= ~val; + return; + } + } + + switch (reg) { + case CPLT_CONF0: + perv->control_regs.cplt_cfg0 = val; + break; + case CPLT_CONF0_OR: + perv->control_regs.cplt_cfg0 |= val; + break; + case CPLT_CONF0_CLEAR: + perv->control_regs.cplt_cfg0 &= ~val; + break; + case CPLT_CONF1: + perv->control_regs.cplt_cfg1 = val; + break; + case CPLT_CONF1_OR: + perv->control_regs.cplt_cfg1 |= val; + break; + case CPLT_CONF1_CLEAR: + perv->control_regs.cplt_cfg1 &= ~val; + break; + case CPLT_STAT0: + perv->control_regs.cplt_stat0 = val; + break; + case CPLT_MASK0: + perv->control_regs.cplt_mask0 = val; + break; + case CPLT_PROTECT_MODE: + perv->control_regs.ctrl_protect_mode = val; + break; + case CPLT_ATOMIC_CLOCK: + perv->control_regs.ctrl_atomic_lock = val; + break; + default: + qemu_log_mask(LOG_UNIMP, "%s: Chiplet_control_regs: Invalid xscom " + "write at 0x%" PRIx64 "\n", + __func__, (unsigned long)reg); + } +} + +static const MemoryRegionOps pnv_perv_control_xscom_ops = { + .read = pnv_chiplet_ctrl_read, + .write = pnv_chiplet_ctrl_write, + .valid.min_access_size = 8, + .valid.max_access_size = 8, + .impl.min_access_size = 8, + .impl.max_access_size = 8, + .endianness = DEVICE_BIG_ENDIAN, +}; + +static void pnv_perv_realize(DeviceState *dev, Error **errp) +{ + PnvPerv *perv = PNV_PERV(dev); + g_autofree char *region_name = NULL; + region_name = g_strdup_printf("xscom-%s-control-regs", + perv->parent_obj_name); + + /* Chiplet control scoms */ + pnv_xscom_region_init(&perv->xscom_perv_ctrl_regs, OBJECT(perv), + &pnv_perv_control_xscom_ops, perv, region_name, + PNV10_XSCOM_CTRL_CHIPLET_SIZE); +} + +void pnv_perv_dt(PnvPerv *perv, uint32_t base_addr, void *fdt, int offset) +{ + g_autofree char *name = NULL; + int perv_offset; + const char compat[] = "ibm,power10-perv-chiplet"; + uint32_t reg[] = { + cpu_to_be32(base_addr), + cpu_to_be32(PNV10_XSCOM_CTRL_CHIPLET_SIZE) + }; + + name = g_strdup_printf("%s-perv@%x", perv->parent_obj_name, base_addr); + perv_offset = fdt_add_subnode(fdt, offset, name); + _FDT(perv_offset); + + _FDT(fdt_setprop(fdt, perv_offset, "reg", reg, sizeof(reg))); + _FDT(fdt_setprop(fdt, perv_offset, "compatible", compat, sizeof(compat))); +} + +static Property pnv_perv_properties[] = { + DEFINE_PROP_STRING("parent-obj-name", PnvPerv, parent_obj_name), + DEFINE_PROP_END_OF_LIST(), +}; + +static void pnv_perv_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->desc = "PowerNV perv chiplet"; + dc->realize = pnv_perv_realize; + device_class_set_props(dc, pnv_perv_properties); +} + +static const TypeInfo pnv_perv_info = { + .name = TYPE_PNV_PERV, + .parent = TYPE_DEVICE, + .instance_size = sizeof(PnvPerv), + .class_init = pnv_perv_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_PNV_XSCOM_INTERFACE }, + { } + } +}; + +static void pnv_perv_register_types(void) +{ + type_register_static(&pnv_perv_info); +} + +type_init(pnv_perv_register_types); diff --git a/hw/ppc/meson.build b/hw/ppc/meson.build index ea44856d43..37a7a8935d 100644 --- a/hw/ppc/meson.build +++ b/hw/ppc/meson.build @@ -51,6 +51,7 @@ ppc_ss.add(when: 'CONFIG_POWERNV', if_true: files( 'pnv_bmc.c', 'pnv_homer.c', 'pnv_pnor.c', + 'pnv_pervasive.c', )) # PowerPC 4xx boards ppc_ss.add(when: 'CONFIG_PPC405', if_true: files( From patchwork Fri Nov 24 10:15:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chalapathi V X-Patchwork-Id: 13467426 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4C5C9C636D0 for ; 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envelope-from=chalapathi.v@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The nest1 chiplet handle the high speed i/o traffic over PCIe and others. The nest1 chiplet consists of PowerBus Fabric controller, nest Memory Management Unit, chiplet control unit and more. This commit creates a nest1 chiplet model and initialize and realize the pervasive chiplet model where chiplet control registers are implemented. This commit also implement the read/write method for the powerbus scom registers Signed-off-by: Chalapathi V --- include/hw/ppc/pnv_nest_chiplet.h | 36 ++++++ include/hw/ppc/pnv_xscom.h | 6 + hw/ppc/pnv_nest1_chiplet.c | 197 ++++++++++++++++++++++++++++++ hw/ppc/meson.build | 1 + 4 files changed, 240 insertions(+) create mode 100644 include/hw/ppc/pnv_nest_chiplet.h create mode 100644 hw/ppc/pnv_nest1_chiplet.c diff --git a/include/hw/ppc/pnv_nest_chiplet.h b/include/hw/ppc/pnv_nest_chiplet.h new file mode 100644 index 0000000000..845030fb1a --- /dev/null +++ b/include/hw/ppc/pnv_nest_chiplet.h @@ -0,0 +1,36 @@ +/* + * QEMU PowerPC nest chiplet model + * + * Copyright (c) 2023, IBM Corporation. + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * This code is licensed under the GPL version 2 or later. See the + * COPYING file in the top-level directory. + * + */ + +#ifndef PPC_PNV_NEST1_CHIPLET_H +#define PPC_PNV_NEST1_CHIPLET_H + +#include "hw/ppc/pnv_pervasive.h" + +#define TYPE_PNV_NEST1 "pnv-nest1-chiplet" +#define PNV_NEST1(obj) OBJECT_CHECK(PnvNest1, (obj), TYPE_PNV_NEST1) + +typedef struct pb_scom { + uint64_t mode; + uint64_t hp_mode2_curr; +} pb_scom; + +typedef struct PnvNest1 { + DeviceState parent; + MemoryRegion xscom_pb_eq_regs; + MemoryRegion xscom_pb_es_regs; + /* common pervasive chiplet unit */ + PnvPerv perv; + /* powerbus racetrack registers */ + pb_scom eq[8]; + pb_scom es[4]; +} PnvNest1; +#endif /*PPC_PNV_NEST1 */ diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h index d09d10f32b..df68a1c20e 100644 --- a/include/hw/ppc/pnv_xscom.h +++ b/include/hw/ppc/pnv_xscom.h @@ -173,6 +173,12 @@ struct PnvXScomInterfaceClass { #define PNV10_XSCOM_NEST1_CTRL_CHIPLET_BASE 0x3000000 #define PNV10_XSCOM_CTRL_CHIPLET_SIZE 0x400 +#define PNV10_XSCOM_NEST1_PB_SCOM_EQ_BASE 0x3011000 +#define PNV10_XSCOM_NEST1_PB_SCOM_EQ_SIZE 0x200 + +#define PNV10_XSCOM_NEST1_PB_SCOM_ES_BASE 0x3011300 +#define PNV10_XSCOM_NEST1_PB_SCOM_ES_SIZE 0x100 + #define PNV10_XSCOM_PEC_NEST_BASE 0x3011800 /* index goes downwards ... */ #define PNV10_XSCOM_PEC_NEST_SIZE 0x100 diff --git a/hw/ppc/pnv_nest1_chiplet.c b/hw/ppc/pnv_nest1_chiplet.c new file mode 100644 index 0000000000..609d5f1be4 --- /dev/null +++ b/hw/ppc/pnv_nest1_chiplet.c @@ -0,0 +1,197 @@ +/* + * QEMU PowerPC nest1 chiplet model + * + * Copyright (c) 2023, IBM Corporation. + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * This code is licensed under the GPL version 2 or later. See the + * COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "hw/qdev-properties.h" +#include "hw/ppc/pnv.h" +#include "hw/ppc/pnv_xscom.h" +#include "hw/ppc/pnv_nest_chiplet.h" +#include "hw/ppc/pnv_pervasive.h" +#include "hw/ppc/fdt.h" +#include + +/* + * The nest1 chiplet contains chiplet control unit, + * PowerBus/RaceTrack/Bridge logic, nest Memory Management Unit(nMMU) + * and more. + */ + +#define PB_SCOM_EQ0_HP_MODE2_CURR 0xe +#define PB_SCOM_ES3_MODE 0x8a + +static uint64_t pnv_nest1_pb_scom_eq_read(void *opaque, hwaddr addr, + unsigned size) +{ + PnvNest1 *nest1 = PNV_NEST1(opaque); + int reg = addr >> 3; + uint64_t val = ~0ull; + + switch (reg) { + case PB_SCOM_EQ0_HP_MODE2_CURR: + val = nest1->eq[0].hp_mode2_curr; + break; + default: + qemu_log_mask(LOG_UNIMP, "%s: Invalid xscom read at 0x%" PRIx32 "\n", + __func__, reg); + } + return val; +} + +static void pnv_nest1_pb_scom_eq_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) +{ + PnvNest1 *nest1 = PNV_NEST1(opaque); + int reg = addr >> 3; + + switch (reg) { + case PB_SCOM_EQ0_HP_MODE2_CURR: + nest1->eq[0].hp_mode2_curr = val; + break; + default: + qemu_log_mask(LOG_UNIMP, "%s: Invalid xscom write at 0x%" PRIx32 "\n", + __func__, reg); + } +} + +static const MemoryRegionOps pnv_nest1_pb_scom_eq_ops = { + .read = pnv_nest1_pb_scom_eq_read, + .write = pnv_nest1_pb_scom_eq_write, + .valid.min_access_size = 8, + .valid.max_access_size = 8, + .impl.min_access_size = 8, + .impl.max_access_size = 8, + .endianness = DEVICE_BIG_ENDIAN, +}; + +static uint64_t pnv_nest1_pb_scom_es_read(void *opaque, hwaddr addr, + unsigned size) +{ + PnvNest1 *nest1 = PNV_NEST1(opaque); + int reg = addr >> 3; + uint64_t val = ~0ull; + + switch (reg) { + case PB_SCOM_ES3_MODE: + val = nest1->es[3].mode; + break; + default: + qemu_log_mask(LOG_UNIMP, "%s: Invalid xscom read at 0x%" PRIx32 "\n", + __func__, reg); + } + return val; +} + +static void pnv_nest1_pb_scom_es_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) +{ + PnvNest1 *nest1 = PNV_NEST1(opaque); + int reg = addr >> 3; + + switch (reg) { + case PB_SCOM_ES3_MODE: + nest1->es[3].mode = val; + break; + default: + qemu_log_mask(LOG_UNIMP, "%s: Invalid xscom write at 0x%" PRIx32 "\n", + __func__, reg); + } +} + +static const MemoryRegionOps pnv_nest1_pb_scom_es_ops = { + .read = pnv_nest1_pb_scom_es_read, + .write = pnv_nest1_pb_scom_es_write, + .valid.min_access_size = 8, + .valid.max_access_size = 8, + .impl.min_access_size = 8, + .impl.max_access_size = 8, + .endianness = DEVICE_BIG_ENDIAN, +}; + +static void pnv_nest1_realize(DeviceState *dev, Error **errp) +{ + PnvNest1 *nest1 = PNV_NEST1(dev); + + /* perv chiplet initialize and realize */ + object_initialize_child(OBJECT(nest1), "perv", &nest1->perv, TYPE_PNV_PERV); + object_property_set_str(OBJECT(&nest1->perv), "parent-obj-name", "nest1", + errp); + if (!qdev_realize(DEVICE(&nest1->perv), NULL, errp)) { + return; + } + + /* Nest1 chiplet power bus EQ xscom region */ + pnv_xscom_region_init(&nest1->xscom_pb_eq_regs, OBJECT(nest1), + &pnv_nest1_pb_scom_eq_ops, nest1, + "xscom-nest1-pb-scom-eq-regs", + PNV10_XSCOM_NEST1_PB_SCOM_EQ_SIZE); + + /* Nest1 chiplet power bus ES xscom region */ + pnv_xscom_region_init(&nest1->xscom_pb_es_regs, OBJECT(nest1), + &pnv_nest1_pb_scom_es_ops, nest1, + "xscom-nest1-pb-scom-es-regs", + PNV10_XSCOM_NEST1_PB_SCOM_ES_SIZE); +} + +static int pnv_nest1_dt_xscom(PnvXScomInterface *dev, void *fdt, + int offset) +{ + PnvNest1 *nest1 = PNV_NEST1(dev); + g_autofree char *name = NULL; + int nest1_offset = 0; + const char compat[] = "ibm,power10-nest1-chiplet"; + uint32_t reg[] = { + cpu_to_be32(PNV10_XSCOM_NEST1_PB_SCOM_EQ_BASE), + cpu_to_be32(PNV10_XSCOM_NEST1_PB_SCOM_EQ_SIZE), + cpu_to_be32(PNV10_XSCOM_NEST1_PB_SCOM_ES_BASE), + cpu_to_be32(PNV10_XSCOM_NEST1_PB_SCOM_ES_SIZE) + }; + + /* populate perv_chiplet control_regs */ + pnv_perv_dt(&nest1->perv, PNV10_XSCOM_NEST1_CTRL_CHIPLET_BASE, fdt, offset); + + name = g_strdup_printf("nest1@%x", PNV10_XSCOM_NEST1_PB_SCOM_EQ_BASE); + nest1_offset = fdt_add_subnode(fdt, offset, name); + _FDT(nest1_offset); + + _FDT(fdt_setprop(fdt, nest1_offset, "reg", reg, sizeof(reg))); + _FDT(fdt_setprop(fdt, nest1_offset, "compatible", compat, sizeof(compat))); + return 0; +} + +static void pnv_nest1_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + PnvXScomInterfaceClass *xscomc = PNV_XSCOM_INTERFACE_CLASS(klass); + + xscomc->dt_xscom = pnv_nest1_dt_xscom; + + dc->desc = "PowerNV nest1 chiplet"; + dc->realize = pnv_nest1_realize; +} + +static const TypeInfo pnv_nest1_info = { + .name = TYPE_PNV_NEST1, + .parent = TYPE_DEVICE, + .instance_size = sizeof(PnvNest1), + .class_init = pnv_nest1_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_PNV_XSCOM_INTERFACE }, + { } + } +}; + +static void pnv_nest1_register_types(void) +{ + type_register_static(&pnv_nest1_info); +} + +type_init(pnv_nest1_register_types); diff --git a/hw/ppc/meson.build b/hw/ppc/meson.build index 37a7a8935d..7b8b87596a 100644 --- a/hw/ppc/meson.build +++ b/hw/ppc/meson.build @@ -52,6 +52,7 @@ ppc_ss.add(when: 'CONFIG_POWERNV', if_true: files( 'pnv_homer.c', 'pnv_pnor.c', 'pnv_pervasive.c', + 'pnv_nest1_chiplet.c', )) # PowerPC 4xx boards ppc_ss.add(when: 'CONFIG_PPC405', if_true: files( From patchwork Fri Nov 24 10:15:34 2023 Content-Type: text/plain; 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Fri, 24 Nov 2023 10:16:12 +0000 (GMT) Received: from smtpav03.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 73ED620085; Fri, 24 Nov 2023 10:16:10 +0000 (GMT) Received: from gfwr515.rchland.ibm.com (unknown [9.10.239.103]) by smtpav03.fra02v.mail.ibm.com (Postfix) with ESMTP; Fri, 24 Nov 2023 10:16:10 +0000 (GMT) From: Chalapathi V To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, fbarrat@linux.ibm.com, npiggin@gmail.com, clg@kaod.org, calebs@us.ibm.com, chalapathi.v@ibm.com, saif.abrar@linux.vnet.ibm.com Subject: [PATCH v5 3/3] hw/ppc: Nest1 chiplet wiring Date: Fri, 24 Nov 2023 04:15:34 -0600 Message-Id: <20231124101534.19454-4-chalapathi.v@linux.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20231124101534.19454-1-chalapathi.v@linux.ibm.com> References: <20231124101534.19454-1-chalapathi.v@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: IoLG4g4jF2OIslMbfLr0vYXCvSGIPaSX X-Proofpoint-ORIG-GUID: xFEvblKV5zC68vau-mCtb1ta5JlPvPXG X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-23_15,2023-11-22_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 suspectscore=0 clxscore=1015 lowpriorityscore=0 phishscore=0 mlxscore=0 malwarescore=0 priorityscore=1501 spamscore=0 mlxlogscore=744 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311240080 Received-SPF: pass client-ip=148.163.158.5; envelope-from=chalapathi.v@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This part of the patchset connects the nest1 chiplet model to p10 chip. Signed-off-by: Chalapathi V --- include/hw/ppc/pnv_chip.h | 2 ++ hw/ppc/pnv.c | 14 ++++++++++++++ 2 files changed, 16 insertions(+) diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h index 0ab5c42308..59a3158a6b 100644 --- a/include/hw/ppc/pnv_chip.h +++ b/include/hw/ppc/pnv_chip.h @@ -4,6 +4,7 @@ #include "hw/pci-host/pnv_phb4.h" #include "hw/ppc/pnv_core.h" #include "hw/ppc/pnv_homer.h" +#include "hw/ppc/pnv_nest_chiplet.h" #include "hw/ppc/pnv_lpc.h" #include "hw/ppc/pnv_occ.h" #include "hw/ppc/pnv_psi.h" @@ -113,6 +114,7 @@ struct Pnv10Chip { PnvOCC occ; PnvSBE sbe; PnvHomer homer; + PnvNest1 nest1; uint32_t nr_quads; PnvQuad *quads; diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 0297871bdd..ba3dfab557 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1680,6 +1680,7 @@ static void pnv_chip_power10_instance_init(Object *obj) object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC); object_initialize_child(obj, "sbe", &chip10->sbe, TYPE_PNV10_SBE); object_initialize_child(obj, "homer", &chip10->homer, TYPE_PNV10_HOMER); + object_initialize_child(obj, "nest1", &chip10->nest1, TYPE_PNV_NEST1); chip->num_pecs = pcc->num_pecs; @@ -1849,6 +1850,19 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) memory_region_add_subregion(get_system_memory(), PNV10_HOMER_BASE(chip), &chip10->homer.regs); + /* nest1 chiplet */ + if (!qdev_realize(DEVICE(&chip10->nest1), NULL, errp)) { + return; + } + pnv_xscom_add_subregion(chip, PNV10_XSCOM_NEST1_CTRL_CHIPLET_BASE, + &chip10->nest1.perv.xscom_perv_ctrl_regs); + + pnv_xscom_add_subregion(chip, PNV10_XSCOM_NEST1_PB_SCOM_EQ_BASE, + &chip10->nest1.xscom_pb_eq_regs); + + pnv_xscom_add_subregion(chip, PNV10_XSCOM_NEST1_PB_SCOM_ES_BASE, + &chip10->nest1.xscom_pb_es_regs); + /* PHBs */ pnv_chip_power10_phb_realize(chip, &local_err); if (local_err) {