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([94.75.70.14]) by smtp.gmail.com with ESMTPSA id g1-20020a170906348100b009de3641d538sm1882374ejb.134.2023.11.24.02.31.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Nov 2023 02:31:09 -0800 (PST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 96425539-8ab4-11ee-98e2-6d05b1d4d9a1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1700821870; x=1701426670; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1GGwlFyEsHHh1M1lPvOTRu5vN91zCPhYcW+euIgRdPc=; b=X5i72WBEYjUCXLJdyg4b5evGkpIGgvze2DlaOwe2uuvggqyxzsJUrIWUy/gTShmnCy dahcnzLuTfpfe21StosdgP0/6Y88QUOeNjT4jxVMmLB5NVo5NtF2oDaclSzDcXxIuncA Sc9sFNSS9xkyi84MidGhpHDPH9J0rmfZ2s9lNy0AHZsps93rFuQmAppNCdOlwXe1zDPE pDUosdkYcjACgQ36LivdC0dHONM1I+NQqYiScRJG1HyY2OCdRoHwyPL0pwc5RrsrJeYX zKqkcphyoIIxcXTZMEbXcnmrPBw3ePMCSNSOVVyjG9yuK/kWOPNYtPQz/3iN3SAuabJ2 j9FA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700821870; x=1701426670; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1GGwlFyEsHHh1M1lPvOTRu5vN91zCPhYcW+euIgRdPc=; b=kpn9cdTZWrIGSntEEwdRfN/1v9L9jemKQO8NCGD8J0XQGFR/PaYVQUdjPUEi1N4cxi tM/LYGqkZ7VJVQEaMVNg8CkPy1iTD6sTW+WcKLx6o25TvVq7rfP3epntI5M3Ikaz/O2n vaZU22OxUuSviPVJRJYZ/nujMXuF7Z+h22iE34reQ8fIvjX0Q1IF7bANyq9v8wjksGZt 4ZROmkZ9IcDg14nPokJBK/2843ZN4O0oT5rE993kHpZwpfBU4LFBiZJBTwvDoGdKoUjq qlR0cU7kFlTCvuKOW7GLvz7NTLbUnMtnlvMXpbmDvxFY/SZNjEB0X2+0gHmF3BCwaK5G jX9Q== X-Gm-Message-State: AOJu0Yxuk3AXxmz80SS4KYfhEOvshAIdTNmLhgWK8qcvPXIosYKvRZ+c /CNxCtKSYlPbdMYm1iCT71ThR53ugwCypg== X-Google-Smtp-Source: AGHT+IHqamxg5VKsBkqvKfJkp7qnvgFjJX41hjLUmZ8Pwg26bv7aLJ1u1lvg+/wFj2QE/guXdEO1KQ== X-Received: by 2002:a17:907:920f:b0:a02:b9c2:87bb with SMTP id ka15-20020a170907920f00b00a02b9c287bbmr1842790ejb.15.1700821870039; Fri, 24 Nov 2023 02:31:10 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Doug Goldstein , Stefano Stabellini , Alistair Francis , Bob Eshleman , Connor Davis Subject: [PATCH v2 01/39] xen/riscv: disable unnecessary configs Date: Fri, 24 Nov 2023 12:30:21 +0200 Message-ID: X-Mailer: git-send-email 2.42.0 In-Reply-To: References: MIME-Version: 1.0 The patch also fixes the build script as conf util expects to have each config on separate line. Signed-off-by: Oleksii Kurochko --- Changes in V2: - update the commit message. - remove xen/arch/riscv/Kconfig changes. --- automation/gitlab-ci/build.yaml | 122 ++++++++++++++++++++++++ automation/scripts/build | 4 +- xen/arch/riscv/configs/tiny64_defconfig | 18 ++++ 3 files changed, 142 insertions(+), 2 deletions(-) diff --git a/automation/gitlab-ci/build.yaml b/automation/gitlab-ci/build.yaml index 32af30cced..f4ef81839a 100644 --- a/automation/gitlab-ci/build.yaml +++ b/automation/gitlab-ci/build.yaml @@ -522,6 +522,38 @@ archlinux-current-gcc-riscv64: CONTAINER: archlinux:current-riscv64 KBUILD_DEFCONFIG: tiny64_defconfig HYPERVISOR_ONLY: y + EXTRA_XEN_CONFIG: + CONFIG_COVERAGE=n + CONFIG_GRANT_TABLE=n + CONFIG_SCHED_CREDIT=n + CONFIG_SCHED_CREDIT2=n + CONFIG_SCHED_RTDS=n + CONFIG_SCHED_NULL=n + CONFIG_SCHED_ARINC653=n + CONFIG_TRACEBUFFER=n + CONFIG_HYPFS=n + CONFIG_GRANT_TABLE=n + CONFIG_SPECULATIVE_HARDEN_ARRAY=n + CONFIG_ARGO=n + CONFIG_HYPFS_CONFIG=n + CONFIG_CORE_PARKING=n + CONFIG_DEBUG_TRACE=n + CONFIG_IOREQ_SERVER=n + CONFIG_CRASH_DEBUG=n + CONFIG_KEXEC=n + CONFIG_LIVEPATCH=n + CONFIG_MEM_ACCESS=n + CONFIG_NUMA=n + CONFIG_PERF_COUNTERS=n + CONFIG_HAS_PMAP=n + CONFIG_TRACEBUFFER=n + CONFIG_XENOPROF=n + CONFIG_COMPAT=n + CONFIG_COVERAGE=n + CONFIG_UBSAN=n + CONFIG_NEEDS_LIBELF=n + CONFIG_XSM=n + archlinux-current-gcc-riscv64-debug: extends: .gcc-riscv64-cross-build-debug @@ -529,6 +561,38 @@ archlinux-current-gcc-riscv64-debug: CONTAINER: archlinux:current-riscv64 KBUILD_DEFCONFIG: tiny64_defconfig HYPERVISOR_ONLY: y + EXTRA_XEN_CONFIG: + CONFIG_COVERAGE=n + CONFIG_GRANT_TABLE=n + CONFIG_SCHED_CREDIT=n + CONFIG_SCHED_CREDIT2=n + CONFIG_SCHED_RTDS=n + CONFIG_SCHED_NULL=n + CONFIG_SCHED_ARINC653=n + CONFIG_TRACEBUFFER=n + CONFIG_HYPFS=n + CONFIG_GRANT_TABLE=n + CONFIG_SPECULATIVE_HARDEN_ARRAY=n + CONFIG_ARGO=n + CONFIG_HYPFS_CONFIG=n + CONFIG_CORE_PARKING=n + CONFIG_DEBUG_TRACE=n + CONFIG_IOREQ_SERVER=n + CONFIG_CRASH_DEBUG=n + CONFIG_KEXEC=n + CONFIG_LIVEPATCH=n + CONFIG_MEM_ACCESS=n + CONFIG_NUMA=n + CONFIG_PERF_COUNTERS=n + CONFIG_HAS_PMAP=n + CONFIG_TRACEBUFFER=n + CONFIG_XENOPROF=n + CONFIG_COMPAT=n + CONFIG_COVERAGE=n + CONFIG_UBSAN=n + CONFIG_NEEDS_LIBELF=n + CONFIG_XSM=n + archlinux-current-gcc-riscv64-randconfig: extends: .gcc-riscv64-cross-build @@ -538,6 +602,35 @@ archlinux-current-gcc-riscv64-randconfig: RANDCONFIG: y EXTRA_FIXED_RANDCONFIG: CONFIG_COVERAGE=n + CONFIG_GRANT_TABLE=n + CONFIG_SCHED_CREDIT=n + CONFIG_SCHED_CREDIT2=n + CONFIG_SCHED_RTDS=n + CONFIG_SCHED_NULL=n + CONFIG_SCHED_ARINC653=n + CONFIG_TRACEBUFFER=n + CONFIG_HYPFS=n + CONFIG_GRANT_TABLE=n + CONFIG_SPECULATIVE_HARDEN_ARRAY=n + CONFIG_ARGO=n + CONFIG_HYPFS_CONFIG=n + CONFIG_CORE_PARKING=n + CONFIG_DEBUG_TRACE=n + CONFIG_IOREQ_SERVER=n + CONFIG_CRASH_DEBUG=n + CONFIG_KEXEC=n + CONFIG_LIVEPATCH=n + CONFIG_MEM_ACCESS=n + CONFIG_NUMA=n + CONFIG_PERF_COUNTERS=n + CONFIG_HAS_PMAP=n + CONFIG_TRACEBUFFER=n + CONFIG_XENOPROF=n + CONFIG_COMPAT=n + CONFIG_COVERAGE=n + CONFIG_UBSAN=n + CONFIG_NEEDS_LIBELF=n + CONFIG_XSM=n archlinux-current-gcc-riscv64-debug-randconfig: extends: .gcc-riscv64-cross-build-debug @@ -547,6 +640,35 @@ archlinux-current-gcc-riscv64-debug-randconfig: RANDCONFIG: y EXTRA_FIXED_RANDCONFIG: CONFIG_COVERAGE=n + CONFIG_GRANT_TABLE=n + CONFIG_SCHED_CREDIT=n + CONFIG_SCHED_CREDIT2=n + CONFIG_SCHED_RTDS=n + CONFIG_SCHED_NULL=n + CONFIG_SCHED_ARINC653=n + CONFIG_TRACEBUFFER=n + CONFIG_HYPFS=n + CONFIG_GRANT_TABLE=n + CONFIG_SPECULATIVE_HARDEN_ARRAY=n + CONFIG_ARGO=n + CONFIG_HYPFS_CONFIG=n + CONFIG_CORE_PARKING=n + CONFIG_DEBUG_TRACE=n + CONFIG_IOREQ_SERVER=n + CONFIG_CRASH_DEBUG=n + CONFIG_KEXEC=n + CONFIG_LIVEPATCH=n + CONFIG_MEM_ACCESS=n + CONFIG_NUMA=n + CONFIG_PERF_COUNTERS=n + CONFIG_HAS_PMAP=n + CONFIG_TRACEBUFFER=n + CONFIG_XENOPROF=n + CONFIG_COMPAT=n + CONFIG_COVERAGE=n + CONFIG_UBSAN=n + CONFIG_NEEDS_LIBELF=n + CONFIG_XSM=n # Power cross-build debian-bullseye-gcc-ppc64le: diff --git a/automation/scripts/build b/automation/scripts/build index b3c71fb6fb..88287b9c46 100755 --- a/automation/scripts/build +++ b/automation/scripts/build @@ -14,7 +14,7 @@ if [[ "${RANDCONFIG}" == "y" ]]; then # Append job-specific fixed configuration if [[ -n "${EXTRA_FIXED_RANDCONFIG}" ]]; then - echo "${EXTRA_FIXED_RANDCONFIG}" >> xen/tools/kconfig/allrandom.config + sed "s/ /\n/g" <<< "${EXTRA_FIXED_RANDCONFIG}" > xen/tools/kconfig/allrandom.config fi make -j$(nproc) -C xen KCONFIG_ALLCONFIG=tools/kconfig/allrandom.config randconfig @@ -28,7 +28,7 @@ else echo "CONFIG_DEBUG=${debug}" >> xen/.config if [[ -n "${EXTRA_XEN_CONFIG}" ]]; then - echo "${EXTRA_XEN_CONFIG}" >> xen/.config + sed "s/ /\n/g" <<< "${EXTRA_XEN_CONFIG}" >> xen/.config fi make -j$(nproc) -C xen olddefconfig diff --git a/xen/arch/riscv/configs/tiny64_defconfig b/xen/arch/riscv/configs/tiny64_defconfig index 3c9a2ff941..ce37c5ae00 100644 --- a/xen/arch/riscv/configs/tiny64_defconfig +++ b/xen/arch/riscv/configs/tiny64_defconfig @@ -6,6 +6,24 @@ # CONFIG_HYPFS is not set # CONFIG_GRANT_TABLE is not set # CONFIG_SPECULATIVE_HARDEN_ARRAY is not set +# CONFIG_ARGO is not set +# CONFIG_HYPFS_CONFIG is not set +# CONFIG_CORE_PARKING is not set +# CONFIG_DEBUG_TRACE is not set +# CONFIG_IOREQ_SERVER is not set +# CONFIG_CRASH_DEBUG is not setz +# CONFIG_KEXEC is not set +# CONFIG_LIVEPATCH is not set +# CONFIG_MEM_ACCESS is not set +# CONFIG_NUMA is not set +# CONFIG_PERF_COUNTERS is not set +# CONFIG_HAS_PMAP is not set +# CONFIG_TRACEBUFFER is not set +# CONFIG_XENOPROF is not set +# CONFIG_COMPAT is not set +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +# CONFIG_NEEDS_LIBELF is not set CONFIG_RISCV_64=y CONFIG_DEBUG=y From patchwork Fri Nov 24 10:30:22 2023 Content-Type: text/plain; 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Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in V2: - New commit introduced in V2. --- xen/arch/riscv/include/asm/Makefile | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 xen/arch/riscv/include/asm/Makefile diff --git a/xen/arch/riscv/include/asm/Makefile b/xen/arch/riscv/include/asm/Makefile new file mode 100644 index 0000000000..4da0c70cc0 --- /dev/null +++ b/xen/arch/riscv/include/asm/Makefile @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-only +generic-y += altp2m.h +generic-y += device.h +generic-y += div64.h +generic-y += hardirq.h +generic-y += hypercall.h +generic-y += iocap.h +generic-y += monitor.h +generic-y += numa.h +generic-y += paging.h +generic-y += percpu.h +generic-y += random.h +generic-y += softirq.h +generic-y += vm_event.h From patchwork Fri Nov 24 10:30:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii X-Patchwork-Id: 13467468 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4232AC636D3 for ; Fri, 24 Nov 2023 10:31:36 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.640368.998423 (Exim 4.92) (envelope-from ) id 1r6TSu-0007R7-Ll; Fri, 24 Nov 2023 10:31:16 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 640368.998423; Fri, 24 Nov 2023 10:31:16 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1r6TSu-0007R0-IY; Fri, 24 Nov 2023 10:31:16 +0000 Received: by outflank-mailman (input) for mailman id 640368; Fri, 24 Nov 2023 10:31:15 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1r6TSs-0006hy-VR for xen-devel@lists.xenproject.org; Fri, 24 Nov 2023 10:31:14 +0000 Received: from mail-ej1-x634.google.com (mail-ej1-x634.google.com [2a00:1450:4864:20::634]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 9786007d-8ab4-11ee-98e2-6d05b1d4d9a1; Fri, 24 Nov 2023 11:31:13 +0100 (CET) Received: by mail-ej1-x634.google.com with SMTP id a640c23a62f3a-a03a900956dso334979266b.1 for ; Fri, 24 Nov 2023 02:31:13 -0800 (PST) Received: from fedora.. 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Only rebase. --- xen/arch/riscv/include/asm/byteorder.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 xen/arch/riscv/include/asm/byteorder.h diff --git a/xen/arch/riscv/include/asm/byteorder.h b/xen/arch/riscv/include/asm/byteorder.h new file mode 100644 index 0000000000..320a03c88f --- /dev/null +++ b/xen/arch/riscv/include/asm/byteorder.h @@ -0,0 +1,16 @@ +#ifndef __ASM_RISCV_BYTEORDER_H__ +#define __ASM_RISCV_BYTEORDER_H__ + +#define __BYTEORDER_HAS_U64__ + +#include + +#endif /* __ASM_RISCV_BYTEORDER_H__ */ +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ From patchwork Fri Nov 24 10:30:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii X-Patchwork-Id: 13467463 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 873DDC61D97 for ; Fri, 24 Nov 2023 10:31:31 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.640369.998429 (Exim 4.92) (envelope-from ) id 1r6TSv-0007Us-1V; Fri, 24 Nov 2023 10:31:17 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 640369.998429; Fri, 24 Nov 2023 10:31:16 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1r6TSu-0007U6-RO; Fri, 24 Nov 2023 10:31:16 +0000 Received: by outflank-mailman (input) for mailman id 640369; Fri, 24 Nov 2023 10:31:16 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1r6TSu-0006hx-08 for xen-devel@lists.xenproject.org; Fri, 24 Nov 2023 10:31:16 +0000 Received: from mail-ej1-x633.google.com (mail-ej1-x633.google.com [2a00:1450:4864:20::633]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 97f58903-8ab4-11ee-9b0e-b553b5be7939; Fri, 24 Nov 2023 11:31:14 +0100 (CET) Received: by mail-ej1-x633.google.com with SMTP id a640c23a62f3a-9fa45e75ed9so246879666b.1 for ; Fri, 24 Nov 2023 02:31:14 -0800 (PST) Received: from fedora.. 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On RISCV is always 8 bytes sizes and 8 bytes + * aligned. + * XEN_GUEST_HANDLE_PARAM represents a guest pointer, when passed as an + * hypercall argument. It is 4 bytes on riscv32 and 8 bytes on riscv64. + */ +#define __DEFINE_XEN_GUEST_HANDLE(name, type) \ + ___DEFINE_XEN_GUEST_HANDLE(name, type); \ + ___DEFINE_XEN_GUEST_HANDLE(const_##name, const type) +#define DEFINE_XEN_GUEST_HANDLE(name) __DEFINE_XEN_GUEST_HANDLE(name, name) +#define __XEN_GUEST_HANDLE(name) __guest_handle_64_ ## name +#define XEN_GUEST_HANDLE(name) __XEN_GUEST_HANDLE(name) +#define XEN_GUEST_HANDLE_PARAM(name) __guest_handle_ ## name +#define set_xen_guest_handle_raw(hnd, val) \ + do { \ + typeof(&(hnd)) sxghr_tmp_ = &(hnd); \ + sxghr_tmp_->q = 0; \ + sxghr_tmp_->p = (val); \ + } while ( 0 ) +#define set_xen_guest_handle(hnd, val) set_xen_guest_handle_raw(hnd, val) + +typedef uint64_t xen_pfn_t; +#define PRI_xen_pfn PRIx64 +#define PRIu_xen_pfn PRIu64 + +typedef uint64_t xen_ulong_t; +#define PRI_xen_ulong PRIx64 + +#if defined(__XEN__) || defined(__XEN_TOOLS__) + +struct vcpu_guest_context { +}; +typedef struct vcpu_guest_context vcpu_guest_context_t; +DEFINE_XEN_GUEST_HANDLE(vcpu_guest_context_t); + +struct xen_arch_domainconfig { +}; + +#endif + +/* TODO: add a placeholder entry if no real ones surface */ +struct arch_vcpu_info { +}; +typedef struct arch_vcpu_info arch_vcpu_info_t; + +/* TODO: add a placeholder entry if no real ones surface */ +struct arch_shared_info { +}; +typedef struct arch_shared_info arch_shared_info_t; + +/* + * Maximum number of virtual CPUs in legacy multi-processor guests. + * Only one. All other VCPUS must use VCPUOP_register_vcpu_info. + */ +#define XEN_LEGACY_MAX_VCPUS 1 + +/* Stub definition of PMU structure */ +typedef struct xen_pmu_arch { uint8_t dummy; } xen_pmu_arch_t; +#endif + +#endif /* __XEN_PUBLIC_ARCH_RISCV_H__ */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * tab-width: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/include/public/xen.h b/xen/include/public/xen.h index b812a0a324..b47d48d0e2 100644 --- a/xen/include/public/xen.h +++ b/xen/include/public/xen.h @@ -18,6 +18,8 @@ #include "arch-arm.h" #elif defined(__powerpc64__) #include "arch-ppc.h" +#elif defined(__riscv) +#include "arch-riscv.h" #else #error "Unsupported architecture" #endif From patchwork Fri Nov 24 10:30:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii X-Patchwork-Id: 13467474 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3862AC636D4 for ; Fri, 24 Nov 2023 10:31:38 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.640370.998442 (Exim 4.92) (envelope-from ) id 1r6TSx-0007xi-8y; Fri, 24 Nov 2023 10:31:19 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 640370.998442; Fri, 24 Nov 2023 10:31:19 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1r6TSx-0007xN-5j; Fri, 24 Nov 2023 10:31:19 +0000 Received: by outflank-mailman (input) for mailman id 640370; Fri, 24 Nov 2023 10:31:17 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1r6TSv-0006hx-0G for xen-devel@lists.xenproject.org; Fri, 24 Nov 2023 10:31:17 +0000 Received: from mail-ej1-x62c.google.com (mail-ej1-x62c.google.com [2a00:1450:4864:20::62c]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 98742273-8ab4-11ee-9b0e-b553b5be7939; Fri, 24 Nov 2023 11:31:15 +0100 (CET) Received: by mail-ej1-x62c.google.com with SMTP id a640c23a62f3a-a0029289b1bso245212366b.1 for ; Fri, 24 Nov 2023 02:31:15 -0800 (PST) Received: from fedora.. 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Only rebase. --- xen/arch/riscv/include/asm/fence.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 xen/arch/riscv/include/asm/fence.h diff --git a/xen/arch/riscv/include/asm/fence.h b/xen/arch/riscv/include/asm/fence.h new file mode 100644 index 0000000000..2b443a3a48 --- /dev/null +++ b/xen/arch/riscv/include/asm/fence.h @@ -0,0 +1,12 @@ +#ifndef _ASM_RISCV_FENCE_H +#define _ASM_RISCV_FENCE_H + +#ifdef CONFIG_SMP +#define RISCV_ACQUIRE_BARRIER "\tfence r , rw\n" +#define RISCV_RELEASE_BARRIER "\tfence rw, w\n" +#else +#define RISCV_ACQUIRE_BARRIER +#define RISCV_RELEASE_BARRIER +#endif + +#endif /* _ASM_RISCV_FENCE_H */ From patchwork Fri Nov 24 10:30:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii X-Patchwork-Id: 13467469 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 458F7C636F2 for ; Fri, 24 Nov 2023 10:31:36 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.640372.998455 (Exim 4.92) (envelope-from ) id 1r6TSy-00089B-Ef; Fri, 24 Nov 2023 10:31:20 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 640372.998455; Fri, 24 Nov 2023 10:31:20 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1r6TSx-00087Y-Uo; Fri, 24 Nov 2023 10:31:19 +0000 Received: by outflank-mailman (input) for mailman id 640372; Fri, 24 Nov 2023 10:31:17 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1r6TSv-0006hy-Qq for xen-devel@lists.xenproject.org; Fri, 24 Nov 2023 10:31:17 +0000 Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [2a00:1450:4864:20::630]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 99a6fc53-8ab4-11ee-98e2-6d05b1d4d9a1; Fri, 24 Nov 2023 11:31:17 +0100 (CET) Received: by mail-ej1-x630.google.com with SMTP id a640c23a62f3a-a00a9c6f1e9so250539766b.3 for ; Fri, 24 Nov 2023 02:31:17 -0800 (PST) Received: from fedora.. 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Only rebase. --- xen/arch/riscv/include/asm/cpufeature.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 xen/arch/riscv/include/asm/cpufeature.h diff --git a/xen/arch/riscv/include/asm/cpufeature.h b/xen/arch/riscv/include/asm/cpufeature.h new file mode 100644 index 0000000000..211827f816 --- /dev/null +++ b/xen/arch/riscv/include/asm/cpufeature.h @@ -0,0 +1,22 @@ +#ifndef __ASM_RISCV_CPUFEATURE_H +#define __ASM_RISCV_CPUFEATURE_H + +#ifndef __ASSEMBLY__ + +static inline int cpu_nr_siblings(unsigned int cpu) +{ + return 1; +} + +#endif /* __ASSEMBLY__ */ + +#endif +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ + From patchwork Fri Nov 24 10:30:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii X-Patchwork-Id: 13467471 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 79D58C61DF4 for ; Fri, 24 Nov 2023 10:31:36 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.640374.998469 (Exim 4.92) (envelope-from ) id 1r6TSz-0008TL-De; Fri, 24 Nov 2023 10:31:21 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 640374.998469; Fri, 24 Nov 2023 10:31:21 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1r6TSz-0008Qm-2e; Fri, 24 Nov 2023 10:31:21 +0000 Received: by outflank-mailman (input) for mailman id 640374; Fri, 24 Nov 2023 10:31:20 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1r6TSx-0006hy-SS for xen-devel@lists.xenproject.org; Fri, 24 Nov 2023 10:31:19 +0000 Received: from mail-ej1-x634.google.com (mail-ej1-x634.google.com [2a00:1450:4864:20::634]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 9aec12ce-8ab4-11ee-98e2-6d05b1d4d9a1; Fri, 24 Nov 2023 11:31:19 +0100 (CET) Received: by mail-ej1-x634.google.com with SMTP id a640c23a62f3a-a0029289b1bso245224866b.1 for ; Fri, 24 Nov 2023 02:31:19 -0800 (PST) Received: from fedora.. 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Only rebase. --- xen/arch/riscv/include/asm/guest_atomics.h | 48 ++++++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 xen/arch/riscv/include/asm/guest_atomics.h diff --git a/xen/arch/riscv/include/asm/guest_atomics.h b/xen/arch/riscv/include/asm/guest_atomics.h new file mode 100644 index 0000000000..9f14f76e92 --- /dev/null +++ b/xen/arch/riscv/include/asm/guest_atomics.h @@ -0,0 +1,48 @@ +#ifndef __ASM_RISCV_GUEST_ATOMICS_H +#define __ASM_RISCV_GUEST_ATOMICS_H + +/* + * TODO: implement guest atomics + */ + +#define guest_testop(name) \ +static inline int guest_##name(struct domain *d, int nr, volatile void *p) \ +{ \ + (void) d; \ + (void) nr; \ + (void) p; \ + \ + return 0; \ +} + +#define guest_bitop(name) \ +static inline void guest_##name(struct domain *d, int nr, volatile void *p) \ +{ \ + (void) d; \ + (void) nr; \ + (void) p; \ +} + +guest_bitop(set_bit) +guest_bitop(clear_bit) +guest_bitop(change_bit) + +#undef guest_bitop + +guest_testop(test_and_set_bit) +guest_testop(test_and_clear_bit) +guest_testop(test_and_change_bit) + +#undef guest_testop + +#define guest_test_bit(d, nr, p) ((void)(d), test_bit(nr, p)) + +#endif /* __ASM_RISCV_GUEST_ATOMICS_H */ +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ From patchwork Fri Nov 24 10:30:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii X-Patchwork-Id: 13467466 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 19A49C61DF7 for ; Fri, 24 Nov 2023 10:31:35 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.640375.998493 (Exim 4.92) (envelope-from ) id 1r6TT1-0000w0-M1; Fri, 24 Nov 2023 10:31:23 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 640375.998493; Fri, 24 Nov 2023 10:31:23 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1r6TT1-0000tE-G2; Fri, 24 Nov 2023 10:31:23 +0000 Received: by outflank-mailman (input) for mailman id 640375; Fri, 24 Nov 2023 10:31:21 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1r6TSz-0006hy-OE for xen-devel@lists.xenproject.org; Fri, 24 Nov 2023 10:31:21 +0000 Received: from mail-ej1-x62b.google.com (mail-ej1-x62b.google.com [2a00:1450:4864:20::62b]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 9bfcfe3f-8ab4-11ee-98e2-6d05b1d4d9a1; Fri, 24 Nov 2023 11:31:21 +0100 (CET) Received: by mail-ej1-x62b.google.com with SMTP id a640c23a62f3a-a002562bd8bso338503166b.0 for ; Fri, 24 Nov 2023 02:31:21 -0800 (PST) Received: from fedora.. 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Only rebase. --- xen/arch/riscv/include/asm/iommu.h | 7 +++++++ 1 file changed, 7 insertions(+) create mode 100644 xen/arch/riscv/include/asm/iommu.h diff --git a/xen/arch/riscv/include/asm/iommu.h b/xen/arch/riscv/include/asm/iommu.h new file mode 100644 index 0000000000..648b6fb922 --- /dev/null +++ b/xen/arch/riscv/include/asm/iommu.h @@ -0,0 +1,7 @@ +#ifndef __ASM_RISCV_IOMMU_H__ +#define __ASM_RISCV_IOMMU_H__ + +struct arch_iommu { +}; + +#endif /* __ASM_IOMMU_H__ */ From patchwork Fri Nov 24 10:30:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii X-Patchwork-Id: 13467478 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BA8FEC61D97 for ; Fri, 24 Nov 2023 10:31:46 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.640376.998502 (Exim 4.92) (envelope-from ) id 1r6TT3-0001D7-2t; Fri, 24 Nov 2023 10:31:25 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 640376.998502; Fri, 24 Nov 2023 10:31:25 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1r6TT2-0001BW-VB; Fri, 24 Nov 2023 10:31:24 +0000 Received: by outflank-mailman (input) for mailman id 640376; Fri, 24 Nov 2023 10:31:22 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1r6TT0-0006hy-O8 for xen-devel@lists.xenproject.org; Fri, 24 Nov 2023 10:31:22 +0000 Received: from mail-ej1-x62d.google.com (mail-ej1-x62d.google.com [2a00:1450:4864:20::62d]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 9c8194c7-8ab4-11ee-98e2-6d05b1d4d9a1; Fri, 24 Nov 2023 11:31:22 +0100 (CET) Received: by mail-ej1-x62d.google.com with SMTP id a640c23a62f3a-a04196fc957so253598266b.2 for ; Fri, 24 Nov 2023 02:31:22 -0800 (PST) Received: from fedora.. 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Only rebase. --- xen/arch/riscv/include/asm/nospec.h | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 xen/arch/riscv/include/asm/nospec.h diff --git a/xen/arch/riscv/include/asm/nospec.h b/xen/arch/riscv/include/asm/nospec.h new file mode 100644 index 0000000000..55087fa831 --- /dev/null +++ b/xen/arch/riscv/include/asm/nospec.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved. */ + +#ifndef _ASM_RISCV_NOSPEC_H +#define _ASM_RISCV_NOSPEC_H + +static inline bool evaluate_nospec(bool condition) +{ + return condition; +} + +static inline void block_speculation(void) +{ +} + +#endif /* _ASM_RISCV_NOSPEC_H */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ From patchwork Fri Nov 24 10:30:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii X-Patchwork-Id: 13467472 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7F9CEC636F3 for ; Fri, 24 Nov 2023 10:31:36 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.640377.998513 (Exim 4.92) (envelope-from ) id 1r6TT5-0001as-0q; Fri, 24 Nov 2023 10:31:27 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 640377.998513; Fri, 24 Nov 2023 10:31:26 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1r6TT4-0001aF-RE; Fri, 24 Nov 2023 10:31:26 +0000 Received: by outflank-mailman (input) for mailman id 640377; Fri, 24 Nov 2023 10:31:24 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1r6TT2-0006hx-NK for xen-devel@lists.xenproject.org; Fri, 24 Nov 2023 10:31:24 +0000 Received: from mail-ej1-x62a.google.com (mail-ej1-x62a.google.com [2a00:1450:4864:20::62a]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 9d3a0577-8ab4-11ee-9b0e-b553b5be7939; Fri, 24 Nov 2023 11:31:23 +0100 (CET) Received: by mail-ej1-x62a.google.com with SMTP id a640c23a62f3a-a02d91ab195so243504966b.3 for ; Fri, 24 Nov 2023 02:31:23 -0800 (PST) Received: from fedora.. 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Only rebase. --- xen/arch/riscv/include/asm/setup.h | 6 ++++++ 1 file changed, 6 insertions(+) create mode 100644 xen/arch/riscv/include/asm/setup.h diff --git a/xen/arch/riscv/include/asm/setup.h b/xen/arch/riscv/include/asm/setup.h new file mode 100644 index 0000000000..a1adb2be0d --- /dev/null +++ b/xen/arch/riscv/include/asm/setup.h @@ -0,0 +1,6 @@ +#ifndef __ASM_RISCV_SETUP_H__ +#define __ASM_RISCV_SETUP_H__ + +#define max_init_domid (0) + +#endif /* __ASM_RISCV_SETUP_H__ */ From patchwork Fri Nov 24 10:30:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii X-Patchwork-Id: 13467477 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BC398C636CB for ; Fri, 24 Nov 2023 10:31:46 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.640378.998518 (Exim 4.92) (envelope-from ) id 1r6TT5-0001ih-UL; Fri, 24 Nov 2023 10:31:27 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 640378.998518; Fri, 24 Nov 2023 10:31:27 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1r6TT5-0001hZ-Ej; Fri, 24 Nov 2023 10:31:27 +0000 Received: by outflank-mailman (input) for mailman id 640378; Fri, 24 Nov 2023 10:31:25 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1r6TT3-0006hy-0F for xen-devel@lists.xenproject.org; Fri, 24 Nov 2023 10:31:25 +0000 Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [2a00:1450:4864:20::630]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 9da6b42b-8ab4-11ee-98e2-6d05b1d4d9a1; Fri, 24 Nov 2023 11:31:24 +0100 (CET) Received: by mail-ej1-x630.google.com with SMTP id a640c23a62f3a-a002562bd8bso338511566b.0 for ; Fri, 24 Nov 2023 02:31:24 -0800 (PST) Received: from fedora.. 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Only rebase. --- xen/arch/riscv/include/asm/system.h | 79 +++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) create mode 100644 xen/arch/riscv/include/asm/system.h diff --git a/xen/arch/riscv/include/asm/system.h b/xen/arch/riscv/include/asm/system.h new file mode 100644 index 0000000000..45bfed4e2b --- /dev/null +++ b/xen/arch/riscv/include/asm/system.h @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef _ASM_RISCV_BARRIER_H +#define _ASM_RISCV_BARRIER_H + +#include + +#ifndef __ASSEMBLY__ + +#define RISCV_FENCE(p, s) \ + __asm__ __volatile__ ("fence " #p "," #s : : : "memory") + +/* These barriers need to enforce ordering on both devices or memory. */ +#define mb() RISCV_FENCE(iorw,iorw) +#define rmb() RISCV_FENCE(ir,ir) +#define wmb() RISCV_FENCE(ow,ow) + +/* These barriers do not need to enforce ordering on devices, just memory. */ +#define smp_mb() RISCV_FENCE(rw,rw) +#define smp_rmb() RISCV_FENCE(r,r) +#define smp_wmb() RISCV_FENCE(w,w) +#define smp_mb__before_atomic() smp_mb() +#define smp_mb__after_atomic() smp_mb() + +/* +#define __smp_store_release(p, v) \ +do { \ + compiletime_assert_atomic_type(*p); \ + RISCV_FENCE(rw,w); \ + WRITE_ONCE(*p, v); \ +} while (0) + +#define __smp_load_acquire(p) \ +({ \ + typeof(*p) ___p1 = READ_ONCE(*p); \ + compiletime_assert_atomic_type(*p); \ + RISCV_FENCE(r,rw); \ + ___p1; \ +}) +*/ + +static inline unsigned long local_save_flags(void) +{ + return csr_read(sstatus); +} + +static inline void local_irq_enable(void) +{ + csr_set(sstatus, SSTATUS_SIE); +} + +static inline void local_irq_disable(void) +{ + csr_clear(sstatus, SSTATUS_SIE); +} + +#define local_irq_save(x) \ +({ \ + x = csr_read_clear(CSR_SSTATUS, SSTATUS_SIE); \ + local_irq_disable(); \ +}) + +static inline void local_irq_restore(unsigned long flags) +{ + csr_set(CSR_SSTATUS, flags & SSTATUS_SIE); +} + +static inline int local_irq_is_enabled(void) +{ + unsigned long flags = local_save_flags(); + + return flags & SSTATUS_SIE; +} + +#define arch_fetch_and_add(x, v) __sync_fetch_and_add(x, v) + +#endif /* __ASSEMBLY__ */ + +#endif /* _ASM_RISCV_BARRIER_H */ From patchwork Fri Nov 24 10:30:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii X-Patchwork-Id: 13467498 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5D590C61D97 for ; Fri, 24 Nov 2023 10:39:34 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.640425.998633 (Exim 4.92) (envelope-from ) id 1r6Tap-0004cd-5A; Fri, 24 Nov 2023 10:39:27 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 640425.998633; Fri, 24 Nov 2023 10:39:27 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1r6Tap-0004cW-0w; Fri, 24 Nov 2023 10:39:27 +0000 Received: by outflank-mailman (input) for mailman id 640425; Fri, 24 Nov 2023 10:39:25 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1r6TT4-0006hy-0X for xen-devel@lists.xenproject.org; Fri, 24 Nov 2023 10:31:26 +0000 Received: from mail-ej1-x629.google.com (mail-ej1-x629.google.com [2a00:1450:4864:20::629]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 9e3929cc-8ab4-11ee-98e2-6d05b1d4d9a1; Fri, 24 Nov 2023 11:31:24 +0100 (CET) Received: by mail-ej1-x629.google.com with SMTP id a640c23a62f3a-a0064353af8so547461766b.0 for ; Fri, 24 Nov 2023 02:31:24 -0800 (PST) Received: from fedora.. ([94.75.70.14]) by smtp.gmail.com with ESMTPSA id g1-20020a170906348100b009de3641d538sm1882374ejb.134.2023.11.24.02.31.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Nov 2023 02:31:23 -0800 (PST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 9e3929cc-8ab4-11ee-98e2-6d05b1d4d9a1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1700821884; x=1701426684; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TFiYo47Y6neKV/659IAnBCy68zaLkdoQh7hTdkj2HW4=; b=U86bwtG2XyFPrSIJtdcxX1Z8MoFNT0T8Op9jGXFO1qR7e9Fs/Zkg7y9rWN08GqR8Yx HuZF7HkzTd5+RUrQ1Ctb2zu7Wdoe2ChVdsJs38uBp2RgygrCFcfVvo7s0hULqUdwoxcn UE66eo8A5xKaeXYm3X663GR1+QR7HCXNGohh4Qn4RBTjSyjDZyB4J9DJCVflbxjnqRhG Xhj8YKGVmutSDJYjP82mp/vlpaiqFhgHsAVGYdX5Su4nqYdpI3ZjSfkS408l8m3WjJU8 McL7w7I6MMShLCewjgpG61P+pvlF3WVKMiVoMNDrYXYI4ftKr2eAyRh2euoJeMJgyrPu cCoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700821884; x=1701426684; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TFiYo47Y6neKV/659IAnBCy68zaLkdoQh7hTdkj2HW4=; b=dLfL6tBv014UIwe6aqLQUfbC0osDPsHOaqil8g/tBayL8pkMcshAtgmVbG6Vt4nBCF D9i3nxgWN1LXWHbTXF6OUX7Z9muxA0eRMOUkjwRmE26tmh0xpdtCK1h7l9XT2yWhwFDp SUCeA68SxUss+dYB+9179JqZfO9go32o1Qxs5DlkW/CmHj9Mdgr8LSBCs5vhkFSjCB5w yJNeANr1/wMUcjOSCidcupck1lXzNgAlLFE7eVI3rUt8tcCeci6GcBOOO4vfs6Y/lufo 4AtXwu529ShZzGAoSnWhHdAYmFze7+INZTWaLBFD3JzIpaxxi3g5r0A9W8HCaJ+Nxhbt hz6A== X-Gm-Message-State: AOJu0Yw1hGUHSRe0DQmYjHCpxCBCKXIfd/bU8YjyfRNNWnsPCzcd7/ZT ybisu/7Yta2O34BPIG4wh16MwROaLgv41Q== X-Google-Smtp-Source: AGHT+IFNByZwBF9ROP5nmS5akxwitHaYUUyJjesb1JJXQW8zGkCDI8+PSeS/4s2MUQuUSPrJWQd+tA== X-Received: by 2002:a17:906:10cf:b0:9ee:295:5693 with SMTP id v15-20020a17090610cf00b009ee02955693mr1735649ejv.7.1700821884099; Fri, 24 Nov 2023 02:31:24 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini , Wei Liu Subject: [PATCH v2 14/39] xen/riscv: introduce bitops.h Date: Fri, 24 Nov 2023 12:30:34 +0200 Message-ID: X-Mailer: git-send-email 2.42.0 In-Reply-To: References: MIME-Version: 1.0 Signed-off-by: Oleksii Kurochko --- Changes in V2: - Nothing changed. Only rebase. --- xen/arch/riscv/include/asm/bitops.h | 288 ++++++++++++++++++++++++++++ 1 file changed, 288 insertions(+) create mode 100644 xen/arch/riscv/include/asm/bitops.h diff --git a/xen/arch/riscv/include/asm/bitops.h b/xen/arch/riscv/include/asm/bitops.h new file mode 100644 index 0000000000..24a49c499b --- /dev/null +++ b/xen/arch/riscv/include/asm/bitops.h @@ -0,0 +1,288 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (C) 2012 Regents of the University of California */ + +#ifndef _ASM_RISCV_BITOPS_H +#define _ASM_RISCV_BITOPS_H + +#include + +#define BITOP_BITS_PER_WORD 32 +#define BITOP_MASK(nr) (1UL << ((nr) % BITOP_BITS_PER_WORD)) +#define BITOP_WORD(nr) ((nr) / BITOP_BITS_PER_WORD) +#define BITS_PER_BYTE 8 + +#define __set_bit(n,p) set_bit(n,p) +#define __clear_bit(n,p) clear_bit(n,p) + +#define __AMO(op) "amo" #op ".w" + +#define __test_and_op_bit_ord(op, mod, nr, addr, ord) \ +({ \ + unsigned long __res, __mask; \ + __mask = BITOP_MASK(nr); \ + __asm__ __volatile__ ( \ + __AMO(op) #ord " %0, %2, %1" \ + : "=r" (__res), "+A" (addr[BITOP_WORD(nr)]) \ + : "r" (mod(__mask)) \ + : "memory"); \ + ((__res & __mask) != 0); \ +}) + +#define __op_bit_ord(op, mod, nr, addr, ord) \ + __asm__ __volatile__ ( \ + __AMO(op) #ord " zero, %1, %0" \ + : "+A" (addr[BITOP_WORD(nr)]) \ + : "r" (mod(BITOP_MASK(nr))) \ + : "memory"); + +#define __test_and_op_bit(op, mod, nr, addr) \ + __test_and_op_bit_ord(op, mod, nr, addr, .aqrl) + +#define __op_bit(op, mod, nr, addr) \ + __op_bit_ord(op, mod, nr, addr, ) + +/* Bitmask modifiers */ +#define __NOP(x) (x) +#define __NOT(x) (~(x)) + +/** + * __test_and_set_bit - Set a bit and return its old value + * @nr: Bit to set + * @addr: Address to count from + * + * This operation may be reordered on other architectures than x86. + */ +static inline int __test_and_set_bit(int nr, volatile void *p) +{ + volatile uint32_t *addr = p; + + return __test_and_op_bit(or, __NOP, nr, addr); +} + +/** + * __test_and_clear_bit - Clear a bit and return its old value + * @nr: Bit to clear + * @addr: Address to count from + * + * This operation can be reordered on other architectures other than x86. + */ +static inline int __test_and_clear_bit(int nr, volatile void *p) +{ + volatile uint32_t *addr = p; + + return __test_and_op_bit(and, __NOT, nr, addr); +} + +/** + * set_bit - Atomically set a bit in memory + * @nr: the bit to set + * @addr: the address to start counting from + * + * Note: there are no guarantees that this function will not be reordered + * on non x86 architectures, so if you are writing portable code, + * make sure not to rely on its reordering guarantees. + * + * Note that @nr may be almost arbitrarily large; this function is not + * restricted to acting on a single-word quantity. + */ +static inline void set_bit(int nr, volatile void *p) +{ + volatile uint32_t *addr = p; + + __op_bit(or, __NOP, nr, addr); +} + +/** + * clear_bit - Clears a bit in memory + * @nr: Bit to clear + * @addr: Address to start counting from + * + * Note: there are no guarantees that this function will not be reordered + * on non x86 architectures, so if you are writing portable code, + * make sure not to rely on its reordering guarantees. + */ +static inline void clear_bit(int nr, volatile void *p) +{ + volatile uint32_t *addr = p; + + __op_bit(and, __NOT, nr, addr); +} + +static inline int test_bit(int nr, const volatile void *p) +{ + const volatile uint32_t *addr = (const volatile uint32_t *)p; + + return 1UL & (addr[BITOP_WORD(nr)] >> (nr & (BITOP_BITS_PER_WORD-1))); +} + +#undef __test_and_op_bit +#undef __op_bit +#undef __NOP +#undef __NOT +#undef __AMO + +static inline int fls(unsigned int x) +{ + return generic_fls(x); +} + +static inline int flsl(unsigned long x) +{ + return generic_flsl(x); +} + +#define test_and_set_bit __test_and_set_bit +#define test_and_clear_bit __test_and_clear_bit + +/* Based on linux/include/asm-generic/bitops/find.h */ + +#ifndef find_next_bit +/** + * find_next_bit - find the next set bit in a memory region + * @addr: The address to base the search on + * @offset: The bitnumber to start searching at + * @size: The bitmap size in bits + */ +extern unsigned long find_next_bit(const unsigned long *addr, unsigned long + size, unsigned long offset); +#endif + +#ifndef find_next_zero_bit +/** + * find_next_zero_bit - find the next cleared bit in a memory region + * @addr: The address to base the search on + * @offset: The bitnumber to start searching at + * @size: The bitmap size in bits + */ +extern unsigned long find_next_zero_bit(const unsigned long *addr, unsigned + long size, unsigned long offset); +#endif + +/** + * find_first_bit - find the first set bit in a memory region + * @addr: The address to start the search at + * @size: The maximum size to search + * + * Returns the bit number of the first set bit. + */ +extern unsigned long find_first_bit(const unsigned long *addr, + unsigned long size); + +/** + * find_first_zero_bit - find the first cleared bit in a memory region + * @addr: The address to start the search at + * @size: The maximum size to search + * + * Returns the bit number of the first cleared bit. + */ +extern unsigned long find_first_zero_bit(const unsigned long *addr, + unsigned long size); + +#define ffs(x) ({ unsigned int __t = (x); fls(__t & -__t); }) + +/** + * ffs - find first bit in word. + * @word: The word to search + * + * Returns 0 if no bit exists, otherwise returns 1-indexed bit location. + */ +static inline unsigned long __ffs(unsigned long word) +{ + int num = 0; + +#if BITS_PER_LONG == 64 + if ((word & 0xffffffff) == 0) { + num += 32; + word >>= 32; + } +#endif + if ((word & 0xffff) == 0) { + num += 16; + word >>= 16; + } + if ((word & 0xff) == 0) { + num += 8; + word >>= 8; + } + if ((word & 0xf) == 0) { + num += 4; + word >>= 4; + } + if ((word & 0x3) == 0) { + num += 2; + word >>= 2; + } + if ((word & 0x1) == 0) + num += 1; + return num; +} + +/** + * ffsl - find first bit in long. + * @word: The word to search + * + * Returns 0 if no bit exists, otherwise returns 1-indexed bit location. + */ +static inline unsigned int ffsl(unsigned long word) +{ + int num = 1; + + if (!word) + return 0; + +#if BITS_PER_LONG == 64 + if ((word & 0xffffffff) == 0) { + num += 32; + word >>= 32; + } +#endif + if ((word & 0xffff) == 0) { + num += 16; + word >>= 16; + } + if ((word & 0xff) == 0) { + num += 8; + word >>= 8; + } + if ((word & 0xf) == 0) { + num += 4; + word >>= 4; + } + if ((word & 0x3) == 0) { + num += 2; + word >>= 2; + } + if ((word & 0x1) == 0) + num += 1; + return num; +} + +/* + * ffz - find first zero in word. + * @word: The word to search + * + * Undefined if no zero exists, so code should check against ~0UL first. + */ +#define ffz(x) __ffs(~(x)) + +/** + * find_first_set_bit - find the first set bit in @word + * @word: the word to search + * + * Returns the bit-number of the first set bit (first bit being 0). + * The input must *not* be zero. + */ +static inline unsigned int find_first_set_bit(unsigned long word) +{ + return ffsl(word) - 1; +} + +/** + * hweightN - returns the hamming weight of a N-bit word + * @x: the word to weigh + * + * The Hamming Weight of a number is the total number of bits set in it. + */ +#define hweight64(x) generic_hweight64(x) + +#endif /* _ASM_RISCV_BITOPS_H */ From patchwork Fri Nov 24 10:30:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii X-Patchwork-Id: 13467475 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3CD07C61DF4 for ; Fri, 24 Nov 2023 10:31:40 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.640379.998528 (Exim 4.92) (envelope-from ) id 1r6TT7-0002Al-SC; Fri, 24 Nov 2023 10:31:29 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 640379.998528; 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Only rebase. --- xen/arch/riscv/include/asm/flushtlb.h | 31 +++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 xen/arch/riscv/include/asm/flushtlb.h diff --git a/xen/arch/riscv/include/asm/flushtlb.h b/xen/arch/riscv/include/asm/flushtlb.h new file mode 100644 index 0000000000..7059a53823 --- /dev/null +++ b/xen/arch/riscv/include/asm/flushtlb.h @@ -0,0 +1,31 @@ +#ifndef __ASM_RISCV_FLUSHTLB_H__ +#define __ASM_RISCV_FLUSHTLB_H__ + +#include + +/* + * Filter the given set of CPUs, removing those that definitely flushed their + * TLB since @page_timestamp. + */ +/* XXX lazy implementation just doesn't clear anything.... */ +static inline void tlbflush_filter(cpumask_t *mask, uint32_t page_timestamp) {} + +#define tlbflush_current_time() (0) + +static inline void page_set_tlbflush_timestamp(struct page_info *page) +{ + BUG(); +} + +/* Flush specified CPUs' TLBs */ +void arch_flush_tlb_mask(const cpumask_t *mask); + +#endif /* __ASM_RISCV_FLUSHTLB_H__ */ +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ From patchwork Fri Nov 24 10:30:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii X-Patchwork-Id: 13467480 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DAF88C61D97 for ; Fri, 24 Nov 2023 10:31:51 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.640380.998534 (Exim 4.92) (envelope-from ) id 1r6TT9-0002Ha-2a; Fri, 24 Nov 2023 10:31:31 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 640380.998534; Fri, 24 Nov 2023 10:31:30 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1r6TT8-0002Es-6D; Fri, 24 Nov 2023 10:31:30 +0000 Received: by outflank-mailman (input) for mailman id 640380; Fri, 24 Nov 2023 10:31:28 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1r6TT6-0006hx-En for xen-devel@lists.xenproject.org; Fri, 24 Nov 2023 10:31:28 +0000 Received: from mail-ej1-x62a.google.com (mail-ej1-x62a.google.com [2a00:1450:4864:20::62a]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 9f72588c-8ab4-11ee-9b0e-b553b5be7939; Fri, 24 Nov 2023 11:31:27 +0100 (CET) Received: by mail-ej1-x62a.google.com with SMTP id a640c23a62f3a-a04196fc957so253609766b.2 for ; Fri, 24 Nov 2023 02:31:27 -0800 (PST) Received: from fedora.. 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Only rebase. --- xen/arch/riscv/include/asm/smp.h | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 xen/arch/riscv/include/asm/smp.h diff --git a/xen/arch/riscv/include/asm/smp.h b/xen/arch/riscv/include/asm/smp.h new file mode 100644 index 0000000000..a7b4f94ce4 --- /dev/null +++ b/xen/arch/riscv/include/asm/smp.h @@ -0,0 +1,23 @@ +#ifndef __ASM_RISCV_SMP_H +#define __ASM_RISCV_SMP_H + +#ifndef __ASSEMBLY__ +#include +#include +#endif + +DECLARE_PER_CPU(cpumask_var_t, cpu_sibling_mask); +DECLARE_PER_CPU(cpumask_var_t, cpu_core_mask); + +#define cpu_is_offline(cpu) unlikely(!cpu_online(cpu)) + +/* + * Do we, for platform reasons, need to actually keep CPUs online when we + * would otherwise prefer them to be off? + */ +#define park_offline_cpus false + +/* TODO: need to be implemeted */ +#define smp_processor_id() (0) + +#endif \ No newline at end of file From patchwork Fri Nov 24 10:30:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii X-Patchwork-Id: 13467476 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 61CA1C61DF4 for ; Fri, 24 Nov 2023 10:31:45 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.640381.998547 (Exim 4.92) (envelope-from ) id 1r6TTB-0002ru-R8; Fri, 24 Nov 2023 10:31:33 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 640381.998547; Fri, 24 Nov 2023 10:31:33 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1r6TTB-0002p0-3X; Fri, 24 Nov 2023 10:31:33 +0000 Received: by outflank-mailman (input) for mailman id 640381; Fri, 24 Nov 2023 10:31:30 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1r6TT8-0006hx-1D for xen-devel@lists.xenproject.org; Fri, 24 Nov 2023 10:31:30 +0000 Received: from mail-ej1-x632.google.com (mail-ej1-x632.google.com [2a00:1450:4864:20::632]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id a042a396-8ab4-11ee-9b0e-b553b5be7939; Fri, 24 Nov 2023 11:31:28 +0100 (CET) Received: by mail-ej1-x632.google.com with SMTP id a640c23a62f3a-9fffa4c4f43so245835166b.3 for ; Fri, 24 Nov 2023 02:31:28 -0800 (PST) Received: from fedora.. ([94.75.70.14]) by smtp.gmail.com with ESMTPSA id g1-20020a170906348100b009de3641d538sm1882374ejb.134.2023.11.24.02.31.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Nov 2023 02:31:26 -0800 (PST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: a042a396-8ab4-11ee-9b0e-b553b5be7939 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1700821887; x=1701426687; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9riaokCWExjFFZnUk2kE6ssbpq4/t90lh8ou5GK8cws=; b=hcBk1MVWFADvXYOajjYsggTEUZs7SwxRg9UZq5djuXc94iyPNXrdJXME/UfRYQWP2h 0Gt0+JqJuKrcyGkaPW4omivg92Biwq3dZLGeAeMddTUjB1Y7vgJMOPqfwZNDnwfxB5SO K3V9BvBHXz94XXCoZwjeU+xHFp171Ql67yq5nlLsE6tnKBs/gXiiiGNIC8yKZNMroDhu HRyGEIc0R7g02adoUINvTNTSbuLAK/VW9AMGcy2zM9hfZI47OJoLFGH6NVBkoVcNqYz/ HFKJiWGg2CXIrfBT2fKPaBlwTsZ67pP4xZjVFnI1BDUq45z5I9B7kyOxjpquj+G5toUi unrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700821887; x=1701426687; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9riaokCWExjFFZnUk2kE6ssbpq4/t90lh8ou5GK8cws=; b=ghY60AROaN3jLH7+0cKeZG5UNvBxu6aYQdr90xsRRh2AtVwUEMJtsq3ehEXN0Kh+9n Z6pUDkb+kO+LcSoAjXQGfTrUPvPCVkjNcWZQ0KZtpBb/Nmgamx9G0/2iEhKXNtvmWRck Efqb1duJQslRRVovwmUWG3BR0uJlKiSBKsPYQgzGd1uQfOUJzqGriAEH5fpaaciHzYe/ Y+VsYBHmUN8BnfpyojAVK5dL6qktOikZ+vhbiX3jUtp5ZhzLjgQCiCfcwxuWL86qe+VN A5PE85uzLfm6vjAkmt0JyWvp1HmLmhCPd046rF0z0K6bBPjGoKymJXK8jC8mdVnLIqlh FyFg== X-Gm-Message-State: AOJu0Yw1hVsAA5kv6GJ3HlZnbaDlrRPFFLCglLouBSDQmgcJMt0zmYXM TyOeH8xCeu1yP/FMMj385p8rxTq8FfgmgA== X-Google-Smtp-Source: AGHT+IG698d3KMDeF4UhW/xSE30Qxjj9yiXgYr3I4OGIxQewyYST6MbRm8Wd9VW0YOU1euKq2wYSeg== X-Received: by 2002:a17:906:5299:b0:a00:8706:c82e with SMTP id c25-20020a170906529900b00a008706c82emr1910109ejm.18.1700821887071; Fri, 24 Nov 2023 02:31:27 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Bobby Eshleman , Alistair Francis , Connor Davis , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini , Wei Liu , Oleksii Kurochko Subject: [PATCH v2 17/39] xen/riscv: introduce asm/atomic.h Date: Fri, 24 Nov 2023 12:30:37 +0200 Message-ID: X-Mailer: git-send-email 2.42.0 In-Reply-To: References: MIME-Version: 1.0 From: Bobby Eshleman Signed-off-by: Oleksii Kurochko --- Changes in V2: - Change an author of commit. I got this header from Bobby's old repo. --- xen/arch/riscv/include/asm/atomic.h | 375 ++++++++++++++++++++++++++++ 1 file changed, 375 insertions(+) create mode 100644 xen/arch/riscv/include/asm/atomic.h diff --git a/xen/arch/riscv/include/asm/atomic.h b/xen/arch/riscv/include/asm/atomic.h new file mode 100644 index 0000000000..d4849cf282 --- /dev/null +++ b/xen/arch/riscv/include/asm/atomic.h @@ -0,0 +1,375 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Taken and modified from Linux. + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Copyright (C) 2012 Regents of the University of California + * Copyright (C) 2017 SiFive + * Copyright (C) 2021 Vates SAS + */ + +#ifndef _ASM_RISCV_ATOMIC_H +#define _ASM_RISCV_ATOMIC_H + +#include +#include +#include +#include +#include + +void __bad_atomic_size(void); + +static always_inline void read_atomic_size(const volatile void *p, + void *res, + unsigned int size) +{ + switch ( size ) { + case 1: *(uint8_t *)res = readb((uint8_t *)p); break; + case 2: *(uint16_t *)res = readw((uint16_t *)p); break; + case 4: *(uint32_t *)res = readl((uint32_t *)p); break; + case 8: *(uint32_t *)res = readq((uint64_t *)p); break; + default: __bad_atomic_size(); break; + } +} + +#define read_atomic(p) ({ \ + union { typeof(*p) val; char c[0]; } x_; \ + read_atomic_size(p, x_.c, sizeof(*p)); \ + x_.val; \ +}) + + +#define write_atomic(p, x) ({ \ + typeof(*p) __x = (x); \ + switch ( sizeof(*p) ) { \ + case 1: writeb((uint8_t)__x, (uint8_t *) p); break; \ + case 2: writew((uint16_t)__x, (uint16_t *) p); break; \ + case 4: writel((uint32_t)__x, (uint32_t *) p); break; \ + case 8: writeq((uint64_t)__x, (uint64_t *) p); break; \ + default: __bad_atomic_size(); break; \ + } \ + __x; \ +}) + +/* TODO: Fix this */ +#define add_sized(p, x) ({ \ + typeof(*(p)) __x = (x); \ + switch ( sizeof(*(p)) ) \ + { \ + case 1: writeb(read_atomic(p) + __x, (uint8_t *)(p)); break; \ + case 2: writew(read_atomic(p) + __x, (uint16_t *)(p)); break; \ + case 4: writel(read_atomic(p) + __x, (uint32_t *)(p)); break; \ + default: __bad_atomic_size(); break; \ + } \ +}) + +/* + * __unqual_scalar_typeof(x) - Declare an unqualified scalar type, leaving + * non-scalar types unchanged. + * + * Prefer C11 _Generic for better compile-times and simpler code. Note: 'char' + * is not type-compatible with 'signed char', and we define a separate case. + */ +#define __scalar_type_to_expr_cases(type) \ + unsigned type: (unsigned type)0, \ + signed type: (signed type)0 + +#define __unqual_scalar_typeof(x) typeof( \ + _Generic((x), \ + char: (char)0, \ + __scalar_type_to_expr_cases(char), \ + __scalar_type_to_expr_cases(short), \ + __scalar_type_to_expr_cases(int), \ + __scalar_type_to_expr_cases(long), \ + __scalar_type_to_expr_cases(long long), \ + default: (x))) + +#define READ_ONCE(x) (*(const volatile __unqual_scalar_typeof(x) *)&(x)) +#define WRITE_ONCE(x, val) \ + do { \ + *(volatile typeof(x) *)&(x) = (val); \ + } while (0) + +#define __atomic_acquire_fence() \ + __asm__ __volatile__(RISCV_ACQUIRE_BARRIER "" ::: "memory") + +#define __atomic_release_fence() \ + __asm__ __volatile__(RISCV_RELEASE_BARRIER "" ::: "memory"); + +static inline int atomic_read(const atomic_t *v) +{ + return READ_ONCE(v->counter); +} + +static inline int _atomic_read(atomic_t v) +{ + return v.counter; +} + +static inline void atomic_set(atomic_t *v, int i) +{ + WRITE_ONCE(v->counter, i); +} + +static inline void _atomic_set(atomic_t *v, int i) +{ + v->counter = i; +} + +static inline int atomic_sub_and_test(int i, atomic_t *v) +{ + return atomic_sub_return(i, v) == 0; +} + +static inline void atomic_inc(atomic_t *v) +{ + atomic_add(1, v); +} + +static inline int atomic_inc_return(atomic_t *v) +{ + return atomic_add_return(1, v); +} + +static inline void atomic_dec(atomic_t *v) +{ + atomic_sub(1, v); +} + +static inline int atomic_dec_return(atomic_t *v) +{ + return atomic_sub_return(1, v); +} + + +static inline int atomic_dec_and_test(atomic_t *v) +{ + return atomic_sub_return(1, v) == 0; +} + +static inline int atomic_add_negative(int i, atomic_t *v) +{ + return atomic_add_return(i, v) < 0; +} + +static inline int atomic_inc_and_test(atomic_t *v) +{ + return atomic_add_return(1, v) == 0; +} + +/* + * First, the atomic ops that have no ordering constraints and therefor don't + * have the AQ or RL bits set. These don't return anything, so there's only + * one version to worry about. + */ +#define ATOMIC_OP(op, asm_op, I, asm_type, c_type, prefix) \ +static inline \ +void atomic##prefix##_##op(c_type i, atomic##prefix##_t *v) \ +{ \ + __asm__ __volatile__ ( \ + " amo" #asm_op "." #asm_type " zero, %1, %0" \ + : "+A" (v->counter) \ + : "r" (I) \ + : "memory"); \ +} \ + +#define ATOMIC_OPS(op, asm_op, I) \ + ATOMIC_OP (op, asm_op, I, w, int, ) + +ATOMIC_OPS(add, add, i) +ATOMIC_OPS(sub, add, -i) +ATOMIC_OPS(and, and, i) +ATOMIC_OPS( or, or, i) +ATOMIC_OPS(xor, xor, i) + +#undef ATOMIC_OP +#undef ATOMIC_OPS + +/* + * Atomic ops that have ordered, relaxed, acquire, and release variants. + * There's two flavors of these: the arithmatic ops have both fetch and return + * versions, while the logical ops only have fetch versions. + */ +#define ATOMIC_FETCH_OP(op, asm_op, I, asm_type, c_type, prefix) \ +static inline \ +c_type atomic##prefix##_fetch_##op##_relaxed(c_type i, \ + atomic##prefix##_t *v) \ +{ \ + register c_type ret; \ + __asm__ __volatile__ ( \ + " amo" #asm_op "." #asm_type " %1, %2, %0" \ + : "+A" (v->counter), "=r" (ret) \ + : "r" (I) \ + : "memory"); \ + return ret; \ +} \ +static inline \ +c_type atomic##prefix##_fetch_##op(c_type i, atomic##prefix##_t *v) \ +{ \ + register c_type ret; \ + __asm__ __volatile__ ( \ + " amo" #asm_op "." #asm_type ".aqrl %1, %2, %0" \ + : "+A" (v->counter), "=r" (ret) \ + : "r" (I) \ + : "memory"); \ + return ret; \ +} + +#define ATOMIC_OP_RETURN(op, asm_op, c_op, I, asm_type, c_type, prefix) \ +static inline \ +c_type atomic##prefix##_##op##_return_relaxed(c_type i, \ + atomic##prefix##_t *v) \ +{ \ + return atomic##prefix##_fetch_##op##_relaxed(i, v) c_op I; \ +} \ +static inline \ +c_type atomic##prefix##_##op##_return(c_type i, atomic##prefix##_t *v) \ +{ \ + return atomic##prefix##_fetch_##op(i, v) c_op I; \ +} + +#define ATOMIC_OPS(op, asm_op, c_op, I) \ + ATOMIC_FETCH_OP( op, asm_op, I, w, int, ) \ + ATOMIC_OP_RETURN(op, asm_op, c_op, I, w, int, ) + +ATOMIC_OPS(add, add, +, i) +ATOMIC_OPS(sub, add, +, -i) + +#define atomic_add_return_relaxed atomic_add_return_relaxed +#define atomic_sub_return_relaxed atomic_sub_return_relaxed +#define atomic_add_return atomic_add_return +#define atomic_sub_return atomic_sub_return + +#define atomic_fetch_add_relaxed atomic_fetch_add_relaxed +#define atomic_fetch_sub_relaxed atomic_fetch_sub_relaxed +#define atomic_fetch_add atomic_fetch_add +#define atomic_fetch_sub atomic_fetch_sub + +#undef ATOMIC_OPS + +#define ATOMIC_OPS(op, asm_op, I) \ + ATOMIC_FETCH_OP(op, asm_op, I, w, int, ) + +ATOMIC_OPS(and, and, i) +ATOMIC_OPS( or, or, i) +ATOMIC_OPS(xor, xor, i) + +#define atomic_fetch_and_relaxed atomic_fetch_and_relaxed +#define atomic_fetch_or_relaxed atomic_fetch_or_relaxed +#define atomic_fetch_xor_relaxed atomic_fetch_xor_relaxed +#define atomic_fetch_and atomic_fetch_and +#define atomic_fetch_or atomic_fetch_or +#define atomic_fetch_xor atomic_fetch_xor + +#undef ATOMIC_OPS + +#undef ATOMIC_FETCH_OP +#undef ATOMIC_OP_RETURN + +/* This is required to provide a full barrier on success. */ +static inline int atomic_add_unless(atomic_t *v, int a, int u) +{ + int prev, rc; + + __asm__ __volatile__ ( + "0: lr.w %[p], %[c]\n" + " beq %[p], %[u], 1f\n" + " add %[rc], %[p], %[a]\n" + " sc.w.rl %[rc], %[rc], %[c]\n" + " bnez %[rc], 0b\n" + " fence rw, rw\n" + "1:\n" + : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) + : [a]"r" (a), [u]"r" (u) + : "memory"); + return prev; +} +#define atomic_fetch_add_unless atomic_fetch_add_unless + +/* + * atomic_{cmp,}xchg is required to have exactly the same ordering semantics as + * {cmp,}xchg and the operations that return, so they need a full barrier. + */ +#define ATOMIC_OP(c_t, prefix, size) \ +static inline \ +c_t atomic##prefix##_xchg_relaxed(atomic##prefix##_t *v, c_t n) \ +{ \ + return __xchg_relaxed(&(v->counter), n, size); \ +} \ +static inline \ +c_t atomic##prefix##_xchg_acquire(atomic##prefix##_t *v, c_t n) \ +{ \ + return __xchg_acquire(&(v->counter), n, size); \ +} \ +static inline \ +c_t atomic##prefix##_xchg_release(atomic##prefix##_t *v, c_t n) \ +{ \ + return __xchg_release(&(v->counter), n, size); \ +} \ +static inline \ +c_t atomic##prefix##_xchg(atomic##prefix##_t *v, c_t n) \ +{ \ + return __xchg(&(v->counter), n, size); \ +} \ +static inline \ +c_t atomic##prefix##_cmpxchg_relaxed(atomic##prefix##_t *v, \ + c_t o, c_t n) \ +{ \ + return __cmpxchg_relaxed(&(v->counter), o, n, size); \ +} \ +static inline \ +c_t atomic##prefix##_cmpxchg_acquire(atomic##prefix##_t *v, \ + c_t o, c_t n) \ +{ \ + return __cmpxchg_acquire(&(v->counter), o, n, size); \ +} \ +static inline \ +c_t atomic##prefix##_cmpxchg_release(atomic##prefix##_t *v, \ + c_t o, c_t n) \ +{ \ + return __cmpxchg_release(&(v->counter), o, n, size); \ +} \ +static inline \ +c_t atomic##prefix##_cmpxchg(atomic##prefix##_t *v, c_t o, c_t n) \ +{ \ + return __cmpxchg(&(v->counter), o, n, size); \ +} + +#define ATOMIC_OPS() \ + ATOMIC_OP(int, , 4) + +ATOMIC_OPS() + +#define atomic_xchg_relaxed atomic_xchg_relaxed +#define atomic_xchg_acquire atomic_xchg_acquire +#define atomic_xchg_release atomic_xchg_release +#define atomic_xchg atomic_xchg +#define atomic_cmpxchg_relaxed atomic_cmpxchg_relaxed +#define atomic_cmpxchg_acquire atomic_cmpxchg_acquire +#define atomic_cmpxchg_release atomic_cmpxchg_release +#define atomic_cmpxchg atomic_cmpxchg + +#undef ATOMIC_OPS +#undef ATOMIC_OP + +static inline int atomic_sub_if_positive(atomic_t *v, int offset) +{ + int prev, rc; + + __asm__ __volatile__ ( + "0: lr.w %[p], %[c]\n" + " sub %[rc], %[p], %[o]\n" + " bltz %[rc], 1f\n" + " sc.w.rl %[rc], %[rc], %[c]\n" + " bnez %[rc], 0b\n" + " fence rw, rw\n" + "1:\n" + : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) + : [o]"r" (offset) + : "memory"); + return prev - offset; +} + +#define atomic_dec_if_positive(v) atomic_sub_if_positive(v, 1) + +#endif /* _ASM_RISCV_ATOMIC_H */ From patchwork Fri Nov 24 10:30:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii X-Patchwork-Id: 13467481 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CB8F4C61D97 for ; Fri, 24 Nov 2023 10:31:54 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.640382.998554 (Exim 4.92) (envelope-from ) id 1r6TTD-00035u-9V; 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([94.75.70.14]) by smtp.gmail.com with ESMTPSA id g1-20020a170906348100b009de3641d538sm1882374ejb.134.2023.11.24.02.31.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Nov 2023 02:31:27 -0800 (PST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: a0b9701d-8ab4-11ee-9b0e-b553b5be7939 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1700821888; x=1701426688; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=z6zyrgWKV9uY+EAKr5mS41Ot5++Nclsc1qYYGHxaNGc=; b=TIdv8Ub8Lt8XU8PBu63pNGvs0MKlPyGQGBTc+hurVGzaNOo0eEsPyncQ+RqA1UbP5R pQRVzpz802ipkx07tQiPV016sw0f5Joepfs/Z16kc7b1cX7tLEuao7rxAHcmqlu/4jCC 77ahvVJgmdEZgCWvanD9EsfwRobp+ZbQJ9qFvRpbGgn8EXcGcKOibfLMIQZfSpdiuFsy 4FT6WIVZL72q42qRglEIgqxKEnZWGMzTdOyTK7s1AKJXxfD50wiOyMPAvaRPKRNP1k3N uD1ymPdEyI2YBQO817zeUIRel74BmbZ+BnrZ+ZdC35hY7FozoWLcaR6n01U7k3AVOOWI YmAA== X-Google-DKIM-Signature: v=1; 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\ + __typeof__(new) __new = (new); \ + __typeof__(*(ptr)) __ret; \ + switch (size) { \ + case 4: \ + __asm__ __volatile__ ( \ + " amoswap.w %0, %2, %1\n" \ + : "=r" (__ret), "+A" (*__ptr) \ + : "r" (__new) \ + : "memory"); \ + break; \ + case 8: \ + __asm__ __volatile__ ( \ + " amoswap.d %0, %2, %1\n" \ + : "=r" (__ret), "+A" (*__ptr) \ + : "r" (__new) \ + : "memory"); \ + break; \ + default: \ + ASSERT_UNREACHABLE(); \ + } \ + __ret; \ +}) + +#define xchg_relaxed(ptr, x) \ +({ \ + __typeof__(*(ptr)) _x_ = (x); \ + (__typeof__(*(ptr))) __xchg_relaxed((ptr), \ + _x_, sizeof(*(ptr))); \ +}) + +#define __xchg_acquire(ptr, new, size) \ +({ \ + __typeof__(ptr) __ptr = (ptr); \ + __typeof__(new) __new = (new); \ + __typeof__(*(ptr)) __ret; \ + switch (size) { \ + case 4: \ + __asm__ __volatile__ ( \ + " amoswap.w %0, %2, %1\n" \ + RISCV_ACQUIRE_BARRIER \ + : "=r" (__ret), "+A" (*__ptr) \ + : "r" (__new) \ + : "memory"); \ + break; \ + case 8: \ + __asm__ __volatile__ ( \ + " amoswap.d %0, %2, %1\n" \ + RISCV_ACQUIRE_BARRIER \ + : "=r" (__ret), "+A" (*__ptr) \ + : "r" (__new) \ + : "memory"); \ + break; \ + default: \ + ASSERT_UNREACHABLE(); \ + } \ + __ret; \ +}) + +#define xchg_acquire(ptr, x) \ +({ \ + __typeof__(*(ptr)) _x_ = (x); \ + (__typeof__(*(ptr))) __xchg_acquire((ptr), \ + _x_, sizeof(*(ptr))); \ +}) + +#define __xchg_release(ptr, new, size) \ +({ \ + __typeof__(ptr) __ptr = (ptr); \ + __typeof__(new) __new = (new); \ + __typeof__(*(ptr)) __ret; \ + switch (size) { \ + case 4: \ + __asm__ __volatile__ ( \ + RISCV_RELEASE_BARRIER \ + " amoswap.w %0, %2, %1\n" \ + : "=r" (__ret), "+A" (*__ptr) \ + : "r" (__new) \ + : "memory"); \ + break; \ + case 8: \ + __asm__ __volatile__ ( \ + RISCV_RELEASE_BARRIER \ + " amoswap.d %0, %2, %1\n" \ + : "=r" (__ret), "+A" (*__ptr) \ + : "r" (__new) \ + : "memory"); \ + break; \ + default: \ + ASSERT_UNREACHABLE(); \ + } \ + __ret; \ +}) + +#define xchg_release(ptr, x) \ +({ \ + __typeof__(*(ptr)) _x_ = (x); \ + (__typeof__(*(ptr))) __xchg_release((ptr), \ + _x_, sizeof(*(ptr))); \ +}) + +#define __xchg(ptr, new, size) \ +({ \ + __typeof__(ptr) __ptr = (ptr); \ + __typeof__(new) __new = (new); \ + __typeof__(*(ptr)) __ret; \ + switch (size) { \ + case 4: \ + __asm__ __volatile__ ( \ + " amoswap.w.aqrl %0, %2, %1\n" \ + : "=r" (__ret), "+A" (*__ptr) \ + : "r" (__new) \ + : "memory"); \ + break; \ + case 8: \ + __asm__ __volatile__ ( \ + " amoswap.d.aqrl %0, %2, %1\n" \ + : "=r" (__ret), "+A" (*__ptr) \ + : "r" (__new) \ + : "memory"); \ + break; \ + default: \ + __ret = 0; \ + ASSERT_UNREACHABLE(); \ + } \ + __ret; \ +}) + +#define xchg(ptr, x) \ +({ \ + __typeof__(*(ptr)) _x_ = (x); \ + (__typeof__(*(ptr))) __xchg((ptr), _x_, sizeof(*(ptr))); \ +}) + +#define xchg32(ptr, x) \ +({ \ + BUILD_BUG_ON(sizeof(*(ptr)) != 4); \ + xchg((ptr), (x)); \ +}) + +#define xchg64(ptr, x) \ +({ \ + BUILD_BUG_ON(sizeof(*(ptr)) != 8); \ + xchg((ptr), (x)); \ +}) + +/* + * Atomic compare and exchange. Compare OLD with MEM, if identical, + * store NEW in MEM. Return the initial value in MEM. Success is + * indicated by comparing RETURN with OLD. + */ +#define __cmpxchg_relaxed(ptr, old, new, size) \ +({ \ + __typeof__(ptr) __ptr = (ptr); \ + __typeof__(*(ptr)) __old = (old); \ + __typeof__(*(ptr)) __new = (new); \ + __typeof__(*(ptr)) __ret; \ + register unsigned int __rc; \ + switch (size) { \ + case 4: \ + __asm__ __volatile__ ( \ + "0: lr.w %0, %2\n" \ + " bne %0, %z3, 1f\n" \ + " sc.w %1, %z4, %2\n" \ + " bnez %1, 0b\n" \ + "1:\n" \ + : "=&r" (__ret), "=&r" (__rc), "+A" (*__ptr) \ + : "rJ" (__old), "rJ" (__new) \ + : "memory"); \ + break; \ + case 8: \ + __asm__ __volatile__ ( \ + "0: lr.d %0, %2\n" \ + " bne %0, %z3, 1f\n" \ + " sc.d %1, %z4, %2\n" \ + " bnez %1, 0b\n" \ + "1:\n" \ + : "=&r" (__ret), "=&r" (__rc), "+A" (*__ptr) \ + : "rJ" (__old), "rJ" (__new) \ + : "memory"); \ + break; \ + default: \ + ASSERT_UNREACHABLE(); \ + } \ + __ret; \ +}) + +#define cmpxchg_relaxed(ptr, o, n) \ +({ \ + __typeof__(*(ptr)) _o_ = (o); \ + __typeof__(*(ptr)) _n_ = (n); \ + (__typeof__(*(ptr))) __cmpxchg_relaxed((ptr), \ + _o_, _n_, sizeof(*(ptr))); \ +}) + +#define __cmpxchg_acquire(ptr, old, new, size) \ +({ \ + __typeof__(ptr) __ptr = (ptr); \ + __typeof__(*(ptr)) __old = (old); \ + __typeof__(*(ptr)) __new = (new); \ + __typeof__(*(ptr)) __ret; \ + register unsigned int __rc; \ + switch (size) { \ + case 4: \ + __asm__ __volatile__ ( \ + "0: lr.w %0, %2\n" \ + " bne %0, %z3, 1f\n" \ + " sc.w %1, %z4, %2\n" \ + " bnez %1, 0b\n" \ + RISCV_ACQUIRE_BARRIER \ + "1:\n" \ + : "=&r" (__ret), "=&r" (__rc), "+A" (*__ptr) \ + : "rJ" (__old), "rJ" (__new) \ + : "memory"); \ + break; \ + case 8: \ + __asm__ __volatile__ ( \ + "0: lr.d %0, %2\n" \ + " bne %0, %z3, 1f\n" \ + " sc.d %1, %z4, %2\n" \ + " bnez %1, 0b\n" \ + RISCV_ACQUIRE_BARRIER \ + "1:\n" \ + : "=&r" (__ret), "=&r" (__rc), "+A" (*__ptr) \ + : "rJ" (__old), "rJ" (__new) \ + : "memory"); \ + break; \ + default: \ + ASSERT_UNREACHABLE(); \ + } \ + __ret; \ +}) + +#define cmpxchg_acquire(ptr, o, n) \ +({ \ + __typeof__(*(ptr)) _o_ = (o); \ + __typeof__(*(ptr)) _n_ = (n); \ + (__typeof__(*(ptr))) __cmpxchg_acquire((ptr), \ + _o_, _n_, sizeof(*(ptr))); \ +}) + +#define __cmpxchg_release(ptr, old, new, size) \ +({ \ + __typeof__(ptr) __ptr = (ptr); \ + __typeof__(*(ptr)) __old = (old); \ + __typeof__(*(ptr)) __new = (new); \ + __typeof__(*(ptr)) __ret; \ + register unsigned int __rc; \ + switch (size) { \ + case 4: \ + __asm__ __volatile__ ( \ + RISCV_RELEASE_BARRIER \ + "0: lr.w %0, %2\n" \ + " bne %0, %z3, 1f\n" \ + " sc.w %1, %z4, %2\n" \ + " bnez %1, 0b\n" \ + "1:\n" \ + : "=&r" (__ret), "=&r" (__rc), "+A" (*__ptr) \ + : "rJ" (__old), "rJ" (__new) \ + : "memory"); \ + break; \ + case 8: \ + __asm__ __volatile__ ( \ + RISCV_RELEASE_BARRIER \ + "0: lr.d %0, %2\n" \ + " bne %0, %z3, 1f\n" \ + " sc.d %1, %z4, %2\n" \ + " bnez %1, 0b\n" \ + "1:\n" \ + : "=&r" (__ret), "=&r" (__rc), "+A" (*__ptr) \ + : "rJ" (__old), "rJ" (__new) \ + : "memory"); \ + break; \ + default: \ + ASSERT_UNREACHABLE(); \ + } \ + __ret; \ +}) + +#define cmpxchg_release(ptr, o, n) \ +({ \ + __typeof__(*(ptr)) _o_ = (o); \ + __typeof__(*(ptr)) _n_ = (n); \ + (__typeof__(*(ptr))) __cmpxchg_release((ptr), \ + _o_, _n_, sizeof(*(ptr))); \ +}) + +#define __cmpxchg(ptr, old, new, size) \ +({ \ + __typeof__(ptr) __ptr = (ptr); \ + __typeof__(*(ptr)) __old = (__typeof__(*(ptr)))(old); \ + __typeof__(*(ptr)) __new = (__typeof__(*(ptr)))(new); \ + __typeof__(*(ptr)) __ret; \ + register unsigned int __rc; \ + switch (size) { \ + case 4: \ + __asm__ __volatile__ ( \ + "0: lr.w %0, %2\n" \ + " bne %0, %z3, 1f\n" \ + " sc.w.rl %1, %z4, %2\n" \ + " bnez %1, 0b\n" \ + " fence rw, rw\n" \ + "1:\n" \ + : "=&r" (__ret), "=&r" (__rc), "+A" (*__ptr) \ + : "rJ" (__old), "rJ" (__new) \ + : "memory"); \ + break; \ + case 8: \ + __asm__ __volatile__ ( \ + "0: lr.d %0, %2\n" \ + " bne %0, %z3, 1f\n" \ + " sc.d.rl %1, %z4, %2\n" \ + " bnez %1, 0b\n" \ + " fence rw, rw\n" \ + "1:\n" \ + : "=&r" (__ret), "=&r" (__rc), "+A" (*__ptr) \ + : "rJ" (__old), "rJ" (__new) \ + : "memory"); \ + break; \ + default: \ + __ret = 0; \ + ASSERT_UNREACHABLE(); \ + } \ + __ret; \ +}) + +#define cmpxchg(ptr, o, n) \ +({ \ + __typeof__(*(ptr)) _o_ = (o); \ + __typeof__(*(ptr)) _n_ = (n); \ + (__typeof__(*(ptr))) __cmpxchg((ptr), \ + _o_, _n_, sizeof(*(ptr))); \ +}) + +#define cmpxchg_local(ptr, o, n) \ + (__cmpxchg_relaxed((ptr), (o), (n), sizeof(*(ptr)))) + +#define cmpxchg32(ptr, o, n) \ +({ \ + BUILD_BUG_ON(sizeof(*(ptr)) != 4); \ + cmpxchg((ptr), (o), (n)); \ +}) + +#define cmpxchg32_local(ptr, o, n) \ +({ \ + BUILD_BUG_ON(sizeof(*(ptr)) != 4); \ + cmpxchg_relaxed((ptr), (o), (n)) \ +}) + +#define cmpxchg64(ptr, o, n) \ +({ \ + BUILD_BUG_ON(sizeof(*(ptr)) != 8); \ + cmpxchg((ptr), (o), (n)); \ +}) + +#define cmpxchg64_local(ptr, o, n) \ +({ \ + BUILD_BUG_ON(sizeof(*(ptr)) != 8); \ + cmpxchg_relaxed((ptr), (o), (n)); \ +}) + +#endif /* _ASM_RISCV_CMPXCHG_H */ From patchwork Fri Nov 24 10:30:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii X-Patchwork-Id: 13467479 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 15B6FC61DF4 for ; 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([94.75.70.14]) by smtp.gmail.com with ESMTPSA id g1-20020a170906348100b009de3641d538sm1882374ejb.134.2023.11.24.02.31.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Nov 2023 02:31:28 -0800 (PST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: a1a6cbda-8ab4-11ee-9b0e-b553b5be7939 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1700821889; x=1701426689; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=C1jvDsawJ31XovOPo0nLihxqmUBfwMrjgsOrZCb823c=; b=dwYt15DWg9P8nkaJFu4NiRpgSHbaVd6jIWt7yGEo7Q6U++XR0acjqMUr/bVKWe8n07 mhPE6iyIQhNzfVY1e3RyzmJGXtpHSGyiNAoyooXXnLbqNo4OJm8jdsePltlJupSrXseo M2A1idJTAZ4E/uW6NJOwNR8wfQglJtmN5rfGNKAPq7DGdUkQejeoK3hP6TkRwdKiajPp Sgbh92cDFfjcovPskCuFToUaklR1AxBRzJYK6ewv8H4TtuethpRW1pvECthPEY+qxtQL LfM5uAcCv7bxz8r4po+cgI06/aAGagLRKmFMeesBwormthe7gy0d/wfWGNSzReOS5m05 lSMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700821889; x=1701426689; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=C1jvDsawJ31XovOPo0nLihxqmUBfwMrjgsOrZCb823c=; b=Ds6L3CbdR28CLxnC4jCuCgBqEKfB6enUPZzpXqP87OX3ewuqHOqu2CKtW2yAb+DHkh 5Q3Hi9pbZ8LH2jVpo0zuWr/LUVxGgs1Dxj100NsxlHvUdw9MPYfbS6ZD0jCf7hM/GvHL /s3Nlk4VJH2gr1pgogtGzNzdidD2JkTPFtn0TU0GN3oJtIfrcy7c8GTed3Ot9o5ZFQQ6 5QuJiU769bflWw68zck00k6KK/2yo5DFNUtD+c+zcH/7mJqMG2821cT96tlZZEJRu2KX WiSUjZpmADWe1cisIRo8VdnvAHxiq896atfkprUJY/nvfrdAtsm69iNZAZyrLyi9u6yO qDcw== X-Gm-Message-State: AOJu0Yx//8iPSf3MBSkjElV3bd70naj6Xd7raATJitZ68lsaN903PPaI 3YbDifcZ8cIlxLQs4gGPAEP9G5+AZ7HZ4w== X-Google-Smtp-Source: AGHT+IH1BjL6fZIUCzu3aiDD79RyC6q7nlBs9yd2qn1CwU21TpTlZBja/OKgtBaSgAMTM6e1le79nA== X-Received: by 2002:a17:906:7158:b0:a03:9dfb:5298 with SMTP id z24-20020a170906715800b00a039dfb5298mr1782312ejj.57.1700821889234; Fri, 24 Nov 2023 02:31:29 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini , Wei Liu Subject: [PATCH v2 19/39] xen/riscv: introduce asm/io.h Date: Fri, 24 Nov 2023 12:30:39 +0200 Message-ID: <5fdef2f1039c4c7c9d213e77f4d3dec3ada9c1d6.1700761381.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: References: MIME-Version: 1.0 Signed-off-by: Oleksii Kurochko --- Changes in V2: - Nothing changed. Only rebase. --- xen/arch/riscv/include/asm/io.h | 134 ++++++++++++++++++++++++++++++++ 1 file changed, 134 insertions(+) create mode 100644 xen/arch/riscv/include/asm/io.h diff --git a/xen/arch/riscv/include/asm/io.h b/xen/arch/riscv/include/asm/io.h new file mode 100644 index 0000000000..987fddf902 --- /dev/null +++ b/xen/arch/riscv/include/asm/io.h @@ -0,0 +1,134 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Taken and modified from Linux. + * + * {read,write}{b,w,l,q} based on arch/arm64/include/asm/io.h + * which was based on arch/arm/include/io.h + * + * Copyright (C) 1996-2000 Russell King + * Copyright (C) 2012 ARM Ltd. + * Copyright (C) 2014 Regents of the University of California + */ + +#ifndef _ASM_RISCV_IO_H +#define _ASM_RISCV_IO_H + +#include + +/* + * The RISC-V ISA doesn't yet specify how to query or modify PMAs, so we can't + * change the properties of memory regions. This should be fixed by the + * upcoming platform spec. + */ +#define ioremap_nocache(addr, size) ioremap((addr), (size)) +#define ioremap_wc(addr, size) ioremap((addr), (size)) +#define ioremap_wt(addr, size) ioremap((addr), (size)) + +/* Generic IO read/write. These perform native-endian accesses. */ +#define __raw_writeb __raw_writeb +static inline void __raw_writeb(u8 val, volatile void __iomem *addr) +{ + asm volatile("sb %0, 0(%1)" : : "r" (val), "r" (addr)); +} + +#define __raw_writew __raw_writew +static inline void __raw_writew(u16 val, volatile void __iomem *addr) +{ + asm volatile("sh %0, 0(%1)" : : "r" (val), "r" (addr)); +} + +#define __raw_writel __raw_writel +static inline void __raw_writel(u32 val, volatile void __iomem *addr) +{ + asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr)); +} + +#ifdef CONFIG_64BIT +#define __raw_writeq __raw_writeq +static inline void __raw_writeq(u64 val, volatile void __iomem *addr) +{ + asm volatile("sd %0, 0(%1)" : : "r" (val), "r" (addr)); +} +#endif + +#define __raw_readb __raw_readb +static inline u8 __raw_readb(const volatile void __iomem *addr) +{ + u8 val; + + asm volatile("lb %0, 0(%1)" : "=r" (val) : "r" (addr)); + return val; +} + +#define __raw_readw __raw_readw +static inline u16 __raw_readw(const volatile void __iomem *addr) +{ + u16 val; + + asm volatile("lh %0, 0(%1)" : "=r" (val) : "r" (addr)); + return val; +} + +#define __raw_readl __raw_readl +static inline u32 __raw_readl(const volatile void __iomem *addr) +{ + u32 val; + + asm volatile("lw %0, 0(%1)" : "=r" (val) : "r" (addr)); + return val; +} + +#ifdef CONFIG_64BIT +#define __raw_readq __raw_readq +static inline u64 __raw_readq(const volatile void __iomem *addr) +{ + u64 val; + + asm volatile("ld %0, 0(%1)" : "=r" (val) : "r" (addr)); + return val; +} +#endif + +/* + * Unordered I/O memory access primitives. These are even more relaxed than + * the relaxed versions, as they don't even order accesses between successive + * operations to the I/O regions. + */ +#define readb_cpu(c) ({ u8 __r = __raw_readb(c); __r; }) +#define readw_cpu(c) ({ u16 __r = le16_to_cpu((__force __le16)__raw_readw(c)); __r; }) +#define readl_cpu(c) ({ u32 __r = le32_to_cpu((__force __le32)__raw_readl(c)); __r; }) + +#define writeb_cpu(v,c) ((void)__raw_writeb((v),(c))) +#define writew_cpu(v,c) ((void)__raw_writew((__force u16)cpu_to_le16(v),(c))) +#define writel_cpu(v,c) ((void)__raw_writel((__force u32)cpu_to_le32(v),(c))) + +#ifdef CONFIG_64BIT +#define readq_cpu(c) ({ u64 __r = le64_to_cpu((__force __le64)__raw_readq(c)); __r; }) +#define writeq_cpu(v,c) ((void)__raw_writeq((__force u64)cpu_to_le64(v),(c))) +#endif + +/* + * I/O memory access primitives. Reads are ordered relative to any + * following Normal memory access. Writes are ordered relative to any prior + * Normal memory access. The memory barriers here are necessary as RISC-V + * doesn't define any ordering between the memory space and the I/O space. + */ +#define __io_br() do {} while (0) +#define __io_ar(v) __asm__ __volatile__ ("fence i,r" : : : "memory"); +#define __io_bw() __asm__ __volatile__ ("fence w,o" : : : "memory"); +#define __io_aw() do { } while (0) + +#define readb(c) ({ u8 __v; __io_br(); __v = readb_cpu(c); __io_ar(__v); __v; }) +#define readw(c) ({ u16 __v; __io_br(); __v = readw_cpu(c); __io_ar(__v); __v; }) +#define readl(c) ({ u32 __v; __io_br(); __v = readl_cpu(c); __io_ar(__v); __v; }) + +#define writeb(v,c) ({ __io_bw(); writeb_cpu((v),(c)); __io_aw(); }) +#define writew(v,c) ({ __io_bw(); writew_cpu((v),(c)); __io_aw(); }) +#define writel(v,c) ({ __io_bw(); writel_cpu((v),(c)); __io_aw(); }) + +#ifdef CONFIG_64BIT +#define readq(c) ({ u64 __v; __io_br(); __v = readq_cpu(c); __io_ar(__v); __v; }) +#define writeq(v,c) ({ __io_bw(); writeq_cpu((v),(c)); __io_aw(); }) +#endif + +#endif /* _ASM_RISCV_IO_H */ From patchwork Fri Nov 24 10:30:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii X-Patchwork-Id: 13467513 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 129BEC61DF4 for ; Fri, 24 Nov 2023 10:42:38 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.640464.998756 (Exim 4.92) (envelope-from ) id 1r6Tdg-0004uC-6O; Fri, 24 Nov 2023 10:42:24 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 640464.998756; Fri, 24 Nov 2023 10:42:24 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1r6Tdg-0004tK-2t; Fri, 24 Nov 2023 10:42:24 +0000 Received: by outflank-mailman (input) for mailman id 640464; Fri, 24 Nov 2023 10:42:22 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1r6TTA-0006hy-29 for xen-devel@lists.xenproject.org; Fri, 24 Nov 2023 10:31:32 +0000 Received: from mail-ed1-x533.google.com (mail-ed1-x533.google.com [2a00:1450:4864:20::533]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id a21746d4-8ab4-11ee-98e2-6d05b1d4d9a1; Fri, 24 Nov 2023 11:31:31 +0100 (CET) Received: by mail-ed1-x533.google.com with SMTP id 4fb4d7f45d1cf-5441ba3e53cso2377807a12.1 for ; Fri, 24 Nov 2023 02:31:31 -0800 (PST) Received: from fedora.. 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Only rebase. --- xen/arch/riscv/xen.lds.S | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/xen/arch/riscv/xen.lds.S b/xen/arch/riscv/xen.lds.S index 3fa7db3bf9..a10e0ad87c 100644 --- a/xen/arch/riscv/xen.lds.S +++ b/xen/arch/riscv/xen.lds.S @@ -45,6 +45,16 @@ SECTIONS . = ALIGN(PAGE_SIZE); .rodata : { _srodata = .; /* Read-only data */ + /* Bug frames table */ + __start_bug_frames = .; + *(.bug_frames.0) + __stop_bug_frames_0 = .; + *(.bug_frames.1) + __stop_bug_frames_1 = .; + *(.bug_frames.2) + __stop_bug_frames_2 = .; + *(.bug_frames.3) + __stop_bug_frames_3 = .; *(.rodata) *(.rodata.*) *(.data.rel.ro) From patchwork Fri Nov 24 10:30:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii X-Patchwork-Id: 13467502 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CCA8EC61DF4 for ; Fri, 24 Nov 2023 10:40:01 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.640438.998686 (Exim 4.92) (envelope-from ) id 1r6TbG-0006l4-44; Fri, 24 Nov 2023 10:39:54 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 640438.998686; Fri, 24 Nov 2023 10:39:54 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1r6TbF-0006iP-PT; Fri, 24 Nov 2023 10:39:53 +0000 Received: by outflank-mailman (input) for mailman id 640438; Fri, 24 Nov 2023 10:39:52 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1r6TTB-0006hy-80 for xen-devel@lists.xenproject.org; Fri, 24 Nov 2023 10:31:33 +0000 Received: from mail-ej1-x62d.google.com (mail-ej1-x62d.google.com [2a00:1450:4864:20::62d]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id a2b94eba-8ab4-11ee-98e2-6d05b1d4d9a1; Fri, 24 Nov 2023 11:31:32 +0100 (CET) Received: by mail-ej1-x62d.google.com with SMTP id a640c23a62f3a-a00c200782dso254455666b.1 for ; Fri, 24 Nov 2023 02:31:32 -0800 (PST) Received: from fedora.. ([94.75.70.14]) by smtp.gmail.com with ESMTPSA id g1-20020a170906348100b009de3641d538sm1882374ejb.134.2023.11.24.02.31.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Nov 2023 02:31:31 -0800 (PST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: a2b94eba-8ab4-11ee-98e2-6d05b1d4d9a1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1700821891; x=1701426691; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=b0V+5S8U4gOZUoEwGD71e+WEGaWmpek3DzntqBhyokA=; b=ax5M9HFOrr1+ebpURsHh3hX7bCKHrB6bYI0EYJYEdI7l/EEpY/i0FuwmvbthTysINt XEWFtty6RKKkFhPpkKGV4hqLkIxHTTRuc3h96mdHEuKii793dA0zeMFVJlU/5FBDcflv uRV0NPnIai48UHt1l9weqsnNIwuTB3NL//1MxVCOfifIHTzZfkaEVYGiG8HCi1RT2AJl dBW4Xk1Kb5K/yA7YDga9yT2EaOnGSpjQENNilikAWLWAGCYI8xcUASQDkjnkdT8iHzBx rdZx34Memz+olA8tW8dtyquAd3NmaSd6MTWDs6/gnUWho0wcotJUcgnIZbEzok+vTRcj k13Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700821891; x=1701426691; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=b0V+5S8U4gOZUoEwGD71e+WEGaWmpek3DzntqBhyokA=; b=bHbBoLT9pZ7AKmSgIAA8SpQi1nvQ2V0YapPm/8xzU7y9cQorV7/eILSeBC0HvjryYF mr95ODhViXv2d5F5wLNNIdqeFSorCYmEWex5notVo6xZWWgXZRNBNgE0xlTkyiGRfeUr gKdxBD4uvjo909M8B91aiL8r+11DQKtYiCNpAqvijZWfUiiqsW3Lt+PHoXhyiqBOFmG5 U4C8Hc+6AtdapEqbZBgQD0NPdpkwXhL/KElUcrX/x2l0k5Qep+4edCDc/l4JSlEHtFgC MHR7gqsFJvl+F3G76RiU7PbZn0YADQHG0QACFPRw4ce+BFsBv6f8Nwjmo4f+meOTVG0K fLmw== X-Gm-Message-State: AOJu0YzwhubqHsC+SzNjaraM2a5c2kiS5obqtqjV6J8fPU1gTQWXrbMe LJU+jPeHrtbi9fNylzNaaRwDh5eZxnReRg== X-Google-Smtp-Source: AGHT+IH/GAOh8Kpk2bWC0miN/+Y2n1wlkrcA/6D90k406fXKp10il+UnUUrRo4C+fZsNj9gor8lTHw== X-Received: by 2002:a17:906:118:b0:9e4:6ff2:131a with SMTP id 24-20020a170906011800b009e46ff2131amr1712667eje.48.1700821891564; Fri, 24 Nov 2023 02:31:31 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini , Wei Liu Subject: [PATCH v2 21/39] xen/riscv: introduce bit operations Date: Fri, 24 Nov 2023 12:30:41 +0200 Message-ID: <20732007fb103115c0e01cefea7d113b8a7ad8e9.1700761381.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: References: MIME-Version: 1.0 Signed-off-by: Oleksii Kurochko --- Changes in V2: - Nothing changed. Only rebase. --- xen/arch/riscv/Makefile | 1 + xen/arch/riscv/lib/Makefile | 1 + xen/arch/riscv/lib/find_next_bit.c | 278 +++++++++++++++++++++++++++++ 3 files changed, 280 insertions(+) create mode 100644 xen/arch/riscv/lib/Makefile create mode 100644 xen/arch/riscv/lib/find_next_bit.c diff --git a/xen/arch/riscv/Makefile b/xen/arch/riscv/Makefile index 2fefe14e7c..b08048948f 100644 --- a/xen/arch/riscv/Makefile +++ b/xen/arch/riscv/Makefile @@ -1,5 +1,6 @@ obj-$(CONFIG_EARLY_PRINTK) += early_printk.o obj-y += entry.o +obj-y += lib/ obj-y += mm.o obj-$(CONFIG_RISCV_64) += riscv64/ obj-y += sbi.o diff --git a/xen/arch/riscv/lib/Makefile b/xen/arch/riscv/lib/Makefile new file mode 100644 index 0000000000..6fae6a1f10 --- /dev/null +++ b/xen/arch/riscv/lib/Makefile @@ -0,0 +1 @@ +obj-y += find_next_bit.o diff --git a/xen/arch/riscv/lib/find_next_bit.c b/xen/arch/riscv/lib/find_next_bit.c new file mode 100644 index 0000000000..ac5a4687e3 --- /dev/null +++ b/xen/arch/riscv/lib/find_next_bit.c @@ -0,0 +1,278 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * find_next_bit.c: fallback find next bit implementation + * + * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + */ +#include +#include +#include + +#ifndef find_next_bit +/* + * Find the next set bit in a memory region. + */ +unsigned long find_next_bit(const unsigned long *addr, unsigned long size, + unsigned long offset) +{ + const unsigned long *p = addr + BIT_WORD(offset); + unsigned long result = offset & ~(BITS_PER_LONG-1); + unsigned long tmp; + + if (offset >= size) + return size; + size -= result; + offset %= BITS_PER_LONG; + if (offset) { + tmp = *(p++); + tmp &= (~0UL << offset); + if (size < BITS_PER_LONG) + goto found_first; + if (tmp) + goto found_middle; + size -= BITS_PER_LONG; + result += BITS_PER_LONG; + } + while (size & ~(BITS_PER_LONG-1)) { + if ((tmp = *(p++))) + goto found_middle; + result += BITS_PER_LONG; + size -= BITS_PER_LONG; + } + if (!size) + return result; + tmp = *p; + +found_first: + tmp &= (~0UL >> (BITS_PER_LONG - size)); + if (tmp == 0UL) /* Are any bits set? */ + return result + size; /* Nope. */ +found_middle: + return result + __ffs(tmp); +} +EXPORT_SYMBOL(find_next_bit); +#endif + +#ifndef find_next_zero_bit +/* + * This implementation of find_{first,next}_zero_bit was stolen from + * Linus' asm-alpha/bitops.h. + */ +unsigned long find_next_zero_bit(const unsigned long *addr, unsigned long size, + unsigned long offset) +{ + const unsigned long *p = addr + BIT_WORD(offset); + unsigned long result = offset & ~(BITS_PER_LONG-1); + unsigned long tmp; + + if (offset >= size) + return size; + size -= result; + offset %= BITS_PER_LONG; + if (offset) { + tmp = *(p++); + tmp |= ~0UL >> (BITS_PER_LONG - offset); + if (size < BITS_PER_LONG) + goto found_first; + if (~tmp) + goto found_middle; + size -= BITS_PER_LONG; + result += BITS_PER_LONG; + } + while (size & ~(BITS_PER_LONG-1)) { + if (~(tmp = *(p++))) + goto found_middle; + result += BITS_PER_LONG; + size -= BITS_PER_LONG; + } + if (!size) + return result; + tmp = *p; + +found_first: + tmp |= ~0UL << size; + if (tmp == ~0UL) /* Are any bits zero? */ + return result + size; /* Nope. */ +found_middle: + return result + ffz(tmp); +} +EXPORT_SYMBOL(find_next_zero_bit); +#endif + +#ifndef find_first_bit +/* + * Find the first set bit in a memory region. + */ +unsigned long find_first_bit(const unsigned long *addr, unsigned long size) +{ + const unsigned long *p = addr; + unsigned long result = 0; + unsigned long tmp; + + while (size & ~(BITS_PER_LONG-1)) { + if ((tmp = *(p++))) + goto found; + result += BITS_PER_LONG; + size -= BITS_PER_LONG; + } + if (!size) + return result; + + tmp = (*p) & (~0UL >> (BITS_PER_LONG - size)); + if (tmp == 0UL) /* Are any bits set? */ + return result + size; /* Nope. */ +found: + return result + __ffs(tmp); +} +EXPORT_SYMBOL(find_first_bit); +#endif + +#ifndef find_first_zero_bit +/* + * Find the first cleared bit in a memory region. + */ +unsigned long find_first_zero_bit(const unsigned long *addr, unsigned long size) +{ + const unsigned long *p = addr; + unsigned long result = 0; + unsigned long tmp; + + while (size & ~(BITS_PER_LONG-1)) { + if (~(tmp = *(p++))) + goto found; + result += BITS_PER_LONG; + size -= BITS_PER_LONG; + } + if (!size) + return result; + + tmp = (*p) | (~0UL << size); + if (tmp == ~0UL) /* Are any bits zero? */ + return result + size; /* Nope. */ +found: + return result + ffz(tmp); +} +EXPORT_SYMBOL(find_first_zero_bit); +#endif + +#ifdef __BIG_ENDIAN + +/* include/linux/byteorder does not support "unsigned long" type */ +static inline unsigned long ext2_swabp(const unsigned long * x) +{ +#if BITS_PER_LONG == 64 + return (unsigned long) __swab64p((u64 *) x); +#elif BITS_PER_LONG == 32 + return (unsigned long) __swab32p((u32 *) x); +#else +#error BITS_PER_LONG not defined +#endif +} + +/* include/linux/byteorder doesn't support "unsigned long" type */ +static inline unsigned long ext2_swab(const unsigned long y) +{ +#if BITS_PER_LONG == 64 + return (unsigned long) __swab64((u64) y); +#elif BITS_PER_LONG == 32 + return (unsigned long) __swab32((u32) y); +#else +#error BITS_PER_LONG not defined +#endif +} + +#ifndef find_next_zero_bit_le +unsigned long find_next_zero_bit_le(const void *addr, unsigned + long size, unsigned long offset) +{ + const unsigned long *p = addr; + unsigned long result = offset & ~(BITS_PER_LONG - 1); + unsigned long tmp; + + if (offset >= size) + return size; + p += BIT_WORD(offset); + size -= result; + offset &= (BITS_PER_LONG - 1UL); + if (offset) { + tmp = ext2_swabp(p++); + tmp |= (~0UL >> (BITS_PER_LONG - offset)); + if (size < BITS_PER_LONG) + goto found_first; + if (~tmp) + goto found_middle; + size -= BITS_PER_LONG; + result += BITS_PER_LONG; + } + + while (size & ~(BITS_PER_LONG - 1)) { + if (~(tmp = *(p++))) + goto found_middle_swap; + result += BITS_PER_LONG; + size -= BITS_PER_LONG; + } + if (!size) + return result; + tmp = ext2_swabp(p); +found_first: + tmp |= ~0UL << size; + if (tmp == ~0UL) /* Are any bits zero? */ + return result + size; /* Nope. Skip ffz */ +found_middle: + return result + ffz(tmp); + +found_middle_swap: + return result + ffz(ext2_swab(tmp)); +} +EXPORT_SYMBOL(find_next_zero_bit_le); +#endif + +#ifndef find_next_bit_le +unsigned long find_next_bit_le(const void *addr, unsigned + long size, unsigned long offset) +{ + const unsigned long *p = addr; + unsigned long result = offset & ~(BITS_PER_LONG - 1); + unsigned long tmp; + + if (offset >= size) + return size; + p += BIT_WORD(offset); + size -= result; + offset &= (BITS_PER_LONG - 1UL); + if (offset) { + tmp = ext2_swabp(p++); + tmp &= (~0UL << offset); + if (size < BITS_PER_LONG) + goto found_first; + if (tmp) + goto found_middle; + size -= BITS_PER_LONG; + result += BITS_PER_LONG; + } + + while (size & ~(BITS_PER_LONG - 1)) { + tmp = *(p++); + if (tmp) + goto found_middle_swap; + result += BITS_PER_LONG; + size -= BITS_PER_LONG; + } + if (!size) + return result; + tmp = ext2_swabp(p); +found_first: + tmp &= (~0UL >> (BITS_PER_LONG - size)); + if (tmp == 0UL) /* Are any bits set? */ + return result + size; /* Nope. */ +found_middle: + return result + __ffs(tmp); + +found_middle_swap: + return result + __ffs(ext2_swab(tmp)); +} +EXPORT_SYMBOL(find_next_bit_le); +#endif + +#endif /* __BIG_ENDIAN */ From patchwork Fri Nov 24 10:30:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii X-Patchwork-Id: 13467500 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 597ABC61D97 for ; Fri, 24 Nov 2023 10:39:48 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.640428.998653 (Exim 4.92) (envelope-from ) id 1r6Tb4-0005O3-Il; Fri, 24 Nov 2023 10:39:42 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 640428.998653; Fri, 24 Nov 2023 10:39:42 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1r6Tb4-0005Np-G0; Fri, 24 Nov 2023 10:39:42 +0000 Received: by outflank-mailman (input) for mailman id 640428; Fri, 24 Nov 2023 10:39:41 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1r6TTC-0006hy-6I for xen-devel@lists.xenproject.org; Fri, 24 Nov 2023 10:31:34 +0000 Received: from mail-ej1-x636.google.com (mail-ej1-x636.google.com [2a00:1450:4864:20::636]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id a36b0e0d-8ab4-11ee-98e2-6d05b1d4d9a1; Fri, 24 Nov 2023 11:31:33 +0100 (CET) Received: by mail-ej1-x636.google.com with SMTP id a640c23a62f3a-a02ba1f500fso254069466b.0 for ; Fri, 24 Nov 2023 02:31:33 -0800 (PST) Received: from fedora.. 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Only rebase. --- xen/arch/riscv/include/asm/domain.h | 43 +++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 xen/arch/riscv/include/asm/domain.h diff --git a/xen/arch/riscv/include/asm/domain.h b/xen/arch/riscv/include/asm/domain.h new file mode 100644 index 0000000000..f2dccf370f --- /dev/null +++ b/xen/arch/riscv/include/asm/domain.h @@ -0,0 +1,43 @@ +#ifndef __ASM_RISCV_DOMAIN_H__ +#define __ASM_RISCV_DOMAIN_H__ + +#include +#include + +struct hvm_domain +{ + uint64_t params[HVM_NR_PARAMS]; +}; + +#define is_domain_direct_mapped(d) ((void)(d), 0) + +struct arch_vcpu_io { +}; + +struct arch_vcpu { +}; + +struct arch_domain { + struct hvm_domain hvm; +}; + +#include + +static inline struct vcpu_guest_context *alloc_vcpu_guest_context(void) +{ + return xmalloc(struct vcpu_guest_context); +} + +static inline void free_vcpu_guest_context(struct vcpu_guest_context *vgc) +{ + xfree(vgc); +} + +struct guest_memory_policy {}; +static inline void update_guest_memory_policy(struct vcpu *v, + struct guest_memory_policy *gmp) +{} + +static inline void arch_vcpu_block(struct vcpu *v) {} + +#endif /* __ASM_RISCV_DOMAIN_H__ */ From patchwork Fri Nov 24 10:30:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii X-Patchwork-Id: 13467505 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7A81FC61D97 for ; Fri, 24 Nov 2023 10:40:09 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.640440.998703 (Exim 4.92) (envelope-from ) id 1r6TbI-0007QP-7R; Fri, 24 Nov 2023 10:39:56 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 640440.998703; Fri, 24 Nov 2023 10:39:56 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1r6TbI-0007QA-4a; Fri, 24 Nov 2023 10:39:56 +0000 Received: by outflank-mailman (input) for mailman id 640440; Fri, 24 Nov 2023 10:39:55 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1r6TTG-0006hx-AF for xen-devel@lists.xenproject.org; Fri, 24 Nov 2023 10:31:38 +0000 Received: from mail-ej1-x62c.google.com (mail-ej1-x62c.google.com [2a00:1450:4864:20::62c]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id a4207aef-8ab4-11ee-9b0e-b553b5be7939; Fri, 24 Nov 2023 11:31:34 +0100 (CET) Received: by mail-ej1-x62c.google.com with SMTP id a640c23a62f3a-a002562bd8bso338542166b.0 for ; Fri, 24 Nov 2023 02:31:34 -0800 (PST) Received: from fedora.. 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Fri, 24 Nov 2023 02:31:34 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini , Wei Liu Subject: [PATCH v2 24/39] xen/riscv: introduce asm/irq.h Date: Fri, 24 Nov 2023 12:30:44 +0200 Message-ID: X-Mailer: git-send-email 2.42.0 In-Reply-To: References: MIME-Version: 1.0 Signed-off-by: Oleksii Kurochko --- Changes in V2: - add ifdef CONFIG_HAS_DEVICE_TREE for things that shouldn't be in case !CONFIG_HAS_DEVICE_TREE - use proper includes. --- xen/arch/riscv/include/asm/irq.h | 37 ++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 xen/arch/riscv/include/asm/irq.h diff --git a/xen/arch/riscv/include/asm/irq.h b/xen/arch/riscv/include/asm/irq.h new file mode 100644 index 0000000000..ca49d3f9b4 --- /dev/null +++ b/xen/arch/riscv/include/asm/irq.h @@ -0,0 +1,37 @@ +#ifndef __ASM_RISCV_IRQ_H__ +#define __ASM_RISCV_IRQ_H__ + +#include +#ifdef CONFIG_HAS_DEVICE_TREE +#include +#endif + +/* TODO */ +#define nr_irqs 0U +#define nr_static_irqs 0 +#define arch_hwdom_irqs(domid) 0U + +#define domain_pirq_to_irq(d, pirq) (pirq) + +#define arch_evtchn_bind_pirq(d, pirq) ((void)((d) + (pirq))) + +struct arch_pirq { +}; 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([94.75.70.14]) by smtp.gmail.com with ESMTPSA id g1-20020a170906348100b009de3641d538sm1882374ejb.134.2023.11.24.02.31.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Nov 2023 02:31:35 -0800 (PST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: a55788b0-8ab4-11ee-9b0e-b553b5be7939 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1700821896; x=1701426696; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DJRjUvdwuuad2efuExKOiQ+ed+OjR0ZfoiyU0hrJwyQ=; b=BLCH2jOgcpPZz0xTBNyf6oSdRS/LJqn5Irh0ACRl0XaANNUcxPeMtwv8IUar9ygayC rgMB4/XB21A2Z0dkMgbppZQ1CieVFEwEZ8crr+TPzpobdVwHIV8dyeCwDsyCIVCJ4vPP daG+Xyghv4PXJT4Vni1BwD4bW7JmI0JARcvCOyu+2Adqr9G6bCvgAInCv8u070EkDukx YsSjldkM8R5aSKMBz32lA4q+lg4ZFNjh7TSqqICNOaJYDQfF0YSFJAvpyR1mfNxjqb6P /1rSI6XnQbpiNTgmiz9eRE/oZQOmmXxn6GXViljLvBqHA5iyhJDYQanez9EZ+/bNcM+i CAfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700821896; x=1701426696; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DJRjUvdwuuad2efuExKOiQ+ed+OjR0ZfoiyU0hrJwyQ=; b=mmTxNBFfvxaqyuAKKoATd3vTNfS2zESXVQddM/ittAMG3sBSoG1BRSPj0wBfJBjOhb r/n0LaQzjUwhEdjpLClFMKrsNTQ21tj4HCk0eeQ04FYKj16NriGV41n0IDQEP5Af68Ns CR25bofY/xv0G1YJLqSBwc1fi+tccqINgu34woR2NFimCsBy7AACLTjGb4ZcTcnY/vIE zd4opRnd27ez0eljfKkm4d0SQEvMSuXwHEGtZ7U4iAHcvONItAVwvAv5Tf0kd+iX3PZK yeoempW38VMNKdILPJku7lNQWWt2QMkoh1EE6BG3qr5dpjSIl2Cq92RSLIVMSWjOyl0n iztA== X-Gm-Message-State: AOJu0Yy7eVCu4dWdIdsUZ+6UooTKgoNHc/ePH1j0w7pdnXvsqOcUFdmp pDZD0ll3WnTX933I+VAehipXX8Mj9d8B0g== X-Google-Smtp-Source: AGHT+IGpih3co3kvDZv/3jxn98aNZyNxgpf5T1LzAvpcmJAKB7f7T7q7e77bVQTfk3l7qT4x1EBIYg== X-Received: by 2002:a17:906:b6d3:b0:a03:a3c4:ed99 with SMTP id ec19-20020a170906b6d300b00a03a3c4ed99mr1807229ejb.41.1700821895729; Fri, 24 Nov 2023 02:31:35 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini , Wei Liu Subject: [PATCH v2 25/39] xen/riscv: introduce asm/p2m.h Date: Fri, 24 Nov 2023 12:30:45 +0200 Message-ID: X-Mailer: git-send-email 2.42.0 In-Reply-To: References: MIME-Version: 1.0 Signed-off-by: Oleksii Kurochko --- Changes in V2: - Nothing changed. Only rebase. --- xen/arch/riscv/include/asm/p2m.h | 105 +++++++++++++++++++++++++++++++ 1 file changed, 105 insertions(+) create mode 100644 xen/arch/riscv/include/asm/p2m.h diff --git a/xen/arch/riscv/include/asm/p2m.h b/xen/arch/riscv/include/asm/p2m.h new file mode 100644 index 0000000000..993aec6d2c --- /dev/null +++ b/xen/arch/riscv/include/asm/p2m.h @@ -0,0 +1,105 @@ +#ifndef __ASM_RISCV_P2M_H__ +#define __ASM_RISCV_P2M_H__ + +#include + +#define paddr_bits PADDR_BITS + +/* + * List of possible type for each page in the p2m entry. + * The number of available bit per page in the pte for this purpose is 4 bits. + * So it's possible to only have 16 fields. If we run out of value in the + * future, it's possible to use higher value for pseudo-type and don't store + * them in the p2m entry. + */ +typedef enum { + p2m_invalid = 0, /* Nothing mapped here */ + p2m_ram_rw, /* Normal read/write guest RAM */ + p2m_ram_ro, /* Read-only; writes are silently dropped */ + p2m_mmio_direct_dev,/* Read/write mapping of genuine Device MMIO area */ + p2m_mmio_direct_nc, /* Read/write mapping of genuine MMIO area non-cacheable */ + p2m_mmio_direct_c, /* Read/write mapping of genuine MMIO area cacheable */ + p2m_map_foreign_rw, /* Read/write RAM pages from foreign domain */ + p2m_map_foreign_ro, /* Read-only RAM pages from foreign domain */ + p2m_grant_map_rw, /* Read/write grant mapping */ + p2m_grant_map_ro, /* Read-only grant mapping */ + /* The types below are only used to decide the page attribute in the P2M */ + p2m_iommu_map_rw, /* Read/write iommu mapping */ + p2m_iommu_map_ro, /* Read-only iommu mapping */ + p2m_max_real_type, /* Types after this won't be store in the p2m */ +} p2m_type_t; + +#include + +static inline int get_page_and_type(struct page_info *page, + struct domain *domain, + unsigned long type) +{ + BUG(); + return 1; +} + +/* Look up a GFN and take a reference count on the backing page. */ +typedef unsigned int p2m_query_t; +#define P2M_ALLOC (1u<<0) /* Populate PoD and paged-out entries */ +#define P2M_UNSHARE (1u<<1) /* Break CoW sharing */ + +static inline struct page_info *get_page_from_gfn( + struct domain *d, unsigned long gfn, p2m_type_t *t, p2m_query_t q) +{ + BUG(); + return NULL; +} + +static inline void memory_type_changed(struct domain *d) +{ + BUG(); +} + + +static inline int guest_physmap_mark_populate_on_demand(struct domain *d, unsigned long gfn, + unsigned int order) +{ + BUG(); + return 1; +} + +static inline int guest_physmap_add_entry(struct domain *d, + gfn_t gfn, + mfn_t mfn, + unsigned long page_order, + p2m_type_t t) +{ + BUG(); + return 1; +} + +/* Untyped version for RAM only, for compatibility */ +static inline int __must_check +guest_physmap_add_page(struct domain *d, gfn_t gfn, mfn_t mfn, + unsigned int page_order) +{ + return guest_physmap_add_entry(d, gfn, mfn, page_order, p2m_ram_rw); +} + +static inline mfn_t gfn_to_mfn(struct domain *d, gfn_t gfn) +{ + BUG(); + return _mfn(0); +} + +static inline bool arch_acquire_resource_check(struct domain *d) +{ + /* + * The reference counting of foreign entries in set_foreign_p2m_entry() + * is supported on RISCV. + */ + return true; +} + +static inline void p2m_altp2m_check(struct vcpu *v, uint16_t idx) +{ + /* Not supported on RISCV. */ +} + +#endif /* __ASM_RISCV_P2M_H__ */ \ No newline at end of file From patchwork Fri Nov 24 10:30:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii X-Patchwork-Id: 13467515 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 14112C61DF7 for ; Fri, 24 Nov 2023 10:44:47 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.640485.998793 (Exim 4.92) (envelope-from ) id 1r6Tfo-0008Ck-E0; Fri, 24 Nov 2023 10:44:36 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 640485.998793; Fri, 24 Nov 2023 10:44:36 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1r6Tfo-0008Cd-Ar; Fri, 24 Nov 2023 10:44:36 +0000 Received: by outflank-mailman (input) for mailman id 640485; Fri, 24 Nov 2023 10:44:34 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1r6TTO-0006hx-BQ for xen-devel@lists.xenproject.org; Fri, 24 Nov 2023 10:31:46 +0000 Received: from mail-ej1-x633.google.com (mail-ej1-x633.google.com [2a00:1450:4864:20::633]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id a5d19f9d-8ab4-11ee-9b0e-b553b5be7939; Fri, 24 Nov 2023 11:31:37 +0100 (CET) Received: by mail-ej1-x633.google.com with SMTP id a640c23a62f3a-a08e4352992so67622066b.1 for ; Fri, 24 Nov 2023 02:31:37 -0800 (PST) Received: from fedora.. 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Only rebase. --- xen/arch/riscv/include/asm/event.h | 34 ++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 xen/arch/riscv/include/asm/event.h diff --git a/xen/arch/riscv/include/asm/event.h b/xen/arch/riscv/include/asm/event.h new file mode 100644 index 0000000000..48630c77b3 --- /dev/null +++ b/xen/arch/riscv/include/asm/event.h @@ -0,0 +1,34 @@ +#ifndef __ASM_RISCV_EVENT_H__ +#define __ASM_RISCV_EVENT_H__ + +void vcpu_mark_events_pending(struct vcpu *v); + +static inline int vcpu_event_delivery_is_enabled(struct vcpu *v) +{ + return 0; +} + +static inline int local_events_need_delivery(void) +{ + return 0; +} + +static inline void local_event_delivery_enable(void) +{ +} + +/* No arch specific virq definition now. Default to global. */ +static inline bool arch_virq_is_global(unsigned int virq) +{ + return true; +} + +#endif +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ From patchwork Fri Nov 24 10:30:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii X-Patchwork-Id: 13467517 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9DE96C61DF4 for ; Fri, 24 Nov 2023 10:47:02 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.640498.998813 (Exim 4.92) (envelope-from ) id 1r6Thx-0001zS-6G; Fri, 24 Nov 2023 10:46:49 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 640498.998813; Fri, 24 Nov 2023 10:46:49 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1r6Thx-0001zL-39; Fri, 24 Nov 2023 10:46:49 +0000 Received: by outflank-mailman (input) for mailman id 640498; Fri, 24 Nov 2023 10:46:47 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1r6TTJ-0006hy-Cv for xen-devel@lists.xenproject.org; Fri, 24 Nov 2023 10:31:41 +0000 Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [2a00:1450:4864:20::630]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id a7c33535-8ab4-11ee-98e2-6d05b1d4d9a1; Fri, 24 Nov 2023 11:31:41 +0100 (CET) Received: by mail-ej1-x630.google.com with SMTP id a640c23a62f3a-a00b056ca38so243303466b.2 for ; Fri, 24 Nov 2023 02:31:40 -0800 (PST) Received: from fedora.. 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Signed-off-by: Oleksii Kurochko --- - update the commit message --- xen/arch/riscv/include/asm/cache.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/xen/arch/riscv/include/asm/cache.h b/xen/arch/riscv/include/asm/cache.h index 69573eb051..94bd94db53 100644 --- a/xen/arch/riscv/include/asm/cache.h +++ b/xen/arch/riscv/include/asm/cache.h @@ -3,4 +3,6 @@ #ifndef _ASM_RISCV_CACHE_H #define _ASM_RISCV_CACHE_H +#define __read_mostly __section(".data.read_mostly") + #endif /* _ASM_RISCV_CACHE_H */ From patchwork Fri Nov 24 10:30:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii X-Patchwork-Id: 13467530 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6D099C61D97 for ; Fri, 24 Nov 2023 10:51:07 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.640527.998893 (Exim 4.92) (envelope-from ) id 1r6Tlu-0000UH-G3; Fri, 24 Nov 2023 10:50:54 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 640527.998893; Fri, 24 Nov 2023 10:50:54 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1r6Tlu-0000TI-DA; Fri, 24 Nov 2023 10:50:54 +0000 Received: by outflank-mailman (input) for mailman id 640527; Fri, 24 Nov 2023 10:50:53 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1r6TTV-0006hx-Cz for xen-devel@lists.xenproject.org; Fri, 24 Nov 2023 10:31:53 +0000 Received: from mail-ed1-x52e.google.com (mail-ed1-x52e.google.com [2a00:1450:4864:20::52e]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id a857fd8c-8ab4-11ee-9b0e-b553b5be7939; Fri, 24 Nov 2023 11:31:41 +0100 (CET) Received: by mail-ed1-x52e.google.com with SMTP id 4fb4d7f45d1cf-54af61f2a40so557238a12.3 for ; Fri, 24 Nov 2023 02:31:41 -0800 (PST) Received: from fedora.. ([94.75.70.14]) by smtp.gmail.com with ESMTPSA id g1-20020a170906348100b009de3641d538sm1882374ejb.134.2023.11.24.02.31.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Nov 2023 02:31:40 -0800 (PST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: a857fd8c-8ab4-11ee-9b0e-b553b5be7939 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1700821901; x=1701426701; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ewmvPOWcxXxVUGRPLKOFAXBqTtU96ll1emuQx9tNHgs=; b=bfVZqK9fokeP/pPx6ZkjXIbFwxzdZFmSYAbmqS7NRy31a5UxDzEG2WcpIaM8lSiKUo 4lEW37+jeXgv7SrRWJp6vGk/6XzxMlMsRGIlfMusaILtnUGbKe9kijDgiQEeOjazHszR aK870EAiL1PUXrhpuA149vt0X9RaAglkXtbcNysNTvMAyz6FfQfzXwdNYTfefIDSAShk yKQycy6/jrtTgIboh+PuHEOvGhfh7TD3r0VLQFngNW1oVpjW5PY4UINvTF+JqdZupuGg mTzMrR6cf487fTQuCzS3NmIDAR9iU977QkzaJJDFnErKqOuTDAFjbNkKiLliYuadMYFH Q7Bg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700821901; x=1701426701; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ewmvPOWcxXxVUGRPLKOFAXBqTtU96ll1emuQx9tNHgs=; b=a3qSTrUA2/fjMuWZqcxWkFrgWq4GiCmkAAGyaOg6fPFUFvcSDRUYrzxaGmqTCfyc8n fqWFntaIO2kQUHV47bdlPl4dGRrd/qNm3nPvvVFAAT9l6M/63om0bDaf0Puue/rfs9DX /NP3j4+exya01tQtOtdeh3ILVfc1p3tHZxbXZZQOC21/YJUzFLYkVj6AsgW2pBg81doe oawxyPd0ocyWcBOQt6Z20EZNk+Eafd/jUaoIxZW1IVCfOEbIR9QZO6QFG5zV1i5saJ5r 7CyD/vtIzJls/hyMRr0u+lo4FbJCpdifaKUGGk3jVRf84iLwzzyp56UCYDyWh7w1xRRC zG4Q== X-Gm-Message-State: AOJu0YzjVyotOPdq2TRnQO+UIB/eXA7eAPHEXPP69uNYrQ2vEXpIrIlF qmmdrzDqIS8KctbJNOrafjZKOU+mvfyeQg== X-Google-Smtp-Source: AGHT+IEwu6D6lPHMTWs7SWKMKn6i4rjMA0EnoJMbAbbZBjIMTQE4NAUTFH75Ae7qP7ba4XEn4c63AQ== X-Received: by 2002:a17:906:b34f:b0:9fe:3b2c:d044 with SMTP id cd15-20020a170906b34f00b009fe3b2cd044mr1555143ejb.44.1700821901182; Fri, 24 Nov 2023 02:31:41 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini , Wei Liu Subject: [PATCH v2 30/39] xen/riscv: define an address of frame table Date: Fri, 24 Nov 2023 12:30:50 +0200 Message-ID: <13ad41657814e4fc235772fa0928de1723ae7c3d.1700761381.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: References: MIME-Version: 1.0 Also the patchs adds some helpful macros. Signed-off-by: Oleksii Kurochko --- Changes in V2: - Nothing changed. Only rebase. --- xen/arch/riscv/include/asm/config.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/xen/arch/riscv/include/asm/config.h b/xen/arch/riscv/include/asm/config.h index f0544c6a20..8d2103b3ce 100644 --- a/xen/arch/riscv/include/asm/config.h +++ b/xen/arch/riscv/include/asm/config.h @@ -77,12 +77,31 @@ name: #endif +#define VPN_BITS (9) +#define OFFSET_BITS (12) + #ifdef CONFIG_RISCV_64 + +#define SLOTN_ENTRY_BITS (HYP_PT_ROOT_LEVEL * VPN_BITS + OFFSET_BITS) +#define SLOTN(slot) (_AT(vaddr_t,slot) << SLOTN_ENTRY_BITS) +#define SLOTN_ENTRY_SIZE SLOTN(1) + #define XEN_VIRT_START 0xFFFFFFFFC0000000 /* (_AC(-1, UL) + 1 - GB(1)) */ + +#define FRAMETABLE_VIRT_START SLOTN(196) +#define FRAMETABLE_SIZE GB(3) +#define FRAMETABLE_NR (FRAMETABLE_SIZE / sizeof(*frame_table)) +#define FRAMETABLE_VIRT_END (FRAMETABLE_VIRT_START + FRAMETABLE_SIZE - 1) + +#define VMAP_VIRT_START SLOTN(194) +#define VMAP_VIRT_SIZE GB(1) + #else #error "RV32 isn't supported" #endif +#define HYPERVISOR_VIRT_START XEN_VIRT_START + #define SMP_CACHE_BYTES (1 << 6) #define STACK_SIZE PAGE_SIZE @@ -95,6 +114,8 @@ #define RV_STAGE1_MODE SATP_MODE_SV32 #endif +#define HYP_PT_ROOT_LEVEL (CONFIG_PAGING_LEVELS - 1) + #define IDENT_AREA_SIZE 64 #endif /* __RISCV_CONFIG_H__ */ From patchwork Fri Nov 24 10:30:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii X-Patchwork-Id: 13467504 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B9F79C61DF4 for ; Fri, 24 Nov 2023 10:40:08 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.640437.998678 (Exim 4.92) (envelope-from ) id 1r6TbF-0006dW-KJ; Fri, 24 Nov 2023 10:39:53 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 640437.998678; Fri, 24 Nov 2023 10:39:53 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1r6TbF-0006cX-D3; Fri, 24 Nov 2023 10:39:53 +0000 Received: by outflank-mailman (input) for mailman id 640437; Fri, 24 Nov 2023 10:39:51 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1r6TTL-0006hy-91 for xen-devel@lists.xenproject.org; Fri, 24 Nov 2023 10:31:43 +0000 Received: from mail-ej1-x634.google.com (mail-ej1-x634.google.com [2a00:1450:4864:20::634]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id a8e02581-8ab4-11ee-98e2-6d05b1d4d9a1; Fri, 24 Nov 2023 11:31:42 +0100 (CET) Received: by mail-ej1-x634.google.com with SMTP id a640c23a62f3a-9ffb5a4f622so246791366b.0 for ; Fri, 24 Nov 2023 02:31:42 -0800 (PST) Received: from fedora.. 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Signed-off-by: Oleksii Kurochko --- Changes in V2: - Nothing changed. Only rebase. --- xen/arch/riscv/include/asm/current.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/xen/arch/riscv/include/asm/current.h b/xen/arch/riscv/include/asm/current.h index d84f15dc50..e105329bf3 100644 --- a/xen/arch/riscv/include/asm/current.h +++ b/xen/arch/riscv/include/asm/current.h @@ -3,6 +3,22 @@ #ifndef __ASM_CURRENT_H #define __ASM_CURRENT_H +#include +#include + +#ifndef __ASSEMBLY__ + +struct vcpu; + +/* Which VCPU is "current" on this PCPU. */ +DECLARE_PER_CPU(struct vcpu *, curr_vcpu); + +#define current (this_cpu(curr_vcpu)) +#define set_current(vcpu) do { current = (vcpu); } while (0) +#define get_cpu_current(cpu) (per_cpu(curr_vcpu, cpu)) + +#define guest_cpu_user_regs() (0) + #define switch_stack_and_jump(stack, fn) do { \ asm volatile ( \ "mv sp, %0\n" \ @@ -10,4 +26,8 @@ unreachable(); \ } while ( false ) +#define get_per_cpu_offset() __per_cpu_offset[get_processor_id()] + +#endif /* __ASSEMBLY__ */ + #endif /* __ASM_CURRENT_H */ From patchwork Fri Nov 24 10:30:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii X-Patchwork-Id: 13467524 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 30B89C61DF4 for ; Fri, 24 Nov 2023 10:48:07 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.640503.998823 (Exim 4.92) (envelope-from ) id 1r6Tj4-0002wU-Gg; Fri, 24 Nov 2023 10:47:58 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 640503.998823; Fri, 24 Nov 2023 10:47:58 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1r6Tj4-0002wJ-E8; Fri, 24 Nov 2023 10:47:58 +0000 Received: by outflank-mailman (input) for mailman id 640503; Fri, 24 Nov 2023 10:47:57 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1r6TTW-0006hx-Cy for xen-devel@lists.xenproject.org; Fri, 24 Nov 2023 10:31:54 +0000 Received: from mail-ej1-x632.google.com (mail-ej1-x632.google.com [2a00:1450:4864:20::632]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id a95c321a-8ab4-11ee-9b0e-b553b5be7939; Fri, 24 Nov 2023 11:31:43 +0100 (CET) Received: by mail-ej1-x632.google.com with SMTP id a640c23a62f3a-a00b056ca38so243310666b.2 for ; Fri, 24 Nov 2023 02:31:43 -0800 (PST) Received: from fedora.. ([94.75.70.14]) by smtp.gmail.com with ESMTPSA id g1-20020a170906348100b009de3641d538sm1882374ejb.134.2023.11.24.02.31.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Nov 2023 02:31:42 -0800 (PST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: a95c321a-8ab4-11ee-9b0e-b553b5be7939 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1700821903; x=1701426703; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SZYBaKtqO03IaPhGnfIlixMtQetp2xv8QqhEqqcwd+k=; b=UlhwHxmRKQbKJ2Inz952T3MgMb0VNYMJdlAyhczHMPDuto30FTWJvx3IPj2Ss/ergy Kq+O+XL84u7JQgD463sI3yV/u3ubWHIMlTDPjxBmHmU+2+TGDPiele4S6HsysGfv8p17 P1lp28u4iJTqUPW18FUmYeRm6eIALjyIHKzSdKhICO7EEDxCHwiTLxEn9BTyb7WembWS EFVnbmY+Nr66CvHTGsrkwFEEchBNvkDTz7R89291WRtKwQNsx0DMdoUPbZWZFb+HSxky LNbVjDIV7j73COlL2UOQi6QlYXlsmTw8l1cpamly60HjR1+lFchU01//uOtTK8G1Hz2D qELA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700821903; x=1701426703; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SZYBaKtqO03IaPhGnfIlixMtQetp2xv8QqhEqqcwd+k=; b=ghdpoCmjN4acDN36eBbbRPIioNJZ0dUB8Vqw03Zv2/MXQ85OZsX5MMNxCtsBYWkFoq lxQE9vEZbf8x9T5r9c5YtnaO9jBPPrUAjwgFTF5/wKL+Ew7pLsdmu4ib0g/n+i/08Plq tYueGFZEUrzcvYqSh81hV1lQvEWrZFcadPxlNwE/SM2H/qs6uQkJ2ikiZPY2N+Mvw0lj Up+nUWGoe7nr9WCC5GCdwrPN1HVK+Cy+z1AU2tPPGj61yc7xFOp6mGT+HDZy6YLjy/4C oMTKyqsAu1dhq4DI0ZzoF8sz8l1DTo2sh/s0ujVPZfRO1cJYQQxYkRQFoUxPq3yQpirV tLaw== X-Gm-Message-State: AOJu0YzquoPiPCeSUumtL8nrChyylve3zOjIgssucmHrof/dO70E6Yrz 2kbxCNe5QwasCztB2BxRgTE0nxQlC3ZFqw== X-Google-Smtp-Source: AGHT+IFoisvlUc6sGtkQ0PuK7EpcEjxDt7LEADKp7XJ8gqN7fWPxILq2oTpfBFaXOr0WNEMVNtW1tg== X-Received: by 2002:a17:906:35c7:b0:9e4:e405:27b4 with SMTP id p7-20020a17090635c700b009e4e40527b4mr1518113ejb.53.1700821902971; Fri, 24 Nov 2023 02:31:42 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini , Wei Liu Subject: [PATCH v2 32/39] xen/riscv: add minimal stuff to asm/page.h to build full Xen Date: Fri, 24 Nov 2023 12:30:52 +0200 Message-ID: <34a4bc023eb50e1d1cf70fa149825c51f2f4555f.1700761381.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: References: MIME-Version: 1.0 Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in V2: - Nothing changed. Only rebase. --- xen/arch/riscv/include/asm/page.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/xen/arch/riscv/include/asm/page.h b/xen/arch/riscv/include/asm/page.h index 95074e29b3..abbae75aaf 100644 --- a/xen/arch/riscv/include/asm/page.h +++ b/xen/arch/riscv/include/asm/page.h @@ -6,6 +6,7 @@ #ifndef __ASSEMBLY__ #include +#include #include #include @@ -32,6 +33,9 @@ #define PTE_LEAF_DEFAULT (PTE_VALID | PTE_READABLE | PTE_WRITABLE) #define PTE_TABLE (PTE_VALID) +/* TODO */ +#define PAGE_HYPERVISOR 0 + /* Calculate the offsets into the pagetables for a given VA */ #define pt_linear_offset(lvl, va) ((va) >> XEN_PT_LEVEL_SHIFT(lvl)) @@ -46,6 +50,9 @@ typedef struct { #endif } pte_t; +#define pfn_to_paddr(pfn) ((paddr_t)(pfn) << PAGE_SHIFT) +#define paddr_to_pfn(pa) ((unsigned long)((pa) >> PAGE_SHIFT)) + static inline pte_t paddr_to_pte(paddr_t paddr, unsigned int permissions) { @@ -62,6 +69,20 @@ static inline bool pte_is_valid(pte_t p) return p.pte & PTE_VALID; } +static inline void invalidate_icache(void) +{ + BUG(); +} + +#define clear_page(page) memset((void *)(page), 0, PAGE_SIZE) +#define copy_page(dp, sp) memcpy(dp, sp, PAGE_SIZE) + +/* TODO: Flush the dcache for an entire page. */ +static inline void flush_page_to_ram(unsigned long mfn, bool sync_icache) +{ + BUG(); +} + #endif /* __ASSEMBLY__ */ #endif /* _ASM_RISCV_PAGE_H */ From patchwork Fri Nov 24 10:30:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii X-Patchwork-Id: 13467516 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1C1ACC61DF4 for ; Fri, 24 Nov 2023 10:46:16 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.640496.998803 (Exim 4.92) (envelope-from ) id 1r6ThI-0000yl-VE; Fri, 24 Nov 2023 10:46:08 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 640496.998803; Fri, 24 Nov 2023 10:46:08 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1r6ThI-0000ye-R9; Fri, 24 Nov 2023 10:46:08 +0000 Received: by outflank-mailman (input) for mailman id 640496; Fri, 24 Nov 2023 10:46:07 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1r6TTX-0006hx-D2 for xen-devel@lists.xenproject.org; Fri, 24 Nov 2023 10:31:55 +0000 Received: from mail-ed1-x530.google.com (mail-ed1-x530.google.com [2a00:1450:4864:20::530]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id a9e978e5-8ab4-11ee-9b0e-b553b5be7939; Fri, 24 Nov 2023 11:31:44 +0100 (CET) Received: by mail-ed1-x530.google.com with SMTP id 4fb4d7f45d1cf-5431614d90eso2509960a12.1 for ; Fri, 24 Nov 2023 02:31:44 -0800 (PST) Received: from fedora.. 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Only rebase. --- xen/arch/riscv/include/asm/processor.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/xen/arch/riscv/include/asm/processor.h b/xen/arch/riscv/include/asm/processor.h index 6db681d805..b6218a00a7 100644 --- a/xen/arch/riscv/include/asm/processor.h +++ b/xen/arch/riscv/include/asm/processor.h @@ -12,6 +12,9 @@ #ifndef __ASSEMBLY__ +/* TODO: need to be implemeted */ +#define get_processor_id() 0 + /* On stack VCPU state */ struct cpu_user_regs { @@ -53,6 +56,18 @@ struct cpu_user_regs unsigned long pregs; }; +/* TODO: need to implement */ +#define cpu_to_core(_cpu) (0) +#define cpu_to_socket(_cpu) (0) + +static inline void cpu_relax(void) +{ + int dummy; + /* In lieu of a halt instruction, induce a long-latency stall. */ + __asm__ __volatile__ ("div %0, %0, zero" : "=r" (dummy)); + barrier(); +} + static inline void wfi(void) { __asm__ __volatile__ ("wfi"); From patchwork Fri Nov 24 10:30:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii X-Patchwork-Id: 13467506 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A712BC61D97 for ; Fri, 24 Nov 2023 10:40:19 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.640448.998713 (Exim 4.92) (envelope-from ) id 1r6TbY-0001OH-P0; Fri, 24 Nov 2023 10:40:12 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 640448.998713; Fri, 24 Nov 2023 10:40:12 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1r6TbY-0001O3-JX; Fri, 24 Nov 2023 10:40:12 +0000 Received: by outflank-mailman (input) for mailman id 640448; Fri, 24 Nov 2023 10:40:10 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1r6TTN-0006hy-Qy for xen-devel@lists.xenproject.org; Fri, 24 Nov 2023 10:31:45 +0000 Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [2a00:1450:4864:20::630]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id aa5af560-8ab4-11ee-98e2-6d05b1d4d9a1; Fri, 24 Nov 2023 11:31:45 +0100 (CET) Received: by mail-ej1-x630.google.com with SMTP id a640c23a62f3a-a02d91ab195so243561266b.3 for ; Fri, 24 Nov 2023 02:31:45 -0800 (PST) Received: from fedora.. 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Only rebase. --- xen/include/public/pmu.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/xen/include/public/pmu.h b/xen/include/public/pmu.h index 5a176b6ac3..af8b7babdd 100644 --- a/xen/include/public/pmu.h +++ b/xen/include/public/pmu.h @@ -13,6 +13,8 @@ #include "arch-arm.h" #elif defined (__powerpc64__) #include "arch-ppc.h" +#elif defined(__riscv) +#include "arch-riscv.h" #else #error "Unsupported architecture" #endif From patchwork Fri Nov 24 10:30:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii X-Patchwork-Id: 13467526 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5EBC9C61DF4 for ; Fri, 24 Nov 2023 10:49:05 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.640511.998853 (Exim 4.92) (envelope-from ) id 1r6Tjw-0004sz-D5; Fri, 24 Nov 2023 10:48:52 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 640511.998853; Fri, 24 Nov 2023 10:48:52 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1r6Tjw-0004sq-AS; Fri, 24 Nov 2023 10:48:52 +0000 Received: by outflank-mailman (input) for mailman id 640511; Fri, 24 Nov 2023 10:48:52 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1r6TTQ-0006hy-Lv for xen-devel@lists.xenproject.org; Fri, 24 Nov 2023 10:31:48 +0000 Received: from mail-ed1-x533.google.com (mail-ed1-x533.google.com [2a00:1450:4864:20::533]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id aad39247-8ab4-11ee-98e2-6d05b1d4d9a1; Fri, 24 Nov 2023 11:31:46 +0100 (CET) Received: by mail-ed1-x533.google.com with SMTP id 4fb4d7f45d1cf-54af2498e85so681570a12.0 for ; Fri, 24 Nov 2023 02:31:46 -0800 (PST) Received: from fedora.. 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+ return NULL; +} + +/* + * We define non-underscored wrappers for above conversion functions. + * These are overriden in various source files while underscored version + * remain intact. + */ +#define virt_to_mfn(va) __virt_to_mfn(va) +#define mfn_to_virt(mfn) __mfn_to_virt(mfn) + +struct page_info +{ + /* Each frame can be threaded onto a doubly-linked list. */ + struct page_list_entry list; + + /* Reference count and various PGC_xxx flags and fields. */ + unsigned long count_info; + + /* Context-dependent fields follow... */ + union { + /* Page is in use: ((count_info & PGC_count_mask) != 0). */ + struct { + /* Type reference count and various PGT_xxx flags and fields. */ + unsigned long type_info; + } inuse; + /* Page is on a free list: ((count_info & PGC_count_mask) == 0). */ + union { + struct { + /* + * Index of the first *possibly* unscrubbed page in the buddy. + * One more bit than maximum possible order to accommodate + * INVALID_DIRTY_IDX. + */ +#define INVALID_DIRTY_IDX ((1UL << (MAX_ORDER + 1)) - 1) + unsigned long first_dirty:MAX_ORDER + 1; + + /* Do TLBs need flushing for safety before next page use? */ + bool need_tlbflush:1; + +#define BUDDY_NOT_SCRUBBING 0 +#define BUDDY_SCRUBBING 1 +#define BUDDY_SCRUB_ABORT 2 + unsigned long scrub_state:2; + }; + + unsigned long val; + } free; + + } u; + + union { + /* Page is in use, but not as a shadow. */ + struct { + /* Owner of this page (zero if page is anonymous). */ + struct domain *domain; + } inuse; + + /* Page is on a free list. */ + struct { + /* Order-size of the free chunk this page is the head of. */ + unsigned int order; + } free; + + } v; + + union { + /* + * Timestamp from 'TLB clock', used to avoid extra safety flushes. + * Only valid for: a) free pages, and b) pages with zero type count + */ + u32 tlbflush_timestamp; + }; + u64 pad; +}; + +#define frame_table ((struct page_info *)FRAMETABLE_VIRT_START) + +/* PDX of the first page in the frame table. */ +extern unsigned long frametable_base_pdx; + +/* Convert between machine frame numbers and page-info structures. */ +#define mfn_to_page(mfn) \ + (frame_table + (mfn_to_pdx(mfn) - frametable_base_pdx)) +#define page_to_mfn(pg) \ + pdx_to_mfn((unsigned long)((pg) - frame_table) + frametable_base_pdx) + +static inline void *page_to_virt(const struct page_info *pg) +{ + return mfn_to_virt(mfn_x(page_to_mfn(pg))); +} + +/* + * Common code requires get_page_type and put_page_type. + * We don't care about typecounts so we just do the minimum to make it + * happy. + */ +static inline int get_page_type(struct page_info *page, unsigned long type) +{ + return 1; +} + +static inline void put_page_type(struct page_info *page) +{ + return; +} + +/* TODO */ +static inline bool get_page_nr(struct page_info *page, const struct domain *domain, + unsigned long nr) +{ + BUG(); +} +static inline void put_page_nr(struct page_info *page, unsigned long nr) +{ + BUG(); +} + +static inline void put_page_and_type(struct page_info *page) +{ + put_page_type(page); + put_page(page); +} + +/* + * RISCV does not have an M2P, but common code expects a handful of + * M2P-related defines and functions. Provide dummy versions of these. + */ +#define INVALID_M2P_ENTRY (~0UL) +#define SHARED_M2P_ENTRY (~0UL - 1UL) +#define SHARED_M2P(_e) ((_e) == SHARED_M2P_ENTRY) + +/* Xen always owns P2M on PPC */ +#define set_gpfn_from_mfn(mfn, pfn) do { (void) (mfn), (void)(pfn); } while (0) +#define mfn_to_gfn(d, mfn) ((void)(d), _gfn(mfn_x(mfn))) + +#define PDX_GROUP_SHIFT (16 + 5) + +static inline unsigned long domain_get_maximum_gpfn(struct domain *d) +{ + BUG(); + return 0; +} + +static inline long arch_memory_op(int op, XEN_GUEST_HANDLE_PARAM(void) arg) +{ + BUG(); + return 0; +} + +/* + * On RISCV, all the RAM is currently direct mapped in Xen. + * Hence return always true. + */ +static inline bool arch_mfns_in_directmap(unsigned long mfn, unsigned long nr) +{ + return true; +} + +#define PG_shift(idx) (BITS_PER_LONG - (idx)) +#define PG_mask(x, idx) (x ## UL << PG_shift(idx)) + +#define PGT_none PG_mask(0, 1) /* no special uses of this page */ +#define PGT_writable_page PG_mask(1, 1) /* has writable mappings? */ +#define PGT_type_mask PG_mask(1, 1) /* Bits 31 or 63. */ + + /* Count of uses of this frame as its current type. */ +#define PGT_count_width PG_shift(2) +#define PGT_count_mask ((1UL<count_info&PGC_state) == PGC_state_##st) + +/* Count of references to this frame. */ +#define PGC_count_width PG_shift(9) +#define PGC_count_mask ((1UL<count_info&PGC_state) == PGC_state_##st) + +#define _PGC_extra PG_shift(10) +#define PGC_extra PG_mask(1, 10) + +#define is_xen_heap_page(page) ((page)->count_info & PGC_xen_heap) +#define is_xen_heap_mfn(mfn) \ + (mfn_valid(mfn) && is_xen_heap_page(mfn_to_page(mfn))) + +#define is_xen_fixed_mfn(mfn) \ + ((mfn_to_maddr(mfn) >= virt_to_maddr(&_start)) && \ + (mfn_to_maddr(mfn) <= virt_to_maddr((vaddr_t)_end - 1))) + +#define page_get_owner(_p) (_p)->v.inuse.domain +#define page_set_owner(_p,_d) ((_p)->v.inuse.domain = (_d)) + +/* TODO: implement */ +#define mfn_valid(mfn) ({ (void) (mfn); 0; }) +// #define max_page (0UL) + +#define mfn_to_gfn(d, mfn) ((void)(d), _gfn(mfn_x(mfn))) + +#define domain_set_alloc_bitsize(d) ((void)0) +#define domain_clamp_alloc_bitsize(d, b) (b) + +#define PFN_ORDER(_pfn) ((_pfn)->v.free.order) extern unsigned char cpu0_boot_stack[]; @@ -20,4 +281,9 @@ unsigned long calc_phys_offset(void); void turn_on_mmu(unsigned long ra); +static inline unsigned int arch_get_dma_bitsize(void) +{ + return 32; /* TODO */ +} + #endif /* _ASM_RISCV_MM_H */ From patchwork Fri Nov 24 10:30:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii X-Patchwork-Id: 13467510 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B2B60C61DF4 for ; Fri, 24 Nov 2023 10:42:30 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.640463.998753 (Exim 4.92) (envelope-from ) id 1r6Tdf-0004rc-Uc; Fri, 24 Nov 2023 10:42:23 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 640463.998753; Fri, 24 Nov 2023 10:42:23 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1r6Tdf-0004rV-Rh; Fri, 24 Nov 2023 10:42:23 +0000 Received: by outflank-mailman (input) for mailman id 640463; Fri, 24 Nov 2023 10:42:22 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1r6TTS-0006hy-M9 for xen-devel@lists.xenproject.org; Fri, 24 Nov 2023 10:31:50 +0000 Received: from mail-ej1-x632.google.com (mail-ej1-x632.google.com [2a00:1450:4864:20::632]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id abde6b3d-8ab4-11ee-98e2-6d05b1d4d9a1; Fri, 24 Nov 2023 11:31:47 +0100 (CET) Received: by mail-ej1-x632.google.com with SMTP id a640c23a62f3a-9e1021dbd28so233225166b.3 for ; Fri, 24 Nov 2023 02:31:47 -0800 (PST) Received: from fedora.. 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} } - -/* - * The following #if 1 ... #endif should be removed after printk - * and related stuff are ready. - */ -#if 1 - -#include -#include - -/** - * strlen - Find the length of a string - * @s: The string to be sized - */ -size_t (strlen)(const char * s) -{ - const char *sc; - - for (sc = s; *sc != '\0'; ++sc) - /* nothing */; - return sc - s; -} - -/** - * memcpy - Copy one area of memory to another - * @dest: Where to copy to - * @src: Where to copy from - * @count: The size of the area. - * - * You should not use this function to access IO space, use memcpy_toio() - * or memcpy_fromio() instead. - */ -void *(memcpy)(void *dest, const void *src, size_t count) -{ - char *tmp = (char *) dest, *s = (char *) src; - - while (count--) - *tmp++ = *s++; - - return dest; -} - -int vsnprintf(char* str, size_t size, const char* format, va_list args) -{ - size_t i = 0; /* Current position in the output string */ - size_t written = 0; /* Total number of characters written */ - char* dest = str; - - while ( format[i] != '\0' && written < size - 1 ) - { - if ( format[i] == '%' ) - { - i++; - - if ( format[i] == '\0' ) - break; - - if ( format[i] == '%' ) - { - if ( written < size - 1 ) - { - dest[written] = '%'; - written++; - } - i++; - continue; - } - - /* - * Handle format specifiers. - * For simplicity, only %s and %d are implemented here. - */ - - if ( format[i] == 's' ) - { - char* arg = va_arg(args, char*); - size_t arglen = strlen(arg); - - size_t remaining = size - written - 1; - - if ( arglen > remaining ) - arglen = remaining; - - memcpy(dest + written, arg, arglen); - - written += arglen; - i++; - } - else if ( format[i] == 'd' ) - { - int arg = va_arg(args, int); - - /* Convert the integer to string representation */ - char numstr[32]; /* Assumes a maximum of 32 digits */ - int numlen = 0; - int num = arg; - size_t remaining; - - if ( arg < 0 ) - { - if ( written < size - 1 ) - { - dest[written] = '-'; - written++; - } - - num = -arg; - } - - do - { - numstr[numlen] = '0' + num % 10; - num = num / 10; - numlen++; - } while ( num > 0 ); - - /* Reverse the string */ - for (int j = 0; j < numlen / 2; j++) - { - char tmp = numstr[j]; - numstr[j] = numstr[numlen - 1 - j]; - numstr[numlen - 1 - j] = tmp; - } - - remaining = size - written - 1; - - if ( numlen > remaining ) - numlen = remaining; - - memcpy(dest + written, numstr, numlen); - - written += numlen; - i++; - } - } - else - { - if ( written < size - 1 ) - { - dest[written] = format[i]; - written++; - } - i++; - } - } - - if ( size > 0 ) - dest[written] = '\0'; - - return written; -} - -void printk(const char *format, ...) -{ - static char buf[1024]; - - va_list args; - va_start(args, format); - - (void)vsnprintf(buf, sizeof(buf), format, args); - - early_printk(buf); - - va_end(args); -} - -#endif - diff --git a/xen/arch/riscv/mm.c b/xen/arch/riscv/mm.c index 053f043a3d..f0eddab56c 100644 --- a/xen/arch/riscv/mm.c +++ b/xen/arch/riscv/mm.c @@ -1,19 +1,23 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include #include #include +#include #include #include #include #include -#include #include #include +unsigned long frametable_base_pdx __read_mostly; +unsigned long frametable_virt_end __read_mostly; + struct mmu_desc { unsigned int num_levels; unsigned int pgtbl_count; @@ -294,3 +298,49 @@ unsigned long __init calc_phys_offset(void) phys_offset = load_start - XEN_VIRT_START; return phys_offset; } + +void put_page(struct page_info *page) +{ + assert_failed(__func__); +} + +unsigned long get_upper_mfn_bound(void) +{ + /* No memory hotplug yet, so current memory limit is the final one. */ + return max_page - 1; +} + +void arch_dump_shared_mem_info(void) +{ + WARN(); +} + +int populate_pt_range(unsigned long virt, unsigned long nr_mfns) +{ + assert_failed(__func__); + return -1; +} + +int xenmem_add_to_physmap_one(struct domain *d, unsigned int space, + union add_to_physmap_extra extra, + unsigned long idx, gfn_t gfn) +{ + WARN(); + + return 0; +} + +int destroy_xen_mappings(unsigned long s, unsigned long e) +{ + assert_failed(__func__); + return -1; +} + +int map_pages_to_xen(unsigned long virt, + mfn_t mfn, + unsigned long nr_mfns, + unsigned int flags) +{ + assert_failed(__func__); + return -1; +} diff --git a/xen/arch/riscv/setup.c b/xen/arch/riscv/setup.c index 6593f601c1..8944e0ecfe 100644 --- a/xen/arch/riscv/setup.c +++ b/xen/arch/riscv/setup.c @@ -2,9 +2,16 @@ #include #include +#include + +#include #include -#include + +void arch_get_xen_caps(xen_capabilities_info_t *info) +{ + assert_failed("need to be implemented"); +} /* Xen stack for bringing up the first CPU. */ unsigned char __initdata cpu0_boot_stack[STACK_SIZE] diff --git a/xen/arch/riscv/stubs.c b/xen/arch/riscv/stubs.c new file mode 100644 index 0000000000..2031ef6bde --- /dev/null +++ b/xen/arch/riscv/stubs.c @@ -0,0 +1,426 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include +#include +#include +#include +#include +#include + +#include + +/* smpboot.c */ + +cpumask_t cpu_online_map; +cpumask_t cpu_present_map; +cpumask_t cpu_possible_map; + +/* ID of the PCPU we're running on */ +DEFINE_PER_CPU(unsigned int, cpu_id); +/* XXX these seem awfully x86ish... */ +/* representing HT siblings of each logical CPU */ +DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_mask); +/* representing HT and core siblings of each logical CPU */ +DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_mask); + +nodemask_t __read_mostly node_online_map = { { [0] = 1UL } }; + +/* time.c */ + +unsigned long __read_mostly cpu_khz; /* CPU clock frequency in kHz. */ + +s_time_t get_s_time(void) +{ + BUG(); +} + +int reprogram_timer(s_time_t timeout) +{ + BUG(); +} + +void send_timer_event(struct vcpu *v) +{ + BUG(); +} + +void domain_set_time_offset(struct domain *d, int64_t time_offset_seconds) +{ + BUG(); +} + +/* shutdown.c */ + +void machine_restart(unsigned int delay_millisecs) +{ + BUG(); +} + +void machine_halt(void) +{ + BUG(); +} + +/* vm_event.c */ + +void vm_event_fill_regs(vm_event_request_t *req) +{ + BUG(); +} + +void vm_event_set_registers(struct vcpu *v, vm_event_response_t *rsp) +{ + BUG(); +} + +void vm_event_monitor_next_interrupt(struct vcpu *v) +{ + /* Not supported on RISCV. */ +} + +void vm_event_reset_vmtrace(struct vcpu *v) +{ + /* Not supported on RISCV. */ +} + +/* domctl.c */ + +long arch_do_domctl(struct xen_domctl *domctl, struct domain *d, + XEN_GUEST_HANDLE_PARAM(xen_domctl_t) u_domctl) +{ + BUG(); +} + +void arch_get_domain_info(const struct domain *d, + struct xen_domctl_getdomaininfo *info) +{ + BUG(); +} + +void arch_get_info_guest(struct vcpu *v, vcpu_guest_context_u c) +{ + BUG(); +} + +/* monitor.c */ + +int arch_monitor_domctl_event(struct domain *d, + struct xen_domctl_monitor_op *mop) +{ + BUG(); +} + +/* smp.c */ + +void arch_flush_tlb_mask(const cpumask_t *mask) +{ + BUG(); +} + +void smp_send_event_check_mask(const cpumask_t *mask) +{ + BUG(); +} + +void smp_send_call_function_mask(const cpumask_t *mask) +{ + BUG(); +} + +/* irq.c */ + +struct pirq *alloc_pirq_struct(struct domain *d) +{ + BUG(); +} + +int pirq_guest_bind(struct vcpu *v, struct pirq *pirq, int will_share) +{ + BUG(); +} + +void pirq_guest_unbind(struct domain *d, struct pirq *pirq) +{ + BUG(); +} + +void pirq_set_affinity(struct domain *d, int pirq, const cpumask_t *mask) +{ + BUG(); +} + +static void ack_none(struct irq_desc *irq) +{ + BUG(); +} + +static void end_none(struct irq_desc *irq) +{ + BUG(); +} + +hw_irq_controller no_irq_type = { + .typename = "none", + .startup = irq_startup_none, + .shutdown = irq_shutdown_none, + .enable = irq_enable_none, + .disable = irq_disable_none, + .ack = ack_none, + .end = end_none +}; + +int arch_init_one_irq_desc(struct irq_desc *desc) +{ + BUG(); +} + +void smp_send_state_dump(unsigned int cpu) +{ + BUG(); +} + +/* domain.c */ + +DEFINE_PER_CPU(struct vcpu *, curr_vcpu); +unsigned long __per_cpu_offset[NR_CPUS]; + +void context_switch(struct vcpu *prev, struct vcpu *next) +{ + BUG(); +} + +void continue_running(struct vcpu *same) +{ + BUG(); +} + +void sync_local_execstate(void) +{ + BUG(); +} + +void sync_vcpu_execstate(struct vcpu *v) +{ + BUG(); +} + +void startup_cpu_idle_loop(void) +{ + BUG(); +} + +void free_domain_struct(struct domain *d) +{ + BUG(); +} + +void dump_pageframe_info(struct domain *d) +{ + BUG(); +} + +void free_vcpu_struct(struct vcpu *v) +{ + BUG(); +} + +int arch_vcpu_create(struct vcpu *v) +{ + BUG(); +} + +void arch_vcpu_destroy(struct vcpu *v) +{ + BUG(); +} + +void vcpu_switch_to_aarch64_mode(struct vcpu *v) +{ + BUG(); +} + +int arch_sanitise_domain_config(struct xen_domctl_createdomain *config) +{ + BUG(); +} + +int arch_domain_create(struct domain *d, + struct xen_domctl_createdomain *config, + unsigned int flags) +{ + BUG(); +} + +int arch_domain_teardown(struct domain *d) +{ + BUG(); +} + +void arch_domain_destroy(struct domain *d) +{ + BUG(); +} + +void arch_domain_shutdown(struct domain *d) +{ + BUG(); +} + +void arch_domain_pause(struct domain *d) +{ + BUG(); +} + +void arch_domain_unpause(struct domain *d) +{ + BUG(); +} + +int arch_domain_soft_reset(struct domain *d) +{ + BUG(); +} + +void arch_domain_creation_finished(struct domain *d) +{ + BUG(); +} + +int arch_set_info_guest(struct vcpu *v, vcpu_guest_context_u c) +{ + BUG(); +} + +int arch_initialise_vcpu(struct vcpu *v, XEN_GUEST_HANDLE_PARAM(void) arg) +{ + BUG(); +} + +int arch_vcpu_reset(struct vcpu *v) +{ + BUG(); +} + +int domain_relinquish_resources(struct domain *d) +{ + BUG(); +} + +void arch_dump_domain_info(struct domain *d) +{ + BUG(); +} + +void arch_dump_vcpu_info(struct vcpu *v) +{ + BUG(); +} + +void vcpu_mark_events_pending(struct vcpu *v) +{ + BUG(); +} + +void vcpu_update_evtchn_irq(struct vcpu *v) +{ + BUG(); +} + +void vcpu_block_unless_event_pending(struct vcpu *v) +{ + BUG(); +} + +void vcpu_kick(struct vcpu *v) +{ + BUG(); +} + +struct domain *alloc_domain_struct(void) +{ + BUG(); +} + +struct vcpu *alloc_vcpu_struct(const struct domain *d) +{ + BUG(); +} + +unsigned long +hypercall_create_continuation(unsigned int op, const char *format, ...) +{ + BUG(); +} + +int __init parse_arch_dom0_param(const char *s, const char *e) +{ + BUG(); +} + +/* guestcopy.c */ + +unsigned long raw_copy_to_guest(void *to, const void *from, unsigned int len) +{ + BUG(); +} + +unsigned long raw_copy_from_guest(void *to, const void __user *from, + unsigned int len) +{ + BUG(); +} + +/* sysctl.c */ + +long arch_do_sysctl(struct xen_sysctl *sysctl, + XEN_GUEST_HANDLE_PARAM(xen_sysctl_t) u_sysctl) +{ + BUG(); +} + +void arch_do_physinfo(struct xen_sysctl_physinfo *pi) +{ + BUG(); +} + +/* p2m.c */ + +int arch_set_paging_mempool_size(struct domain *d, uint64_t size) +{ + BUG(); +} + +int unmap_mmio_regions(struct domain *d, + gfn_t start_gfn, + unsigned long nr, + mfn_t mfn) +{ + BUG(); +} + +int map_mmio_regions(struct domain *d, + gfn_t start_gfn, + unsigned long nr, + mfn_t mfn) +{ + BUG(); +} + +int set_foreign_p2m_entry(struct domain *d, const struct domain *fd, + unsigned long gfn, mfn_t mfn) +{ + BUG(); +} + +/* Return the size of the pool, in bytes. */ +int arch_get_paging_mempool_size(struct domain *d, uint64_t *size) +{ + BUG(); +} + +/* delay.c */ + +void udelay(unsigned long usecs) +{ + BUG_ON("unimplemented"); +} diff --git a/xen/arch/riscv/traps.c b/xen/arch/riscv/traps.c index ccd3593f5a..ca56df75d8 100644 --- a/xen/arch/riscv/traps.c +++ b/xen/arch/riscv/traps.c @@ -4,6 +4,10 @@ * * RISC-V Trap handlers */ + +#include +#include + #include #include @@ -11,3 +15,24 @@ void do_trap(struct cpu_user_regs *cpu_regs) { die(); } + +void vcpu_show_execution_state(struct vcpu *v) +{ + assert_failed("need to be implented"); +} + +void show_execution_state(const struct cpu_user_regs *regs) +{ + printk("implement show_execution_state(regs)\n"); +} + +void arch_hypercall_tasklet_result(struct vcpu *v, long res) +{ + assert_failed("need to be implented"); +} + +enum mc_disposition arch_do_multicall_call(struct mc_state *state) +{ + assert_failed("need to be implented"); + return mc_continue; +} From patchwork Fri Nov 24 10:30:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii X-Patchwork-Id: 13467501 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0CCAEC61DF4 for ; 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([94.75.70.14]) by smtp.gmail.com with ESMTPSA id g1-20020a170906348100b009de3641d538sm1882374ejb.134.2023.11.24.02.31.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Nov 2023 02:31:47 -0800 (PST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: ac53029a-8ab4-11ee-98e2-6d05b1d4d9a1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1700821908; x=1701426708; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Z1w34BSjUAi4k8RmSoj0kwk7zKOzvOqC/Wauz6/CNUk=; b=P0uy1NiUvsDK9vbmEO3yYsx/EH8fuP7NmSmM8Hnys5cgAHqQ9cZ/xJONb+D8Q3Zpy6 wkHSSBtEHQp3IEM8vXpC5QwYMv3AMB3KU9xzfMv82Iu/Dgg290jSEppctQguyF5KLlll JCrbUIe61QA+ITrFR46z+t+S9yrXVnIBTYcayMgip4EMxnRhXTTdrWnqCUcfg3Zdzrn4 6yaHpI55qce7O1GeLskxO9emNqjbZimrTDhL4ZVEiqBBMgWJe0t9LJG/Rel2s3z51C+K bOATyM0hqndPosPGjfsG3DI5U9Wehm4zhR9IVz5EOPMZmcrQ/pINyuqZtDqp+65vC7Kt u/LQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700821908; x=1701426708; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Z1w34BSjUAi4k8RmSoj0kwk7zKOzvOqC/Wauz6/CNUk=; b=n3Hdy/MwLv7tB+6foZ2a5LpP1AJ95wJe8LWQi6SdKbok9KDWVqT/QRUcZN4HnY5mAn 8ZVxXIl/eO4JkwrvjH3dVSKjG8kyQwJ8dXz+Ts1IPVWJYp7pNidmo52tkk0LWK+Zv4Gc vlflTRZ7HXNdQuU2+aytW5+fon83o3tZ6N+lFn5nyb2ehVyooGPz1velK+WXSKuz3nOh PHH6HBX+62k2k8euJ0Z7kpqtPeUZ69k2tG0XBq39jGQqN7cFKf5FDSUyMyyfo9erUvrf RThT9y8KGo9noM/nevEKvon+HRSW2wHH5eDl57OHpy8YrH84PxRPntCmYyVdccHdUyLI lNHA== X-Gm-Message-State: AOJu0Yxi2kRLlxMhlPSPzp+lA2EgRUjNfe6p+cdFIivVfY6iSt/afI6q 8sQfBRLssJEKJ6F8KvvoeszkluuZ7ZtxUQ== X-Google-Smtp-Source: AGHT+IHegBpC6Wr4W+8DeWaJJI/TRZ9D6YPDNiX62BYLTVqZPon3+2DL1aWyhBud5bWTm/eTPo6CBA== X-Received: by 2002:a17:906:c351:b0:a08:1ea3:e65a with SMTP id ci17-20020a170906c35100b00a081ea3e65amr1724981ejb.30.1700821907858; Fri, 24 Nov 2023 02:31:47 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini , Wei Liu Subject: [PATCH v2 38/39] xen/riscv: enable full Xen build Date: Fri, 24 Nov 2023 12:30:58 +0200 Message-ID: X-Mailer: git-send-email 2.42.0 In-Reply-To: References: MIME-Version: 1.0 Signed-off-by: Oleksii Kurochko Reviewed-by: Jan Beulich --- Changes in V2: - Nothing changed. Only rebase. --- xen/arch/riscv/Makefile | 16 +++++++++++++++- xen/arch/riscv/arch.mk | 4 ---- xen/arch/riscv/configs/tiny64_defconfig | 1 - 3 files changed, 15 insertions(+), 6 deletions(-) diff --git a/xen/arch/riscv/Makefile b/xen/arch/riscv/Makefile index 50c09469a0..9c02cb0ccf 100644 --- a/xen/arch/riscv/Makefile +++ b/xen/arch/riscv/Makefile @@ -12,10 +12,24 @@ $(TARGET): $(TARGET)-syms $(OBJCOPY) -O binary -S $< $@ $(TARGET)-syms: $(objtree)/prelink.o $(obj)/xen.lds - $(LD) $(XEN_LDFLAGS) -T $(obj)/xen.lds -N $< $(build_id_linker) -o $@ + $(LD) $(XEN_LDFLAGS) -T $(obj)/xen.lds -N $< \ + $(objtree)/common/symbols-dummy.o -o $(dot-target).0 + $(NM) -pa --format=sysv $(dot-target).0 \ + | $(objtree)/tools/symbols $(all_symbols) --sysv --sort \ + > $(dot-target).0.S + $(MAKE) $(build)=$(@D) $(dot-target).0.o + $(LD) $(XEN_LDFLAGS) -T $(obj)/xen.lds -N $< \ + $(dot-target).0.o -o $(dot-target).1 + $(NM) -pa --format=sysv $(dot-target).1 \ + | $(objtree)/tools/symbols $(all_symbols) --sysv --sort \ + > $(dot-target).1.S + $(MAKE) $(build)=$(@D) $(dot-target).1.o + $(LD) $(XEN_LDFLAGS) -T $(obj)/xen.lds -N $< $(build_id_linker) \ + $(dot-target).1.o -o $@ $(NM) -pa --format=sysv $@ \ | $(objtree)/tools/symbols --all-symbols --xensyms --sysv --sort \ > $@.map + rm -f $(@D)/.$(@F).[0-9]* $(obj)/xen.lds: $(src)/xen.lds.S FORCE $(call if_changed_dep,cpp_lds_S) diff --git a/xen/arch/riscv/arch.mk b/xen/arch/riscv/arch.mk index 8403f96b6f..12b1673fae 100644 --- a/xen/arch/riscv/arch.mk +++ b/xen/arch/riscv/arch.mk @@ -13,7 +13,3 @@ riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c # -mcmodel=medlow would force Xen into the lower half. CFLAGS += -march=$(riscv-march-y) -mstrict-align -mcmodel=medany - -# TODO: Drop override when more of the build is working -override ALL_OBJS-y = arch/$(SRCARCH)/built_in.o -override ALL_LIBS-y = diff --git a/xen/arch/riscv/configs/tiny64_defconfig b/xen/arch/riscv/configs/tiny64_defconfig index ce37c5ae00..4b488180ae 100644 --- a/xen/arch/riscv/configs/tiny64_defconfig +++ b/xen/arch/riscv/configs/tiny64_defconfig @@ -24,7 +24,6 @@ # CONFIG_COVERAGE is not set # CONFIG_UBSAN is not set # CONFIG_NEEDS_LIBELF is not set - CONFIG_RISCV_64=y CONFIG_DEBUG=y CONFIG_DEBUG_INFO=y From patchwork Fri Nov 24 10:30:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii X-Patchwork-Id: 13467527 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 572A7C61DF4 for ; Fri, 24 Nov 2023 10:49:22 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.640516.998862 (Exim 4.92) (envelope-from ) id 1r6TkC-0005by-Kb; Fri, 24 Nov 2023 10:49:08 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 640516.998862; Fri, 24 Nov 2023 10:49:08 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1r6TkC-0005br-HY; Fri, 24 Nov 2023 10:49:08 +0000 Received: by outflank-mailman (input) for mailman id 640516; Fri, 24 Nov 2023 10:49:07 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1r6TTU-0006hy-MZ for xen-devel@lists.xenproject.org; Fri, 24 Nov 2023 10:31:52 +0000 Received: from mail-ed1-x536.google.com (mail-ed1-x536.google.com [2a00:1450:4864:20::536]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id acca16f6-8ab4-11ee-98e2-6d05b1d4d9a1; Fri, 24 Nov 2023 11:31:49 +0100 (CET) Received: by mail-ed1-x536.google.com with SMTP id 4fb4d7f45d1cf-548f0b7ab11so2450252a12.1 for ; Fri, 24 Nov 2023 02:31:49 -0800 (PST) Received: from fedora.. ([94.75.70.14]) by smtp.gmail.com with ESMTPSA id g1-20020a170906348100b009de3641d538sm1882374ejb.134.2023.11.24.02.31.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Nov 2023 02:31:48 -0800 (PST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: acca16f6-8ab4-11ee-98e2-6d05b1d4d9a1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1700821908; x=1701426708; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0+aQuxKjfQGzFTZoazT2PEhCRLSw5p9w+6+GEIbGRQE=; b=dR66v/Ky2iaNX1EUxZfWCloAZ8t0HeaJ8HzOU9hxBXeBdE9Ygmh9uIqKhXLWF7xzJd UA8INshW8w+PPoIvUfQU0JrOJnk6XWZ2hapRcvYqaXcfciV/8DyAwHu+7BjWwCEFhvxt al/yjdjfANn0FTdo2RbOyxi9SAEL6jU860gEaTpRE97i1CUhaWuBVOHc8FXbL0vj1gq0 9b+MJi1D3LdobKqu5d16oOvZprI9jKbC3g9bvAWrblxhpMOjWvzIKjzYeQglEY367bD0 lygKsWrjXlWt6h5vw9vmh6IT/V9aBbtcvL2qyVmHs2EHBSfpBrnVbGt/lByBB8XR1x/u zfBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700821908; x=1701426708; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0+aQuxKjfQGzFTZoazT2PEhCRLSw5p9w+6+GEIbGRQE=; b=P5k3YS4WvpTx6HASkg6GyKdovOyzmLK6K3cruLq8srhX/BX/B+oahxYIWp/vrrb+KU JK8LMdVxZ75CnNdkkJr1o1K194xlBKG/5lAw+PKxV3LEOirqgZiSK1p9lbBRLxfbRpXK vn8iX/599l5WO/tptherfUmN3/7sNjqhiAlWdn9+uCqe9aG0KlNHCuNOB1oPrCOQeBGF IZ1OW/c3faTxYphHICgoH37izrz6nJSSMzGSK9Si1ZWExx1PhVEqwaYkLKXNFdCgIrgo rlcriSxNXJlG295zuS4OATrNNcL79MblBesbRduso6iUqEwMe/t1Bti/b0N/jAv+jvWR OItQ== X-Gm-Message-State: AOJu0YxVlNbA2bJSrrSswKQIY3jjBjk9BrFSWAw40UfWgaEuLliU4Fr8 mDPAW6qq932y3d0Oh8SMvU7VJg15FEy6ag== X-Google-Smtp-Source: AGHT+IFwI0S4Mg/Ep/Heeyi1TtpQWh+LY+imflpzU/xVjPVSNoFn/noZ0fiWhCkbkZUdq1gr+BwP7A== X-Received: by 2002:a17:906:389b:b0:a02:1e8d:b94f with SMTP id q27-20020a170906389b00b00a021e8db94fmr1568595ejd.57.1700821908613; Fri, 24 Nov 2023 02:31:48 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini , Wei Liu Subject: [PATCH v2 39/39] xen: fix compilation issue of serial.c Date: Fri, 24 Nov 2023 12:30:59 +0200 Message-ID: <6e1f19de1e8a276d487e8517810da3e8e68104ff.1700761381.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: References: MIME-Version: 1.0 The following issue occurs on RISC-V platforms: drivers/char/serial.c: In function 'serial_tx_interrupt': drivers/char/serial.c:88:9: error: implicit declaration of function 'cpu_relax' [-Werror=implicit-function-declaration] 88 | cpu_relax(); cpu_relax() is defined in so it was added an inclusion of the header to serial.c. Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in V2: - New commit introduced in V2 --- xen/drivers/char/serial.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/xen/drivers/char/serial.c b/xen/drivers/char/serial.c index 00efe69574..35df58fe33 100644 --- a/xen/drivers/char/serial.c +++ b/xen/drivers/char/serial.c @@ -13,6 +13,8 @@ #include #include +#include + /* Never drop characters, even if the async transmit buffer fills. */ /* #define SERIAL_NEVER_DROP_CHARS 1 */