From patchwork Sun Nov 26 19:24:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dustin Howett X-Patchwork-Id: 13468905 Received: from mail-qk1-f175.google.com (mail-qk1-f175.google.com [209.85.222.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 189BF12E5E for ; Sun, 26 Nov 2023 19:25:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=howett.net Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=howett.net Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=howett-net.20230601.gappssmtp.com header.i=@howett-net.20230601.gappssmtp.com header.b="VuWrYxg4" Received: by mail-qk1-f175.google.com with SMTP id af79cd13be357-77bc5d8490dso207064485a.2 for ; Sun, 26 Nov 2023 11:25:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=howett-net.20230601.gappssmtp.com; s=20230601; t=1701026735; x=1701631535; darn=lists.linux.dev; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/yjOW47KPDjDxeJtA12FOIyY/Sie9budiJ/BOigC7v0=; b=VuWrYxg470q5gLdCpjkzQ9VZQ+nzz0w6jHTCK7X1YWiS7RLF3VBWRbYKbm3yLTjowj u5eB0xHCO4bgww18rcwkBXfa4NiE56opCmK5hwkCJrcy5n/K3J30ZldVwq3Ny8uacRun clqSRausc417HvciqFdmep7QtiOh/WGCaTBR/0qJ82wBofdgqoOOnf38AAXt8dvZMi/A VnhuKSuFT2GJ5c6Z8oRPP6yo4uComavQ/5VfzLi7b7/WidIyfKZ6Gl2o2bN+2N5G4nOQ 3rwvbhi0xFtTQK8dFq0LOybj/QRlWyfWRDLemKIARWEzUlVjCeNM9vbCU3AuTxw5oI2L qV0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701026735; x=1701631535; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/yjOW47KPDjDxeJtA12FOIyY/Sie9budiJ/BOigC7v0=; b=CnUKsY7RzJcxAQNSh4Zuf0J7xGxvhHtAtS0UJgedmGnb3+09b1vxWvY0M3SFFFe22H zdkJLFMxenEyrqdOdBUeRgtzPHmfEqL+l93XmEwc6M2cACe8geWwrQrCW/vTdl1mKxoC i7sc6MDA49kyJowqDGitQb7CKNnR5fu51IwQaCNXXY9zHMjHvm/KGZoo69poMUcDV5Y/ R5JDbziI8I2aWEm3qug0NzDiBvzc648O96y/QJelT8LZ5FKThEd1mqsOQPxEUH4uA4nf veXJkUDJ+0CGk6repTEprJ6lwG/3C7X/xLrhFDuViVyX6eZkd5e5ap8STbkPh9Vr+t+b DnMQ== X-Gm-Message-State: AOJu0YxKcCUYiNEB2uAX54PA8hsoRLXtvaTDcWJDu5qdwysjXIAyVniY MvS9lL32K0l9HqkCEYnbHSK4jyIVc/1Z1alswoc= X-Google-Smtp-Source: AGHT+IG6OSLrvK2Iz/jGyTCz9moY5EeWD2JGQ4M+8a8m2SvOcaNRYT0Hs5wDJmAYsaapLlQP5asp1Q== X-Received: by 2002:a05:620a:6003:b0:773:cb13:cb7d with SMTP id dw3-20020a05620a600300b00773cb13cb7dmr11377601qkb.48.1701026734807; Sun, 26 Nov 2023 11:25:34 -0800 (PST) Received: from localhost.localdomain ([184.169.45.4]) by smtp.googlemail.com with ESMTPSA id tx10-20020a05620a3f0a00b0076f1d8b1c2dsm3099040qkn.12.2023.11.26.11.25.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Nov 2023 11:25:34 -0800 (PST) From: "Dustin L. Howett" To: Tzung-Bi Shih , Guenter Roeck , chrome-platform@lists.linux.dev Cc: "Dustin L. Howett" Subject: [PATCH v2 1/4] platform/chrome: cros_ec_lpc: introduce a priv struct for the lpc device Date: Sun, 26 Nov 2023 13:24:49 -0600 Message-ID: <20231126192452.97824-2-dustin@howett.net> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231126192452.97824-1-dustin@howett.net> References: <20231005160701.19987-1-dustin@howett.net> <20231126192452.97824-1-dustin@howett.net> Precedence: bulk X-Mailing-List: chrome-platform@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 lpc_driver_data stores the MMIO port base for EC mapped memory. cros_ec_lpc_readmem uses this port base instead of hardcoding EC_LPC_ADDR_MEMMAP. Signed-off-by: Dustin L. Howett --- drivers/platform/chrome/cros_ec_lpc.c | 25 +++++++++++++++++++++---- 1 file changed, 21 insertions(+), 4 deletions(-) diff --git a/drivers/platform/chrome/cros_ec_lpc.c b/drivers/platform/chrome/cros_ec_lpc.c index 356572452898..9f2ea75c76b6 100644 --- a/drivers/platform/chrome/cros_ec_lpc.c +++ b/drivers/platform/chrome/cros_ec_lpc.c @@ -34,6 +34,14 @@ /* True if ACPI device is present */ static bool cros_ec_lpc_acpi_device_found; +/** + * struct cros_ec_lpc - LPC device-specific data + * @mmio_memory_base: The first I/O port addressing EC mapped memory. + */ +struct cros_ec_lpc { + u16 mmio_memory_base; +}; + /** * struct lpc_driver_ops - LPC driver operations * @read: Copy length bytes from EC address offset into buffer dest. Returns @@ -290,6 +298,7 @@ static int cros_ec_cmd_xfer_lpc(struct cros_ec_device *ec, static int cros_ec_lpc_readmem(struct cros_ec_device *ec, unsigned int offset, unsigned int bytes, void *dest) { + struct cros_ec_lpc *ec_lpc = ec->priv; int i = offset; char *s = dest; int cnt = 0; @@ -299,13 +308,13 @@ static int cros_ec_lpc_readmem(struct cros_ec_device *ec, unsigned int offset, /* fixed length */ if (bytes) { - cros_ec_lpc_ops.read(EC_LPC_ADDR_MEMMAP + offset, bytes, s); + cros_ec_lpc_ops.read(ec_lpc->mmio_memory_base + offset, bytes, s); return bytes; } /* string */ for (; i < EC_MEMMAP_SIZE; i++, s++) { - cros_ec_lpc_ops.read(EC_LPC_ADDR_MEMMAP + i, 1, s); + cros_ec_lpc_ops.read(ec_lpc->mmio_memory_base + i, 1, s); cnt++; if (!*s) break; @@ -353,9 +362,16 @@ static int cros_ec_lpc_probe(struct platform_device *pdev) struct acpi_device *adev; acpi_status status; struct cros_ec_device *ec_dev; + struct cros_ec_lpc *ec_lpc; u8 buf[2] = {}; int irq, ret; + ec_lpc = devm_kzalloc(dev, sizeof(*ec_lpc), GFP_KERNEL); + if (!ec_lpc) + return -ENOMEM; + + ec_lpc->mmio_memory_base = EC_LPC_ADDR_MEMMAP; + /* * The Framework Laptop (and possibly other non-ChromeOS devices) * only exposes the eight I/O ports that are required for the Microchip EC. @@ -380,7 +396,7 @@ static int cros_ec_lpc_probe(struct platform_device *pdev) cros_ec_lpc_ops.write = cros_ec_lpc_mec_write_bytes; cros_ec_lpc_ops.read(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_ID, 2, buf); if (buf[0] != 'E' || buf[1] != 'C') { - if (!devm_request_region(dev, EC_LPC_ADDR_MEMMAP, EC_MEMMAP_SIZE, + if (!devm_request_region(dev, ec_lpc->mmio_memory_base, EC_MEMMAP_SIZE, dev_name(dev))) { dev_err(dev, "couldn't reserve memmap region\n"); return -EBUSY; @@ -389,7 +405,7 @@ static int cros_ec_lpc_probe(struct platform_device *pdev) /* Re-assign read/write operations for the non MEC variant */ cros_ec_lpc_ops.read = cros_ec_lpc_read_bytes; cros_ec_lpc_ops.write = cros_ec_lpc_write_bytes; - cros_ec_lpc_ops.read(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_ID, 2, + cros_ec_lpc_ops.read(ec_lpc->mmio_memory_base + EC_MEMMAP_ID, 2, buf); if (buf[0] != 'E' || buf[1] != 'C') { dev_err(dev, "EC ID not detected\n"); @@ -423,6 +439,7 @@ static int cros_ec_lpc_probe(struct platform_device *pdev) ec_dev->din_size = sizeof(struct ec_host_response) + sizeof(struct ec_response_get_protocol_info); ec_dev->dout_size = sizeof(struct ec_host_request); + ec_dev->priv = ec_lpc; /* * Some boards do not have an IRQ allotted for cros_ec_lpc, From patchwork Sun Nov 26 19:24:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dustin Howett X-Patchwork-Id: 13468906 Received: from mail-oi1-f180.google.com (mail-oi1-f180.google.com [209.85.167.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4E5DE12E50 for ; Sun, 26 Nov 2023 19:25:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=howett.net Authentication-Results: smtp.subspace.kernel.org; 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Sun, 26 Nov 2023 11:25:39 -0800 (PST) From: "Dustin L. Howett" To: Tzung-Bi Shih , Guenter Roeck , chrome-platform@lists.linux.dev Cc: "Dustin L. Howett" Subject: [PATCH v2 2/4] platform/chrome: cros_ec_lpc: pass driver_data from DMI to the device Date: Sun, 26 Nov 2023 13:24:50 -0600 Message-ID: <20231126192452.97824-3-dustin@howett.net> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231126192452.97824-1-dustin@howett.net> References: <20231005160701.19987-1-dustin@howett.net> <20231126192452.97824-1-dustin@howett.net> Precedence: bulk X-Mailing-List: chrome-platform@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 lpc_driver_data will be stored in drvdata until probe is complete, at which point it will be replaced with a cros_ec_device. Signed-off-by: Dustin L. Howett --- drivers/platform/chrome/cros_ec_lpc.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/platform/chrome/cros_ec_lpc.c b/drivers/platform/chrome/cros_ec_lpc.c index 9f2ea75c76b6..f1d1615d9b37 100644 --- a/drivers/platform/chrome/cros_ec_lpc.c +++ b/drivers/platform/chrome/cros_ec_lpc.c @@ -615,14 +615,16 @@ static int __init cros_ec_lpc_init(void) { int ret; acpi_status status; + const struct dmi_system_id *dmi_match; status = acpi_get_devices(ACPI_DRV_NAME, cros_ec_lpc_parse_device, &cros_ec_lpc_acpi_device_found, NULL); if (ACPI_FAILURE(status)) pr_warn(DRV_NAME ": Looking for %s failed\n", ACPI_DRV_NAME); - if (!cros_ec_lpc_acpi_device_found && - !dmi_check_system(cros_ec_lpc_dmi_table)) { + dmi_match = dmi_first_match(cros_ec_lpc_dmi_table); + + if (!cros_ec_lpc_acpi_device_found && !dmi_match) { pr_err(DRV_NAME ": unsupported system.\n"); return -ENODEV; } @@ -635,6 +637,9 @@ static int __init cros_ec_lpc_init(void) } if (!cros_ec_lpc_acpi_device_found) { + /* Pass the DMI match's driver data down to the platform device */ + platform_set_drvdata(&cros_ec_lpc_device, dmi_match->driver_data); + /* Register the device, and it'll get hooked up automatically */ ret = platform_device_register(&cros_ec_lpc_device); if (ret) { From patchwork Sun Nov 26 19:24:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dustin Howett X-Patchwork-Id: 13468907 Received: from mail-qk1-f181.google.com (mail-qk1-f181.google.com [209.85.222.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CB70E12E60 for ; Sun, 26 Nov 2023 19:25:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=howett.net Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=howett.net Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=howett-net.20230601.gappssmtp.com header.i=@howett-net.20230601.gappssmtp.com header.b="A2+0EE5M" Received: by mail-qk1-f181.google.com with SMTP id af79cd13be357-77d63b733e4so187106185a.2 for ; Sun, 26 Nov 2023 11:25:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=howett-net.20230601.gappssmtp.com; s=20230601; t=1701026745; x=1701631545; darn=lists.linux.dev; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pOEfYnzVQ/0R7YLkmOSjhQ1I/vLdB55xU9yypEKMGxg=; b=A2+0EE5MpAc70LGTydMO0jc0PK/w9Uc8rEQAvzBKfBknQ/wJMPSxGewvV6OD3kGLOb 3EQjjups7JouGPWLTWQx1xcWmrdacZFNEuAf8AhPXg3TXgN1TYAJKYFDm43gFMs9akEa CQMu90ViFX/3P9AiwAiXkQXp0+nRu0scooIO60PQqhW7gqfxaoJW7VYr744vi76BdCYh HisAr/6nvxvu24jL1QNb0A3FUNYYIqQpFH4ow04Fg7cDBtkaKyPg488UHNOIe3vEvc73 pnQrfe6/Y2ltlARn+sir8B2RR2VBZNIOZcaqaYhKwM6g9fu2I9LZoOArtLi5GNxW4y7G k8og== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701026745; x=1701631545; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pOEfYnzVQ/0R7YLkmOSjhQ1I/vLdB55xU9yypEKMGxg=; b=I0pCzlCIKiA9j44voQqbRrC1qSaLYjPsfN0BE4eGo/Gt0OnSeXJ8lJch/P8uj1YWuv CUeAn/tmPQRVZv9JcCqJnwrHZBXRy0SiTqHWZ7GRluX3FNs8PDiTyISyl/iuJwy/OMre igaSSLuHlDqEjY5a/vXA25B3+wn0UpX/lF4G15cHhg81QZserJLt11MrVpZqHcAjOp/U 3pJXJ8IqMttIRusVV5k9VrFKv7xsWDK3sHX4ziTW3P/k8Qv5gNNV8DbgsQfY4ybvedJg WD6WjeKSheC5jP1BxoKP2NHT6HMJxgLn6L1dO4XPQaN5rKdkJX34KXfSRb1huseBXAmx uJtg== X-Gm-Message-State: AOJu0YzswdFWlJCLUMu2Mvm5IR31+xGGvAjdsCToV8y5LneJ65GvH9Hh o4Bl3VAhvhFKRmI7yxzu0PsPcZ/ePDSlmgXo0aU= X-Google-Smtp-Source: AGHT+IErIveg1DiqJ7LTAYI7BHg6soOgsEfhgBKjH+O+8l9H03en8AOWSL0jx+BApAQX2kbyFFVzYA== X-Received: by 2002:a05:620a:6193:b0:777:73e8:e24d with SMTP id or19-20020a05620a619300b0077773e8e24dmr10268854qkn.21.1701026745415; Sun, 26 Nov 2023 11:25:45 -0800 (PST) Received: from localhost.localdomain ([184.169.45.4]) by smtp.googlemail.com with ESMTPSA id tx10-20020a05620a3f0a00b0076f1d8b1c2dsm3099040qkn.12.2023.11.26.11.25.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Nov 2023 11:25:45 -0800 (PST) From: "Dustin L. Howett" To: Tzung-Bi Shih , Guenter Roeck , chrome-platform@lists.linux.dev Cc: "Dustin L. Howett" Subject: [PATCH v2 3/4] platform/chrome: cros_ec_lpc: add a "quirks" system Date: Sun, 26 Nov 2023 13:24:51 -0600 Message-ID: <20231126192452.97824-4-dustin@howett.net> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231126192452.97824-1-dustin@howett.net> References: <20231005160701.19987-1-dustin@howett.net> <20231126192452.97824-1-dustin@howett.net> Precedence: bulk X-Mailing-List: chrome-platform@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Some devices ship a ChromeOS EC in a non-standard configuration. Quirks allow cros_ec_lpc to account for these non-standard configurations. It supports the following quirks: - CROS_EC_LPC_QUIRK_REMAP_MEMORY: use a different port I/O base for MMIO to the EC's memory region - CROS_EC_LPC_QUIRK_SHORT_HOSTCMD_RESERVATION: only attempt to reserve 0xff (rather than 0x100) I/O ports for the host command region Signed-off-by: Dustin L. Howett --- drivers/platform/chrome/cros_ec_lpc.c | 42 ++++++++++++++++++++++++++- 1 file changed, 41 insertions(+), 1 deletion(-) diff --git a/drivers/platform/chrome/cros_ec_lpc.c b/drivers/platform/chrome/cros_ec_lpc.c index f1d1615d9b37..a65c9a8bca5e 100644 --- a/drivers/platform/chrome/cros_ec_lpc.c +++ b/drivers/platform/chrome/cros_ec_lpc.c @@ -34,6 +34,29 @@ /* True if ACPI device is present */ static bool cros_ec_lpc_acpi_device_found; +/* + * Indicates that the driver should only reserve 0xFF I/O ports + * (rather than 0x100) for the host command mapped memory region. + */ +#define CROS_EC_LPC_QUIRK_SHORT_HOSTCMD_RESERVATION BIT(0) +/* + * Indicates that lpc_driver_data.quirk_mmio_memory_base should + * be used as the base port for EC mapped memory. + */ +#define CROS_EC_LPC_QUIRK_REMAP_MEMORY BIT(1) + +/** + * struct lpc_driver_data - driver data attached to a DMI device ID to indicate + * hardware quirks. + * @quirks: a bitfield composed of quirks from CROS_EC_LPC_QUIRK_* + * @quirk_mmio_memory_base: The first I/O port addressing EC mapped memory (used + * when quirks (...REMAP_MEMORY) is set. + */ +struct lpc_driver_data { + u32 quirks; + u16 quirk_mmio_memory_base; +}; + /** * struct cros_ec_lpc - LPC device-specific data * @mmio_memory_base: The first I/O port addressing EC mapped memory. @@ -363,8 +386,11 @@ static int cros_ec_lpc_probe(struct platform_device *pdev) acpi_status status; struct cros_ec_device *ec_dev; struct cros_ec_lpc *ec_lpc; + struct lpc_driver_data *driver_data; + int region1_size = EC_HOST_CMD_REGION_SIZE; u8 buf[2] = {}; int irq, ret; + u32 quirks = 0; ec_lpc = devm_kzalloc(dev, sizeof(*ec_lpc), GFP_KERNEL); if (!ec_lpc) @@ -372,6 +398,20 @@ static int cros_ec_lpc_probe(struct platform_device *pdev) ec_lpc->mmio_memory_base = EC_LPC_ADDR_MEMMAP; + driver_data = platform_get_drvdata(pdev); + if (driver_data) { + quirks = driver_data->quirks; + + if (quirks) + dev_info(dev, "loaded with quirks %8.08x\n", quirks); + + if (quirks & CROS_EC_LPC_QUIRK_REMAP_MEMORY) + ec_lpc->mmio_memory_base = driver_data->quirk_mmio_memory_base; + + if (quirks & CROS_EC_LPC_QUIRK_SHORT_HOSTCMD_RESERVATION) + region1_size -= 1; + } + /* * The Framework Laptop (and possibly other non-ChromeOS devices) * only exposes the eight I/O ports that are required for the Microchip EC. @@ -420,7 +460,7 @@ static int cros_ec_lpc_probe(struct platform_device *pdev) return -EBUSY; } if (!devm_request_region(dev, EC_HOST_CMD_REGION1, - EC_HOST_CMD_REGION_SIZE, dev_name(dev))) { + region1_size, dev_name(dev))) { dev_err(dev, "couldn't reserve region1\n"); return -EBUSY; } From patchwork Sun Nov 26 19:24:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dustin Howett X-Patchwork-Id: 13468908 Received: from mail-yb1-f175.google.com (mail-yb1-f175.google.com [209.85.219.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0F41410958 for ; Sun, 26 Nov 2023 19:25:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=howett.net Authentication-Results: smtp.subspace.kernel.org; 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Sun, 26 Nov 2023 11:25:50 -0800 (PST) Received: from localhost.localdomain ([184.169.45.4]) by smtp.googlemail.com with ESMTPSA id tx10-20020a05620a3f0a00b0076f1d8b1c2dsm3099040qkn.12.2023.11.26.11.25.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Nov 2023 11:25:50 -0800 (PST) From: "Dustin L. Howett" To: Tzung-Bi Shih , Guenter Roeck , chrome-platform@lists.linux.dev Cc: "Dustin L. Howett" Subject: [PATCH v2 4/4] platform/chrome: cros_ec_lpc: add quirks for the Framework Laptop (AMD) Date: Sun, 26 Nov 2023 13:24:52 -0600 Message-ID: <20231126192452.97824-5-dustin@howett.net> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231126192452.97824-1-dustin@howett.net> References: <20231005160701.19987-1-dustin@howett.net> <20231126192452.97824-1-dustin@howett.net> Precedence: bulk X-Mailing-List: chrome-platform@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The original Framework Laptop 13 platform (Intel 11th, 12th, and 13th Generation at this time) uses a Microchip embedded controller in a standard configuration. The newer devices in this product line--Framework Laptop 13 and 16 (AMD Ryzen)--use a NPCX embedded controller. However, they deviate from the configuration of ChromeOS platforms built with the NPCX EC. * ACPI device _SB.PCI0.LPC0.EC0 only indicates I/O ports [0x800, 0x8FE] as being used, rather than the expected [0x800, 0x8FF]. *However*, the embedded controller does make use of all 0x100 ports. * The MMIO region for EC memory begins at port 0xE00 rather than the expected 0x900. cros_ec_lpc's quirks system is used to address both of these issues. Signed-off-by: Dustin L. Howett --- drivers/platform/chrome/cros_ec_lpc.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/platform/chrome/cros_ec_lpc.c b/drivers/platform/chrome/cros_ec_lpc.c index a65c9a8bca5e..9373c39c3ed9 100644 --- a/drivers/platform/chrome/cros_ec_lpc.c +++ b/drivers/platform/chrome/cros_ec_lpc.c @@ -538,6 +538,13 @@ static const struct acpi_device_id cros_ec_lpc_acpi_device_ids[] = { }; MODULE_DEVICE_TABLE(acpi, cros_ec_lpc_acpi_device_ids); +static const struct lpc_driver_data framework_laptop_amd_lpc_driver_data __initconst = { + .quirks = + CROS_EC_LPC_QUIRK_REMAP_MEMORY | + CROS_EC_LPC_QUIRK_SHORT_HOSTCMD_RESERVATION, + .quirk_mmio_memory_base = 0xE00, +}; + static const struct dmi_system_id cros_ec_lpc_dmi_table[] __initconst = { { /* @@ -592,7 +599,16 @@ static const struct dmi_system_id cros_ec_lpc_dmi_table[] __initconst = { }, /* A small number of non-Chromebook/box machines also use the ChromeOS EC */ { - /* the Framework Laptop */ + /* the Framework Laptop 13 (AMD Ryzen) and 16 (AMD Ryzen) */ + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Framework"), + DMI_MATCH(DMI_PRODUCT_NAME, "AMD Ryzen"), + DMI_MATCH(DMI_PRODUCT_FAMILY, "Laptop"), + }, + .driver_data = (void *)&framework_laptop_amd_lpc_driver_data, + }, + { + /* the Framework Laptop (Intel 11th, 12th, 13th Generation) */ .matches = { DMI_MATCH(DMI_SYS_VENDOR, "Framework"), DMI_MATCH(DMI_PRODUCT_NAME, "Laptop"),