From patchwork Thu Feb 14 17:57:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ray Jui X-Patchwork-Id: 10813399 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5E85D922 for ; Thu, 14 Feb 2019 17:58:05 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4BBB42EEA8 for ; Thu, 14 Feb 2019 17:58:05 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3E1992EED0; Thu, 14 Feb 2019 17:58:05 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id AE0292EEA8 for ; Thu, 14 Feb 2019 17:58:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=slyIxEv3UNcIJam4n7zY95+utt8h/poGdXg3ftMMlas=; b=fFMzp8O+dXlKow/mz4fpTqVkMs 0jZY70owr0fsaBwGnrxFZdDOv2vfnJkjx4epKaKIgQdj+yJAm/LtChnF7eVc63n2CW1JyaOaGgP9K Ux3c9LgZTY2H9mOqWTaux2eyX2+x2fjF/59UAF+trrO+I9iobUi0roTeBsNqLt9MUAAb4f2obrFDw COfefJ2tyBBVzunAu28Ij2HMZGLCZSU9Vo6GpEP7kyO7WARJkAFU+PsUW9PFv4puQRO2LfYKf9RCz 6HHgCz/a7bYSAmEoIq9nc1JT3SEkc7ZZuSy3+lCFvjHs8kyU9xdbqMRMcOiKflbz0Z4SFz6oSPlfQ 2cd768GQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1guLGo-00085A-IP; Thu, 14 Feb 2019 17:57:58 +0000 Received: from mail-it1-x141.google.com ([2607:f8b0:4864:20::141]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1guLGc-0007ms-8x for linux-arm-kernel@lists.infradead.org; Thu, 14 Feb 2019 17:57:50 +0000 Received: by mail-it1-x141.google.com with SMTP id v72so16556938itc.0 for ; Thu, 14 Feb 2019 09:57:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=eMDJ3N4Coywd8ehaqLaAHj4/nVmObQyAb5JBFHqgPAM=; b=iJlnxSXWDH+u2DvUTAfqfPBt8KxkE364uXxBDtbdPjQIVbbl/UIj26c03LfNqfat+4 qYh1HtXPbnMcQf3YwKZ/SgVNFLaBTFmQRug2+dS6EdrMtPewoqk3AqykXc3w+N47zk+K zKPNYhSELHKQoL8JgLXBsgxhTnYwQY2AmjWWI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=eMDJ3N4Coywd8ehaqLaAHj4/nVmObQyAb5JBFHqgPAM=; b=YD0jH3njjbLi8DtUxAQPvAAmxPJBWyY2srFDYDUVBgtkgePLlkWcrpD9rYJ7YLJt9v z9o+KV7okU9LxUn7i2XtujKA/6RD7Ro97l6Beji0HyWUrlqjngyYhbdm1tHTC40qMgO7 IPer49fE5h7bA1ChrTiVVg1d31uWaxX5QF2TR23i0XDmKxA3T4WKRnVBl6nDr5NewkwY 6DHLOgg0hC1hSPWKh7RTH/7YZsQtfH9R6QmSInr6s3wwI2rZj9iXtqjhECxMVayo3tDf t4cUBe3ZRv3fmWi4nYrFlNDkYHh0N10QT/oaZr9ow70MVNEnI0HTfLmihveXMGoSQuFP g5Sg== X-Gm-Message-State: AHQUAuaFp+Qnchhewz0uTDOo7/PCVU655xy00n1WYRyf2C8d2zAZzxcQ 91oPyCD7AhXVKA81OvKII5gGtQ== X-Google-Smtp-Source: AHgI3Ib5pPO2nUKVy3iKWWhra1BA9QmdtQJtabrGqDGe/tF6PyNYLTWmuEv9gYHBmoviVN5Q/YeLRQ== X-Received: by 2002:a24:de87:: with SMTP id d129mr2709056itg.110.1550167065178; Thu, 14 Feb 2019 09:57:45 -0800 (PST) Received: from rj-aorus.ric.broadcom.com ([192.19.228.250]) by smtp.gmail.com with ESMTPSA id t64sm1534178itb.5.2019.02.14.09.57.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 14 Feb 2019 09:57:44 -0800 (PST) From: Ray Jui To: Wolfram Sang , Rob Herring , Mark Rutland Subject: [PATCH v5 1/8] i2c: iproc: Extend I2C read up to 255 bytes Date: Thu, 14 Feb 2019 09:57:18 -0800 Message-Id: <20190214175725.60462-2-ray.jui@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190214175725.60462-1-ray.jui@broadcom.com> References: <20190214175725.60462-1-ray.jui@broadcom.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190214_095746_517819_45391304 X-CRM114-Status: GOOD ( 20.51 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Shreesha Rajashekar , Rayagonda Kokatanur , linux-kernel@vger.kernel.org, bcm-kernel-feedback-list@broadcom.com, linux-i2c@vger.kernel.org, Ray Jui , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Shreesha Rajashekar Add support to allow I2C master read transfer up to 255 bytes. Signed-off-by: Shreesha Rajashekar Signed-off-by: Rayagonda Kokatanur Signed-off-by: Ray Jui --- drivers/i2c/busses/i2c-bcm-iproc.c | 98 +++++++++++++++++++++++------- 1 file changed, 76 insertions(+), 22 deletions(-) diff --git a/drivers/i2c/busses/i2c-bcm-iproc.c b/drivers/i2c/busses/i2c-bcm-iproc.c index 4c8c3bc4669c..eb7339a0280e 100644 --- a/drivers/i2c/busses/i2c-bcm-iproc.c +++ b/drivers/i2c/busses/i2c-bcm-iproc.c @@ -80,6 +80,10 @@ #define I2C_TIMEOUT_MSEC 50000 #define M_TX_RX_FIFO_SIZE 64 +#define M_RX_FIFO_MAX_THLD_VALUE (M_TX_RX_FIFO_SIZE - 1) + +#define M_RX_MAX_READ_LEN 255 +#define M_RX_FIFO_THLD_VALUE 50 enum bus_speed_index { I2C_SPD_100K = 0, @@ -102,17 +106,41 @@ struct bcm_iproc_i2c_dev { /* bytes that have been transferred */ unsigned int tx_bytes; + /* bytes that have been read */ + unsigned int rx_bytes; + unsigned int thld_bytes; }; /* * Can be expanded in the future if more interrupt status bits are utilized */ -#define ISR_MASK (BIT(IS_M_START_BUSY_SHIFT) | BIT(IS_M_TX_UNDERRUN_SHIFT)) +#define ISR_MASK (BIT(IS_M_START_BUSY_SHIFT) | BIT(IS_M_TX_UNDERRUN_SHIFT)\ + | BIT(IS_M_RX_THLD_SHIFT)) + +static void bcm_iproc_i2c_read_valid_bytes(struct bcm_iproc_i2c_dev *iproc_i2c) +{ + struct i2c_msg *msg = iproc_i2c->msg; + + /* Read valid data from RX FIFO */ + while (iproc_i2c->rx_bytes < msg->len) { + if (!((readl(iproc_i2c->base + + M_FIFO_CTRL_OFFSET) >> + M_FIFO_RX_CNT_SHIFT) & + M_FIFO_RX_CNT_MASK)) + break; + + msg->buf[iproc_i2c->rx_bytes] = + (readl(iproc_i2c->base + M_RX_OFFSET) >> + M_RX_DATA_SHIFT) & M_RX_DATA_MASK; + iproc_i2c->rx_bytes++; + } +} static irqreturn_t bcm_iproc_i2c_isr(int irq, void *data) { struct bcm_iproc_i2c_dev *iproc_i2c = data; u32 status = readl(iproc_i2c->base + IS_OFFSET); + u32 tmp; status &= ISR_MASK; @@ -136,8 +164,6 @@ static irqreturn_t bcm_iproc_i2c_isr(int irq, void *data) /* mark the last byte */ if (idx == msg->len - 1) { - u32 tmp; - val |= BIT(M_TX_WR_STATUS_SHIFT); /* @@ -156,6 +182,32 @@ static irqreturn_t bcm_iproc_i2c_isr(int irq, void *data) iproc_i2c->tx_bytes += tx_bytes; } + if (status & BIT(IS_M_RX_THLD_SHIFT)) { + struct i2c_msg *msg = iproc_i2c->msg; + u32 bytes_left; + + bcm_iproc_i2c_read_valid_bytes(iproc_i2c); + bytes_left = msg->len - iproc_i2c->rx_bytes; + if (bytes_left == 0) { + /* finished reading all data, disable rx thld event */ + tmp = readl(iproc_i2c->base + IE_OFFSET); + tmp &= ~BIT(IS_M_RX_THLD_SHIFT); + writel(tmp, iproc_i2c->base + IE_OFFSET); + } else if (bytes_left < iproc_i2c->thld_bytes) { + /* set bytes left as threshold */ + tmp = readl(iproc_i2c->base + M_FIFO_CTRL_OFFSET); + tmp &= ~(M_FIFO_RX_THLD_MASK << M_FIFO_RX_THLD_SHIFT); + tmp |= (bytes_left << M_FIFO_RX_THLD_SHIFT); + writel(tmp, iproc_i2c->base + M_FIFO_CTRL_OFFSET); + iproc_i2c->thld_bytes = bytes_left; + } + /* + * bytes_left >= iproc_i2c->thld_bytes, + * hence no need to change the THRESHOLD SET. + * It will remain as iproc_i2c->thld_bytes itself + */ + } + if (status & BIT(IS_M_START_BUSY_SHIFT)) { iproc_i2c->xfer_is_done = 1; complete(&iproc_i2c->done); @@ -253,7 +305,7 @@ static int bcm_iproc_i2c_xfer_single_msg(struct bcm_iproc_i2c_dev *iproc_i2c, { int ret, i; u8 addr; - u32 val; + u32 val, tmp, val_intr_en; unsigned int tx_bytes; unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT_MSEC); @@ -298,7 +350,7 @@ static int bcm_iproc_i2c_xfer_single_msg(struct bcm_iproc_i2c_dev *iproc_i2c, * transaction is done, i.e., the internal start_busy bit, transitions * from 1 to 0. */ - val = BIT(IE_M_START_BUSY_SHIFT); + val_intr_en = BIT(IE_M_START_BUSY_SHIFT); /* * If TX data size is larger than the TX FIFO, need to enable TX @@ -307,9 +359,7 @@ static int bcm_iproc_i2c_xfer_single_msg(struct bcm_iproc_i2c_dev *iproc_i2c, */ if (!(msg->flags & I2C_M_RD) && msg->len > iproc_i2c->tx_bytes) - val |= BIT(IE_M_TX_UNDERRUN_SHIFT); - - writel(val, iproc_i2c->base + IE_OFFSET); + val_intr_en |= BIT(IE_M_TX_UNDERRUN_SHIFT); /* * Now we can activate the transfer. For a read operation, specify the @@ -317,11 +367,27 @@ static int bcm_iproc_i2c_xfer_single_msg(struct bcm_iproc_i2c_dev *iproc_i2c, */ val = BIT(M_CMD_START_BUSY_SHIFT); if (msg->flags & I2C_M_RD) { + iproc_i2c->rx_bytes = 0; + if (msg->len > M_RX_FIFO_MAX_THLD_VALUE) + iproc_i2c->thld_bytes = M_RX_FIFO_THLD_VALUE; + else + iproc_i2c->thld_bytes = msg->len; + + /* set threshold value */ + tmp = readl(iproc_i2c->base + M_FIFO_CTRL_OFFSET); + tmp &= ~(M_FIFO_RX_THLD_MASK << M_FIFO_RX_THLD_SHIFT); + tmp |= iproc_i2c->thld_bytes << M_FIFO_RX_THLD_SHIFT; + writel(tmp, iproc_i2c->base + M_FIFO_CTRL_OFFSET); + + /* enable the RX threshold interrupt */ + val_intr_en |= BIT(IE_M_RX_THLD_SHIFT); + val |= (M_CMD_PROTOCOL_BLK_RD << M_CMD_PROTOCOL_SHIFT) | (msg->len << M_CMD_RD_CNT_SHIFT); } else { val |= (M_CMD_PROTOCOL_BLK_WR << M_CMD_PROTOCOL_SHIFT); } + writel(val_intr_en, iproc_i2c->base + IE_OFFSET); writel(val, iproc_i2c->base + M_CMD_OFFSET); time_left = wait_for_completion_timeout(&iproc_i2c->done, time_left); @@ -353,17 +419,6 @@ static int bcm_iproc_i2c_xfer_single_msg(struct bcm_iproc_i2c_dev *iproc_i2c, return ret; } - /* - * For a read operation, we now need to load the data from FIFO - * into the memory buffer - */ - if (msg->flags & I2C_M_RD) { - for (i = 0; i < msg->len; i++) { - msg->buf[i] = (readl(iproc_i2c->base + M_RX_OFFSET) >> - M_RX_DATA_SHIFT) & M_RX_DATA_MASK; - } - } - return 0; } @@ -395,9 +450,8 @@ static const struct i2c_algorithm bcm_iproc_algo = { .functionality = bcm_iproc_i2c_functionality, }; -static const struct i2c_adapter_quirks bcm_iproc_i2c_quirks = { - /* need to reserve one byte in the FIFO for the slave address */ - .max_read_len = M_TX_RX_FIFO_SIZE - 1, +static struct i2c_adapter_quirks bcm_iproc_i2c_quirks = { + .max_read_len = M_RX_MAX_READ_LEN, }; static int bcm_iproc_i2c_cfg_speed(struct bcm_iproc_i2c_dev *iproc_i2c) From patchwork Thu Feb 14 17:57:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ray Jui X-Patchwork-Id: 10813405 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E4D05922 for ; Thu, 14 Feb 2019 17:58:25 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D04292EED0 for ; Thu, 14 Feb 2019 17:58:25 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C3ED72EEE9; Thu, 14 Feb 2019 17:58:25 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id D90132EED0 for ; Thu, 14 Feb 2019 17:58:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=MZZgjuyoxBkGaEqDNYBcWXyoNydmVZ2xdJGXAynaZd0=; b=YCqVLQCIP8D1elw1Wb09iCgrjv gRBg+csfZT5yadTYNuaDLHQScnPKTLCQxogY87pHUMXhp2qgqhINlKxYwjdv10GOPCs7ANcr5+fEq CSIpF8IUuYSTL3XXXAFCCK/Hf0lztq9KadJCaLx8ImJMBfYs7ddy8+TvKQGt6jQp3hTlmtXYDTrPJ Umy07f9B/7VegimOM/98UBYG0Mun601noj+LQua/qz+35V13/uyYfCuw+UyHmXVx0RK0VlLIz9P2I izzoMHqUyP5JJhTr4+iPJdlVtf3CywvlKjHR4Jjl8m79SqqjHUK6bN6aw11lcx+Nsnvipw+Z0WwQO 946UU/kA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1guLHD-00008w-IL; Thu, 14 Feb 2019 17:58:23 +0000 Received: from mail-it1-x144.google.com ([2607:f8b0:4864:20::144]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1guLGf-0007rz-T0 for linux-arm-kernel@lists.infradead.org; Thu, 14 Feb 2019 17:57:56 +0000 Received: by mail-it1-x144.google.com with SMTP id l66so6389898itg.3 for ; Thu, 14 Feb 2019 09:57:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=3i4gUCnYFw3ZLY5kdJTtqJXFky8h7lyhLbYuAvzEmCA=; b=Ae4mWUHEi05pSRpGU3fhcUgaAzfaEoKO/l+a8qLzGEV29nYTXTRa/ITSPcftX1+I/J AFlX939TcrrK4rJy0iwKREENtXry2cvirsWwGeBWwNncjjzp8EMe9AZkISXhkDfMLbik N+/DqDHYFcOi6R5sS3fUE2UzCGgq+v42jYZcM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3i4gUCnYFw3ZLY5kdJTtqJXFky8h7lyhLbYuAvzEmCA=; b=LLe++LZ2cTqejncgkIYVfoOqKooBrqgMt2N7AhmAp2yja0KXFJ53dmXI7XAqfOgIMI B7p80xQlcvxDzvOvcp0DbknU4jBUeETmCZoSA9VWiqRbbHk3jMi60I4GY8ennAZs+CB+ DvM1qyw0rV0TQskQDPgidGE5J/QyJ+QwUYWcP82ovY+JdK0OmGdkL49VmcQ7oOtdd4EZ rgIN0ZBL8PQOTQxGZVfsv+DUKI3/OeHZsR57gIJ8qsVBI5O7HfoVc1P3/pdtIPQTeUsx gaIjzZe/LQCP4T0kNH1HfnQXlv4SP3loV/rzsr8JhA7oxVx9z7mOzqZG6BpoJo6YeSdT 0lpQ== X-Gm-Message-State: AHQUAuY2TDgx8ZAHry0bB4G7oeC2mVo9cY1JzP3hAcNT3LGIpy8kzU8E bMcfsdM+5cAkGS/Y5e/C5KHRxQ== X-Google-Smtp-Source: AHgI3IYRExub64yA+DM00e6FqFSUWZR1ROsKZyJFvmmv/PhmjygONmCCyKq5BFoTIAIn371BjFPFuQ== X-Received: by 2002:a24:8788:: with SMTP id f130mr31557ite.90.1550167069005; Thu, 14 Feb 2019 09:57:49 -0800 (PST) Received: from rj-aorus.ric.broadcom.com ([192.19.228.250]) by smtp.gmail.com with ESMTPSA id t64sm1534178itb.5.2019.02.14.09.57.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 14 Feb 2019 09:57:48 -0800 (PST) From: Ray Jui To: Wolfram Sang , Rob Herring , Mark Rutland Subject: [PATCH v5 2/8] i2c: iproc: Add slave mode support Date: Thu, 14 Feb 2019 09:57:19 -0800 Message-Id: <20190214175725.60462-3-ray.jui@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190214175725.60462-1-ray.jui@broadcom.com> References: <20190214175725.60462-1-ray.jui@broadcom.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190214_095750_350309_64E1530E X-CRM114-Status: GOOD ( 22.67 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Rayagonda Kokatanur , linux-kernel@vger.kernel.org, Shreesha Rajashekar , bcm-kernel-feedback-list@broadcom.com, linux-i2c@vger.kernel.org, Michael Cheng , Ray Jui , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Shreesha Rajashekar Add slave mode support to the iProc I2C driver. Signed-off-by: Rayagonda Kokatanur Signed-off-by: Michael Cheng Signed-off-by: Shreesha Rajashekar Signed-off-by: Ray Jui --- drivers/i2c/busses/Kconfig | 1 + drivers/i2c/busses/i2c-bcm-iproc.c | 314 ++++++++++++++++++++++++++++- 2 files changed, 309 insertions(+), 6 deletions(-) diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index f2c681971201..e0798b82b3bc 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -424,6 +424,7 @@ config I2C_BCM_IPROC tristate "Broadcom iProc I2C controller" depends on ARCH_BCM_IPROC || COMPILE_TEST default ARCH_BCM_IPROC + select I2C_SLAVE help If you say yes to this option, support will be included for the Broadcom iProc I2C controller. diff --git a/drivers/i2c/busses/i2c-bcm-iproc.c b/drivers/i2c/busses/i2c-bcm-iproc.c index eb7339a0280e..775b3d89a9c4 100644 --- a/drivers/i2c/busses/i2c-bcm-iproc.c +++ b/drivers/i2c/busses/i2c-bcm-iproc.c @@ -23,11 +23,30 @@ #define CFG_OFFSET 0x00 #define CFG_RESET_SHIFT 31 #define CFG_EN_SHIFT 30 +#define CFG_SLAVE_ADDR_0_SHIFT 28 #define CFG_M_RETRY_CNT_SHIFT 16 #define CFG_M_RETRY_CNT_MASK 0x0f #define TIM_CFG_OFFSET 0x04 #define TIM_CFG_MODE_400_SHIFT 31 +#define TIM_RAND_SLAVE_STRETCH_SHIFT 24 +#define TIM_RAND_SLAVE_STRETCH_MASK 0x7f +#define TIM_PERIODIC_SLAVE_STRETCH_SHIFT 16 +#define TIM_PERIODIC_SLAVE_STRETCH_MASK 0x7f + +#define S_CFG_SMBUS_ADDR_OFFSET 0x08 +#define S_CFG_EN_NIC_SMB_ADDR3_SHIFT 31 +#define S_CFG_NIC_SMB_ADDR3_SHIFT 24 +#define S_CFG_NIC_SMB_ADDR3_MASK 0x7f +#define S_CFG_EN_NIC_SMB_ADDR2_SHIFT 23 +#define S_CFG_NIC_SMB_ADDR2_SHIFT 16 +#define S_CFG_NIC_SMB_ADDR2_MASK 0x7f +#define S_CFG_EN_NIC_SMB_ADDR1_SHIFT 15 +#define S_CFG_NIC_SMB_ADDR1_SHIFT 8 +#define S_CFG_NIC_SMB_ADDR1_MASK 0x7f +#define S_CFG_EN_NIC_SMB_ADDR0_SHIFT 7 +#define S_CFG_NIC_SMB_ADDR0_SHIFT 0 +#define S_CFG_NIC_SMB_ADDR0_MASK 0x7f #define M_FIFO_CTRL_OFFSET 0x0c #define M_FIFO_RX_FLUSH_SHIFT 31 @@ -37,6 +56,14 @@ #define M_FIFO_RX_THLD_SHIFT 8 #define M_FIFO_RX_THLD_MASK 0x3f +#define S_FIFO_CTRL_OFFSET 0x10 +#define S_FIFO_RX_FLUSH_SHIFT 31 +#define S_FIFO_TX_FLUSH_SHIFT 30 +#define S_FIFO_RX_CNT_SHIFT 16 +#define S_FIFO_RX_CNT_MASK 0x7f +#define S_FIFO_RX_THLD_SHIFT 8 +#define S_FIFO_RX_THLD_MASK 0x3f + #define M_CMD_OFFSET 0x30 #define M_CMD_START_BUSY_SHIFT 31 #define M_CMD_STATUS_SHIFT 25 @@ -46,6 +73,8 @@ #define M_CMD_STATUS_NACK_ADDR 0x2 #define M_CMD_STATUS_NACK_DATA 0x3 #define M_CMD_STATUS_TIMEOUT 0x4 +#define M_CMD_STATUS_FIFO_UNDERRUN 0x5 +#define M_CMD_STATUS_RX_FIFO_FULL 0x6 #define M_CMD_PROTOCOL_SHIFT 9 #define M_CMD_PROTOCOL_MASK 0xf #define M_CMD_PROTOCOL_BLK_WR 0x7 @@ -54,17 +83,36 @@ #define M_CMD_RD_CNT_SHIFT 0 #define M_CMD_RD_CNT_MASK 0xff +#define S_CMD_OFFSET 0x34 +#define S_CMD_START_BUSY_SHIFT 31 +#define S_CMD_STATUS_SHIFT 23 +#define S_CMD_STATUS_MASK 0x07 +#define S_CMD_STATUS_SUCCESS 0x0 +#define S_CMD_STATUS_TIMEOUT 0x5 + #define IE_OFFSET 0x38 #define IE_M_RX_FIFO_FULL_SHIFT 31 #define IE_M_RX_THLD_SHIFT 30 #define IE_M_START_BUSY_SHIFT 28 #define IE_M_TX_UNDERRUN_SHIFT 27 +#define IE_S_RX_FIFO_FULL_SHIFT 26 +#define IE_S_RX_THLD_SHIFT 25 +#define IE_S_RX_EVENT_SHIFT 24 +#define IE_S_START_BUSY_SHIFT 23 +#define IE_S_TX_UNDERRUN_SHIFT 22 +#define IE_S_RD_EVENT_SHIFT 21 #define IS_OFFSET 0x3c #define IS_M_RX_FIFO_FULL_SHIFT 31 #define IS_M_RX_THLD_SHIFT 30 #define IS_M_START_BUSY_SHIFT 28 #define IS_M_TX_UNDERRUN_SHIFT 27 +#define IS_S_RX_FIFO_FULL_SHIFT 26 +#define IS_S_RX_THLD_SHIFT 25 +#define IS_S_RX_EVENT_SHIFT 24 +#define IS_S_START_BUSY_SHIFT 23 +#define IS_S_TX_UNDERRUN_SHIFT 22 +#define IS_S_RD_EVENT_SHIFT 21 #define M_TX_OFFSET 0x40 #define M_TX_WR_STATUS_SHIFT 31 @@ -78,6 +126,18 @@ #define M_RX_DATA_SHIFT 0 #define M_RX_DATA_MASK 0xff +#define S_TX_OFFSET 0x48 +#define S_TX_WR_STATUS_SHIFT 31 +#define S_TX_DATA_SHIFT 0 +#define S_TX_DATA_MASK 0xff + +#define S_RX_OFFSET 0x4c +#define S_RX_STATUS_SHIFT 30 +#define S_RX_STATUS_MASK 0x03 +#define S_RX_PEC_ERR_SHIFT 29 +#define S_RX_DATA_SHIFT 0 +#define S_RX_DATA_MASK 0xff + #define I2C_TIMEOUT_MSEC 50000 #define M_TX_RX_FIFO_SIZE 64 #define M_RX_FIFO_MAX_THLD_VALUE (M_TX_RX_FIFO_SIZE - 1) @@ -85,6 +145,30 @@ #define M_RX_MAX_READ_LEN 255 #define M_RX_FIFO_THLD_VALUE 50 +#define IE_M_ALL_INTERRUPT_SHIFT 27 +#define IE_M_ALL_INTERRUPT_MASK 0x1e + +#define SLAVE_READ_WRITE_BIT_MASK 0x1 +#define SLAVE_READ_WRITE_BIT_SHIFT 0x1 +#define SLAVE_MAX_SIZE_TRANSACTION 64 +#define SLAVE_CLOCK_STRETCH_TIME 25 + +#define IE_S_ALL_INTERRUPT_SHIFT 21 +#define IE_S_ALL_INTERRUPT_MASK 0x3f + +enum i2c_slave_read_status { + I2C_SLAVE_RX_FIFO_EMPTY = 0, + I2C_SLAVE_RX_START, + I2C_SLAVE_RX_DATA, + I2C_SLAVE_RX_END, +}; + +enum i2c_slave_xfer_dir { + I2C_SLAVE_DIR_READ = 0, + I2C_SLAVE_DIR_WRITE, + I2C_SLAVE_DIR_NONE, +}; + enum bus_speed_index { I2C_SPD_100K = 0, I2C_SPD_400K, @@ -104,6 +188,9 @@ struct bcm_iproc_i2c_dev { struct i2c_msg *msg; + struct i2c_client *slave; + enum i2c_slave_xfer_dir xfer_dir; + /* bytes that have been transferred */ unsigned int tx_bytes; /* bytes that have been read */ @@ -117,6 +204,156 @@ struct bcm_iproc_i2c_dev { #define ISR_MASK (BIT(IS_M_START_BUSY_SHIFT) | BIT(IS_M_TX_UNDERRUN_SHIFT)\ | BIT(IS_M_RX_THLD_SHIFT)) +#define ISR_MASK_SLAVE (BIT(IS_S_START_BUSY_SHIFT)\ + | BIT(IS_S_RX_EVENT_SHIFT) | BIT(IS_S_RD_EVENT_SHIFT)) + +static int bcm_iproc_i2c_reg_slave(struct i2c_client *slave); +static int bcm_iproc_i2c_unreg_slave(struct i2c_client *slave); +static void bcm_iproc_i2c_enable_disable(struct bcm_iproc_i2c_dev *iproc_i2c, + bool enable); + +static void bcm_iproc_i2c_slave_init( + struct bcm_iproc_i2c_dev *iproc_i2c, bool need_reset) +{ + u32 val; + + if (need_reset) { + /* put controller in reset */ + val = readl(iproc_i2c->base + CFG_OFFSET); + val |= BIT(CFG_RESET_SHIFT); + writel(val, iproc_i2c->base + CFG_OFFSET); + + /* wait 100 usec per spec */ + udelay(100); + + /* bring controller out of reset */ + val &= ~(BIT(CFG_RESET_SHIFT)); + writel(val, iproc_i2c->base + CFG_OFFSET); + } + + /* flush TX/RX FIFOs */ + val = (BIT(S_FIFO_RX_FLUSH_SHIFT) | BIT(S_FIFO_TX_FLUSH_SHIFT)); + writel(val, iproc_i2c->base + S_FIFO_CTRL_OFFSET); + + /* RANDOM SLAVE STRETCH time - 20ms*/ + val = readl(iproc_i2c->base + TIM_CFG_OFFSET); + val &= ~(TIM_RAND_SLAVE_STRETCH_MASK << TIM_RAND_SLAVE_STRETCH_SHIFT); + val |= (SLAVE_CLOCK_STRETCH_TIME << TIM_RAND_SLAVE_STRETCH_SHIFT); + writel(val, iproc_i2c->base + TIM_CFG_OFFSET); + + /* Configure the slave address */ + val = readl(iproc_i2c->base + S_CFG_SMBUS_ADDR_OFFSET); + val |= BIT(S_CFG_EN_NIC_SMB_ADDR3_SHIFT); + val &= ~(S_CFG_NIC_SMB_ADDR3_MASK << S_CFG_NIC_SMB_ADDR3_SHIFT); + val |= (iproc_i2c->slave->addr << S_CFG_NIC_SMB_ADDR3_SHIFT); + writel(val, iproc_i2c->base + S_CFG_SMBUS_ADDR_OFFSET); + + /* clear all pending slave interrupts */ + writel(ISR_MASK_SLAVE, iproc_i2c->base + IS_OFFSET); + + /* Enable interrupt register for any READ event */ + val = BIT(IE_S_RD_EVENT_SHIFT); + /* Enable interrupt register to indicate a valid byte in receive fifo */ + val |= BIT(IE_S_RX_EVENT_SHIFT); + /* Enable interrupt register for the Slave BUSY command */ + val |= BIT(IE_S_START_BUSY_SHIFT); + writel(val, iproc_i2c->base + IE_OFFSET); + + iproc_i2c->xfer_dir = I2C_SLAVE_DIR_NONE; +} + +static void bcm_iproc_i2c_check_slave_status( + struct bcm_iproc_i2c_dev *iproc_i2c) +{ + u32 val; + + val = readl(iproc_i2c->base + S_CMD_OFFSET); + val = (val >> S_CMD_STATUS_SHIFT) & S_CMD_STATUS_MASK; + + if (val == S_CMD_STATUS_TIMEOUT) { + dev_err(iproc_i2c->device, "slave random stretch time timeout\n"); + + /* re-initialize i2c for recovery */ + bcm_iproc_i2c_enable_disable(iproc_i2c, false); + bcm_iproc_i2c_slave_init(iproc_i2c, true); + bcm_iproc_i2c_enable_disable(iproc_i2c, true); + } +} + +static bool bcm_iproc_i2c_slave_isr(struct bcm_iproc_i2c_dev *iproc_i2c, + u32 status) +{ + u8 value; + u32 val; + u32 rd_status; + u32 tmp; + + /* Start of transaction. check address and populate the direction */ + if (iproc_i2c->xfer_dir == I2C_SLAVE_DIR_NONE) { + tmp = readl(iproc_i2c->base + S_RX_OFFSET); + rd_status = (tmp >> S_RX_STATUS_SHIFT) & S_RX_STATUS_MASK; + /* This condition checks whether the request is a new request */ + if (((rd_status == I2C_SLAVE_RX_START) && + (status & BIT(IS_S_RX_EVENT_SHIFT))) || + ((rd_status == I2C_SLAVE_RX_END) && + (status & BIT(IS_S_RD_EVENT_SHIFT)))) { + + /* Last bit is W/R bit. + * If 1 then its a read request(by master). + */ + iproc_i2c->xfer_dir = tmp & SLAVE_READ_WRITE_BIT_MASK; + if (iproc_i2c->xfer_dir == I2C_SLAVE_DIR_WRITE) + i2c_slave_event(iproc_i2c->slave, + I2C_SLAVE_READ_REQUESTED, &value); + else + i2c_slave_event(iproc_i2c->slave, + I2C_SLAVE_WRITE_REQUESTED, &value); + } + } + + /* read request from master */ + if ((status & BIT(IS_S_RD_EVENT_SHIFT)) && + (iproc_i2c->xfer_dir == I2C_SLAVE_DIR_WRITE)) { + i2c_slave_event(iproc_i2c->slave, + I2C_SLAVE_READ_PROCESSED, &value); + writel(value, iproc_i2c->base + S_TX_OFFSET); + + val = BIT(S_CMD_START_BUSY_SHIFT); + writel(val, iproc_i2c->base + S_CMD_OFFSET); + } + + /* write request from master */ + if ((status & BIT(IS_S_RX_EVENT_SHIFT)) && + (iproc_i2c->xfer_dir == I2C_SLAVE_DIR_READ)) { + val = readl(iproc_i2c->base + S_RX_OFFSET); + /* Its a write request by Master to Slave. + * We read data present in receive FIFO + */ + value = (u8)((val >> S_RX_DATA_SHIFT) & S_RX_DATA_MASK); + i2c_slave_event(iproc_i2c->slave, + I2C_SLAVE_WRITE_RECEIVED, &value); + + /* check the status for the last byte of the transaction */ + rd_status = (val >> S_RX_STATUS_SHIFT) & S_RX_STATUS_MASK; + if (rd_status == I2C_SLAVE_RX_END) + iproc_i2c->xfer_dir = I2C_SLAVE_DIR_NONE; + + dev_dbg(iproc_i2c->device, "\nread value = 0x%x\n", value); + } + + /* Stop */ + if (status & BIT(IS_S_START_BUSY_SHIFT)) { + i2c_slave_event(iproc_i2c->slave, I2C_SLAVE_STOP, &value); + iproc_i2c->xfer_dir = I2C_SLAVE_DIR_NONE; + } + + /* clear interrupt status */ + writel(status, iproc_i2c->base + IS_OFFSET); + + bcm_iproc_i2c_check_slave_status(iproc_i2c); + return true; +} + static void bcm_iproc_i2c_read_valid_bytes(struct bcm_iproc_i2c_dev *iproc_i2c) { struct i2c_msg *msg = iproc_i2c->msg; @@ -142,6 +379,18 @@ static irqreturn_t bcm_iproc_i2c_isr(int irq, void *data) u32 status = readl(iproc_i2c->base + IS_OFFSET); u32 tmp; + + bool ret; + u32 sl_status = status & ISR_MASK_SLAVE; + + if (sl_status) { + ret = bcm_iproc_i2c_slave_isr(iproc_i2c, sl_status); + if (ret) + return IRQ_HANDLED; + else + return IRQ_NONE; + } + status &= ISR_MASK; if (!status) @@ -224,22 +473,25 @@ static int bcm_iproc_i2c_init(struct bcm_iproc_i2c_dev *iproc_i2c) /* put controller in reset */ val = readl(iproc_i2c->base + CFG_OFFSET); - val |= 1 << CFG_RESET_SHIFT; - val &= ~(1 << CFG_EN_SHIFT); + val |= BIT(CFG_RESET_SHIFT); + val &= ~(BIT(CFG_EN_SHIFT)); writel(val, iproc_i2c->base + CFG_OFFSET); /* wait 100 usec per spec */ udelay(100); /* bring controller out of reset */ - val &= ~(1 << CFG_RESET_SHIFT); + val &= ~(BIT(CFG_RESET_SHIFT)); writel(val, iproc_i2c->base + CFG_OFFSET); /* flush TX/RX FIFOs and set RX FIFO threshold to zero */ - val = (1 << M_FIFO_RX_FLUSH_SHIFT) | (1 << M_FIFO_TX_FLUSH_SHIFT); + val = (BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT)); writel(val, iproc_i2c->base + M_FIFO_CTRL_OFFSET); /* disable all interrupts */ - writel(0, iproc_i2c->base + IE_OFFSET); + val = readl(iproc_i2c->base + IE_OFFSET); + val &= ~(IE_M_ALL_INTERRUPT_MASK << + IE_M_ALL_INTERRUPT_SHIFT); + writel(val, iproc_i2c->base + IE_OFFSET); /* clear all pending interrupts */ writel(0xffffffff, iproc_i2c->base + IS_OFFSET); @@ -288,6 +540,14 @@ static int bcm_iproc_i2c_check_status(struct bcm_iproc_i2c_dev *iproc_i2c, dev_dbg(iproc_i2c->device, "bus timeout\n"); return -ETIMEDOUT; + case M_CMD_STATUS_FIFO_UNDERRUN: + dev_dbg(iproc_i2c->device, "FIFO under-run\n"); + return -ENXIO; + + case M_CMD_STATUS_RX_FIFO_FULL: + dev_dbg(iproc_i2c->device, "Master Rx FIFO full > 10ms\n"); + return -ETIMEDOUT; + default: dev_dbg(iproc_i2c->device, "unknown error code=%d\n", val); @@ -442,12 +702,14 @@ static int bcm_iproc_i2c_xfer(struct i2c_adapter *adapter, static uint32_t bcm_iproc_i2c_functionality(struct i2c_adapter *adap) { - return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SLAVE; } static const struct i2c_algorithm bcm_iproc_algo = { .master_xfer = bcm_iproc_i2c_xfer, .functionality = bcm_iproc_i2c_functionality, + .reg_slave = bcm_iproc_i2c_reg_slave, + .unreg_slave = bcm_iproc_i2c_unreg_slave, }; static struct i2c_adapter_quirks bcm_iproc_i2c_quirks = { @@ -612,6 +874,46 @@ static const struct dev_pm_ops bcm_iproc_i2c_pm_ops = { #define BCM_IPROC_I2C_PM_OPS NULL #endif /* CONFIG_PM_SLEEP */ + +static int bcm_iproc_i2c_reg_slave(struct i2c_client *slave) +{ + struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(slave->adapter); + + if (iproc_i2c->slave) + return -EBUSY; + + if (slave->flags & I2C_CLIENT_TEN) + return -EAFNOSUPPORT; + + iproc_i2c->slave = slave; + bcm_iproc_i2c_slave_init(iproc_i2c, false); + return 0; +} + +static int bcm_iproc_i2c_unreg_slave(struct i2c_client *slave) +{ + u32 tmp; + struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(slave->adapter); + + if (!iproc_i2c->slave) + return -EINVAL; + + iproc_i2c->slave = NULL; + + /* disable all slave interrupts */ + tmp = readl(iproc_i2c->base + IE_OFFSET); + tmp &= ~(IE_S_ALL_INTERRUPT_MASK << + IE_S_ALL_INTERRUPT_SHIFT); + writel(tmp, iproc_i2c->base + IE_OFFSET); + + /* Erase the slave address programmed */ + tmp = readl(iproc_i2c->base + S_CFG_SMBUS_ADDR_OFFSET); + tmp &= ~BIT(S_CFG_EN_NIC_SMB_ADDR3_SHIFT); + writel(tmp, iproc_i2c->base + S_CFG_SMBUS_ADDR_OFFSET); + + return 0; +} + static const struct of_device_id bcm_iproc_i2c_of_match[] = { { .compatible = "brcm,iproc-i2c" }, { /* sentinel */ } From patchwork Thu Feb 14 17:57:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ray Jui X-Patchwork-Id: 10813401 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2FF3E1399 for ; Thu, 14 Feb 2019 17:58:15 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1E0C72EEA8 for ; Thu, 14 Feb 2019 17:58:15 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 121392EED0; Thu, 14 Feb 2019 17:58:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id B858F2EEA8 for ; Thu, 14 Feb 2019 17:58:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=fFX6KZcb4B1++TGo45galqcJpMz8bn8ggjBpV8ZqXKI=; b=tDnNZOP2nmzR7SGemw4T5Zfdcg QzLmW752jbdRjkVblb/SjANIdIka7g9mgzGz/lz/C5+l9VhRMkTLTyruTL9aWzu1rr4Xg/GYIonNR vse5nWM+9S06GzlIdBPatWPq/k4Bk8Zg6Vu0dHdk7JzkMqdtETeRtLdXvkIf9zuUF4W5ez01jORY6 A1W+pdF3rLXoxfjk/FHe6vOfJI2v5FsJpgU+91gySRcyaT0Qh2Cm8bj6ftwiUO0lVy1c1CYBgJKeX UhFVydkEeSuQ0ZCXe6b3H5oBJKC4yO8YKEImml07HooYQ0AxXEhvvVQveo5ofj8P0VtEwTGv5DDK7 Wgepklfw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1guLH3-0008OO-Qc; Thu, 14 Feb 2019 17:58:13 +0000 Received: from mail-it1-x143.google.com ([2607:f8b0:4864:20::143]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1guLGj-0007xD-HQ for linux-arm-kernel@lists.infradead.org; Thu, 14 Feb 2019 17:57:56 +0000 Received: by mail-it1-x143.google.com with SMTP id z7so17265790iti.0 for ; Thu, 14 Feb 2019 09:57:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=qd5kI+SJawXscvy5gQFO6CdGhw4ESxIavmw5z4kZ0JE=; b=IhlLw0Jf9Ut/A90TYhXhoRD+hkewG/boZsw/12RupQo+z5Z0IcUcQ6SvcCS5o0M4fU 3a/A3P61va0qcZohzWHF/mb6bHmZj71/KwYLFpsATu/igCw410WnKmbBImRzWOAuUzyP wkWOeMfjI0nf2SO5efto6SnXCdzcpoBOE5EJ4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=qd5kI+SJawXscvy5gQFO6CdGhw4ESxIavmw5z4kZ0JE=; b=mo2dvvXY5Aj3Q2lnpX8XkDX09dnZZ5J6OEvgrKq4VziB1kjAMauD/ypP/jVfPOUz2W KCdZwtorI+go3Pf0IHCEJBL0kq1OcvofSQ3DhcHxLFNPGEKvHvkopnIegXUq6fxb8PBk LLkVAJeWZaz6MeY1S0pZVeBYhGQ7O5X8VLliu1dC3NG11wR348u3ihJtMoi07/goEoJq 0OyGHTp85gYz4/scPzK1facFRPhiWSCyPaEX0e6J4kssyJxVZipW0hpaMSxwspy7Icrq 81IcrYQOchHSH60ZYZnbJUpWLF1rsbr9BGe3VP5PLxe5lT/7IV4ezV9JAjtg5fRQIX6t tWxQ== X-Gm-Message-State: AHQUAuY5R3T9Fu4U85G5q07lVt0nKtN5CrSkhABVuyajQ2FPLccYeFKH TkUaQBbF/fjjugXL49YqqkuehA== X-Google-Smtp-Source: AHgI3IYC8QBY5QAdgIeyfE2U1qAUURc9s9naP+Q4N8K1ULjptwjVPqo1znC2pqepovVwCFVkNkiplw== X-Received: by 2002:a02:9c16:: with SMTP id q22mr2884177jak.49.1550167072510; Thu, 14 Feb 2019 09:57:52 -0800 (PST) Received: from rj-aorus.ric.broadcom.com ([192.19.228.250]) by smtp.gmail.com with ESMTPSA id t64sm1534178itb.5.2019.02.14.09.57.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 14 Feb 2019 09:57:51 -0800 (PST) From: Ray Jui To: Wolfram Sang , Rob Herring , Mark Rutland Subject: [PATCH v5 3/8] dt-bindings: i2c: iproc: make 'interrupts' optional Date: Thu, 14 Feb 2019 09:57:20 -0800 Message-Id: <20190214175725.60462-4-ray.jui@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190214175725.60462-1-ray.jui@broadcom.com> References: <20190214175725.60462-1-ray.jui@broadcom.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190214_095754_305285_F830E149 X-CRM114-Status: GOOD ( 11.51 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Rayagonda Kokatanur , linux-kernel@vger.kernel.org, bcm-kernel-feedback-list@broadcom.com, linux-i2c@vger.kernel.org, Ray Jui , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Update the binding document to make the 'interrupts' property optional. For certain revisions of the I2C controller (e.g., iProc NIC I2C), I2C interrupt is unwired to the interrupt controller. In such case, this 'interrupts' property should be left unspecified, and driver will fall back to polling mode Signed-off-by: Ray Jui Signed-off-by: Rayagonda Kokatanur Reviewed-by: Rob Herring --- .../devicetree/bindings/i2c/brcm,iproc-i2c.txt | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/i2c/brcm,iproc-i2c.txt b/Documentation/devicetree/bindings/i2c/brcm,iproc-i2c.txt index 81f982ccca31..7a32bf81bfa9 100644 --- a/Documentation/devicetree/bindings/i2c/brcm,iproc-i2c.txt +++ b/Documentation/devicetree/bindings/i2c/brcm,iproc-i2c.txt @@ -9,9 +9,6 @@ Required properties: Define the base and range of the I/O address space that contain the iProc I2C controller registers -- interrupts: - Should contain the I2C interrupt - - clock-frequency: This is the I2C bus clock. Need to be either 100000 or 400000 @@ -21,6 +18,14 @@ Required properties: - #size-cells: Always 0 +Optional properties: + +- interrupts: + Should contain the I2C interrupt. For certain revisions of the I2C + controller, I2C interrupt is unwired to the interrupt controller. In such + case, this property should be left unspecified, and driver will fall back + to polling mode + Example: i2c0: i2c@18008000 { compatible = "brcm,iproc-i2c"; From patchwork Thu Feb 14 17:57:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ray Jui X-Patchwork-Id: 10813407 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 76036922 for ; Thu, 14 Feb 2019 17:58:44 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 626D82EEE5 for ; Thu, 14 Feb 2019 17:58:44 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5362F2EEF5; Thu, 14 Feb 2019 17:58:44 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 887AC2EEE5 for ; Thu, 14 Feb 2019 17:58:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=XKIkqO9ZNxbvzoSyuN6s6DKIfZyIvCzkj+uVG3sUeog=; b=c+lDmNe+cDFVzVPa4/zzKvoKIo Bgv8/aoTJiI8r30himW0aaSLDw+bUpSXjOHL3xkfP60VodLriX2SwPQewaNge0vPdIv2ZfUex0dpD qO50yDt/83kC8YUnbSe6euKpcGphT9VL0Lg35+ecp8ziA0ppleW43EUxJpIzK29DnqAzmhGYc/0Ws FLKa+YKQywdM1KqXsYZR4JfOwBbhg2aswZhVoMrfmim9qNfXvkkpyzb5O5NiH7slFr4v1tN+FJAR4 nht+advsuTkQniFuQB/OzwPQAgbfwlXYbtdk+AsmPtQ4AXvGTrNjDgw8v6G/kHUtiUritR9WM8TZa 8+oZs29w==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1guLHP-0000NA-NM; Thu, 14 Feb 2019 17:58:35 +0000 Received: from mail-it1-x144.google.com ([2607:f8b0:4864:20::144]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1guLGm-00082M-Eu for linux-arm-kernel@lists.infradead.org; Thu, 14 Feb 2019 17:58:02 +0000 Received: by mail-it1-x144.google.com with SMTP id l131so16404657ita.2 for ; Thu, 14 Feb 2019 09:57:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=l2ed/3/mPo7eGVi+/XTD6G8oylS839DTYEu+KI40Uu8=; b=bSeKNmtT1ezmnbjRJYnjiazgJl/jHn+7ntmhS09t14/jiP113zwOjMr/GkRwQFnukX SLSVPXrjTOC44hwqC/T+yLe5RXW1aC5adBwzvplw6aRwysBTFxO2xbhUoaQxmaER/TDp PqDGrgrD9I2HKbmcj6fcmBJRCV7Jni3NiZ8k0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=l2ed/3/mPo7eGVi+/XTD6G8oylS839DTYEu+KI40Uu8=; b=A8gHT9XGPVEAtWApMe4Hhm74cAgj4pGh8HGEw9LF4EKfXjA04Y/nyxfeOpbacUKxWk pf97xoGUZYcJZNy09t4Euczqq9HfZhIEayvtAR9HBfDSv4h/TnfARk35HRFc2S0ppsm1 GH45EOZCboAKLITOPpwqAbh11/MBWMVZvg4zCUscEGB6pa8IXbCwbEIi8T6BhtSHK5aR 3BpFR8/S6vSkytHV2IR+1zqR4/rhkZSav3ZXUgSwmOn1a/Io4OApgJQthkXH+PChPy4u T6S0vAFpJIKmx4CocCoIns79SnjMxi71Gsom1hbwwHFJUE1YOWQho+KTk2r2JeyY9SgG 1C3g== X-Gm-Message-State: AHQUAuZv57IAzavDtjLAx07WIIqi/3ChmiqO2rs1RsUinkQJb2jKD6gf 6v3dL/IDftVp+MM9w8QJX1OwJg== X-Google-Smtp-Source: AHgI3IZi5uUesOtmmJ6RpIbqqkfbSoKIfBS/z/jOdZXcoF9Nmw222bEnDod/XKiyh11HyDu9YcyjOg== X-Received: by 2002:a24:9f87:: with SMTP id c129mr2753291ite.114.1550167075717; Thu, 14 Feb 2019 09:57:55 -0800 (PST) Received: from rj-aorus.ric.broadcom.com ([192.19.228.250]) by smtp.gmail.com with ESMTPSA id t64sm1534178itb.5.2019.02.14.09.57.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 14 Feb 2019 09:57:55 -0800 (PST) From: Ray Jui To: Wolfram Sang , Rob Herring , Mark Rutland Subject: [PATCH v5 4/8] i2c: iproc: add polling support Date: Thu, 14 Feb 2019 09:57:21 -0800 Message-Id: <20190214175725.60462-5-ray.jui@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190214175725.60462-1-ray.jui@broadcom.com> References: <20190214175725.60462-1-ray.jui@broadcom.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190214_095756_556059_1EFC24E6 X-CRM114-Status: GOOD ( 26.67 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Rayagonda Kokatanur , linux-kernel@vger.kernel.org, bcm-kernel-feedback-list@broadcom.com, linux-i2c@vger.kernel.org, Ray Jui , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Rayagonda Kokatanur Add polling support to the iProc I2C driver. Polling mode is activated when the driver fails to obtain an interrupt ID from device tree Signed-off-by: Rayagonda Kokatanur Signed-off-by: Ray Jui --- drivers/i2c/busses/i2c-bcm-iproc.c | 298 ++++++++++++++++++----------- 1 file changed, 181 insertions(+), 117 deletions(-) diff --git a/drivers/i2c/busses/i2c-bcm-iproc.c b/drivers/i2c/busses/i2c-bcm-iproc.c index 775b3d89a9c4..073e5a8888ad 100644 --- a/drivers/i2c/busses/i2c-bcm-iproc.c +++ b/drivers/i2c/busses/i2c-bcm-iproc.c @@ -373,95 +373,115 @@ static void bcm_iproc_i2c_read_valid_bytes(struct bcm_iproc_i2c_dev *iproc_i2c) } } -static irqreturn_t bcm_iproc_i2c_isr(int irq, void *data) +static void bcm_iproc_i2c_send(struct bcm_iproc_i2c_dev *iproc_i2c) { - struct bcm_iproc_i2c_dev *iproc_i2c = data; - u32 status = readl(iproc_i2c->base + IS_OFFSET); - u32 tmp; - - - bool ret; - u32 sl_status = status & ISR_MASK_SLAVE; - - if (sl_status) { - ret = bcm_iproc_i2c_slave_isr(iproc_i2c, sl_status); - if (ret) - return IRQ_HANDLED; - else - return IRQ_NONE; - } + struct i2c_msg *msg = iproc_i2c->msg; + unsigned int tx_bytes = msg->len - iproc_i2c->tx_bytes; + unsigned int i; + u32 val; - status &= ISR_MASK; + /* can only fill up to the FIFO size */ + tx_bytes = min_t(unsigned int, tx_bytes, M_TX_RX_FIFO_SIZE); + for (i = 0; i < tx_bytes; i++) { + /* start from where we left over */ + unsigned int idx = iproc_i2c->tx_bytes + i; - if (!status) - return IRQ_NONE; + val = msg->buf[idx]; - /* TX FIFO is empty and we have more data to send */ - if (status & BIT(IS_M_TX_UNDERRUN_SHIFT)) { - struct i2c_msg *msg = iproc_i2c->msg; - unsigned int tx_bytes = msg->len - iproc_i2c->tx_bytes; - unsigned int i; - u32 val; - - /* can only fill up to the FIFO size */ - tx_bytes = min_t(unsigned int, tx_bytes, M_TX_RX_FIFO_SIZE); - for (i = 0; i < tx_bytes; i++) { - /* start from where we left over */ - unsigned int idx = iproc_i2c->tx_bytes + i; + /* mark the last byte */ + if (idx == msg->len - 1) { + val |= BIT(M_TX_WR_STATUS_SHIFT); - val = msg->buf[idx]; - - /* mark the last byte */ - if (idx == msg->len - 1) { - val |= BIT(M_TX_WR_STATUS_SHIFT); + if (iproc_i2c->irq) { + u32 tmp; /* - * Since this is the last byte, we should - * now disable TX FIFO underrun interrupt + * Since this is the last byte, we should now + * disable TX FIFO underrun interrupt */ tmp = readl(iproc_i2c->base + IE_OFFSET); tmp &= ~BIT(IE_M_TX_UNDERRUN_SHIFT); writel(tmp, iproc_i2c->base + IE_OFFSET); } - - /* load data into TX FIFO */ - writel(val, iproc_i2c->base + M_TX_OFFSET); } - /* update number of transferred bytes */ - iproc_i2c->tx_bytes += tx_bytes; + + /* load data into TX FIFO */ + writel(val, iproc_i2c->base + M_TX_OFFSET); } - if (status & BIT(IS_M_RX_THLD_SHIFT)) { - struct i2c_msg *msg = iproc_i2c->msg; - u32 bytes_left; + /* update number of transferred bytes */ + iproc_i2c->tx_bytes += tx_bytes; +} - bcm_iproc_i2c_read_valid_bytes(iproc_i2c); - bytes_left = msg->len - iproc_i2c->rx_bytes; - if (bytes_left == 0) { +static void bcm_iproc_i2c_read(struct bcm_iproc_i2c_dev *iproc_i2c) +{ + struct i2c_msg *msg = iproc_i2c->msg; + u32 bytes_left, val; + + bcm_iproc_i2c_read_valid_bytes(iproc_i2c); + bytes_left = msg->len - iproc_i2c->rx_bytes; + if (bytes_left == 0) { + if (iproc_i2c->irq) { /* finished reading all data, disable rx thld event */ - tmp = readl(iproc_i2c->base + IE_OFFSET); - tmp &= ~BIT(IS_M_RX_THLD_SHIFT); - writel(tmp, iproc_i2c->base + IE_OFFSET); - } else if (bytes_left < iproc_i2c->thld_bytes) { - /* set bytes left as threshold */ - tmp = readl(iproc_i2c->base + M_FIFO_CTRL_OFFSET); - tmp &= ~(M_FIFO_RX_THLD_MASK << M_FIFO_RX_THLD_SHIFT); - tmp |= (bytes_left << M_FIFO_RX_THLD_SHIFT); - writel(tmp, iproc_i2c->base + M_FIFO_CTRL_OFFSET); - iproc_i2c->thld_bytes = bytes_left; + val = readl(iproc_i2c->base + IE_OFFSET); + val &= ~BIT(IS_M_RX_THLD_SHIFT); + writel(val, iproc_i2c->base + IE_OFFSET); } - /* - * bytes_left >= iproc_i2c->thld_bytes, - * hence no need to change the THRESHOLD SET. - * It will remain as iproc_i2c->thld_bytes itself - */ + } else if (bytes_left < iproc_i2c->thld_bytes) { + /* set bytes left as threshold */ + val = readl(iproc_i2c->base + M_FIFO_CTRL_OFFSET); + val &= ~(M_FIFO_RX_THLD_MASK << M_FIFO_RX_THLD_SHIFT); + val |= (bytes_left << M_FIFO_RX_THLD_SHIFT); + writel(val, iproc_i2c->base + M_FIFO_CTRL_OFFSET); + iproc_i2c->thld_bytes = bytes_left; } + /* + * bytes_left >= iproc_i2c->thld_bytes, + * hence no need to change the THRESHOLD SET. + * It will remain as iproc_i2c->thld_bytes itself + */ +} +static void bcm_iproc_i2c_process_m_event(struct bcm_iproc_i2c_dev *iproc_i2c, + u32 status) +{ + /* TX FIFO is empty and we have more data to send */ + if (status & BIT(IS_M_TX_UNDERRUN_SHIFT)) + bcm_iproc_i2c_send(iproc_i2c); + + /* RX FIFO threshold is reached and data needs to be read out */ + if (status & BIT(IS_M_RX_THLD_SHIFT)) + bcm_iproc_i2c_read(iproc_i2c); + + /* transfer is done */ if (status & BIT(IS_M_START_BUSY_SHIFT)) { iproc_i2c->xfer_is_done = 1; - complete(&iproc_i2c->done); + if (iproc_i2c->irq) + complete(&iproc_i2c->done); + } +} + +static irqreturn_t bcm_iproc_i2c_isr(int irq, void *data) +{ + struct bcm_iproc_i2c_dev *iproc_i2c = data; + u32 status = readl(iproc_i2c->base + IS_OFFSET); + bool ret; + u32 sl_status = status & ISR_MASK_SLAVE; + + if (sl_status) { + ret = bcm_iproc_i2c_slave_isr(iproc_i2c, sl_status); + if (ret) + return IRQ_HANDLED; + else + return IRQ_NONE; } + status &= ISR_MASK; + if (!status) + return IRQ_NONE; + + /* process all master based events */ + bcm_iproc_i2c_process_m_event(iproc_i2c, status); writel(status, iproc_i2c->base + IS_OFFSET); return IRQ_HANDLED; @@ -560,14 +580,71 @@ static int bcm_iproc_i2c_check_status(struct bcm_iproc_i2c_dev *iproc_i2c, } } +static int bcm_iproc_i2c_xfer_wait(struct bcm_iproc_i2c_dev *iproc_i2c, + struct i2c_msg *msg, + u32 cmd) +{ + unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT_MSEC); + u32 val, status; + int ret; + + writel(cmd, iproc_i2c->base + M_CMD_OFFSET); + + if (iproc_i2c->irq) { + time_left = wait_for_completion_timeout(&iproc_i2c->done, + time_left); + /* disable all interrupts */ + writel(0, iproc_i2c->base + IE_OFFSET); + /* read it back to flush the write */ + readl(iproc_i2c->base + IE_OFFSET); + /* make sure the interrupt handler isn't running */ + synchronize_irq(iproc_i2c->irq); + + } else { /* polling mode */ + unsigned long timeout = jiffies + time_left; + + do { + status = readl(iproc_i2c->base + IS_OFFSET) & ISR_MASK; + bcm_iproc_i2c_process_m_event(iproc_i2c, status); + writel(status, iproc_i2c->base + IS_OFFSET); + + if (time_after(jiffies, timeout)) { + time_left = 0; + break; + } + + cpu_relax(); + cond_resched(); + } while (!iproc_i2c->xfer_is_done); + } + + if (!time_left && !iproc_i2c->xfer_is_done) { + dev_err(iproc_i2c->device, "transaction timed out\n"); + + /* flush both TX/RX FIFOs */ + val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT); + writel(val, iproc_i2c->base + M_FIFO_CTRL_OFFSET); + return -ETIMEDOUT; + } + + ret = bcm_iproc_i2c_check_status(iproc_i2c, msg); + if (ret) { + /* flush both TX/RX FIFOs */ + val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT); + writel(val, iproc_i2c->base + M_FIFO_CTRL_OFFSET); + return ret; + } + + return 0; +} + static int bcm_iproc_i2c_xfer_single_msg(struct bcm_iproc_i2c_dev *iproc_i2c, struct i2c_msg *msg) { - int ret, i; + int i; u8 addr; u32 val, tmp, val_intr_en; unsigned int tx_bytes; - unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT_MSEC); /* check if bus is busy */ if (!!(readl(iproc_i2c->base + M_CMD_OFFSET) & @@ -602,7 +679,9 @@ static int bcm_iproc_i2c_xfer_single_msg(struct bcm_iproc_i2c_dev *iproc_i2c, } /* mark as incomplete before starting the transaction */ - reinit_completion(&iproc_i2c->done); + if (iproc_i2c->irq) + reinit_completion(&iproc_i2c->done); + iproc_i2c->xfer_is_done = 0; /* @@ -647,39 +726,11 @@ static int bcm_iproc_i2c_xfer_single_msg(struct bcm_iproc_i2c_dev *iproc_i2c, } else { val |= (M_CMD_PROTOCOL_BLK_WR << M_CMD_PROTOCOL_SHIFT); } - writel(val_intr_en, iproc_i2c->base + IE_OFFSET); - writel(val, iproc_i2c->base + M_CMD_OFFSET); - time_left = wait_for_completion_timeout(&iproc_i2c->done, time_left); + if (iproc_i2c->irq) + writel(val_intr_en, iproc_i2c->base + IE_OFFSET); - /* disable all interrupts */ - writel(0, iproc_i2c->base + IE_OFFSET); - /* read it back to flush the write */ - readl(iproc_i2c->base + IE_OFFSET); - - /* make sure the interrupt handler isn't running */ - synchronize_irq(iproc_i2c->irq); - - if (!time_left && !iproc_i2c->xfer_is_done) { - dev_err(iproc_i2c->device, "transaction timed out\n"); - - /* flush FIFOs */ - val = (1 << M_FIFO_RX_FLUSH_SHIFT) | - (1 << M_FIFO_TX_FLUSH_SHIFT); - writel(val, iproc_i2c->base + M_FIFO_CTRL_OFFSET); - return -ETIMEDOUT; - } - - ret = bcm_iproc_i2c_check_status(iproc_i2c, msg); - if (ret) { - /* flush both TX/RX FIFOs */ - val = (1 << M_FIFO_RX_FLUSH_SHIFT) | - (1 << M_FIFO_TX_FLUSH_SHIFT); - writel(val, iproc_i2c->base + M_FIFO_CTRL_OFFSET); - return ret; - } - - return 0; + return bcm_iproc_i2c_xfer_wait(iproc_i2c, msg, val); } static int bcm_iproc_i2c_xfer(struct i2c_adapter *adapter, @@ -781,17 +832,20 @@ static int bcm_iproc_i2c_probe(struct platform_device *pdev) return ret; irq = platform_get_irq(pdev, 0); - if (irq <= 0) { - dev_err(iproc_i2c->device, "no irq resource\n"); - return irq; - } - iproc_i2c->irq = irq; + if (irq > 0) { + ret = devm_request_irq(iproc_i2c->device, irq, + bcm_iproc_i2c_isr, 0, pdev->name, + iproc_i2c); + if (ret < 0) { + dev_err(iproc_i2c->device, + "unable to request irq %i\n", irq); + return ret; + } - ret = devm_request_irq(iproc_i2c->device, irq, bcm_iproc_i2c_isr, 0, - pdev->name, iproc_i2c); - if (ret < 0) { - dev_err(iproc_i2c->device, "unable to request irq %i\n", irq); - return ret; + iproc_i2c->irq = irq; + } else { + dev_warn(iproc_i2c->device, + "no irq resource, falling back to poll mode\n"); } bcm_iproc_i2c_enable_disable(iproc_i2c, true); @@ -811,10 +865,15 @@ static int bcm_iproc_i2c_remove(struct platform_device *pdev) { struct bcm_iproc_i2c_dev *iproc_i2c = platform_get_drvdata(pdev); - /* make sure there's no pending interrupt when we remove the adapter */ - writel(0, iproc_i2c->base + IE_OFFSET); - readl(iproc_i2c->base + IE_OFFSET); - synchronize_irq(iproc_i2c->irq); + if (iproc_i2c->irq) { + /* + * Make sure there's no pending interrupt when we remove the + * adapter + */ + writel(0, iproc_i2c->base + IE_OFFSET); + readl(iproc_i2c->base + IE_OFFSET); + synchronize_irq(iproc_i2c->irq); + } i2c_del_adapter(&iproc_i2c->adapter); bcm_iproc_i2c_enable_disable(iproc_i2c, false); @@ -828,10 +887,15 @@ static int bcm_iproc_i2c_suspend(struct device *dev) { struct bcm_iproc_i2c_dev *iproc_i2c = dev_get_drvdata(dev); - /* make sure there's no pending interrupt when we go into suspend */ - writel(0, iproc_i2c->base + IE_OFFSET); - readl(iproc_i2c->base + IE_OFFSET); - synchronize_irq(iproc_i2c->irq); + if (iproc_i2c->irq) { + /* + * Make sure there's no pending interrupt when we go into + * suspend + */ + writel(0, iproc_i2c->base + IE_OFFSET); + readl(iproc_i2c->base + IE_OFFSET); + synchronize_irq(iproc_i2c->irq); + } /* now disable the controller */ bcm_iproc_i2c_enable_disable(iproc_i2c, false); From patchwork Thu Feb 14 17:57:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ray Jui X-Patchwork-Id: 10813409 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8390D922 for ; Thu, 14 Feb 2019 17:59:08 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6DA6F2E8C0 for ; Thu, 14 Feb 2019 17:59:08 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5F0572E8F6; Thu, 14 Feb 2019 17:59:08 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 4E6842E8C0 for ; Thu, 14 Feb 2019 17:59:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=61L72PZ35n2AGdvrO0g74E28MgmpWHL2Cd6mK6T0Pkg=; b=NueHo0VIF90HWcBC+ZHTJuQv4f 9KxNBX3RifFePM9pGHMJy3jWMSB+FgK/s80GRT8ngfMUd2KErhmZVsbpu/BLBOyOriv8YaW3FAO/k QuOsO0d4fnxrkH496FLPoGs1hnYOvPijxzoGXLUUj6enUy8BBYPiyNMw+5cPq5axJV1CyhstxqXfw AYCMxPGvp/qO+8CFp/HTWcbn6O+YzSm9XelK607dECERYmDL4sfWU4KsQh61GyVt5/EdeNBG8MHl0 MAsh/t2lASsSATJD7LIyED9n0VAzNtb5MrxRltsbki+wOgEljdvoWk6xa2Oa6lwvOyUydjK8Rb9cX t0S5dJMQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1guLHl-0000nj-Ag; Thu, 14 Feb 2019 17:58:57 +0000 Received: from mail-it1-x143.google.com ([2607:f8b0:4864:20::143]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1guLGq-00087D-19 for linux-arm-kernel@lists.infradead.org; Thu, 14 Feb 2019 17:58:13 +0000 Received: by mail-it1-x143.google.com with SMTP id z9so15354268itc.4 for ; Thu, 14 Feb 2019 09:57:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Me9XXS4EbKCUGepbHlS7WPPRS+DQurUbgVfda7V56wg=; b=g1bPfV2YOhpSLIPwgfgMuMbMIb8r4+1qgZSc/lO0XQVeIi+xzc74Z09ry+gSOSAgf5 HWrNUksurPez8I+SF7JWib15etE8xdS/0a1Mddd2Sfr+mhUD6bXUNQPMmiUB17/H7TGt tFP9Ej4H8MlMEtHS3uJ92KnwpxW2okoJTfdZs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Me9XXS4EbKCUGepbHlS7WPPRS+DQurUbgVfda7V56wg=; b=i+IyMlA5IPmtuTWzI5cCIp2hiVqn3Gx501yy77ZkwHPuHI2YzwqCSSAeRokmuizHOp 9FC4OYDSWntydLA41RaiwQZBqAhK3sXlDhmiKKsz6Cpc/kxPspjqbouCAtROyUe9Wskc QElwhMIeIpXLMINwyhFtM+fAsiXkyZbJUUmr2ZYFrFd3iJMyBN3kh6Vx5nvSsdU4krks zezlxrm58wAFt4QWj6amS5YfP462n5+C4u+1GKcxqkQoIi2Ca4Dd75HCBjd5wwxHmCJj XiBExOJj3d7DiGozYb03VjJZ68+Xw22fxwMrWbw/n0b5c+QimfEPbnRcVXXX4j+7nCSk Tu8Q== X-Gm-Message-State: AHQUAuaTjrVGmKaM0fGxqZIrURsU1ZHr/i5o6F314Ukm3iTA+cIfM7UA 9iNQIr2bgd3OsaA20kXvJWx4Mw== X-Google-Smtp-Source: AHgI3IbDrPVHD6FXhmIq5gl002owvr2GlBIzeygqKNzQOFy/Fdq8U+ACxPhmqgkJuq+aXS8lxE8zew== X-Received: by 2002:a24:94cb:: with SMTP id j194mr2646394ite.117.1550167079167; Thu, 14 Feb 2019 09:57:59 -0800 (PST) Received: from rj-aorus.ric.broadcom.com ([192.19.228.250]) by smtp.gmail.com with ESMTPSA id t64sm1534178itb.5.2019.02.14.09.57.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 14 Feb 2019 09:57:58 -0800 (PST) From: Ray Jui To: Wolfram Sang , Rob Herring , Mark Rutland Subject: [PATCH v5 5/8] i2c: iproc: use wrapper for read/write access Date: Thu, 14 Feb 2019 09:57:22 -0800 Message-Id: <20190214175725.60462-6-ray.jui@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190214175725.60462-1-ray.jui@broadcom.com> References: <20190214175725.60462-1-ray.jui@broadcom.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190214_095800_951375_E3ABB02C X-CRM114-Status: GOOD ( 20.54 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Rayagonda Kokatanur , linux-kernel@vger.kernel.org, bcm-kernel-feedback-list@broadcom.com, linux-i2c@vger.kernel.org, Ray Jui , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Rayagonda Kokatanur Use the following wrapper for read/write access of iProc i2c registers: u32 iproc_i2c_rd_reg(struct bcm_iproc_i2c_dev *iproc_i2c, u32 offset) void iproc_i2c_wr_reg(struct bcm_iproc_i2c_dev *iproc_i2c, u32 offset, u32 val) This preps the driver for support of indirect register access required by certain SoCs with this iProc I2C block integrated Signed-off-by: Rayagonda Kokatanur Signed-off-by: Ray Jui --- drivers/i2c/busses/i2c-bcm-iproc.c | 145 ++++++++++++++++------------- 1 file changed, 79 insertions(+), 66 deletions(-) diff --git a/drivers/i2c/busses/i2c-bcm-iproc.c b/drivers/i2c/busses/i2c-bcm-iproc.c index 073e5a8888ad..5b9cbd7a3776 100644 --- a/drivers/i2c/busses/i2c-bcm-iproc.c +++ b/drivers/i2c/busses/i2c-bcm-iproc.c @@ -212,6 +212,18 @@ static int bcm_iproc_i2c_unreg_slave(struct i2c_client *slave); static void bcm_iproc_i2c_enable_disable(struct bcm_iproc_i2c_dev *iproc_i2c, bool enable); +static inline u32 iproc_i2c_rd_reg(struct bcm_iproc_i2c_dev *iproc_i2c, + u32 offset) +{ + return readl(iproc_i2c->base + offset); +} + +static inline void iproc_i2c_wr_reg(struct bcm_iproc_i2c_dev *iproc_i2c, + u32 offset, u32 val) +{ + writel(val, iproc_i2c->base + offset); +} + static void bcm_iproc_i2c_slave_init( struct bcm_iproc_i2c_dev *iproc_i2c, bool need_reset) { @@ -219,37 +231,37 @@ static void bcm_iproc_i2c_slave_init( if (need_reset) { /* put controller in reset */ - val = readl(iproc_i2c->base + CFG_OFFSET); + val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET); val |= BIT(CFG_RESET_SHIFT); - writel(val, iproc_i2c->base + CFG_OFFSET); + iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val); /* wait 100 usec per spec */ udelay(100); /* bring controller out of reset */ val &= ~(BIT(CFG_RESET_SHIFT)); - writel(val, iproc_i2c->base + CFG_OFFSET); + iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val); } /* flush TX/RX FIFOs */ val = (BIT(S_FIFO_RX_FLUSH_SHIFT) | BIT(S_FIFO_TX_FLUSH_SHIFT)); - writel(val, iproc_i2c->base + S_FIFO_CTRL_OFFSET); + iproc_i2c_wr_reg(iproc_i2c, S_FIFO_CTRL_OFFSET, val); /* RANDOM SLAVE STRETCH time - 20ms*/ - val = readl(iproc_i2c->base + TIM_CFG_OFFSET); + val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET); val &= ~(TIM_RAND_SLAVE_STRETCH_MASK << TIM_RAND_SLAVE_STRETCH_SHIFT); val |= (SLAVE_CLOCK_STRETCH_TIME << TIM_RAND_SLAVE_STRETCH_SHIFT); - writel(val, iproc_i2c->base + TIM_CFG_OFFSET); + iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val); /* Configure the slave address */ - val = readl(iproc_i2c->base + S_CFG_SMBUS_ADDR_OFFSET); + val = iproc_i2c_rd_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET); val |= BIT(S_CFG_EN_NIC_SMB_ADDR3_SHIFT); val &= ~(S_CFG_NIC_SMB_ADDR3_MASK << S_CFG_NIC_SMB_ADDR3_SHIFT); val |= (iproc_i2c->slave->addr << S_CFG_NIC_SMB_ADDR3_SHIFT); - writel(val, iproc_i2c->base + S_CFG_SMBUS_ADDR_OFFSET); + iproc_i2c_wr_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET, val); /* clear all pending slave interrupts */ - writel(ISR_MASK_SLAVE, iproc_i2c->base + IS_OFFSET); + iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, ISR_MASK_SLAVE); /* Enable interrupt register for any READ event */ val = BIT(IE_S_RD_EVENT_SHIFT); @@ -257,7 +269,7 @@ static void bcm_iproc_i2c_slave_init( val |= BIT(IE_S_RX_EVENT_SHIFT); /* Enable interrupt register for the Slave BUSY command */ val |= BIT(IE_S_START_BUSY_SHIFT); - writel(val, iproc_i2c->base + IE_OFFSET); + iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val); iproc_i2c->xfer_dir = I2C_SLAVE_DIR_NONE; } @@ -267,7 +279,7 @@ static void bcm_iproc_i2c_check_slave_status( { u32 val; - val = readl(iproc_i2c->base + S_CMD_OFFSET); + val = iproc_i2c_rd_reg(iproc_i2c, S_CMD_OFFSET); val = (val >> S_CMD_STATUS_SHIFT) & S_CMD_STATUS_MASK; if (val == S_CMD_STATUS_TIMEOUT) { @@ -290,7 +302,7 @@ static bool bcm_iproc_i2c_slave_isr(struct bcm_iproc_i2c_dev *iproc_i2c, /* Start of transaction. check address and populate the direction */ if (iproc_i2c->xfer_dir == I2C_SLAVE_DIR_NONE) { - tmp = readl(iproc_i2c->base + S_RX_OFFSET); + tmp = iproc_i2c_rd_reg(iproc_i2c, S_RX_OFFSET); rd_status = (tmp >> S_RX_STATUS_SHIFT) & S_RX_STATUS_MASK; /* This condition checks whether the request is a new request */ if (((rd_status == I2C_SLAVE_RX_START) && @@ -316,16 +328,16 @@ static bool bcm_iproc_i2c_slave_isr(struct bcm_iproc_i2c_dev *iproc_i2c, (iproc_i2c->xfer_dir == I2C_SLAVE_DIR_WRITE)) { i2c_slave_event(iproc_i2c->slave, I2C_SLAVE_READ_PROCESSED, &value); - writel(value, iproc_i2c->base + S_TX_OFFSET); + iproc_i2c_wr_reg(iproc_i2c, S_TX_OFFSET, value); val = BIT(S_CMD_START_BUSY_SHIFT); - writel(val, iproc_i2c->base + S_CMD_OFFSET); + iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val); } /* write request from master */ if ((status & BIT(IS_S_RX_EVENT_SHIFT)) && (iproc_i2c->xfer_dir == I2C_SLAVE_DIR_READ)) { - val = readl(iproc_i2c->base + S_RX_OFFSET); + val = iproc_i2c_rd_reg(iproc_i2c, S_RX_OFFSET); /* Its a write request by Master to Slave. * We read data present in receive FIFO */ @@ -348,7 +360,7 @@ static bool bcm_iproc_i2c_slave_isr(struct bcm_iproc_i2c_dev *iproc_i2c, } /* clear interrupt status */ - writel(status, iproc_i2c->base + IS_OFFSET); + iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, status); bcm_iproc_i2c_check_slave_status(iproc_i2c); return true; @@ -360,14 +372,13 @@ static void bcm_iproc_i2c_read_valid_bytes(struct bcm_iproc_i2c_dev *iproc_i2c) /* Read valid data from RX FIFO */ while (iproc_i2c->rx_bytes < msg->len) { - if (!((readl(iproc_i2c->base + - M_FIFO_CTRL_OFFSET) >> - M_FIFO_RX_CNT_SHIFT) & - M_FIFO_RX_CNT_MASK)) + if (!((iproc_i2c_rd_reg(iproc_i2c, + M_FIFO_CTRL_OFFSET) >> + M_FIFO_RX_CNT_SHIFT) & M_FIFO_RX_CNT_MASK)) break; msg->buf[iproc_i2c->rx_bytes] = - (readl(iproc_i2c->base + M_RX_OFFSET) >> + (iproc_i2c_rd_reg(iproc_i2c, M_RX_OFFSET) >> M_RX_DATA_SHIFT) & M_RX_DATA_MASK; iproc_i2c->rx_bytes++; } @@ -399,14 +410,15 @@ static void bcm_iproc_i2c_send(struct bcm_iproc_i2c_dev *iproc_i2c) * Since this is the last byte, we should now * disable TX FIFO underrun interrupt */ - tmp = readl(iproc_i2c->base + IE_OFFSET); + tmp = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET); tmp &= ~BIT(IE_M_TX_UNDERRUN_SHIFT); - writel(tmp, iproc_i2c->base + IE_OFFSET); + iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, + tmp); } } /* load data into TX FIFO */ - writel(val, iproc_i2c->base + M_TX_OFFSET); + iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val); } /* update number of transferred bytes */ @@ -423,16 +435,16 @@ static void bcm_iproc_i2c_read(struct bcm_iproc_i2c_dev *iproc_i2c) if (bytes_left == 0) { if (iproc_i2c->irq) { /* finished reading all data, disable rx thld event */ - val = readl(iproc_i2c->base + IE_OFFSET); + val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET); val &= ~BIT(IS_M_RX_THLD_SHIFT); - writel(val, iproc_i2c->base + IE_OFFSET); + iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val); } } else if (bytes_left < iproc_i2c->thld_bytes) { /* set bytes left as threshold */ - val = readl(iproc_i2c->base + M_FIFO_CTRL_OFFSET); + val = iproc_i2c_rd_reg(iproc_i2c, M_FIFO_CTRL_OFFSET); val &= ~(M_FIFO_RX_THLD_MASK << M_FIFO_RX_THLD_SHIFT); val |= (bytes_left << M_FIFO_RX_THLD_SHIFT); - writel(val, iproc_i2c->base + M_FIFO_CTRL_OFFSET); + iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val); iproc_i2c->thld_bytes = bytes_left; } /* @@ -464,7 +476,7 @@ static void bcm_iproc_i2c_process_m_event(struct bcm_iproc_i2c_dev *iproc_i2c, static irqreturn_t bcm_iproc_i2c_isr(int irq, void *data) { struct bcm_iproc_i2c_dev *iproc_i2c = data; - u32 status = readl(iproc_i2c->base + IS_OFFSET); + u32 status = iproc_i2c_rd_reg(iproc_i2c, IS_OFFSET); bool ret; u32 sl_status = status & ISR_MASK_SLAVE; @@ -482,7 +494,7 @@ static irqreturn_t bcm_iproc_i2c_isr(int irq, void *data) /* process all master based events */ bcm_iproc_i2c_process_m_event(iproc_i2c, status); - writel(status, iproc_i2c->base + IS_OFFSET); + iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, status); return IRQ_HANDLED; } @@ -492,29 +504,29 @@ static int bcm_iproc_i2c_init(struct bcm_iproc_i2c_dev *iproc_i2c) u32 val; /* put controller in reset */ - val = readl(iproc_i2c->base + CFG_OFFSET); + val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET); val |= BIT(CFG_RESET_SHIFT); val &= ~(BIT(CFG_EN_SHIFT)); - writel(val, iproc_i2c->base + CFG_OFFSET); + iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val); /* wait 100 usec per spec */ udelay(100); /* bring controller out of reset */ val &= ~(BIT(CFG_RESET_SHIFT)); - writel(val, iproc_i2c->base + CFG_OFFSET); + iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val); /* flush TX/RX FIFOs and set RX FIFO threshold to zero */ val = (BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT)); - writel(val, iproc_i2c->base + M_FIFO_CTRL_OFFSET); + iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val); /* disable all interrupts */ - val = readl(iproc_i2c->base + IE_OFFSET); + val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET); val &= ~(IE_M_ALL_INTERRUPT_MASK << IE_M_ALL_INTERRUPT_SHIFT); - writel(val, iproc_i2c->base + IE_OFFSET); + iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val); /* clear all pending interrupts */ - writel(0xffffffff, iproc_i2c->base + IS_OFFSET); + iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, 0xffffffff); return 0; } @@ -524,12 +536,12 @@ static void bcm_iproc_i2c_enable_disable(struct bcm_iproc_i2c_dev *iproc_i2c, { u32 val; - val = readl(iproc_i2c->base + CFG_OFFSET); + val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET); if (enable) val |= BIT(CFG_EN_SHIFT); else val &= ~BIT(CFG_EN_SHIFT); - writel(val, iproc_i2c->base + CFG_OFFSET); + iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val); } static int bcm_iproc_i2c_check_status(struct bcm_iproc_i2c_dev *iproc_i2c, @@ -537,7 +549,7 @@ static int bcm_iproc_i2c_check_status(struct bcm_iproc_i2c_dev *iproc_i2c, { u32 val; - val = readl(iproc_i2c->base + M_CMD_OFFSET); + val = iproc_i2c_rd_reg(iproc_i2c, M_CMD_OFFSET); val = (val >> M_CMD_STATUS_SHIFT) & M_CMD_STATUS_MASK; switch (val) { @@ -588,15 +600,15 @@ static int bcm_iproc_i2c_xfer_wait(struct bcm_iproc_i2c_dev *iproc_i2c, u32 val, status; int ret; - writel(cmd, iproc_i2c->base + M_CMD_OFFSET); + iproc_i2c_wr_reg(iproc_i2c, M_CMD_OFFSET, cmd); if (iproc_i2c->irq) { time_left = wait_for_completion_timeout(&iproc_i2c->done, time_left); /* disable all interrupts */ - writel(0, iproc_i2c->base + IE_OFFSET); + iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0); /* read it back to flush the write */ - readl(iproc_i2c->base + IE_OFFSET); + iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET); /* make sure the interrupt handler isn't running */ synchronize_irq(iproc_i2c->irq); @@ -604,9 +616,10 @@ static int bcm_iproc_i2c_xfer_wait(struct bcm_iproc_i2c_dev *iproc_i2c, unsigned long timeout = jiffies + time_left; do { - status = readl(iproc_i2c->base + IS_OFFSET) & ISR_MASK; + status = iproc_i2c_rd_reg(iproc_i2c, + IS_OFFSET) & ISR_MASK; bcm_iproc_i2c_process_m_event(iproc_i2c, status); - writel(status, iproc_i2c->base + IS_OFFSET); + iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, status); if (time_after(jiffies, timeout)) { time_left = 0; @@ -623,7 +636,7 @@ static int bcm_iproc_i2c_xfer_wait(struct bcm_iproc_i2c_dev *iproc_i2c, /* flush both TX/RX FIFOs */ val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT); - writel(val, iproc_i2c->base + M_FIFO_CTRL_OFFSET); + iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val); return -ETIMEDOUT; } @@ -631,7 +644,7 @@ static int bcm_iproc_i2c_xfer_wait(struct bcm_iproc_i2c_dev *iproc_i2c, if (ret) { /* flush both TX/RX FIFOs */ val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT); - writel(val, iproc_i2c->base + M_FIFO_CTRL_OFFSET); + iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val); return ret; } @@ -647,8 +660,8 @@ static int bcm_iproc_i2c_xfer_single_msg(struct bcm_iproc_i2c_dev *iproc_i2c, unsigned int tx_bytes; /* check if bus is busy */ - if (!!(readl(iproc_i2c->base + M_CMD_OFFSET) & - BIT(M_CMD_START_BUSY_SHIFT))) { + if (!!(iproc_i2c_rd_reg(iproc_i2c, + M_CMD_OFFSET) & BIT(M_CMD_START_BUSY_SHIFT))) { dev_warn(iproc_i2c->device, "bus is busy\n"); return -EBUSY; } @@ -657,7 +670,7 @@ static int bcm_iproc_i2c_xfer_single_msg(struct bcm_iproc_i2c_dev *iproc_i2c, /* format and load slave address into the TX FIFO */ addr = i2c_8bit_addr_from_msg(msg); - writel(addr, iproc_i2c->base + M_TX_OFFSET); + iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, addr); /* * For a write transaction, load data into the TX FIFO. Only allow @@ -673,7 +686,7 @@ static int bcm_iproc_i2c_xfer_single_msg(struct bcm_iproc_i2c_dev *iproc_i2c, if (i == msg->len - 1) val |= 1 << M_TX_WR_STATUS_SHIFT; - writel(val, iproc_i2c->base + M_TX_OFFSET); + iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val); } iproc_i2c->tx_bytes = tx_bytes; } @@ -713,10 +726,10 @@ static int bcm_iproc_i2c_xfer_single_msg(struct bcm_iproc_i2c_dev *iproc_i2c, iproc_i2c->thld_bytes = msg->len; /* set threshold value */ - tmp = readl(iproc_i2c->base + M_FIFO_CTRL_OFFSET); + tmp = iproc_i2c_rd_reg(iproc_i2c, M_FIFO_CTRL_OFFSET); tmp &= ~(M_FIFO_RX_THLD_MASK << M_FIFO_RX_THLD_SHIFT); tmp |= iproc_i2c->thld_bytes << M_FIFO_RX_THLD_SHIFT; - writel(tmp, iproc_i2c->base + M_FIFO_CTRL_OFFSET); + iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, tmp); /* enable the RX threshold interrupt */ val_intr_en |= BIT(IE_M_RX_THLD_SHIFT); @@ -728,7 +741,7 @@ static int bcm_iproc_i2c_xfer_single_msg(struct bcm_iproc_i2c_dev *iproc_i2c, } if (iproc_i2c->irq) - writel(val_intr_en, iproc_i2c->base + IE_OFFSET); + iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val_intr_en); return bcm_iproc_i2c_xfer_wait(iproc_i2c, msg, val); } @@ -792,10 +805,10 @@ static int bcm_iproc_i2c_cfg_speed(struct bcm_iproc_i2c_dev *iproc_i2c) } iproc_i2c->bus_speed = bus_speed; - val = readl(iproc_i2c->base + TIM_CFG_OFFSET); + val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET); val &= ~(1 << TIM_CFG_MODE_400_SHIFT); val |= (bus_speed == 400000) << TIM_CFG_MODE_400_SHIFT; - writel(val, iproc_i2c->base + TIM_CFG_OFFSET); + iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val); dev_info(iproc_i2c->device, "bus set to %u Hz\n", bus_speed); @@ -870,8 +883,8 @@ static int bcm_iproc_i2c_remove(struct platform_device *pdev) * Make sure there's no pending interrupt when we remove the * adapter */ - writel(0, iproc_i2c->base + IE_OFFSET); - readl(iproc_i2c->base + IE_OFFSET); + iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0); + iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET); synchronize_irq(iproc_i2c->irq); } @@ -892,8 +905,8 @@ static int bcm_iproc_i2c_suspend(struct device *dev) * Make sure there's no pending interrupt when we go into * suspend */ - writel(0, iproc_i2c->base + IE_OFFSET); - readl(iproc_i2c->base + IE_OFFSET); + iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0); + iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET); synchronize_irq(iproc_i2c->irq); } @@ -918,10 +931,10 @@ static int bcm_iproc_i2c_resume(struct device *dev) return ret; /* configure to the desired bus speed */ - val = readl(iproc_i2c->base + TIM_CFG_OFFSET); + val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET); val &= ~(1 << TIM_CFG_MODE_400_SHIFT); val |= (iproc_i2c->bus_speed == 400000) << TIM_CFG_MODE_400_SHIFT; - writel(val, iproc_i2c->base + TIM_CFG_OFFSET); + iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val); bcm_iproc_i2c_enable_disable(iproc_i2c, true); @@ -965,15 +978,15 @@ static int bcm_iproc_i2c_unreg_slave(struct i2c_client *slave) iproc_i2c->slave = NULL; /* disable all slave interrupts */ - tmp = readl(iproc_i2c->base + IE_OFFSET); + tmp = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET); tmp &= ~(IE_S_ALL_INTERRUPT_MASK << IE_S_ALL_INTERRUPT_SHIFT); - writel(tmp, iproc_i2c->base + IE_OFFSET); + iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, tmp); /* Erase the slave address programmed */ - tmp = readl(iproc_i2c->base + S_CFG_SMBUS_ADDR_OFFSET); + tmp = iproc_i2c_rd_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET); tmp &= ~BIT(S_CFG_EN_NIC_SMB_ADDR3_SHIFT); - writel(tmp, iproc_i2c->base + S_CFG_SMBUS_ADDR_OFFSET); + iproc_i2c_wr_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET, tmp); return 0; } From patchwork Thu Feb 14 17:57:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ray Jui X-Patchwork-Id: 10813411 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A4614922 for ; Thu, 14 Feb 2019 17:59:09 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8FE432E8C0 for ; Thu, 14 Feb 2019 17:59:09 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 83BFE2E8F6; Thu, 14 Feb 2019 17:59:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id E5F652E8C0 for ; Thu, 14 Feb 2019 17:59:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=N2DX66Zcfg1I3BqASzetkzpMOQXSRayq8tG6S0C6abo=; b=XoYxFgYkQT2+j+8uauYLwOETzM ILl40csjInWGKqav7qvKh1b38yUUV9H5kNyowR5ECq+Xnh3hqo/alvtvmr5Z0E33sBFuS0Rva66E9 3PBJC2ak1Wn7pPj/9u6CLvChG8AryMGPzCkKBammfp4azn+ecmRVXvIgAnM+sM4GEoS/fWrSb3xVJ 5VAQXm0wGzLMvsuxlYrnVANLM+nzkpYap6EHc84SqKSVVnf+iBs3mCY9Tk653P5LwmfQlWm73KXYX n/2BCQ54lUVUiPjB7nouiONI4fGGkwJZasZX4TA38nEvsB2n3jr85ecSEw9qC+kOSZkqqLdQ9d3rF z/EP2I9Q==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1guLHu-0000wc-9P; Thu, 14 Feb 2019 17:59:06 +0000 Received: from mail-it1-x144.google.com ([2607:f8b0:4864:20::144]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1guLGt-0008Bu-4c for linux-arm-kernel@lists.infradead.org; Thu, 14 Feb 2019 17:58:16 +0000 Received: by mail-it1-x144.google.com with SMTP id z7so17267088iti.0 for ; Thu, 14 Feb 2019 09:58:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=fGCGdqm3RAepP74+LvCBxZoDYBWuJpR+3MyMVFFDokE=; b=IRBoYPkzSdiQztYw6MxHVNC+x9VpkbxkNWUNyAFXuG8qenf4Juxpr1qN9jqg8Tkipv tFD9NubGpVq1Kgk+i/1fqwEj2YS9MDV5Coi0h0HZgxmrnMIwhzH07qx7+Yuk0L+VtaCA ist8UFHCcmjiS9Yk1DPG7nIjmr3Yr6sJaY5ho= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=fGCGdqm3RAepP74+LvCBxZoDYBWuJpR+3MyMVFFDokE=; b=iAafC0N3V+CB4Igk0fmoJ3l9CPBE51Vxp5Gn6zWz/eKZvATci7hSF7HutO6uYcavAH bUGOeC2dPT+I+E1ABhpTCnirRrNgJfidIKs2sh4L82j0m6UHXxg2YKNukl757103spIL hPlLdEWKWQ3SqkkiW4JAjDnVDo2nKqCktC3Q+CcknY80zVRp717XHAygJsAgU36pyhuy mtnvTNsyJ9MCDgQXtVd4GKxYWHEg9omz/TlAFhuageABlRwptKj2fMjdLgRcEMMDkKAr 3ytBfzu3/kkLBGSpZpCE12ABhVywu5k1nzfcobp+gzYPzuuZqxeidQhQxLzRpE58XDFC QdIw== X-Gm-Message-State: AHQUAubhiOm69vYKlg511u3xm/PyZF8n6DjX2fF/uIAl64r4kxRIqKZM +NpqLk3hbm5C7Kw2+uWzMmp2XQ== X-Google-Smtp-Source: AHgI3IZdkA++LNv7Ts5SFqk3VxLEQJTkpqqhr7pwHg3I8pWazyHPFkUL6jF4SzUfI6ttFbpGZHEdBA== X-Received: by 2002:a6b:b644:: with SMTP id g65mr2927148iof.198.1550167082407; Thu, 14 Feb 2019 09:58:02 -0800 (PST) Received: from rj-aorus.ric.broadcom.com ([192.19.228.250]) by smtp.gmail.com with ESMTPSA id t64sm1534178itb.5.2019.02.14.09.58.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 14 Feb 2019 09:58:01 -0800 (PST) From: Ray Jui To: Wolfram Sang , Rob Herring , Mark Rutland Subject: [PATCH v5 6/8] dt-bindings: i2c: iproc: add "brcm, iproc-nic-i2c" compatible string Date: Thu, 14 Feb 2019 09:57:23 -0800 Message-Id: <20190214175725.60462-7-ray.jui@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190214175725.60462-1-ray.jui@broadcom.com> References: <20190214175725.60462-1-ray.jui@broadcom.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190214_095803_623708_2950B1B0 X-CRM114-Status: GOOD ( 12.01 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Rayagonda Kokatanur , linux-kernel@vger.kernel.org, bcm-kernel-feedback-list@broadcom.com, linux-i2c@vger.kernel.org, Ray Jui , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Rayagonda Kokatanur Update iProc I2C binding document to add new compatible string "brcm,iproc-nic-i2c". Optional property "brcm,ape-hsls-addr-mask" is also added that allows configuration of the host view into the APE's address for "brcm,iproc-nic-i2c" Signed-off-by: Rayagonda Kokatanur Signed-off-by: Ray Jui Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/i2c/brcm,iproc-i2c.txt | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/i2c/brcm,iproc-i2c.txt b/Documentation/devicetree/bindings/i2c/brcm,iproc-i2c.txt index 7a32bf81bfa9..d12cc33cca6c 100644 --- a/Documentation/devicetree/bindings/i2c/brcm,iproc-i2c.txt +++ b/Documentation/devicetree/bindings/i2c/brcm,iproc-i2c.txt @@ -3,7 +3,7 @@ Broadcom iProc I2C controller Required properties: - compatible: - Must be "brcm,iproc-i2c" + Must be "brcm,iproc-i2c" or "brcm,iproc-nic-i2c" - reg: Define the base and range of the I/O address space that contain the iProc @@ -26,6 +26,10 @@ Optional properties: case, this property should be left unspecified, and driver will fall back to polling mode +- brcm,ape-hsls-addr-mask: + Required for "brcm,iproc-nic-i2c". Host view of address mask into the + 'APE' co-processor. Value must be unsigned, 32-bit + Example: i2c0: i2c@18008000 { compatible = "brcm,iproc-i2c"; From patchwork Thu Feb 14 17:57:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ray Jui X-Patchwork-Id: 10813417 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 59121922 for ; Thu, 14 Feb 2019 17:59:31 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 44E3A2EEF1 for ; Thu, 14 Feb 2019 17:59:31 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 389102EEFB; Thu, 14 Feb 2019 17:59:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 2DA572EEF1 for ; Thu, 14 Feb 2019 17:59:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=/0lyvzr6I+yrXFmHoJn4kJaiJf2uY9ZP1gDfv6to4FQ=; b=oJw6cWFqWPJ4xymlL/cUXe9T+X 6F3sa17D0bgQWpGXoQOwK1CxYQy3uJdIvzt/YA5RUI7EmfVkv7GvBkMykEpHoIsIDLShBsHdkGJe1 Ejox5dR1/jGDrRIAOAWz/3tsqDxxRJRAuOhWxuMgckDWim7QTli1SeeWOFWGq7Eaph9k0+LBUstBZ GSUOymLkF30GNC0wSrn5HTKfgEe8wzQrF8oePloOWKZ9AJDluZmO4n2rJqXa+bzH7JHeKDsSJAA2/ mukEn5rbh+RW++wBixM5+tq9uNnBcnriiCoxBmcoRmatbq03fjDl3LrFf7krhFGPQFhFJpNGx/k9Q GHeLjUew==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1guLIG-0001UG-HZ; Thu, 14 Feb 2019 17:59:28 +0000 Received: from mail-it1-x142.google.com ([2607:f8b0:4864:20::142]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1guLGw-0008Fb-PY for linux-arm-kernel@lists.infradead.org; Thu, 14 Feb 2019 17:58:27 +0000 Received: by mail-it1-x142.google.com with SMTP id l131so16405928ita.2 for ; Thu, 14 Feb 2019 09:58:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=fF0LtqiU+ezqKDEGBPuxdJhivCCihna6QbzlCwznwyo=; b=GZL7bMWsuhT/yxy1rHdCzEmJxBLDze3KipqjsMO9AXNUmndIK/l3k0kAWpt/whJBt9 9fHjkTAAbCBKGNdGJbpPGGpTT6Bc/+4M8mQ7NCRNgL8bcPE+xk6WHXsTpKU++DxO4/YU +0igyBni8rrMxWl00/XM07aa3JleVBnu28Da4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=fF0LtqiU+ezqKDEGBPuxdJhivCCihna6QbzlCwznwyo=; b=GCbgq92bxj/yo+QmuVuwgPHDAI3OSJNVA3X3kNxHyjilH/EaUIA1J2kbOHOsOMqvbb EKMTOxJ9xgPYck0BcmNRGQgteoPZu//weDePSKSsoA2SCznawbNv+3hSJVDlreZ5cO1V +FYQNwCB/i0ANwGo4aEaRhxq0vdUDOPWaE78M0dWUgh2Bfi2wYE1gLmdPEYzxvRauCQx irUoHczE1PI/Zy+04djW7Spn0mQ1bEko/JuzdD1lv+Zrq3TG4b2AJk/AHMsConfVVVuB Vrb0hwp1/70ZgNhaWl7BYo+g1mjM4vyB5AdmDYy/7aMvWOWtsYX0hrQTLoQGYD9WAdpp ihUA== X-Gm-Message-State: AHQUAuZtrYTovACBPc/spVEjOqDogwl30ZQiKw+1Xi7xP7BdRBghSzCa j/P9jtf17kQ6Dvg8OG543HWDRQ== X-Google-Smtp-Source: AHgI3IY5j6xsuyyk1XVs+BpvsO4vD5bIoDMrBNL02aS+ROITaVKAg9qVntm6joUMi1D2DR5QQ70b7w== X-Received: by 2002:a24:bdcc:: with SMTP id x195mr1541749ite.149.1550167085551; Thu, 14 Feb 2019 09:58:05 -0800 (PST) Received: from rj-aorus.ric.broadcom.com ([192.19.228.250]) by smtp.gmail.com with ESMTPSA id t64sm1534178itb.5.2019.02.14.09.58.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 14 Feb 2019 09:58:04 -0800 (PST) From: Ray Jui To: Wolfram Sang , Rob Herring , Mark Rutland Subject: [PATCH v5 7/8] i2c: iproc: add NIC I2C support Date: Thu, 14 Feb 2019 09:57:24 -0800 Message-Id: <20190214175725.60462-8-ray.jui@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190214175725.60462-1-ray.jui@broadcom.com> References: <20190214175725.60462-1-ray.jui@broadcom.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190214_095807_058529_79583582 X-CRM114-Status: GOOD ( 18.66 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Rayagonda Kokatanur , linux-kernel@vger.kernel.org, bcm-kernel-feedback-list@broadcom.com, linux-i2c@vger.kernel.org, Ray Jui , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Rayagonda Kokatanur Add NIC I2C support to the iProc I2C driver. Access to the NIC I2C base registers requires going through the IDM wrapper to map into the NIC's address space Signed-off-by: Rayagonda Kokatanur Signed-off-by: Ray Jui --- drivers/i2c/busses/i2c-bcm-iproc.c | 79 ++++++++++++++++++++++++++++-- 1 file changed, 75 insertions(+), 4 deletions(-) diff --git a/drivers/i2c/busses/i2c-bcm-iproc.c b/drivers/i2c/busses/i2c-bcm-iproc.c index 5b9cbd7a3776..9598e1d0048e 100644 --- a/drivers/i2c/busses/i2c-bcm-iproc.c +++ b/drivers/i2c/busses/i2c-bcm-iproc.c @@ -17,9 +17,11 @@ #include #include #include +#include #include #include +#define IDM_CTRL_DIRECT_OFFSET 0x00 #define CFG_OFFSET 0x00 #define CFG_RESET_SHIFT 31 #define CFG_EN_SHIFT 30 @@ -174,11 +176,26 @@ enum bus_speed_index { I2C_SPD_400K, }; +enum bcm_iproc_i2c_type { + IPROC_I2C, + IPROC_I2C_NIC +}; + struct bcm_iproc_i2c_dev { struct device *device; + enum bcm_iproc_i2c_type type; int irq; void __iomem *base; + void __iomem *idm_base; + + u32 ape_addr_mask; + + /* lock for indirect access through IDM */ + spinlock_t idm_lock; + + /* indicates no slave mode support */ + bool no_slave; struct i2c_adapter adapter; unsigned int bus_speed; @@ -215,13 +232,33 @@ static void bcm_iproc_i2c_enable_disable(struct bcm_iproc_i2c_dev *iproc_i2c, static inline u32 iproc_i2c_rd_reg(struct bcm_iproc_i2c_dev *iproc_i2c, u32 offset) { - return readl(iproc_i2c->base + offset); + u32 val; + + if (iproc_i2c->idm_base) { + spin_lock(&iproc_i2c->idm_lock); + writel(iproc_i2c->ape_addr_mask, + iproc_i2c->idm_base + IDM_CTRL_DIRECT_OFFSET); + val = readl(iproc_i2c->base + offset); + spin_unlock(&iproc_i2c->idm_lock); + } else { + val = readl(iproc_i2c->base + offset); + } + + return val; } static inline void iproc_i2c_wr_reg(struct bcm_iproc_i2c_dev *iproc_i2c, u32 offset, u32 val) { - writel(val, iproc_i2c->base + offset); + if (iproc_i2c->idm_base) { + spin_lock(&iproc_i2c->idm_lock); + writel(iproc_i2c->ape_addr_mask, + iproc_i2c->idm_base + IDM_CTRL_DIRECT_OFFSET); + writel(val, iproc_i2c->base + offset); + spin_unlock(&iproc_i2c->idm_lock); + } else { + writel(val, iproc_i2c->base + offset); + } } static void bcm_iproc_i2c_slave_init( @@ -766,7 +803,13 @@ static int bcm_iproc_i2c_xfer(struct i2c_adapter *adapter, static uint32_t bcm_iproc_i2c_functionality(struct i2c_adapter *adap) { - return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SLAVE; + struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(adap); + u32 val = I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; + + if (!iproc_i2c->no_slave) + val |= I2C_FUNC_SLAVE; + + return val; } static const struct i2c_algorithm bcm_iproc_algo = { @@ -829,6 +872,8 @@ static int bcm_iproc_i2c_probe(struct platform_device *pdev) platform_set_drvdata(pdev, iproc_i2c); iproc_i2c->device = &pdev->dev; + iproc_i2c->type = + (enum bcm_iproc_i2c_type) of_device_get_match_data(&pdev->dev); init_completion(&iproc_i2c->done); res = platform_get_resource(pdev, IORESOURCE_MEM, 0); @@ -836,6 +881,26 @@ static int bcm_iproc_i2c_probe(struct platform_device *pdev) if (IS_ERR(iproc_i2c->base)) return PTR_ERR(iproc_i2c->base); + if (iproc_i2c->type == IPROC_I2C_NIC) { + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + iproc_i2c->idm_base = devm_ioremap_resource(iproc_i2c->device, + res); + if (IS_ERR(iproc_i2c->idm_base)) + return PTR_ERR(iproc_i2c->idm_base); + + ret = of_property_read_u32(iproc_i2c->device->of_node, + "brcm,ape-hsls-addr-mask", + &iproc_i2c->ape_addr_mask); + if (ret < 0) { + dev_err(iproc_i2c->device, + "'brcm,ape-hsls-addr-mask' missing\n"); + return -EINVAL; + } + + spin_lock_init(&iproc_i2c->idm_lock); + iproc_i2c->no_slave = true; + } + ret = bcm_iproc_i2c_init(iproc_i2c); if (ret) return ret; @@ -992,7 +1057,13 @@ static int bcm_iproc_i2c_unreg_slave(struct i2c_client *slave) } static const struct of_device_id bcm_iproc_i2c_of_match[] = { - { .compatible = "brcm,iproc-i2c" }, + { + .compatible = "brcm,iproc-i2c", + .data = (int *)IPROC_I2C, + }, { + .compatible = "brcm,iproc-nic-i2c", + .data = (int *)IPROC_I2C_NIC, + }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, bcm_iproc_i2c_of_match); From patchwork Thu Feb 14 17:57:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ray Jui X-Patchwork-Id: 10813415 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2B3AD1399 for ; Thu, 14 Feb 2019 17:59:28 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 192F82EEF1 for ; Thu, 14 Feb 2019 17:59:28 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0D9572EEFB; Thu, 14 Feb 2019 17:59:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id B971C2EEF1 for ; Thu, 14 Feb 2019 17:59:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=6uHsZ0LWP/NuQic3w+wGom4W/TyGuZeRK/dAZmw2i0Y=; b=BMXOCe3evJKjGvI82xpYqD2cS8 cEnUHmyuhDXzdx3ti/uR2Kd1SbUCYh745FBnln3j2n9pdNHPNOA26yL46fH/jzAOqdPUs/PM4HWIG 9KiFDkeUxeebYF37FSnTX/mvBZsPUoDZN8PaSYHrcRnQHuRCyjawAyFb1UjsVeEP7aL+LVzd6apCy OYkEVZAxAyfghw5CXVdPcRfpBvFGugf/yzXYjoUJUfF5u1cf1EpMm5EpNLUlJuh+CHlJgXs4vnJ54 j1P2z1rh7vRb1QMS66BxS7gbXXZA8lhm+vXGcG7GfHnDgq4EyVskFf8wi/sR9zMWc9DwXMAOBo8Kk pCfeoTBA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1guLI6-0001C5-0G; Thu, 14 Feb 2019 17:59:18 +0000 Received: from mail-it1-x142.google.com ([2607:f8b0:4864:20::142]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1guLGz-0008JO-A4 for linux-arm-kernel@lists.infradead.org; Thu, 14 Feb 2019 17:58:28 +0000 Received: by mail-it1-x142.google.com with SMTP id l15so3677249iti.4 for ; Thu, 14 Feb 2019 09:58:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=gd56skZROQuoUVaN4sNpxlterBec6i5NZQ5F4gBEN3E=; b=QudLWP+sniBzsE8uYjGXuJXcEydbgmJhe/GvRfu9kTa9EIp4Z2eDYZ8REpNLIpE1Zm fyaW5eIjNG4/Fzzq+CL+z8f2UIIQqAc0EXYUO/coSwHV5l5bgbqTBH1lZAA+PV32UUS5 rKgOyUjPR/1hen90tuQTJdD8IJTesj2YRH23g= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=gd56skZROQuoUVaN4sNpxlterBec6i5NZQ5F4gBEN3E=; b=bfZLGRrAbfigHbGd45AIKDrQATABTh41Zyy1VxinxjwBlb1ixuZCPApdkK0N3TRoAs 4nHuoLHrshhnX8dDjEtMo0WquYjGY6jFNdrI+t5JFpiLVAJKULouKE3Wnxzkn3bFrS8c x5UcoOInHMcC0d6Viv6dGF+KAhXqdIrkZQQaeXVcg9bigAb3PJQxTC/US0nlBIEg+wUV eTWd0iZVDY09APbO7xj/3DqxYO+YW5IAUOLtNx5jlwZQ3rqOQVA9iYk7mgC+B/pXUXRO OgqjGr+PRxOHD9iXkw09Y2EAOkEVQSqXnHllGZJqktEQTpBhlU49mRMJ9ocW1zj447hy GUww== X-Gm-Message-State: AHQUAuY9+AWrO37uGx5Ptbspzbah7pV3NQGusyNGtA0CIAiDvZFQpY3T RNIQ4z9AL91aSuw2D6y2mlT8CQ== X-Google-Smtp-Source: AHgI3IbI06wiWDqUs7HRa1Q+9hP8xygHiei3IcNiwtWZlToH3VapRCyZPICy+iKeXQfRl1apGw4DCA== X-Received: by 2002:a5d:9287:: with SMTP id s7mr2799518iom.295.1550167088620; Thu, 14 Feb 2019 09:58:08 -0800 (PST) Received: from rj-aorus.ric.broadcom.com ([192.19.228.250]) by smtp.gmail.com with ESMTPSA id t64sm1534178itb.5.2019.02.14.09.58.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 14 Feb 2019 09:58:07 -0800 (PST) From: Ray Jui To: Wolfram Sang , Rob Herring , Mark Rutland Subject: [PATCH v5 8/8] arm64: dts: Stingray: Add NIC i2c device node Date: Thu, 14 Feb 2019 09:57:25 -0800 Message-Id: <20190214175725.60462-9-ray.jui@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190214175725.60462-1-ray.jui@broadcom.com> References: <20190214175725.60462-1-ray.jui@broadcom.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190214_095809_520237_04C5877B X-CRM114-Status: GOOD ( 11.52 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Rayagonda Kokatanur , linux-kernel@vger.kernel.org, bcm-kernel-feedback-list@broadcom.com, linux-i2c@vger.kernel.org, Ray Jui , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Rayagonda Kokatanur Add NIC i2c device node. Signed-off-by: Rayagonda Kokatanur Signed-off-by: Ray Jui --- .../boot/dts/broadcom/stingray/stingray.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi index cfeaa855bd05..67e53768a84a 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi @@ -612,4 +612,22 @@ status = "disabled"; }; }; + + nic-hsls { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x7fffffff>; + + nic_i2c0: i2c@60826100 { + compatible = "brcm,iproc-nic-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x60826100 0x100>, + <0x60e00408 0x1000>; + brcm,ape-hsls-addr-mask = <0x03400000>; + clock-frequency = <100000>; + status = "disabled"; + }; + }; };