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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org i.MX95 has a more precise counting capability than i.MX93. This will add a compatible for it. Signed-off-by: Xu Yang --- Documentation/devicetree/bindings/perf/fsl-imx-ddr.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/perf/fsl-imx-ddr.yaml b/Documentation/devicetree/bindings/perf/fsl-imx-ddr.yaml index e9fad4b3de68..1bc7bf1c8368 100644 --- a/Documentation/devicetree/bindings/perf/fsl-imx-ddr.yaml +++ b/Documentation/devicetree/bindings/perf/fsl-imx-ddr.yaml @@ -20,6 +20,7 @@ properties: - fsl,imx8mn-ddr-pmu - fsl,imx8mp-ddr-pmu - fsl,imx93-ddr-pmu + - fsl,imx95-ddr-pmu - items: - enum: - fsl,imx8mm-ddr-pmu From patchwork Mon Nov 27 07:32:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xu Yang X-Patchwork-Id: 13469254 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E2458C4167B for ; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: KlIFib8NZNPlTZXMKviYQ9lusyBN171RTSmB4jSQphkT5CWAbg7h9AyZCjgr+YJg+R8cWB4O7MWGc7HT6D0UfmQAaJ1kioQcBvX/iLEcdDmlG8AKcHMc8WaNltddTFSf3VsMDyU20QLZLVPNH0x0hdl9c1FXVGsvdgmzqeNRvJ+DHN1K63EkpD4De7o9/9CKxl2wYSYNFaPDOiw9Beog6XUZFFJoMmkwYVEp5V62NJRR/jnxv07lAaIoSZI0mkDhoNK9x4cBtBkOeUrYYBMRvAcB5Xt9lUn2c+USBOazYWNhOMqvNmDbm56SfEXSa3lcG5GKVQcj6nzUgpD6jL6Lj3qHj45zw9PZRSWo9eMMBJVQ4zNxdc4v/mxgL4qWO8BUI1ysZAGexD7t107txuZfeOjg/VvXm6n7h7Jzj9GlGbRvRgpHD5X1oxN+NIfH2j3dhuxLxA7v6+4UT9M/QOi9hUbz7xfGu1a954t5oiNARuVUhHV8ew8tno+SX3Lemx9vU1Ui1LFvwkHIfoF3/ijddK03xD6xM0i5DOrgH7iU2P8tRpFDf/NdfoRCNis5l7073d+YHzwrg97iKEifw7IQHceR+gpMZpRW3RaB5uLyXE8DjKDtww6v9ZFxUihO5epXahfcUtzbk292509lzUloyzcS3sob8xm5PS7Grvavm0foAtVquBPfgNLqCFkkB5HyVpCQaU5wEQNllZty8MXIQqg1/46Z4BvrnGyqGMNbCCmF4FiHl2mlqwkGIc76N8oWzbFA5LJHwtiomqqXiqLPj/PagtRyJPS4zBblk11smGZ4X6hE6R8f37pidrwV3OdaUJKVao70pNC2ed33G2HR9vFpiArcuC6dbjuSF2GFe12M9LfE8Z+d1KZp/N4fYwVNb9UZI7V2+yi8+tqdMQEioIwO900WgDsUvBtTYiO4jMNBquTCqfW6uPA2Vgevrz9Xavv8iPGrF8aCubS1+aKM9dklQYJqx7pqXmYR8SYAglh2mIlXc5tsZMEGi90Nw1sZQmEneXTN5fmgZA+vptYVFiA+7NtRrB58w7TuyKY2ZpDsq7RKQB//u/CmSLApNtTX4hNiirfUWG54/bd/0+96jsA/tvVc+Ws4v1W1cKBI6sr7NFoaQ4wdQBefrX+MzmE/1klCpQDmaMu1I6jVnCgxUu8taSft4+ItpqHBWml/QQ9cuYA4NLMzuiT6Zgf92dDFOxeJDDrCctXm2jKOq2KfTpM3bBj4JoBDgcazgCE5WAy3wG42jhKJptt0pt+bdmORQXwaP8sR13g4fK/Yj2hKHuBuWgf5j80oXO8Lq9oK+zwmFQTD7VEDzSDOl7EhkPpLi/R9xJDwIcwOBOjWP+XfrvlYiA01scMNFSPF1m/S2BZHqGGRctyOiQf9cplxIbbAyOVPzCJmo2EK5PPEQk27QWb8t0W872j68tI/G4uaiy6vsC4oNv1k5bBEL6H6NM3UDm5Npon72wUbfP5rl/YBOv9YLK/m0GpoYkhuNbkrtEtc4xhozhzRT+4yhifqiD+OUeyvxrbo1y1z8HU3wsRYY3427KoFOxdjATmQ00nJKDwfrBkb/5lacb2+VDhh2Cit X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: fea5c770-59b8-4051-c919-08dbef1a32c0 X-MS-Exchange-CrossTenant-AuthSource: DB7PR04MB5146.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Nov 2023 07:26:40.5639 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 0Uic+w5xftM1dvF8FlL0JAqPy3zRYFAiNmd3d6OaoCAe7jE8I4o1/40e2d0QVlH/jKFEgv3mPBZguo9+3+O83Q== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DUZPR04MB9871 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231126_234058_332982_E2D0844D X-CRM114-Status: GOOD ( 16.88 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org i.MX95 has a DDR PMU which is almostly same as i.MX93, it now supports read beat and write beat filter capabilities. This will add support for i.MX95 and enhance the driver to support specific filter handling for it. Usage: For read beat: ~# perf stat -a -I 1000 -e imx9_ddr0/eddrtq_pm_rd_beat_filt2,counter=3,axi_mask=ID_MASK,axi_id=ID/ ~# perf stat -a -I 1000 -e imx9_ddr0/eddrtq_pm_rd_beat_filt1,counter=4,axi_mask=ID_MASK,axi_id=ID/ ~# perf stat -a -I 1000 -e imx9_ddr0/eddrtq_pm_rd_beat_filt0,counter=5,axi_mask=ID_MASK,axi_id=ID/ eg: For edma2: perf stat -a -I 1000 -e imx9_ddr0/eddrtq_pm_rd_beat_filt0,counter=5,axi_mask=0x00f,axi_id=0x00c/ For write beat: ~# perf stat -a -I 1000 -e imx9_ddr0/eddrtq_pm_wr_beat_filt,counter=2,axi_mask=ID_MASK,axi_id=ID/ eg: For edma2: perf stat -a -I 1000 -e imx9_ddr0/eddrtq_pm_wr_beat_filt,counter=2,axi_mask=0x00f,axi_id=0x00c/ Signed-off-by: Xu Yang --- drivers/perf/fsl_imx9_ddr_perf.c | 187 +++++++++++++++++++++++++++---- 1 file changed, 164 insertions(+), 23 deletions(-) diff --git a/drivers/perf/fsl_imx9_ddr_perf.c b/drivers/perf/fsl_imx9_ddr_perf.c index 5cf770a1bc31..5e531d94cf3b 100644 --- a/drivers/perf/fsl_imx9_ddr_perf.c +++ b/drivers/perf/fsl_imx9_ddr_perf.c @@ -11,14 +11,24 @@ #include /* Performance monitor configuration */ -#define PMCFG1 0x00 -#define PMCFG1_RD_TRANS_FILT_EN BIT(31) -#define PMCFG1_WR_TRANS_FILT_EN BIT(30) -#define PMCFG1_RD_BT_FILT_EN BIT(29) -#define PMCFG1_ID_MASK GENMASK(17, 0) +#define PMCFG1 0x00 +#define MX93_PMCFG1_RD_TRANS_FILT_EN BIT(31) +#define MX93_PMCFG1_WR_TRANS_FILT_EN BIT(30) +#define MX93_PMCFG1_RD_BT_FILT_EN BIT(29) +#define MX93_PMCFG1_ID_MASK GENMASK(17, 0) -#define PMCFG2 0x04 -#define PMCFG2_ID GENMASK(17, 0) +#define MX95_PMCFG1_WR_BEAT_FILT_EN BIT(31) +#define MX95_PMCFG1_RD_BEAT_FILT_EN BIT(30) + +#define PMCFG2 0x04 +#define MX93_PMCFG2_ID GENMASK(17, 0) + +#define PMCFG3 0x08 +#define PMCFG4 0x0C +#define PMCFG5 0x10 +#define PMCFG6 0x14 +#define MX95_PMCFG_ID_MASK GENMASK(9, 0) +#define MX95_PMCFG_ID GENMASK(25, 16) /* Global control register affects all counters and takes priority over local control registers */ #define PMGC0 0x40 @@ -71,12 +81,22 @@ static const struct imx_ddr_devtype_data imx93_devtype_data = { .identifier = "imx93", }; +static const struct imx_ddr_devtype_data imx95_devtype_data = { + .identifier = "imx95", +}; + static const struct of_device_id imx_ddr_pmu_dt_ids[] = { {.compatible = "fsl,imx93-ddr-pmu", .data = &imx93_devtype_data}, + {.compatible = "fsl,imx95-ddr-pmu", .data = &imx95_devtype_data}, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, imx_ddr_pmu_dt_ids); +static inline bool is_imx93(struct ddr_pmu *pmu) +{ + return pmu->devtype_data == &imx93_devtype_data; +} + static ssize_t ddr_perf_identifier_show(struct device *dev, struct device_attribute *attr, char *page) @@ -178,7 +198,6 @@ static struct attribute *ddr_perf_events_attrs[] = { IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_6, 70), IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_7, 71), IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_empty, 72), - IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_trans_filt, 73), /* counter3 specific events */ IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_0, 64), @@ -190,7 +209,6 @@ static struct attribute *ddr_perf_events_attrs[] = { IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_6, 70), IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_7, 71), IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_full, 72), - IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_wr_trans_filt, 73), /* counter4 specific events */ IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_0, 64), @@ -202,7 +220,6 @@ static struct attribute *ddr_perf_events_attrs[] = { IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_6, 70), IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_7, 71), IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq2_rmw, 72), - IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt, 73), /* counter5 specific events */ IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_0, 64), @@ -242,6 +259,26 @@ static const struct attribute_group ddr_perf_events_attr_group = { .attrs = ddr_perf_events_attrs, }; +static struct attribute *imx93_ddr_perf_events_attrs[] = { + /* counter2 specific events */ + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_trans_filt, 73), + /* counter3 specific events */ + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_wr_trans_filt, 73), + /* counter4 specific events */ + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt, 73), +}; + +static struct attribute *imx95_ddr_perf_events_attrs[] = { + /* counter2 specific events */ + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_wr_beat_filt, 73), + /* counter3 specific events */ + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt2, 73), + /* counter4 specific events */ + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt1, 73), + /* counter5 specific events */ + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt0, 73), +}; + PMU_FORMAT_ATTR(event, "config:0-7"); PMU_FORMAT_ATTR(counter, "config:8-15"); PMU_FORMAT_ATTR(axi_id, "config1:0-17"); @@ -361,7 +398,7 @@ static void ddr_perf_counter_local_config(struct ddr_pmu *pmu, int config, } } -static void ddr_perf_monitor_config(struct ddr_pmu *pmu, int cfg, int cfg1, int cfg2) +static void imx93_ddr_perf_monitor_config(struct ddr_pmu *pmu, int cfg, int cfg1, int cfg2) { u32 pmcfg1, pmcfg2; int event, counter; @@ -372,30 +409,80 @@ static void ddr_perf_monitor_config(struct ddr_pmu *pmu, int cfg, int cfg1, int pmcfg1 = readl_relaxed(pmu->base + PMCFG1); if (counter == 2 && event == 73) - pmcfg1 |= PMCFG1_RD_TRANS_FILT_EN; + pmcfg1 |= MX93_PMCFG1_RD_TRANS_FILT_EN; else if (counter == 2 && event != 73) - pmcfg1 &= ~PMCFG1_RD_TRANS_FILT_EN; + pmcfg1 &= ~MX93_PMCFG1_RD_TRANS_FILT_EN; if (counter == 3 && event == 73) - pmcfg1 |= PMCFG1_WR_TRANS_FILT_EN; + pmcfg1 |= MX93_PMCFG1_WR_TRANS_FILT_EN; else if (counter == 3 && event != 73) - pmcfg1 &= ~PMCFG1_WR_TRANS_FILT_EN; + pmcfg1 &= ~MX93_PMCFG1_WR_TRANS_FILT_EN; if (counter == 4 && event == 73) - pmcfg1 |= PMCFG1_RD_BT_FILT_EN; + pmcfg1 |= MX93_PMCFG1_RD_BT_FILT_EN; else if (counter == 4 && event != 73) - pmcfg1 &= ~PMCFG1_RD_BT_FILT_EN; + pmcfg1 &= ~MX93_PMCFG1_RD_BT_FILT_EN; - pmcfg1 &= ~FIELD_PREP(PMCFG1_ID_MASK, 0x3FFFF); - pmcfg1 |= FIELD_PREP(PMCFG1_ID_MASK, cfg2); + pmcfg1 &= ~FIELD_PREP(MX93_PMCFG1_ID_MASK, 0x3FFFF); + pmcfg1 |= FIELD_PREP(MX93_PMCFG1_ID_MASK, cfg2); writel(pmcfg1, pmu->base + PMCFG1); pmcfg2 = readl_relaxed(pmu->base + PMCFG2); - pmcfg2 &= ~FIELD_PREP(PMCFG2_ID, 0x3FFFF); - pmcfg2 |= FIELD_PREP(PMCFG2_ID, cfg1); + pmcfg2 &= ~FIELD_PREP(MX93_PMCFG2_ID, 0x3FFFF); + pmcfg2 |= FIELD_PREP(MX93_PMCFG2_ID, cfg1); writel(pmcfg2, pmu->base + PMCFG2); } +static void imx95_ddr_perf_monitor_config(struct ddr_pmu *pmu, int cfg, int cfg1, int cfg2) +{ + u32 pmcfg1, pmcfg, offset = 0; + int event, counter; + + event = cfg & 0x000000FF; + counter = (cfg & 0x0000FF00) >> 8; + + pmcfg1 = readl_relaxed(pmu->base + PMCFG1); + + if (counter == 2 && event == 73) { + pmcfg1 |= MX95_PMCFG1_WR_BEAT_FILT_EN; + offset = PMCFG3; + } else if (counter == 2 && event != 73) { + pmcfg1 &= ~MX95_PMCFG1_WR_BEAT_FILT_EN; + } + + if (counter == 3 && event == 73) { + pmcfg1 |= MX95_PMCFG1_RD_BEAT_FILT_EN; + offset = PMCFG4; + } else if (counter == 3 && event != 73) { + pmcfg1 &= ~MX95_PMCFG1_RD_BEAT_FILT_EN; + } + + if (counter == 4 && event == 73) { + pmcfg1 |= MX95_PMCFG1_RD_BEAT_FILT_EN; + offset = PMCFG5; + } else if (counter == 4 && event != 73) { + pmcfg1 &= ~MX95_PMCFG1_RD_BEAT_FILT_EN; + } + + if (counter == 5 && event == 73) { + pmcfg1 |= MX95_PMCFG1_RD_BEAT_FILT_EN; + offset = PMCFG6; + } else if (counter == 5 && event != 73) { + pmcfg1 &= ~MX95_PMCFG1_RD_BEAT_FILT_EN; + } + + writel(pmcfg1, pmu->base + PMCFG1); + + if (offset) { + pmcfg = readl_relaxed(pmu->base + offset); + pmcfg &= ~FIELD_PREP(MX95_PMCFG_ID_MASK, 0x3FF); + pmcfg |= FIELD_PREP(MX95_PMCFG_ID_MASK, cfg2); + pmcfg &= ~FIELD_PREP(MX95_PMCFG_ID, 0x3FF); + pmcfg |= FIELD_PREP(MX95_PMCFG_ID, cfg1); + writel(pmcfg, pmu->base + offset); + } +} + static void ddr_perf_event_update(struct perf_event *event) { struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); @@ -479,8 +566,13 @@ static int ddr_perf_event_add(struct perf_event *event, int flags) if (flags & PERF_EF_START) ddr_perf_event_start(event, flags); - /* read trans, write trans, read beat */ - ddr_perf_monitor_config(pmu, cfg, cfg1, cfg2); + if (is_imx93(pmu)) { + /* read trans, write trans, read beat */ + imx93_ddr_perf_monitor_config(pmu, cfg, cfg1, cfg2); + } else { + /* write beat, read beat2, read beat1, read beat */ + imx95_ddr_perf_monitor_config(pmu, cfg, cfg1, cfg2); + } return 0; } @@ -596,6 +688,49 @@ static int ddr_perf_offline_cpu(unsigned int cpu, struct hlist_node *node) return 0; } +static int ddr_perf_add_events(struct ddr_pmu *pmu) +{ + int i, ret, events; + struct attribute **attrs; + struct device *pmu_dev = pmu->pmu.dev; + + if (is_imx93(pmu)) { + events = sizeof(imx93_ddr_perf_events_attrs)/sizeof(struct attribute *); + attrs = imx93_ddr_perf_events_attrs; + } else { + events = sizeof(imx95_ddr_perf_events_attrs)/sizeof(struct attribute *); + attrs = imx95_ddr_perf_events_attrs; + } + + for (i = 0; i < events; i++) { + ret = sysfs_add_file_to_group(&pmu_dev->kobj, attrs[i], "events"); + if (ret) { + dev_warn(pmu->dev, "i.MX9 DDR Perf add events failed (%d)\n", ret); + return ret; + } + } + + return 0; +} + +static void ddr_perf_remove_events(struct ddr_pmu *pmu) +{ + int i, events; + struct attribute **attrs; + struct device *pmu_dev = pmu->pmu.dev; + + if (is_imx93(pmu)) { + events = sizeof(imx93_ddr_perf_events_attrs)/sizeof(struct attribute *); + attrs = imx93_ddr_perf_events_attrs; + } else { + events = sizeof(imx95_ddr_perf_events_attrs)/sizeof(struct attribute *); + attrs = imx95_ddr_perf_events_attrs; + } + + for (i = 0; i < events; i++) + sysfs_remove_file_from_group(&pmu_dev->kobj, attrs[i], "events"); +} + static int ddr_perf_probe(struct platform_device *pdev) { struct ddr_pmu *pmu; @@ -666,6 +801,10 @@ static int ddr_perf_probe(struct platform_device *pdev) if (ret) goto ddr_perf_err; + ret = ddr_perf_add_events(pmu); + if (ret) + dev_warn(&pdev->dev, "i.MX9 DDR Perf filter events are missing\n"); + return 0; ddr_perf_err: @@ -683,6 +822,8 @@ static int ddr_perf_remove(struct platform_device *pdev) { struct ddr_pmu *pmu = platform_get_drvdata(pdev); + ddr_perf_remove_events(pmu); + cpuhp_state_remove_instance_nocalls(pmu->cpuhp_state, &pmu->node); cpuhp_remove_multi_state(pmu->cpuhp_state); From patchwork Mon Nov 27 07:32:08 2023 Content-Type: text/plain; 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Signed-off-by: Xu Yang --- .../arch/arm64/freescale/imx95/sys/ddrc.json | 9 + .../arm64/freescale/imx95/sys/metrics.json | 1098 +++++++++++++++++ tools/perf/pmu-events/jevents.py | 1 + 3 files changed, 1108 insertions(+) create mode 100644 tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/ddrc.json create mode 100644 tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/metrics.json diff --git a/tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/ddrc.json b/tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/ddrc.json new file mode 100644 index 000000000000..4dc9d2968bdc --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/ddrc.json @@ -0,0 +1,9 @@ +[ + { + "BriefDescription": "ddr cycles event", + "EventCode": "0x00", + "EventName": "imx95_ddr.cycles", + "Unit": "imx9_ddr", + "Compat": "imx95" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/metrics.json b/tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/metrics.json new file mode 100644 index 000000000000..629b9bae5d46 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/metrics.json @@ -0,0 +1,1098 @@ +[ + { + "BriefDescription": "bytes of all masters read from ddr", + "MetricName": "imx95_ddr_read.all", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x000\\,axi_id\\=0x000@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of all masters write to ddr", + "MetricName": "imx95_ddr_write.all", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x000\\,axi_id\\=0x000@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of all a55 read from ddr", + "MetricName": "imx95_ddr_read.a55_all", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x3fc\\,axi_id\\=0x000@ + imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,counter\\=4\\,axi_mask\\=0x3fe\\,axi_id\\=0x004@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of a55 core 0 read from ddr", + "MetricName": "imx95_ddr_read.a55_0", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x00f\\,axi_id\\=0x000@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of a55 core 0 write to ddr", + "MetricName": "imx95_ddr_write.a55_0", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x00f\\,axi_id\\=0x000@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of a55 core 1 read from ddr", + "MetricName": "imx95_ddr_read.a55_1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x00f\\,axi_id\\=0x001@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of a55 core 1 write to ddr", + "MetricName": "imx95_ddr_write.a55_1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x00f\\,axi_id\\=0x001@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of a55 core 2 read from ddr", + "MetricName": "imx95_ddr_read.a55_2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x00f\\,axi_id\\=0x002@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of a55 core 2 write to ddr", + "MetricName": "imx95_ddr_write.a55_2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x00f\\,axi_id\\=0x002@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of a55 core 3 read from ddr", + "MetricName": "imx95_ddr_read.a55_3", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x00f\\,axi_id\\=0x003@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of a55 core 3 write to ddr", + "MetricName": "imx95_ddr_write.a55_3", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x00f\\,axi_id\\=0x003@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of a55 core 4 read from ddr", + "MetricName": "imx95_ddr_read.a55_4", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x00f\\,axi_id\\=0x004@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of a55 core 4 write to ddr", + "MetricName": "imx95_ddr_write.a55_4", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x00f\\,axi_id\\=0x004@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of a55 core 5 read from ddr", + "MetricName": "imx95_ddr_read.a55_5", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x00f\\,axi_id\\=0x005@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of a55 core 5 write to ddr", + "MetricName": "imx95_ddr_write.a55_5", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x00f\\,axi_id\\=0x005@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of Cortex-A DSU L3 evicted/ACP transactions read from ddr", + "MetricName": "imx95_ddr_read.cortexa_dsu_l3", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x00f\\,axi_id\\=0x00F@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of Cortex-A DSU L3 evicted/ACP transactions write to ddr", + "MetricName": "imx95_ddr_write.cortexa_dsu_l3", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x00f\\,axi_id\\=0x00F@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of m33 read from ddr", + "MetricName": "imx95_ddr_read.m33", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x00f\\,axi_id\\=0x008@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of m33 write to ddr", + "MetricName": "imx95_ddr_write.m33", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x00f\\,axi_id\\=0x008@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of m7 read from ddr", + "MetricName": "imx95_ddr_read.m7", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x00f\\,axi_id\\=0x009@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of m7 write to ddr", + "MetricName": "imx95_ddr_write.m7", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x00f\\,axi_id\\=0x009@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of sentinel read from ddr", + "MetricName": "imx95_ddr_read.sentinel", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x00f\\,axi_id\\=0x00a@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of sentinel write to ddr", + "MetricName": "imx95_ddr_write.sentinel", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x00f\\,axi_id\\=0x00a@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of edma1 read from ddr", + "MetricName": "imx95_ddr_read.edma1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x00f\\,axi_id\\=0x00b@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of edma1 write to ddr", + "MetricName": "imx95_ddr_write.edma1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x00f\\,axi_id\\=0x00b@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of edma2 read from ddr", + "MetricName": "imx95_ddr_read.edma2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x00f\\,axi_id\\=0x00c@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of edma2 write to ddr", + "MetricName": "imx95_ddr_write.edma2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x00f\\,axi_id\\=0x00c@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of netc read from ddr", + "MetricName": "imx95_ddr_read.netc", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x00f\\,axi_id\\=0x00d@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of netc write to ddr", + "MetricName": "imx95_ddr_write.netc", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x00f\\,axi_id\\=0x00d@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of v2x-fh read from ddr", + "MetricName": "imx95_ddr_read.v2x-fh", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x00f\\,axi_id\\=0x00e@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of v2x-fh write to ddr", + "MetricName": "imx95_ddr_write.v2x-fh", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x00f\\,axi_id\\=0x00e@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of mtr(aonmix) read from ddr", + "MetricName": "imx95_ddr_read.mtr", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x00f\\,axi_id\\=0x00f@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of mtr(aonmix) write to ddr", + "MetricName": "imx95_ddr_write.mtr", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x00f\\,axi_id\\=0x00f@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of npu read from ddr", + "MetricName": "imx95_ddr_read.npu", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x03f\\,axi_id\\=0x010@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of npu write to ddr", + "MetricName": "imx95_ddr_write.npu", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x03f\\,axi_id\\=0x010@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of gpu read from ddr", + "MetricName": "imx95_ddr_read.gpu", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x03f\\,axi_id\\=0x020@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of gpu write to ddr", + "MetricName": "imx95_ddr_write.gpu", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x03f\\,axi_id\\=0x020@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of caam read from ddr", + "MetricName": "imx95_ddr_read.caam", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x03f\\,axi_id\\=0x030@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of caam write to ddr", + "MetricName": "imx95_ddr_write.caam", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x03f\\,axi_id\\=0x030@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of coresignt read from ddr", + "MetricName": "imx95_ddr_read.coresignt", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x03f\\,axi_id\\=0x080@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of coresignt write to ddr", + "MetricName": "imx95_ddr_write.coresignt", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x03f\\,axi_id\\=0x080@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of dap ahb-ap read from ddr", + "MetricName": "imx95_ddr_read.dap", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x03f\\,axi_id\\=0x090@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of dap ahb-ap write to ddr", + "MetricName": "imx95_ddr_write.dap", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x03f\\,axi_id\\=0x090@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of test port read from ddr", + "MetricName": "imx95_ddr_read.test_port", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x03f\\,axi_id\\=0x0a0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of test port write to ddr", + "MetricName": "imx95_ddr_write.test_port", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x03f\\,axi_id\\=0x0a0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of usdhc1 read from ddr", + "MetricName": "imx95_ddr_read.usdhc1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x03f\\,axi_id\\=0x0b0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of usdhc1 write to ddr", + "MetricName": "imx95_ddr_write.usdhc1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x03f\\,axi_id\\=0x0b0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of usdhc2 read from ddr", + "MetricName": "imx95_ddr_read.usdhc2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x03f\\,axi_id\\=0x0c0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of usdhc2 write to ddr", + "MetricName": "imx95_ddr_write.usdhc2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x03f\\,axi_id\\=0x0c0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of usdhc3 read from ddr", + "MetricName": "imx95_ddr_read.usdhc3", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x03f\\,axi_id\\=0x0d0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of usdhc3 write to ddr", + "MetricName": "imx95_ddr_write.usdhc3", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x03f\\,axi_id\\=0x0d0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of v2h-fx read from ddr", + "MetricName": "imx95_ddr_read.v2h-fx", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x03f\\,axi_id\\=0x0e0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of v2h-fx write to ddr", + "MetricName": "imx95_ddr_write.v2h-fx", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x03f\\,axi_id\\=0x0e0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of xspi read from ddr", + "MetricName": "imx95_ddr_read.xspi", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x03f\\,axi_id\\=0x0f0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of xspi write to ddr", + "MetricName": "imx95_ddr_write.xspi", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x03f\\,axi_id\\=0x0f0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of pcie1 read from ddr", + "MetricName": "imx95_ddr_read.pcie1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x03f\\,axi_id\\=0x100@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of pcie1 write to ddr", + "MetricName": "imx95_ddr_write.pcie1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x03f\\,axi_id\\=0x100@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of pcie2 read from ddr", + "MetricName": "imx95_ddr_read.pcie2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x00f\\,axi_id\\=0x006@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of pcie2 write to ddr", + "MetricName": "imx95_ddr_write.pcie2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x00f\\,axi_id\\=0x006@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of pcie3 read from ddr", + "MetricName": "imx95_ddr_read.pcie3", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x03f\\,axi_id\\=0x120@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of pcie3 write to ddr", + "MetricName": "imx95_ddr_write.pcie3", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x03f\\,axi_id\\=0x120@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of pcie4 read from ddr", + "MetricName": "imx95_ddr_read.pcie4", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x03f\\,axi_id\\=0x130@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of pcie4 write to ddr", + "MetricName": "imx95_ddr_write.pcie4", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x03f\\,axi_id\\=0x130@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of usb1 read from ddr", + "MetricName": "imx95_ddr_read.usb1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x03f\\,axi_id\\=0x140@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of usb1 write to ddr", + "MetricName": "imx95_ddr_write.usb1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x03f\\,axi_id\\=0x140@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of usb2 read from ddr", + "MetricName": "imx95_ddr_read.usb2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x03f\\,axi_id\\=0x150@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of usb2 write to ddr", + "MetricName": "imx95_ddr_write.usb2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x03f\\,axi_id\\=0x150@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of vpu codec primary bus read from ddr", + "MetricName": "imx95_ddr_read.vpu_primy", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x03f\\,axi_id\\=0x180@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of vpu codec primary bus write to ddr", + "MetricName": "imx95_ddr_write.vpu_primy", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x03f\\,axi_id\\=0x180@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of vpu codec secondary bus read from ddr", + "MetricName": "imx95_ddr_read.vpu_secndy", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x03f\\,axi_id\\=0x190@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of vpu codec secondary bus write to ddr", + "MetricName": "imx95_ddr_write.vpu_secndy", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x03f\\,axi_id\\=0x190@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of jpeg decoder read from ddr", + "MetricName": "imx95_ddr_read.jpeg_dec", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x03f\\,axi_id\\=0x1a0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of jpeg decoder write to ddr", + "MetricName": "imx95_ddr_write.jpeg_dec", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x03f\\,axi_id\\=0x1a0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of jpeg encoder read from ddr", + "MetricName": "imx95_ddr_read.jpeg_dec", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x03f\\,axi_id\\=0x1b0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of jpeg encoder write to ddr", + "MetricName": "imx95_ddr_write.jpeg_enc", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x03f\\,axi_id\\=0x1b0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of hifi dsp read from ddr", + "MetricName": "imx95_ddr_read.hifi_dsp", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x03f\\,axi_id\\=0x1c0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of hifi dsp write to ddr", + "MetricName": "imx95_ddr_write.hifi_dsp", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x03f\\,axi_id\\=0x1c0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of cortex m0+ read from ddr", + "MetricName": "imx95_ddr_read.m0", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x03f\\,axi_id\\=0x200@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of cortex m0+ write to ddr", + "MetricName": "imx95_ddr_write.m0", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x03f\\,axi_id\\=0x200@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of camera edma read from ddr", + "MetricName": "imx95_ddr_read.camera_edma", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x03f\\,axi_id\\=0x210@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of camera edma write to ddr", + "MetricName": "imx95_ddr_write.camera_edma", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x03f\\,axi_id\\=0x210@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isi rd read from ddr", + "MetricName": "imx95_ddr_read.isi_rd", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x03f\\,axi_id\\=0x220@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isi rd write to ddr", + "MetricName": "imx95_ddr_write.isi_rd", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x03f\\,axi_id\\=0x220@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isi wr y read from ddr", + "MetricName": "imx95_ddr_read.isi_wr_y", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x03f\\,axi_id\\=0x230@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isi wr y write to ddr", + "MetricName": "imx95_ddr_write.isi_wr_y", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x03f\\,axi_id\\=0x230@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isi wr u read from ddr", + "MetricName": "imx95_ddr_read.isi_wr_u", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x03f\\,axi_id\\=0x240@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isi wr u write to ddr", + "MetricName": "imx95_ddr_write.isi_wr_u", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x03f\\,axi_id\\=0x240@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isi wr v read from ddr", + "MetricName": "imx95_ddr_read.isi_wr_v", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x03f\\,axi_id\\=0x250@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isi wr v write to ddr", + "MetricName": "imx95_ddr_write.isi_wr_v", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x03f\\,axi_id\\=0x250@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isp input dma1 read from ddr", + "MetricName": "imx95_ddr_read.isp_in_dma1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x03f\\,axi_id\\=0x260@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isp input dma1 write to ddr", + "MetricName": "imx95_ddr_write.isp_in_dma1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x03f\\,axi_id\\=0x260@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isp input dma2 read from ddr", + "MetricName": "imx95_ddr_read.isp_in_dma2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x03f\\,axi_id\\=0x270@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isp input dma2 write to ddr", + "MetricName": "imx95_ddr_write.isp_in_dma2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x03f\\,axi_id\\=0x270@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isp output dma1 read from ddr", + "MetricName": "imx95_ddr_read.isp_out_dma1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x03f\\,axi_id\\=0x280@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isp output dma1 write to ddr", + "MetricName": "imx95_ddr_write.isp_out_dma1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x03f\\,axi_id\\=0x280@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isp output dma2 read from ddr", + "MetricName": "imx95_ddr_read.isp_out_dma2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x03f\\,axi_id\\=0x290@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isp output dma2 write to ddr", + "MetricName": "imx95_ddr_write.isp_out_dma2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x03f\\,axi_id\\=0x290@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of display blitter store read from ddr", + "MetricName": "imx95_ddr_read.disp_blit", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x03f\\,axi_id\\=0x2a0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of display blitter write to ddr", + "MetricName": "imx95_ddr_write.disp_blit", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x03f\\,axi_id\\=0x2a0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of display command sequencer read from ddr", + "MetricName": "imx95_ddr_read.disp_cmd", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x03f\\,axi_id\\=0x2b0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of display command sequencer write to ddr", + "MetricName": "imx95_ddr_write.disp_cmd", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x03f\\,axi_id\\=0x2b0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of display usb3.1 read from ddr", + "MetricName": "imx95_ddr_read.disp_usb3", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x03f\\,axi_id\\=0x2c0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of display usb3.1 write to ddr", + "MetricName": "imx95_ddr_write.disp_usb3", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x03f\\,axi_id\\=0x2c0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of fu initiator 1 read from ddr", + "MetricName": "imx95_ddr_read.fu_init1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x03f\\,axi_id\\=0x2f0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of initiator 1 write to ddr", + "MetricName": "imx95_ddr_write.fu_init1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x03f\\,axi_id\\=0x2f0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of fu initiator 2 read from ddr", + "MetricName": "imx95_ddr_read.fu_init2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x03f\\,axi_id\\=0x300@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of initiator 2 write to ddr", + "MetricName": "imx95_ddr_write.fu_init2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x03f\\,axi_id\\=0x300@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of fu initiator 3 read from ddr", + "MetricName": "imx95_ddr_read.fu_init3", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x03f\\,axi_id\\=0x310@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of initiator 3 write to ddr", + "MetricName": "imx95_ddr_write.fu_init3", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x03f\\,axi_id\\=0x310@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of fu initiator 4 read from ddr", + "MetricName": "imx95_ddr_read.fu_init4", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x03f\\,axi_id\\=0x320@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of initiator 4 write to ddr", + "MetricName": "imx95_ddr_write.fu_init4", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x03f\\,axi_id\\=0x320@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of fu initiator 5 read from ddr", + "MetricName": "imx95_ddr_read.fu_init5", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x03f\\,axi_id\\=0x330@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of initiator 5 write to ddr", + "MetricName": "imx95_ddr_write.fu_init5", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x03f\\,axi_id\\=0x330@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of fu initiator 6 read from ddr", + "MetricName": "imx95_ddr_read.fu_init6", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x03f\\,axi_id\\=0x340@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of initiator 6 write to ddr", + "MetricName": "imx95_ddr_write.fu_init6", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x03f\\,axi_id\\=0x340@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of fu initiator 7 read from ddr", + "MetricName": "imx95_ddr_read.fu_init7", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x03f\\,axi_id\\=0x350@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of initiator 7 write to ddr", + "MetricName": "imx95_ddr_write.fu_init7", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x03f\\,axi_id\\=0x350@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of fu initiator 8 read from ddr", + "MetricName": "imx95_ddr_read.fu_init8", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x03f\\,axi_id\\=0x360@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of initiator 8 write to ddr", + "MetricName": "imx95_ddr_write.fu_init8", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x03f\\,axi_id\\=0x360@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of fu initiator 9 read from ddr", + "MetricName": "imx95_ddr_read.fu_init9", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x03f\\,axi_id\\=0x370@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of initiator 9 write to ddr", + "MetricName": "imx95_ddr_write.fu_init9", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x03f\\,axi_id\\=0x370@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of fu initiator 10 read from ddr", + "MetricName": "imx95_ddr_read.fu_init10", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x03f\\,axi_id\\=0x380@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of initiator 10 write to ddr", + "MetricName": "imx95_ddr_write.fu_init10", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x03f\\,axi_id\\=0x380@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of fu initiator 11 read from ddr", + "MetricName": "imx95_ddr_read.fu_init11", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x03f\\,axi_id\\=0x390@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of initiator 11 write to ddr", + "MetricName": "imx95_ddr_write.fu_init11", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x03f\\,axi_id\\=0x390@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of fu initiator 12 read from ddr", + "MetricName": "imx95_ddr_read.fu_init12", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x03f\\,axi_id\\=0x3a0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of initiator 12 write to ddr", + "MetricName": "imx95_ddr_write.fu_init12", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x03f\\,axi_id\\=0x3a0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of fu initiator 13 read from ddr", + "MetricName": "imx95_ddr_read.fu_init13", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x03f\\,axi_id\\=0x3b0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of initiator 13 write to ddr", + "MetricName": "imx95_ddr_write.fu_init13", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x03f\\,axi_id\\=0x3b0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of fu initiator 14 read from ddr", + "MetricName": "imx95_ddr_read.fu_init14", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x03f\\,axi_id\\=0x3c0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of initiator 14 write to ddr", + "MetricName": "imx95_ddr_write.fu_init14", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x03f\\,axi_id\\=0x3c0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of fu initiator 15 read from ddr", + "MetricName": "imx95_ddr_read.fu_init15", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x03f\\,axi_id\\=0x3d0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of initiator 15 write to ddr", + "MetricName": "imx95_ddr_write.fu_init15", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x03f\\,axi_id\\=0x3d0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of fu initiator 16 read from ddr", + "MetricName": "imx95_ddr_read.fu_init16", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x03f\\,axi_id\\=0x3e0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of initiator 16 write to ddr", + "MetricName": "imx95_ddr_write.fu_init16", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x03f\\,axi_id\\=0x3e0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of fu initiator 17 read from ddr", + "MetricName": "imx95_ddr_read.fu_init17", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x03f\\,axi_id\\=0x3f0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of initiator 17 write to ddr", + "MetricName": "imx95_ddr_write.fu_init17", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x03f\\,axi_id\\=0x3f0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + } +] diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jevents.py index 3c091ab75305..89652b32fdec 100755 --- a/tools/perf/pmu-events/jevents.py +++ b/tools/perf/pmu-events/jevents.py @@ -284,6 +284,7 @@ class JsonEvent: 'hisi_sccl,hha': 'hisi_sccl,hha', 'hisi_sccl,l3c': 'hisi_sccl,l3c', 'imx8_ddr': 'imx8_ddr', + 'imx9_ddr': 'imx9_ddr', 'L3PMC': 'amd_l3', 'DFPMC': 'amd_df', 'cpu_core': 'cpu_core',