From patchwork Mon Nov 27 15:52:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13469881 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="OhfiMbAS" Received: from mail-ej1-x62e.google.com (mail-ej1-x62e.google.com [IPv6:2a00:1450:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 476D7D4C for ; Mon, 27 Nov 2023 07:52:33 -0800 (PST) Received: by mail-ej1-x62e.google.com with SMTP id a640c23a62f3a-a00b01955acso631021866b.1 for ; Mon, 27 Nov 2023 07:52:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1701100351; x=1701705151; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=47QyN1mARPQG0EF8lxrYb1VJmjeAmYEb6KvC/0GnTPA=; b=OhfiMbASj2LyZHj2bFCrD9V0OopmoIztmDEcoF4UGiolgSC8/XEo21WgQkyx59VRUs 4W0PkZzP+e0vwsXe1+ru9QnPA0J+oH/lKwRHH5e+FfIh16JeVJWgYlaCsBP9BMHvIU8M L8icG/i42Yc3jfBLFg0oYwItJYAOczt0m2hYPPV2WxQ8t/OQf2hoO26zudVh0O4PMoe4 5e0OBEYUjvE6su19SQmrhcSJRxs0My+Oa397zeeBwBRDFU/xyN5qh27BlrtJk2JxbYQb SL/fqF+CgsIrx1nQ5cYzS/mQuadoBi0N+YJt95tVgSAwqY0CyTdcjEqJmx97AboZfyf1 rGaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701100351; x=1701705151; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=47QyN1mARPQG0EF8lxrYb1VJmjeAmYEb6KvC/0GnTPA=; b=XnTHL51eUAaovfifl5a/oPNfMQ49Wp3TNtuWPZ4srkXHtk3OIz7jfrWE8SG/u9m0uF s20X2NMQQDXMPetN4aveEgF+1Rzkxk2sMaTZsaqnO8imH2co3XNB/deLF+5H+EnUe2WV Ca+AMHXKopm47wtT8HMOr0sRTeWtXfylz3hbQe5P/PWM6OHX0YivVgMlY9NTgHqXKwd4 IbVMG01Mm+o01f1Wluagv+Zre3ParPEMGH+/xa+CF3omOUMuXkVaWhNovU9YDm0+4XBn rKlGABb9LPfDDO0+zQ0tdpe8y6SIvn9YGGj+mUwX7qiiFmlM+EMVJOM/nXpLVx9Iq8PP 8bSw== X-Gm-Message-State: AOJu0YwsiUqoNBnGkTrpRTCOX1MlDHCNbHebtM+vPTFhGF+piwJEOmCn 9s8T93i3v+auxmbtpulcGtL0ubKAqM7tGPLEIrw= X-Google-Smtp-Source: AGHT+IHlI+2GyN+pTXPLUIHl82AsYDnLdrlfx6uE0wlcWEcsj6YRdcmqrTlbA7tiW0BFKy303dKM8g== X-Received: by 2002:a17:906:2c4c:b0:a04:bd7c:b7f7 with SMTP id f12-20020a1709062c4c00b00a04bd7cb7f7mr8818684ejh.64.1701100351376; Mon, 27 Nov 2023 07:52:31 -0800 (PST) Received: from [10.167.154.1] (178235187180.dynamic-4-waw-k-2-3-0.vectranet.pl. [178.235.187.180]) by smtp.gmail.com with ESMTPSA id mb22-20020a170906eb1600b009fc0c42098csm5855150ejb.173.2023.11.27.07.52.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Nov 2023 07:52:31 -0800 (PST) From: Konrad Dybcio Date: Mon, 27 Nov 2023 16:52:12 +0100 Subject: [PATCH v7 1/2] dt-bindings: interrupt-controller: mpm: Pass MSG RAM slice through phandle Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20230328-topic-msgram_mpm-v7-1-6ee2bfeaac2c@linaro.org> References: <20230328-topic-msgram_mpm-v7-0-6ee2bfeaac2c@linaro.org> In-Reply-To: <20230328-topic-msgram_mpm-v7-0-6ee2bfeaac2c@linaro.org> To: Andy Gross , Bjorn Andersson , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Shawn Guo , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio , Krzysztof Kozlowski X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1701100347; l=3285; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=UnAJ2EWA9JR18tWPDeobMem6WcpQTcTZkHcMBc8DA5o=; b=6hyNFuljkC0LUFiRqT23DUyz8Mhfre8bXxB7IXiD5VbX/ZqGXggcwRPETj6PbbKE0naEU5tQV pzzAeZ5fIZVC3JF8oeSLTD8o3hEgLRxtDLGu96oOQmgRNVbwiEa7YTR X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Due to the wild nature of the Qualcomm RPM Message RAM, we can't really use 'reg' to point to the MPM's slice of Message RAM without cutting into an already-defined RPM MSG RAM node used for GLINK and SMEM. Document passing the register space as a slice of SRAM through the qcom,rpm-msg-ram property. This also makes 'reg' deprecated. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio --- .../bindings/interrupt-controller/qcom,mpm.yaml | 52 +++++++++++++++------- 1 file changed, 35 insertions(+), 17 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml index 509d20c091af..4ce7912d8047 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml @@ -29,6 +29,12 @@ properties: maxItems: 1 description: Specifies the base address and size of vMPM registers in RPM MSG RAM. + deprecated: true + + qcom,rpm-msg-ram: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the APSS MPM slice of the RPM Message RAM interrupts: maxItems: 1 @@ -64,33 +70,45 @@ properties: required: - compatible - - reg - interrupts - mboxes - interrupt-controller - '#interrupt-cells' - qcom,mpm-pin-count - qcom,mpm-pin-map + - qcom,rpm-msg-ram additionalProperties: false examples: - | #include - mpm: interrupt-controller@45f01b8 { - compatible = "qcom,mpm"; - interrupts = ; - reg = <0x45f01b8 0x1000>; - mboxes = <&apcs_glb 1>; - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - qcom,mpm-pin-count = <96>; - qcom,mpm-pin-map = <2 275>, - <5 296>, - <12 422>, - <24 79>, - <86 183>, - <90 260>, - <91 260>; + + remoteproc-rpm { + compatible = "qcom,msm8998-rpm-proc", "qcom,rpm-proc"; + + glink-edge { + compatible = "qcom,glink-rpm"; + + interrupts = ; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&apcs_glb 0>; + }; + + mpm: interrupt-controller { + compatible = "qcom,mpm"; + qcom,rpm-msg-ram = <&apss_mpm>; + interrupts = ; + mboxes = <&apcs_glb 1>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + qcom,mpm-pin-count = <96>; + qcom,mpm-pin-map = <2 275>, + <5 296>, + <12 422>, + <24 79>, + <86 183>, + <91 260>; + }; }; From patchwork Mon Nov 27 15:52:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13469882 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="hEJ9T6vl" Received: from mail-ej1-x62a.google.com (mail-ej1-x62a.google.com [IPv6:2a00:1450:4864:20::62a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F04C6D5A for ; Mon, 27 Nov 2023 07:52:34 -0800 (PST) Received: by mail-ej1-x62a.google.com with SMTP id a640c23a62f3a-a00c200782dso642615766b.1 for ; Mon, 27 Nov 2023 07:52:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1701100353; x=1701705153; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Nr05hrGkuwY0DK8aGF98uretWKGuiZWVGVkXoVNznFQ=; b=hEJ9T6vlLFeLoKzEN9giyFjhRxFnttJoX9wqPfCkc4i35yb9e0C34LSYvT1XwY1CP8 /Qch3PeMq6QYMqgCvqxPfDaFirpq+p6pQq+1RjYwAsWRC0qjf3YJ2VWlpsu1ULe4TXsV gdy7OJANGa+7/iggFyg8oq18s6WLgmSp2meivvwUtfSVKWHCOrOY1/kpOIqDTr1bgfRB HiAMH3JWEnBKqYr0exaDmLyhWCzWpV67G7tZBQ4e2EYTj0SN7R5mMGfdEA0Zs/ViKSuG H7YAGfgGXxEJRmNPGp4peaJah6PlQNTQQ2jXNFbMrBjkE168vpzJypSVEKf5mvzY+WFz L0Hg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701100353; x=1701705153; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Nr05hrGkuwY0DK8aGF98uretWKGuiZWVGVkXoVNznFQ=; b=gXflmDmfYTkKe93v+iJOagezaWDh4gRVQkHoQsq6v/RI0yiLa4HRysm2h3vkTbdldS B6fc6c8U70DOnkL395fyj/YEfiwYyqucccOySXN0WyQdYrYWug/GSwOGe85DSDa/Njxn V4OU0qBJxHVr9r3ov05RXt5wUpKSK+dcKqu8Nv4p5oVlE4Mj7HmqU8YyBzRc1nX0s0r0 hm94O8WmD3+r+IS4SOXUKN3WzoXk+cUUgV2DLgaYLq6EW98YtFnOqkxiEaGGaB2XjmZZ OB4KE2w411nNV/1KPDJ6Q+5lj+Rvy96xkfjxyHOcM+BMAsudj2znBNatzOigULYzaUHa rUIQ== X-Gm-Message-State: AOJu0Yyw84KOxDsHoB+IDxYHORjmDqHnM5DlFrYJL16g/Ik0CPpSHJAh viJcScJbQxrnd2kjkbK6u/YxqbQOKa10WohE3Jk= X-Google-Smtp-Source: AGHT+IEkZqbakDX6RaUQMrgNoB1fjuVjSjnDF0xLT5VTu9acxiYeOJPI7DIGLRk8T+aAMsn2tYqiwQ== X-Received: by 2002:a17:906:66c1:b0:9ff:77c2:e67f with SMTP id k1-20020a17090666c100b009ff77c2e67fmr8380126ejp.33.1701100353110; Mon, 27 Nov 2023 07:52:33 -0800 (PST) Received: from [10.167.154.1] (178235187180.dynamic-4-waw-k-2-3-0.vectranet.pl. [178.235.187.180]) by smtp.gmail.com with ESMTPSA id mb22-20020a170906eb1600b009fc0c42098csm5855150ejb.173.2023.11.27.07.52.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Nov 2023 07:52:32 -0800 (PST) From: Konrad Dybcio Date: Mon, 27 Nov 2023 16:52:13 +0100 Subject: [PATCH v7 2/2] irqchip: irq-qcom-mpm: Support passing a slice of SRAM as reg space Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20230328-topic-msgram_mpm-v7-2-6ee2bfeaac2c@linaro.org> References: <20230328-topic-msgram_mpm-v7-0-6ee2bfeaac2c@linaro.org> In-Reply-To: <20230328-topic-msgram_mpm-v7-0-6ee2bfeaac2c@linaro.org> To: Andy Gross , Bjorn Andersson , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Shawn Guo , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio , Bryan O'Donoghue X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1701100347; l=2888; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=xv+mWCEly/nIv85AR5MmmU/wkLvnOBn7Ei5h/U9JNy0=; b=d0wDKn96S5wPzxqpjV9SfTtHRQKUGg0oVkzShzFNVW58PHwEZQNEFHHiBEflYbkWgBSJY96Bo dermZgeioXjBYae0UzHuHrS04+dp0cFDYzidoyvkZUuBtBTXjCOdJO1 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= The MPM hardware is accessible to us from the ARM CPUs through a shared memory region (RPM MSG RAM) that's also concurrently accessed by other kinds of cores on the system (like modem, ADSP etc.). Modeling this relation in a (somewhat) sane manner in the device tree basically requires us to either present the MPM as a child of said memory region (which makes little sense, as a mapped memory carveout is not a bus), define nodes which bleed their register spaces into one another, or passing their slice of the MSG RAM through some kind of a property. Go with the third option and add a way to map a region passed through the "qcom,rpm-msg-ram" property as our register space. The current way of using 'reg' is preserved for ABI reasons. Acked-by: Shawn Guo Reviewed-by: Bryan O'Donoghue Signed-off-by: Konrad Dybcio --- drivers/irqchip/irq-qcom-mpm.c | 26 +++++++++++++++++++++++--- 1 file changed, 23 insertions(+), 3 deletions(-) diff --git a/drivers/irqchip/irq-qcom-mpm.c b/drivers/irqchip/irq-qcom-mpm.c index 7124565234a5..cda5838d2232 100644 --- a/drivers/irqchip/irq-qcom-mpm.c +++ b/drivers/irqchip/irq-qcom-mpm.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -322,8 +323,10 @@ static int qcom_mpm_init(struct device_node *np, struct device_node *parent) struct device *dev = &pdev->dev; struct irq_domain *parent_domain; struct generic_pm_domain *genpd; + struct device_node *msgram_np; struct qcom_mpm_priv *priv; unsigned int pin_cnt; + struct resource res; int i, irq; int ret; @@ -374,9 +377,26 @@ static int qcom_mpm_init(struct device_node *np, struct device_node *parent) raw_spin_lock_init(&priv->lock); - priv->base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(priv->base)) - return PTR_ERR(priv->base); + /* If we have a handle to an RPM message ram partition, use it. */ + msgram_np = of_parse_phandle(np, "qcom,rpm-msg-ram", 0); + if (msgram_np) { + ret = of_address_to_resource(msgram_np, 0, &res); + if (ret) { + of_node_put(msgram_np); + return ret; + } + + /* Don't use devm_ioremap_resource, as we're accessing a shared region. */ + priv->base = devm_ioremap(dev, res.start, resource_size(&res)); + of_node_put(msgram_np); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + } else { + /* Otherwise, fall back to simple MMIO. */ + priv->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + } for (i = 0; i < priv->reg_stride; i++) { qcom_mpm_write(priv, MPM_REG_ENABLE, i, 0);