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[178.235.187.180]) by smtp.gmail.com with ESMTPSA id m12-20020a1709062acc00b009c3828fec06sm5734760eje.81.2023.11.27.08.20.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Nov 2023 08:20:12 -0800 (PST) From: Konrad Dybcio Date: Mon, 27 Nov 2023 17:20:03 +0100 Subject: [PATCH 1/6] dt-bindings: arm-smmu: Document SM8[45]50 GPU SMMU MIME-Version: 1.0 Message-Id: <20231127-topic-a7xx_dt-v1-1-a228b8122ebf@linaro.org> References: <20231127-topic-a7xx_dt-v1-0-a228b8122ebf@linaro.org> In-Reply-To: <20231127-topic-a7xx_dt-v1-0-a228b8122ebf@linaro.org> To: Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson Cc: Marijn Suijten , Neil Armstrong , Dmitry Baryshkov , linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1701102008; l=2687; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=74tAYPhFS0JRCe3sr6MjDifnedbnYgVr+albesY88R0=; b=No3Vb43Hd8bD4NOsHXSg5ppXhq7oWxb1HCy48OeWtBGzmM/Vf85XVb4qfsN85FKcmgSofqivP np1tT3yPxGoBCcURjbxS75Vp3ViOIvu5TsM+75m9B+XJYAMDFfL629i X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231127_082016_665333_F94FF55F X-CRM114-Status: GOOD ( 10.98 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org SM8450 and SM8550 both use a Qualcomm-modified MMU500 for their GPU. In both cases, it requires a set of clocks to be enabled. Describe that. Signed-off-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/iommu/arm,smmu.yaml | 48 +++++++++++++++++++++- 1 file changed, 46 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index aa9e1c0895a5..19dba93a7654 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -89,6 +89,8 @@ properties: - qcom,sm8150-smmu-500 - qcom,sm8250-smmu-500 - qcom,sm8350-smmu-500 + - qcom,sm8450-smmu-500 + - qcom,sm8550-smmu-500 - const: qcom,adreno-smmu - const: qcom,smmu-500 - const: arm,mmu-500 @@ -453,6 +455,50 @@ allOf: - description: Voter clock required for HLOS SMMU access - description: Interface clock required for register access + - if: + properties: + compatible: + const: qcom,sm8450-smmu-500 + then: + properties: + clock-names: + items: + - const: gmu + - const: hub + - const: hlos + - const: bus + - const: iface + - const: ahb + + clocks: + items: + - description: GMU clock + - description: GPU HUB clock + - description: HLOS vote clock + - description: GPU memory bus clock + - description: GPU SNoC bus clock + - description: GPU AHB clock + + - if: + properties: + compatible: + const: qcom,sm8550-smmu-500 + then: + properties: + clock-names: + items: + - const: hlos + - const: bus + - const: iface + - const: ahb + + clocks: + items: + - description: HLOS vote clock + - description: GPU memory bus clock + - description: GPU SNoC bus clock + - description: GPU AHB clock + # Disallow clocks for all other platforms with specific compatibles - if: properties: @@ -473,8 +519,6 @@ allOf: - qcom,sm6350-smmu-500 - qcom,sm6375-smmu-500 - qcom,sm8350-smmu-500 - - qcom,sm8450-smmu-500 - - qcom,sm8550-smmu-500 then: properties: clock-names: false From patchwork Mon Nov 27 16:20:04 2023 Content-Type: text/plain; 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[178.235.187.180]) by smtp.gmail.com with ESMTPSA id m12-20020a1709062acc00b009c3828fec06sm5734760eje.81.2023.11.27.08.20.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Nov 2023 08:20:14 -0800 (PST) From: Konrad Dybcio Date: Mon, 27 Nov 2023 17:20:04 +0100 Subject: [PATCH 2/6] arm64: dts: qcom: sm8450: Add GPU nodes MIME-Version: 1.0 Message-Id: <20231127-topic-a7xx_dt-v1-2-a228b8122ebf@linaro.org> References: <20231127-topic-a7xx_dt-v1-0-a228b8122ebf@linaro.org> In-Reply-To: <20231127-topic-a7xx_dt-v1-0-a228b8122ebf@linaro.org> To: Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson Cc: Marijn Suijten , Neil Armstrong , Dmitry Baryshkov , linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1701102008; l=7123; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=I5oAq4yvU3S7sBbp5DBP75jCv9QJAYvsZHzH8XavMSU=; b=HoaVPcrRvjXrREUWeLaJt3R2+uJce6mBb18Ppr+odKdWMibsFYokteuvpay3z5ROgGRGAbOrn dlbTW4nz8kMCq0TN9SpOcjf9dm0DocD7Sairm1/44Z/7BgYh9MDJGHm X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231127_082018_433986_A473CD88 X-CRM114-Status: GOOD ( 10.21 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add the required nodes to support the A730 GPU. Signed-off-by: Konrad Dybcio Reviewed-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 202 +++++++++++++++++++++++++++++++++++ 1 file changed, 202 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index bde9c1093384..e9664672c160 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -18,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -2019,6 +2021,206 @@ tcsr: syscon@1fc0000 { reg = <0x0 0x1fc0000 0x0 0x30000>; }; + gpu: gpu@3d00000 { + compatible = "qcom,adreno-730.1", "qcom,adreno"; + reg = <0x0 0x03d00000 0x0 0x40000>, + <0x0 0x03d9e000 0x0 0x1000>, + <0x0 0x03d61000 0x0 0x800>; + reg-names = "kgsl_3d0_reg_memory", + "cx_mem", + "cx_dbgc"; + + interrupts = ; + + iommus = <&adreno_smmu 0 0x400>, + <&adreno_smmu 1 0x400>; + + operating-points-v2 = <&gpu_opp_table>; + + qcom,gmu = <&gmu>; + + status = "disabled"; + + zap-shader { + memory-region = <&gpu_micro_code_mem>; + }; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-818000000 { + opp-hz = /bits/ 64 <818000000>; + opp-level = ; + }; + + opp-791000000 { + opp-hz = /bits/ 64 <791000000>; + opp-level = ; + }; + + opp-734000000 { + opp-hz = /bits/ 64 <734000000>; + opp-level = ; + }; + + opp-640000000 { + opp-hz = /bits/ 64 <640000000>; + opp-level = ; + }; + + opp-599000000 { + opp-hz = /bits/ 64 <599000000>; + opp-level = ; + }; + + opp-545000000 { + opp-hz = /bits/ 64 <545000000>; + opp-level = ; + }; + + opp-492000000 { + opp-hz = /bits/ 64 <492000000>; + opp-level = ; + }; + + opp-421000000 { + opp-hz = /bits/ 64 <421000000>; + opp-level = ; + }; + + opp-350000000 { + opp-hz = /bits/ 64 <350000000>; + opp-level = ; + }; + + opp-317000000 { + opp-hz = /bits/ 64 <317000000>; + opp-level = ; + }; + + opp-285000000 { + opp-hz = /bits/ 64 <285000000>; + opp-level = ; + }; + + opp-220000000 { + opp-hz = /bits/ 64 <220000000>; + opp-level = ; + }; + }; + }; + + gmu: gmu@3d6a000 { + compatible = "qcom,adreno-gmu-730.1", "qcom,adreno-gmu"; + reg = <0x0 0x03d6a000 0x0 0x35000>, + <0x0 0x03d50000 0x0 0x10000>, + <0x0 0x0b290000 0x0 0x10000>; + reg-names = "gmu", "rscc", "gmu_pdc"; + + interrupts = , + ; + interrupt-names = "hfi", "gmu"; + + clocks = <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_DEMET_CLK>; + clock-names = "ahb", + "gmu", + "cxo", + "axi", + "memnoc", + "hub", + "demet"; + + power-domains = <&gpucc GPU_CX_GDSC>, + <&gpucc GPU_GX_GDSC>; + power-domain-names = "cx", + "gx"; + + iommus = <&adreno_smmu 5 0x400>; + + qcom,qmp = <&aoss_qmp>; + + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-level = ; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-level = ; + }; + }; + }; + + gpucc: clock-controller@3d90000 { + compatible = "qcom,sm8450-gpucc"; + reg = <0x0 0x03d90000 0x0 0xa000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + adreno_smmu: iommu@3da0000 { + compatible = "qcom,sm8450-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x03da0000 0x0 0x40000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>; + clock-names = "gmu", + "hub", + "hlos", + "bus", + "iface", + "ahb"; + power-domains = <&gpucc GPU_CX_GDSC>; + dma-coherent; + }; + usb_1_hsphy: phy@88e3000 { compatible = "qcom,sm8450-usb-hs-phy", "qcom,usb-snps-hs-7nm-phy"; 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[178.235.187.180]) by smtp.gmail.com with ESMTPSA id m12-20020a1709062acc00b009c3828fec06sm5734760eje.81.2023.11.27.08.20.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Nov 2023 08:20:16 -0800 (PST) From: Konrad Dybcio Date: Mon, 27 Nov 2023 17:20:05 +0100 Subject: [PATCH 3/6] arm64: dts: qcom: sm8550: Add GPU nodes MIME-Version: 1.0 Message-Id: <20231127-topic-a7xx_dt-v1-3-a228b8122ebf@linaro.org> References: <20231127-topic-a7xx_dt-v1-0-a228b8122ebf@linaro.org> In-Reply-To: <20231127-topic-a7xx_dt-v1-0-a228b8122ebf@linaro.org> To: Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson Cc: Marijn Suijten , Neil Armstrong , Dmitry Baryshkov , linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1701102008; l=5572; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=zs3rMUmNrxdSrAAcrhg7P26RbaOTU6dGtl32v7guU6Q=; b=e1rrRcDcznSKhXJckpVjzmPlMWYvIviY5+mO0EUkcv8jDrnaXlpypvc+ixkkL04SwZfjQmZtz eEfK7YPm2HcC0QYXrU7OP5at2TW9b5jHZCqpqhIv8NFtg1UyRX1LbuP X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231127_082021_020607_721698F0 X-CRM114-Status: UNSURE ( 9.77 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add the required nodes to support the A740 GPU. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 166 +++++++++++++++++++++++++++++++++++ 1 file changed, 166 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 7bafb3d88d69..8f6641c58b3b 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2841,6 +2841,172 @@ dispcc: clock-controller@af00000 { #power-domain-cells = <1>; }; + gpu: gpu@3d00000 { + compatible = "qcom,adreno-740.1", "qcom,adreno"; + reg = <0x0 0x03d00000 0x0 0x40000>, + <0x0 0x03d9e000 0x0 0x1000>, + <0x0 0x03d61000 0x0 0x800>; + reg-names = "kgsl_3d0_reg_memory", + "cx_mem", + "cx_dbgc"; + + interrupts = ; + + iommus = <&adreno_smmu 0 0x0>, + <&adreno_smmu 1 0x0>; + + operating-points-v2 = <&gpu_opp_table>; + + qcom,gmu = <&gmu>; + + status = "disabled"; + + zap-shader { + memory-region = <&gpu_micro_code_mem>; + }; + + /* Speedbin needs more work on A740+, keep only lower freqs */ + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-680000000 { + opp-hz = /bits/ 64 <680000000>; + opp-level = ; + }; + + opp-615000000 { + opp-hz = /bits/ 64 <615000000>; + opp-level = ; + }; + + opp-550000000 { + opp-hz = /bits/ 64 <550000000>; + opp-level = ; + }; + + opp-475000000 { + opp-hz = /bits/ 64 <475000000>; + opp-level = ; + }; + + opp-401000000 { + opp-hz = /bits/ 64 <401000000>; + opp-level = ; + }; + + opp-348000000 { + opp-hz = /bits/ 64 <348000000>; + opp-level = ; + }; + + opp-295000000 { + opp-hz = /bits/ 64 <295000000>; + opp-level = ; + }; + + opp-220000000 { + opp-hz = /bits/ 64 <220000000>; + opp-level = ; + }; + }; + }; + + gmu: gmu@3d6a000 { + compatible = "qcom,adreno-gmu-740.1", "qcom,adreno-gmu"; + reg = <0x0 0x03d6a000 0x0 0x35000>, + <0x0 0x03d50000 0x0 0x10000>, + <0x0 0x0b280000 0x0 0x10000>; + reg-names = "gmu", "rscc", "gmu_pdc"; + + interrupts = , + ; + interrupt-names = "hfi", "gmu"; + + clocks = <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_DEMET_CLK>; + clock-names = "ahb", + "gmu", + "cxo", + "axi", + "memnoc", + "hub", + "demet"; + + power-domains = <&gpucc GPU_CC_CX_GDSC>, + <&gpucc GPU_CC_GX_GDSC>; + power-domain-names = "cx", + "gx"; + + iommus = <&adreno_smmu 5 0x0>; + + qcom,qmp = <&aoss_qmp>; + + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-level = ; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-level = ; + }; + }; + }; + + adreno_smmu: iommu@3da0000 { + compatible = "qcom,sm8550-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x03da0000 0x0 0x40000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>; + clock-names = "hlos", + "bus", + "iface", + "ahb"; + power-domains = <&gpucc GPU_CC_CX_GDSC>; + dma-coherent; + }; + usb_1_hsphy: phy@88e3000 { compatible = "qcom,sm8550-snps-eusb2-phy"; reg = <0x0 0x088e3000 0x0 0x154>; From patchwork Mon Nov 27 16:20:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13469933 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CE9E6C10DAA for ; Mon, 27 Nov 2023 16:20:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Enable the GPU and provide a path for the ZAP blob. Signed-off-by: Konrad Dybcio Reviewed-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts index eef811def39b..9fe51d308675 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts @@ -596,6 +596,14 @@ &gcc { <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; }; +&gpu { + status = "okay"; + + zap-shader { + firmware-name = "qcom/sm8550/a740_zap.mbn"; + }; +}; + &lpass_tlmm { spkr_1_sd_n_active: spkr-1-sd-n-active-state { pins = "gpio17"; From patchwork Mon Nov 27 16:20:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13469936 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7B7C6C07CB1 for ; Mon, 27 Nov 2023 16:21:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=3+JbBo5tFB2vJ9o8nQavH6qfSftBnFJeqX6WSvaHFs4=; b=O7Xdb5VgSOw1Ea zOEbTBUOFwwF1tHdHHr2AvCZhrHOtgdNBU8ZetK9lKvhwbT7Am7nt05M/7EZ1frpIQdCx7quUByWZ +o1hnesFWvJbrfRNcguvJd/KFMOMf1HKzkuIPxNLfKVYZhAmSaBONT9FOf0RLknVlCsQ7TTuujJ4F UaIAvwR8IZBCbgOTD4IAKGiYdnM9GymliTrgUo8khWomVnfBR2YeD2s5jg2wrS0XrEjZkAoAbEgeI hxHcGQiRM85k6DqMfHy8+BOtieatm6ESRzIjLeDqRtOFbWS5aSasG8i8nGpkuGv6HgFeZ7KY8LUzF dXy8lf6iItSktun0GSpw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1r7eLr-002xRi-11; Mon, 27 Nov 2023 16:20:51 +0000 Received: from mail-ej1-x62e.google.com ([2a00:1450:4864:20::62e]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1r7eLQ-002x9J-1j for linux-arm-kernel@lists.infradead.org; Mon, 27 Nov 2023 16:20:27 +0000 Received: by mail-ej1-x62e.google.com with SMTP id a640c23a62f3a-9ffef4b2741so595506366b.3 for ; Mon, 27 Nov 2023 08:20:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1701102020; x=1701706820; darn=lists.infradead.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=R+c7o+g11wQaVIfs6Upk57wmZsR4iWH52vbiNHzvWM8=; b=iA2Br5Y6I0gqmBTgRgrssoTpLl/PxiA1NOx5JMoHsP+PrzH5Wnhi9OB4E5IFuzRYyZ XZxclLRNeVZpvldp8MUdeE/IVydNj9A4cNe7OlAnDc0nUIbyheP4idyEK6NEnjqWD6GI fytMHzgaY3ItfNTMItIf0RczJD7Byd+/u9W2iQXXP62e2hIeS3akq8hphyBIzNfQyhqY LutovYfFOAyvcRrwsWf4UHdoHSm8xzq5NqAhk2T6v1e5mgjdn+pUx3bqnUTNJbw1g3v4 j9IyBcg71RS+4FTk6venWTDdW06wOxx3rYsn+fB+F1KPeStFJwXu3WXI4b87oq3E3098 Emqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701102020; x=1701706820; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=R+c7o+g11wQaVIfs6Upk57wmZsR4iWH52vbiNHzvWM8=; b=agQfYYuW+I2yOGkDly6NpgaY5p1lLM+TaA1TlMlvj5hO9KAQhxGWasTxBnlS2Ydf9i ckGSSe/0R2HhvTp71XAIC9l08SQ+BRbd2sNCcrK+SNxg82ix/W2Tujvu9KSRbgWeBhRi IH5K/c/4aX+P6XWJTSTgG6/AL/lTT6KvTuCWtenD3o9ZaEuv6VXTa1QlWrou359hsw/3 RR7YpS3HohJGLf46n0M7iNnADD3Ye6aBFX7iq6FC9104gCTLUGry4bwSH9YEzgi6ytjh sMZVa4lrVuaTzTgk+ZsMpN4CpUhX3X0NfsI5ukUkijgarL6okD8toXafRsU0EI3pZGW2 /E2w== X-Gm-Message-State: AOJu0YzO6qFRbsHRiloVVX37GKA2sEY7Uq3P/kf+hlH5uOF0SY763o6Y Y+cMaQFkvNhHMnBbrkHlHPC/fg== X-Google-Smtp-Source: AGHT+IEqwnM1Zk0NU5iClHhAf8DuvbmDFdZ/y49v5SALbxoGoB9jxKWr8LOq25RqeNMDSYJdvz5jQg== X-Received: by 2002:a17:906:1dd0:b0:9fe:4d14:800e with SMTP id v16-20020a1709061dd000b009fe4d14800emr9032787ejh.39.1701102020723; Mon, 27 Nov 2023 08:20:20 -0800 (PST) Received: from [10.167.154.1] (178235187180.dynamic-4-waw-k-2-3-0.vectranet.pl. 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Signed-off-by: Konrad Dybcio Reviewed-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts index 9a70875028b7..52244e9bfdee 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -512,6 +512,14 @@ vreg_l3g_1p2: ldo3 { }; }; +&gpu { + status = "okay"; + + zap-shader { + firmware-name = "qcom/sm8550/a740_zap.mbn"; + }; +}; + &i2c_master_hub_0 { status = "okay"; }; From patchwork Mon Nov 27 16:20:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13469935 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 21E12C4167B for ; Mon, 27 Nov 2023 16:21:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=GqkfRlJGH5KsCaattvuHq/8H7vZvGBte7bgHX2WEl+A=; b=tKTQAxsxZAQhZR YFnCOBBenDxEby1KcVuyGE9XlbdKzPVFHYLCQwp61m8jIAYvQ78fkqL5pgh3OyuQUBJGOZqY9JzbS auu1wYWeGROdAv0anHNkWT5nVLVlegTYnZ19G3QMNsU9XLyIyX1DqeW6UMZyyou5m6F4TqBi0Snl7 lnRqP5j7fS4OZ6d2QbhkZup+LR/AQbWyDfCaoSPlTLHGSn5nqkwnbgl+vDnncka1f3CPL+cY2454j FrocQscXXoEf6Rjo+P8ocKY6c1/QVOAGpsNvuvmmmTlLFfbaZXgsmbLE3ihpu66/i8oSxY0PI07CC tdgDtIGJ/obrA7pIH28A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1r7eLs-002xSZ-1p; Mon, 27 Nov 2023 16:20:52 +0000 Received: from mail-ej1-x635.google.com ([2a00:1450:4864:20::635]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1r7eLT-002x9w-0p for linux-arm-kernel@lists.infradead.org; Mon, 27 Nov 2023 16:20:29 +0000 Received: by mail-ej1-x635.google.com with SMTP id a640c23a62f3a-a00c200782dso647908166b.1 for ; Mon, 27 Nov 2023 08:20:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1701102022; x=1701706822; darn=lists.infradead.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=8gQ6YImSRCbx+1xRUL4mfy0bfTlxIzI8pSH1DPk4t6M=; b=k8YS4nZ8npV9MPNtEw7ZgaF4HfkNJeC7aodzStojPfhWsnKTsjHqEno8b5j44tzHG8 vVaz9SxMInTLg9a3pYe23GSJOVj5QVDXmtVXYt+34pgfHqNxoCLs2+Z5SG7BCedUVSFG 6eiMiGGcd8vrfEMrpOelfcT/r81fVWq26nVCoSDt+MREsXFkMVgH0EekgynPKkMKo9Av MFp3eM+Ul3JAjroiUkXeYalWREzZRRME0TAkri0kN/n7UyqxrTG3IJS0RnxplnM4pyMm TRVcmu6MH9mGwkvvyOIOWvrwxlxblgz71EF+5tFvlVdrJqGaGJNm+JpG5tv1yPm/bGxu GFwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701102022; x=1701706822; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8gQ6YImSRCbx+1xRUL4mfy0bfTlxIzI8pSH1DPk4t6M=; b=oPCT2pWOsH2R+hUj6VmYvTixwmSYSrRx/1pH7lmZuuWCfxGtGLx4b5RT3rmffLzH3I mJ38/DfOwbVXVOM1YWRA52mlpRSvvpUc+FS7lYtw6zru+bfiF1VPqVRzdprll7WXA9xp tiaPVgIZwgOur/A5MqtCuTB0nh9DfFKESpXZcsXAP9iBRZTtCUMvLnPGgaXQ5aOInq2z YWqRSyqq9hMjjS0ZHAB7D4AdED3JtlpBSc7akWr6tEVi8WkXHk63cdKPf2zS0cHbbn0X RjCRAn+Z3A1eYvSZ2HK8pPRQSrB8cOiSHqDhXlu2EdECDJ7hbODKVVRmtwexPQqRNUmw IeBA== X-Gm-Message-State: AOJu0YzVGz9DQMJsri5alT1HHEw2NiJvJiKg3wPaMVgIrLvVktxnnLeA IyJ4ICxMaQ1zJsmaAU8We25vNw== X-Google-Smtp-Source: AGHT+IFPmWmSTHMcfL1yecPUgSq8wRk41FMgkXe1PITU3Isy6yZrSpKslVtSqdOYlcbiQ944Gj61HQ== X-Received: by 2002:a17:906:3e0e:b0:9c1:edd8:43c2 with SMTP id k14-20020a1709063e0e00b009c1edd843c2mr8518492eji.42.1701102022689; Mon, 27 Nov 2023 08:20:22 -0800 (PST) Received: from [10.167.154.1] (178235187180.dynamic-4-waw-k-2-3-0.vectranet.pl. [178.235.187.180]) by smtp.gmail.com with ESMTPSA id m12-20020a1709062acc00b009c3828fec06sm5734760eje.81.2023.11.27.08.20.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Nov 2023 08:20:22 -0800 (PST) From: Konrad Dybcio Date: Mon, 27 Nov 2023 17:20:08 +0100 Subject: [PATCH 6/6] arm64: dts: qcom: sm8450-hdk: Enable the A730 GPU MIME-Version: 1.0 Message-Id: <20231127-topic-a7xx_dt-v1-6-a228b8122ebf@linaro.org> References: <20231127-topic-a7xx_dt-v1-0-a228b8122ebf@linaro.org> In-Reply-To: <20231127-topic-a7xx_dt-v1-0-a228b8122ebf@linaro.org> To: Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson Cc: Marijn Suijten , Neil Armstrong , Dmitry Baryshkov , linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1701102008; l=685; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=ZUlIcXR6hgLx+DM+J1BHsWNt1eWJies/ihFtsM1lhWs=; b=Cedfa+rVMp6sij89sdZZMlPzRmUJXcuOfEsRWBEN2D21fqvMOO59apxBjB3KBAs4/TDPO0Kqr SYlvJAJGZQ/CbFapt8rBADbCSma58YbPuNklA1x7+9wefmw9suo3yzI X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231127_082027_310114_87B2A723 X-CRM114-Status: GOOD ( 10.07 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Enable the GPU and provide a path for the ZAP blob. Signed-off-by: Konrad Dybcio Reviewed-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index 20153d08edde..a20d5d76af35 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -580,6 +580,14 @@ &dispcc { status = "okay"; }; +&gpu { + status = "okay"; + + zap-shader { + firmware-name = "qcom/sm8450/a730_zap.mbn"; + }; +}; + &i2c9 { clock-frequency = <400000>; status = "okay";