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Mon, 27 Nov 2023 23:16:26 -0800 From: Mohan Kumar To: , , , CC: , , , , , , Mohan Kumar Subject: [RESEND PATCH V2 1/2] dt-bindings: dma: Add dma-channel-mask to nvidia,tegra210-adma Date: Tue, 28 Nov 2023 12:46:14 +0530 Message-ID: <20231128071615.31447-2-mkumard@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231128071615.31447-1-mkumard@nvidia.com> References: <20231128071615.31447-1-mkumard@nvidia.com> Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044F6:EE_|DM6PR12MB4330:EE_ X-MS-Office365-Filtering-Correlation-Id: bdd30e5f-1b92-4681-3189-08dbefe1f508 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: HFYxJRfIegtHtg6guf+aLiALWvRl6Bpr/WeZgXj60TPtcQ8Iz9+u/jYLMkXBqOd33H/WlgYwDgcaHhIO72H7lwDC5p9K9sLYu07bqp5oxgl6sX0vXaxm46Q03noMM5XRgaHAau3fqfKyvZkBmMWGyskNbcTsJGxBnBR8PegMQVX81iKGbOmuV6qweJJQABxFoC9Ae0PCcL1E4bOQoxFtF7bcC3zZS0aQR+MndsJmp7esH2DYQsPJbV5SVXgcEeN3Ut2hOTZ8qM2sfaXu5SjiCLKFSZtDc6MZf14Vwsi4TeeAzI9/E87b260z/UPDbGdUeOzD6I2MUPqpcYW18t4/ZoSOad1j1uHSYkFUxbE/olQFdsxrupWwAFeakSvvsBoq/jA0shXdNgnbGHXbWD2AP5moa7knuc+5kiyVa+tpsqsUq545wFhVFCU5B57GzvkvXgpi1XeIoMcNHZChGQWlvumba6KBvkeQHoLAWTzjDxG8uVYf15JgbDFM+zjFpWZZibPQxfEuK1O/kYNbphDzrKteoFt41dhw77lOxDhJJ6mmp48UwEBiGmaIgInejrQzLHoZ2oFUKXkie0pD2FYz3qql/PCZ5UJHBkOlZUZJBekID8AqiBF9/CUwRT1dwJHFE8iQ54sqFbd965MkKKqXUJUyD54A63U5s1iDS8fFlN4lfofwaNvmQ9ZRK5WcdWatTkMcCkEkvdPrfk8928RL2x6AlP+LQ0eUIajttH2E0svUDNrwBemwyJgU64DQzHT/ X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(346002)(136003)(39860400002)(396003)(376002)(230922051799003)(186009)(451199024)(64100799003)(1800799012)(82310400011)(46966006)(40470700004)(36840700001)(86362001)(82740400003)(356005)(40460700003)(36756003)(7636003)(478600001)(316002)(54906003)(70206006)(70586007)(26005)(1076003)(110136005)(426003)(336012)(7696005)(2616005)(6666004)(107886003)(5660300002)(4326008)(4744005)(2906002)(8676002)(8936002)(41300700001)(36860700001)(40480700001)(47076005);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Nov 2023 07:16:35.9910 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bdd30e5f-1b92-4681-3189-08dbefe1f508 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F6.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4330 Add dma-channel-mask binding doc support to nvidia,tegra210-adma to reserve the adma channel usage Acked-by: Rob Herring Signed-off-by: Mohan Kumar --- .../devicetree/bindings/dma/nvidia,tegra210-adma.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml b/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml index 4003dbe94940..877147e95ecc 100644 --- a/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml @@ -53,6 +53,9 @@ properties: ADMA_CHn_CTRL register. const: 1 + dma-channel-mask: + maxItems: 1 + required: - compatible - reg From patchwork Tue Nov 28 07:16:15 2023 Content-Type: text/plain; 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Mon, 27 Nov 2023 23:16:31 -0800 From: Mohan Kumar To: , , , CC: , , , , , , Mohan Kumar Subject: [RESEND PATCH V2 2/2] dmaengine: tegra210-adma: Support dma-channel-mask property Date: Tue, 28 Nov 2023 12:46:15 +0530 Message-ID: <20231128071615.31447-3-mkumard@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231128071615.31447-1-mkumard@nvidia.com> References: <20231128071615.31447-1-mkumard@nvidia.com> Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB4F:EE_|CY8PR12MB8316:EE_ X-MS-Office365-Filtering-Correlation-Id: c2cbd8c1-8ff7-48a4-2202-08dbefe1face X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ZvHgpsMs5eSIhzHJ5XHkg3E0tq2YisgC0r8KbJ/kxvf4RBfcxQww1/bRoSuUPNl3Ffxi2o5EUyEtjOQH8rFgp0YgoiAq3EJn1mry0ujFrec1U2gtjX3TV/tYid+PwYn4HNFr2GxbRmU915ah+gc9ya63oZ9zv5GGV4Epd/ag3yYsw5aJ91svAfCrpFAJ4GVUKQpzOaVKYf4474g9yc2XIk0lr+bxlu5qxYcim2GTcD/BonR3ZaPLuvS/rrdqNx5HGtvLW805436fmVrwh2US3bUB40FNHGmql7Q6WYVC9a3QU+B0XrE3gNFoJSFh/6itInm6rXLiXWOYlcGpj9bejcAQwnAQwhsbPO3XZd5cQPmduVH0avGZAcovSzNYU5H0kmhnaIOHKMoIG6OnD32DaAvtIYwb0nxGvZpJ1Jyg5pr8pXZ8zU5QXndur3oALfzMRdJcZAsF+JkBLTXb1CtMFmd9phDJj2cjCCdSN1lCeUeoFgapuixEg290hYTLl7YM9qoxwP1glnymrdTh4AROY6XK+Zkj8gM3zKRx44N1eOy8m5I4syp51kcXkkjzlb0SNSCcQaMKSgSHbFxqgP0h8cJ1E0IqZ17SafEeV4UfWipw/WbfryWCAcCI6QHk+5UiECUdy2r1HvlMYOfMqLF8wFRKbv2k/FApwToKvmg7ad6uy2t3foNKlP7aE2BmEdRNLBIHSghIQmtKS1Sm54Ta4BoRy52Q8XRPDTPJk/WT4QLnfQg9x8D5auSM/TOZFDhG X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(396003)(136003)(376002)(39860400002)(346002)(230922051799003)(186009)(82310400011)(1800799012)(64100799003)(451199024)(46966006)(40470700004)(36840700001)(5660300002)(41300700001)(40480700001)(8936002)(4326008)(8676002)(2906002)(316002)(54906003)(70586007)(70206006)(110136005)(40460700003)(47076005)(26005)(107886003)(2616005)(1076003)(478600001)(7696005)(36756003)(36860700001)(6666004)(426003)(336012)(356005)(86362001)(7636003)(83380400001)(82740400003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Nov 2023 07:16:45.5519 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c2cbd8c1-8ff7-48a4-2202-08dbefe1face X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB4F.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB8316 To support the flexibility to reserve the specific dma channels add the support of dma-channel-mask property in the tegra210-adma driver Signed-off-by: Mohan Kumar --- drivers/dma/tegra210-adma.c | 35 +++++++++++++++++++++++++++++++++-- 1 file changed, 33 insertions(+), 2 deletions(-) diff --git a/drivers/dma/tegra210-adma.c b/drivers/dma/tegra210-adma.c index 7a0586633bf3..24ad7077c53b 100644 --- a/drivers/dma/tegra210-adma.c +++ b/drivers/dma/tegra210-adma.c @@ -153,6 +153,7 @@ struct tegra_adma { void __iomem *base_addr; struct clk *ahub_clk; unsigned int nr_channels; + unsigned long *dma_chan_mask; unsigned long rx_requests_reserved; unsigned long tx_requests_reserved; @@ -741,6 +742,10 @@ static int __maybe_unused tegra_adma_runtime_suspend(struct device *dev) for (i = 0; i < tdma->nr_channels; i++) { tdc = &tdma->channels[i]; + /* skip for reserved channels */ + if (!tdc->tdma) + continue; + ch_reg = &tdc->ch_regs; ch_reg->cmd = tdma_ch_read(tdc, ADMA_CH_CMD); /* skip if channel is not active */ @@ -779,6 +784,9 @@ static int __maybe_unused tegra_adma_runtime_resume(struct device *dev) for (i = 0; i < tdma->nr_channels; i++) { tdc = &tdma->channels[i]; + /* skip for reserved channels */ + if (!tdc->tdma) + continue; ch_reg = &tdc->ch_regs; /* skip if channel was not active earlier */ if (!ch_reg->cmd) @@ -867,10 +875,31 @@ static int tegra_adma_probe(struct platform_device *pdev) return PTR_ERR(tdma->ahub_clk); } + tdma->dma_chan_mask = devm_kzalloc(&pdev->dev, + BITS_TO_LONGS(tdma->nr_channels) * sizeof(unsigned long), + GFP_KERNEL); + if (!tdma->dma_chan_mask) + return -ENOMEM; + + /* Enable all channels by default */ + bitmap_fill(tdma->dma_chan_mask, tdma->nr_channels); + + ret = of_property_read_u32_array(pdev->dev.of_node, "dma-channel-mask", + (u32 *)tdma->dma_chan_mask, + BITS_TO_U32(tdma->nr_channels)); + if (ret < 0 && (ret != -EINVAL)) { + dev_err(&pdev->dev, "dma-channel-mask is not complete.\n"); + return ret; + } + INIT_LIST_HEAD(&tdma->dma_dev.channels); for (i = 0; i < tdma->nr_channels; i++) { struct tegra_adma_chan *tdc = &tdma->channels[i]; + /* skip for reserved channels */ + if (!test_bit(i, tdma->dma_chan_mask)) + continue; + tdc->chan_addr = tdma->base_addr + cdata->ch_base_offset + (cdata->ch_reg_size * i); @@ -957,8 +986,10 @@ static void tegra_adma_remove(struct platform_device *pdev) of_dma_controller_free(pdev->dev.of_node); dma_async_device_unregister(&tdma->dma_dev); - for (i = 0; i < tdma->nr_channels; ++i) - irq_dispose_mapping(tdma->channels[i].irq); + for (i = 0; i < tdma->nr_channels; ++i) { + if (tdma->channels[i].irq) + irq_dispose_mapping(tdma->channels[i].irq); + } pm_runtime_disable(&pdev->dev); }