From patchwork Tue Nov 28 08:37:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanislav Lisovskiy X-Patchwork-Id: 13470646 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 144F9C07E98 for ; Tue, 28 Nov 2023 08:38:06 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1B55D10E454; Tue, 28 Nov 2023 08:38:03 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id C170310E12C for ; Tue, 28 Nov 2023 08:37:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1701160678; x=1732696678; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=4KJEiYAIubEfzD6NpBfjeJy7I986/mMPqLI3Gu/8jbM=; b=bRCZkossCjLXzYSZRJDBJ2ouqW5AwWd/KSWAOlJlJWWrps+Xn376OyKE GXP/wml+V8FIzJU3fMzSC0LbaKY7OXzDWADYzLbja4giWnwJ5loqMBuBw +EH/9RF88l1+qL5hEaUKMJ66YEt2Y7GnL/UuE+HKJAP0TMOsxWXrMvotk 2WVr/rWXqGLRyX34wj+OQIJNC25wNDzTze5u1Ewwz6CvMvKI+jgTI2s4F Xc0Z1UB79QBcyFTy6LjrH8cFlG/YJ90cxxVEQ4Q6Uo2zY5EIyl0QxTlRq qotqbLxxjAnC3sYiFG48FRderDsY87ljXMS9DO6Fzd49fqSIkI6sGo2h1 Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10907"; a="459381745" X-IronPort-AV: E=Sophos;i="6.04,233,1695711600"; d="scan'208";a="459381745" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Nov 2023 00:37:58 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10907"; a="834577654" X-IronPort-AV: E=Sophos;i="6.04,233,1695711600"; d="scan'208";a="834577654" Received: from unknown (HELO slisovsk-Lenovo-ideapad-720S-13IKB.fi.intel.com) ([10.237.72.65]) by fmsmga008.fm.intel.com with ESMTP; 28 Nov 2023 00:37:56 -0800 From: Stanislav Lisovskiy To: intel-gfx@lists.freedesktop.org Date: Tue, 28 Nov 2023 10:37:52 +0200 Message-Id: <20231128083754.20096-2-stanislav.lisovskiy@intel.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20231128083754.20096-1-stanislav.lisovskiy@intel.com> References: <20231128083754.20096-1-stanislav.lisovskiy@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 1/3] drm/i915: Add meaningful traces for QGV point info error handling X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" For debug purposes we need those - error path won't flood the log, however there has been already numerous cases, when due to lack of debugs, we couldn't immediately tell what was the problem on customer machine, which slowed down the investigation, requiring to get access to target device and adding those traces manually. Signed-off-by: Stanislav Lisovskiy --- drivers/gpu/drm/i915/display/intel_bw.c | 4 +++- drivers/gpu/drm/i915/soc/intel_dram.c | 2 ++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c index bef96db62c80..583cd2ebdf89 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.c +++ b/drivers/gpu/drm/i915/display/intel_bw.c @@ -289,8 +289,10 @@ static int icl_get_qgv_points(struct drm_i915_private *dev_priv, struct intel_qgv_point *sp = &qi->points[i]; ret = intel_read_qgv_point_info(dev_priv, sp, i); - if (ret) + if (ret) { + drm_dbg_kms(&dev_priv->drm, "Could not read QGV %d info\n", i); return ret; + } drm_dbg_kms(&dev_priv->drm, "QGV %d: DCLK=%d tRP=%d tRDPRE=%d tRAS=%d tRCD=%d tRC=%d\n", diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c b/drivers/gpu/drm/i915/soc/intel_dram.c index 15492b69f698..37d61dff50a8 100644 --- a/drivers/gpu/drm/i915/soc/intel_dram.c +++ b/drivers/gpu/drm/i915/soc/intel_dram.c @@ -647,6 +647,8 @@ static int xelpdp_get_dram_info(struct drm_i915_private *i915) dram_info->num_channels = REG_FIELD_GET(MTL_N_OF_POPULATED_CH_MASK, val); dram_info->num_qgv_points = REG_FIELD_GET(MTL_N_OF_ENABLED_QGV_POINTS_MASK, val); + drm_dbg_kms(&i915->drm, "Num qgv points from MTL_N_OF_ENABLED_QGV_POINTS_MASK reg: %d\n", + dram_info->num_qgv_points); /* PSF GV points not supported in D14+ */ return 0; From patchwork Tue Nov 28 08:37:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanislav Lisovskiy X-Patchwork-Id: 13470645 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C2903C4167B for ; Tue, 28 Nov 2023 08:38:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A88DC10E156; Tue, 28 Nov 2023 08:38:01 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8248E10E156 for ; Tue, 28 Nov 2023 08:38:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1701160680; x=1732696680; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=TKE+dXvqVmY79Mf5GY4NTEXCADBoMtdJSgMoqQmRvhE=; b=jx1KJY4ZWVLXSgOJy/JBP7AQsudDtUgjmFWMxAGRuocKsJGKnQdD/Xwh BW71n4oKusNXmD3MQM8XR92lg8HTNgppugLJ56fA49HHHFeniAq4GPdg0 /qV1vmbDsi25Ltgr/LJrph432GgEUBwD484YFj8ynWNQIiw6RZtgE/tVP qFHhvClLkb76pEF1W3PwsEbHdmCBIV7xi8WBSNi04/I52XDg1v/F9XVlu VsAO462Xv3RNDLkQ3gpoUuJ8cj1F9kvIKlAfgQopjw2ZHKJqSrI35x1AD mjmP5DEBcmyiJHK/za8dpzZKlbU1eQUf6YxOQFe4nLzaGcouF8f+hl4Io w==; X-IronPort-AV: E=McAfee;i="6600,9927,10907"; a="459381750" X-IronPort-AV: E=Sophos;i="6.04,233,1695711600"; d="scan'208";a="459381750" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Nov 2023 00:38:00 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10907"; a="834577660" X-IronPort-AV: E=Sophos;i="6.04,233,1695711600"; d="scan'208";a="834577660" Received: from unknown (HELO slisovsk-Lenovo-ideapad-720S-13IKB.fi.intel.com) ([10.237.72.65]) by fmsmga008.fm.intel.com with ESMTP; 28 Nov 2023 00:37:58 -0800 From: Stanislav Lisovskiy To: intel-gfx@lists.freedesktop.org Date: Tue, 28 Nov 2023 10:37:53 +0200 Message-Id: <20231128083754.20096-3-stanislav.lisovskiy@intel.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20231128083754.20096-1-stanislav.lisovskiy@intel.com> References: <20231128083754.20096-1-stanislav.lisovskiy@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/3] drm/i915: Extract code required to calculate max qgv/psf gv point X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" We need that in order to force disable SAGV in next patch. Also it is beneficial to separate that code, as in majority cases, when SAGV is enabled, we don't even need those calculations. Also we probably need to determine max PSF GV point as well, however currently we don't do that when we disable SAGV, which might be actually causing some issues in that case. Signed-off-by: Stanislav Lisovskiy --- drivers/gpu/drm/i915/display/intel_bw.c | 82 ++++++++++++++++++++----- 1 file changed, 65 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c index 583cd2ebdf89..efd408e96e8a 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.c +++ b/drivers/gpu/drm/i915/display/intel_bw.c @@ -805,6 +805,64 @@ intel_atomic_get_bw_state(struct intel_atomic_state *state) return to_intel_bw_state(bw_state); } +static unsigned int icl_max_bw_qgv_point(struct drm_i915_private *i915, + int num_active_planes) +{ + unsigned int max_bw_point = 0; + unsigned int max_bw = 0; + unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points; + int i; + + for (i = 0; i < num_qgv_points; i++) { + unsigned int idx; + unsigned int max_data_rate; + + if (DISPLAY_VER(i915) > 11) + idx = tgl_max_bw_index(i915, num_active_planes, i); + else + idx = icl_max_bw_index(i915, num_active_planes, i); + + if (idx >= ARRAY_SIZE(i915->display.bw.max)) + continue; + + max_data_rate = i915->display.bw.max[idx].deratedbw[i]; + + /* + * We need to know which qgv point gives us + * maximum bandwidth in order to disable SAGV + * if we find that we exceed SAGV block time + * with watermarks. By that moment we already + * have those, as it is calculated earlier in + * intel_atomic_check, + */ + if (max_data_rate > max_bw) { + max_bw_point = i; + max_bw = max_data_rate; + } + } + + return max_bw_point; +} + +unsigned int icl_max_bw_psf_gv_point(struct drm_i915_private *i915) +{ + unsigned int num_psf_gv_points = i915->display.bw.max[0].num_psf_gv_points; + unsigned int max_bw = 0; + unsigned int max_bw_point = 0; + int i; + + for (i = 0; i < num_psf_gv_points; i++) { + unsigned int max_data_rate = adl_psf_bw(i915, i); + + if (max_data_rate > max_bw) { + max_bw_point = i; + max_bw = max_data_rate; + } + } + + return max_bw_point; +} + static int mtl_find_qgv_points(struct drm_i915_private *i915, unsigned int data_rate, unsigned int num_active_planes, @@ -882,8 +940,6 @@ static int icl_find_qgv_points(struct drm_i915_private *i915, const struct intel_bw_state *old_bw_state, struct intel_bw_state *new_bw_state) { - unsigned int max_bw_point = 0; - unsigned int max_bw = 0; unsigned int num_psf_gv_points = i915->display.bw.max[0].num_psf_gv_points; unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points; u16 psf_points = 0; @@ -909,18 +965,6 @@ static int icl_find_qgv_points(struct drm_i915_private *i915, max_data_rate = i915->display.bw.max[idx].deratedbw[i]; - /* - * We need to know which qgv point gives us - * maximum bandwidth in order to disable SAGV - * if we find that we exceed SAGV block time - * with watermarks. By that moment we already - * have those, as it is calculated earlier in - * intel_atomic_check, - */ - if (max_data_rate > max_bw) { - max_bw_point = i; - max_bw = max_data_rate; - } if (max_data_rate >= data_rate) qgv_points |= BIT(i); @@ -964,9 +1008,13 @@ static int icl_find_qgv_points(struct drm_i915_private *i915, * cause. */ if (!intel_can_enable_sagv(i915, new_bw_state)) { - qgv_points = BIT(max_bw_point); - drm_dbg_kms(&i915->drm, "No SAGV, using single QGV point %d\n", - max_bw_point); + unsigned int max_bw_qgv_point = icl_max_bw_qgv_point(i915, num_active_planes); + unsigned int max_bw_psf_gv_point = icl_max_bw_psf_gv_point(i915); + + qgv_points = BIT(max_bw_qgv_point); + psf_points = BIT(max_bw_psf_gv_point); + drm_dbg_kms(&i915->drm, "No SAGV, using single QGV point %d PSF GV point %d\n", + max_bw_qgv_point, max_bw_psf_gv_point); } /* From patchwork Tue Nov 28 08:37:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanislav Lisovskiy X-Patchwork-Id: 13470647 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CCEDBC4167B for ; Tue, 28 Nov 2023 08:38:09 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3F71110E455; Tue, 28 Nov 2023 08:38:09 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4353610E454 for ; Tue, 28 Nov 2023 08:38:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1701160682; x=1732696682; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=86LRF4TxVKnHnZ/xhcwCU5xc3pv3vC1u+tEhtJD6YSs=; b=bDhCmPVQ5NVAHLU6LFmZOhNFE9F5QUSL2dFL9Rvz4FSsFLTMsNbGDYyy JLlb5GX0RuJUfY0+x30Mxw/qa68jPRjNIQu9QRceO+Q0JhQSYAYbQjySb 4SIcDVboByJH3eVyfmasn0t6Z9jwrN5nh4JERSjqEZ39f539SDouyMqRx ihp+f8G4HJ8Wemvh523rw0rMvscj8llNwTZVOHS9DRy9mj9zJVEKRpGNr +VnF4DJ4zXMbf5jmpIzHuZF4x8evSzAcYcHDBc279ac4zujoh0n/hPb2v 1e2KFGWTMgq2XLCUxmfzegNrecoJ4rDU//4MQMmVpvHBNOaFIwAI0NW+/ g==; X-IronPort-AV: E=McAfee;i="6600,9927,10907"; a="459381758" X-IronPort-AV: E=Sophos;i="6.04,233,1695711600"; d="scan'208";a="459381758" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Nov 2023 00:38:02 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10907"; a="834577666" X-IronPort-AV: E=Sophos;i="6.04,233,1695711600"; d="scan'208";a="834577666" Received: from unknown (HELO slisovsk-Lenovo-ideapad-720S-13IKB.fi.intel.com) ([10.237.72.65]) by fmsmga008.fm.intel.com with ESMTP; 28 Nov 2023 00:38:00 -0800 From: Stanislav Lisovskiy To: intel-gfx@lists.freedesktop.org Date: Tue, 28 Nov 2023 10:37:54 +0200 Message-Id: <20231128083754.20096-4-stanislav.lisovskiy@intel.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20231128083754.20096-1-stanislav.lisovskiy@intel.com> References: <20231128083754.20096-1-stanislav.lisovskiy@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 3/3] drm/i915: Disable SAGV on bw init, to force QGV point recalculation X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Problem is that on some platforms, we do get QGV point mask in wrong state on boot. However driver assumes it is set to 0 (i.e all points allowed), however in reality we might get them all restricted, causing issues. Lets disable SAGV initially to force proper QGV point state. If more QGV points are available, driver will recalculate and update those then after next commit. Signed-off-by: Stanislav Lisovskiy --- drivers/gpu/drm/i915/display/intel_bw.c | 20 +++++++++++++++++++- drivers/gpu/drm/i915/display/intel_bw.h | 1 + 2 files changed, 20 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c index efd408e96e8a..f23f9f952de3 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.c +++ b/drivers/gpu/drm/i915/display/intel_bw.c @@ -679,6 +679,9 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv) tgl_get_bw_info(dev_priv, &tgl_sa_info); else if (DISPLAY_VER(dev_priv) == 11) icl_get_bw_info(dev_priv, &icl_sa_info); + + if (DISPLAY_VER(dev_priv) < 14) + icl_force_disable_sagv(dev_priv); } static unsigned int intel_bw_crtc_num_active_planes(const struct intel_crtc_state *crtc_state) @@ -844,7 +847,7 @@ static unsigned int icl_max_bw_qgv_point(struct drm_i915_private *i915, return max_bw_point; } -unsigned int icl_max_bw_psf_gv_point(struct drm_i915_private *i915) +static unsigned int icl_max_bw_psf_gv_point(struct drm_i915_private *i915) { unsigned int num_psf_gv_points = i915->display.bw.max[0].num_psf_gv_points; unsigned int max_bw = 0; @@ -863,6 +866,21 @@ unsigned int icl_max_bw_psf_gv_point(struct drm_i915_private *i915) return max_bw_point; } +int icl_force_disable_sagv(struct drm_i915_private *i915) +{ + unsigned int max_bw_qgv_point = icl_max_bw_qgv_point(i915, 0); + unsigned int max_bw_psf_gv_point = icl_max_bw_psf_gv_point(i915); + unsigned int qgv_points; + unsigned int psf_points; + + qgv_points = BIT(max_bw_qgv_point); + psf_points = BIT(max_bw_psf_gv_point); + + return icl_pcode_restrict_qgv_points(i915, ~(ICL_PCODE_REQ_QGV_PT(qgv_points) | + ADLS_PCODE_REQ_PSF_PT(psf_points)) & + icl_qgv_points_mask(i915)); +} + static int mtl_find_qgv_points(struct drm_i915_private *i915, unsigned int data_rate, unsigned int num_active_planes, diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h index 59cb4fc5db76..74acce1ef107 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.h +++ b/drivers/gpu/drm/i915/display/intel_bw.h @@ -74,5 +74,6 @@ int intel_bw_calc_min_cdclk(struct intel_atomic_state *state, bool *need_cdclk_calc); int intel_bw_min_cdclk(struct drm_i915_private *i915, const struct intel_bw_state *bw_state); +int icl_force_disable_sagv(struct drm_i915_private *dev_priv); #endif /* __INTEL_BW_H__ */