From patchwork Tue Nov 28 14:56:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 13471317 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="Ac1l3+8S" Received: from mail-pl1-x632.google.com (mail-pl1-x632.google.com [IPv6:2607:f8b0:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6DAFB170B for ; Tue, 28 Nov 2023 06:56:42 -0800 (PST) Received: by mail-pl1-x632.google.com with SMTP id d9443c01a7336-1cf7a8ab047so42855595ad.1 for ; Tue, 28 Nov 2023 06:56:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1701183402; x=1701788202; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PbBabCqpKOAriwFvw90VUy4f2fqStiwMYR6pxTnYCDM=; b=Ac1l3+8SMVmRHWMcbKGDXqQniiLC2yjJ9swRquTj8EHPOxQKb9d4oY32DZ/oD4uoUN vsfO6iWevn0b/suFCCZKDv/pfHBo84t/EQgNyDrUv0ISjtF6hg2CJUrOqCzYJ9mP+MyP WjRJKt+RAHg4KbVTNbh/qJt1fZz/jMEWgSKHpt84Z4+i8fGlOVob6ju48ZhSeHCaBYFo aVEYXQv6XGVmkbCmXyH4KFnOCxgYCRKIsi9ITXfIFDe8/45M/+86VSz7TrxM1DiHsFTy LPl9Zw9SI8+x1foD9FQWLALAKz7cdtZA7R3p2dUJORdXWP0D5ILvt7c+eBbk86d4QcZX cyvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701183402; x=1701788202; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PbBabCqpKOAriwFvw90VUy4f2fqStiwMYR6pxTnYCDM=; b=LbJPq5T568O89+zsGLv5f3lWWdf9GOHOwIb7segm17ZWt6ypc9AD1ljNI4VyB7rXuT U7rqGL3PDSNvybCsNkUkieb2C08cE9P/5oUnDnCDDuf04SJQClDjvXV1oABc+GeIZTtE 0FQJ8E3uiA2YZyNoo0E3wWNj0cSI0YQx/b4UirU4VvSlWC35S/dQQn30BWhfWRwRPVDJ Hs7qIY3fsHxkErsRcZ4t8ozTOMLOJKu485DJ6mZPo8jIpENrU6uxrLOI7c3IMLfYQNP5 Q++jEz1waa7YCN114yPpt95D5eua4lzRLv4ydUGRw3ayU2FsrhUvkcFoJtxaGB0CUHaq QV2A== X-Gm-Message-State: AOJu0YzN9DzJ/az+doxpAfSNLL+pG4S7VF4yJmt2KzQ/llmIfjVr/l71 Ab4QGzZupipGr/Qkh+3f/KB7xA== X-Google-Smtp-Source: AGHT+IFF37L7mMJpBw0n+wS2iRyFYetjeJokx3+I/4QyQ+stNQxHarf0QWVq5euPcDcRmpAXeUet0g== X-Received: by 2002:a17:902:d38d:b0:1cf:a4e8:d2a1 with SMTP id e13-20020a170902d38d00b001cfa4e8d2a1mr13329156pld.42.1701183401668; Tue, 28 Nov 2023 06:56:41 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id j1-20020a170902c08100b001ab39cd875csm9023580pld.133.2023.11.28.06.56.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Nov 2023 06:56:41 -0800 (PST) From: Anup Patel To: Will Deacon , julien.thierry.kdev@gmail.com, maz@kernel.org Cc: Paolo Bonzini , Atish Patra , Andrew Jones , Anup Patel , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Anup Patel Subject: [kvmtool PATCH 01/10] Sync-up header with Linux-6.7-rc3 for KVM RISC-V Date: Tue, 28 Nov 2023 20:26:19 +0530 Message-Id: <20231128145628.413414-2-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231128145628.413414-1-apatel@ventanamicro.com> References: <20231128145628.413414-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 We sync-up Linux headers to get latest KVM RISC-V headers having Zba, Zbs, Zicntr, Zifencei, Zihpm, Smstateen, XVentanaCondOps Zicond, and SBI DBCN support. Signed-off-by: Anup Patel --- arm/aarch64/include/asm/kvm.h | 32 ++++++++++++++++++++++++++++++++ include/linux/kvm.h | 11 +++++++++++ include/linux/virtio_config.h | 5 +++++ include/linux/virtio_pci.h | 11 +++++++++++ riscv/include/asm/kvm.h | 12 ++++++++++++ 5 files changed, 71 insertions(+) diff --git a/arm/aarch64/include/asm/kvm.h b/arm/aarch64/include/asm/kvm.h index f7ddd73..89d2fc8 100644 --- a/arm/aarch64/include/asm/kvm.h +++ b/arm/aarch64/include/asm/kvm.h @@ -505,6 +505,38 @@ struct kvm_smccc_filter { #define KVM_HYPERCALL_EXIT_SMC (1U << 0) #define KVM_HYPERCALL_EXIT_16BIT (1U << 1) +/* + * Get feature ID registers userspace writable mask. + * + * From DDI0487J.a, D19.2.66 ("ID_AA64MMFR2_EL1, AArch64 Memory Model + * Feature Register 2"): + * + * "The Feature ID space is defined as the System register space in + * AArch64 with op0==3, op1=={0, 1, 3}, CRn==0, CRm=={0-7}, + * op2=={0-7}." + * + * This covers all currently known R/O registers that indicate + * anything useful feature wise, including the ID registers. + * + * If we ever need to introduce a new range, it will be described as + * such in the range field. + */ +#define KVM_ARM_FEATURE_ID_RANGE_IDX(op0, op1, crn, crm, op2) \ + ({ \ + __u64 __op1 = (op1) & 3; \ + __op1 -= (__op1 == 3); \ + (__op1 << 6 | ((crm) & 7) << 3 | (op2)); \ + }) + +#define KVM_ARM_FEATURE_ID_RANGE 0 +#define KVM_ARM_FEATURE_ID_RANGE_SIZE (3 * 8 * 8) + +struct reg_mask_range { + __u64 addr; /* Pointer to mask array */ + __u32 range; /* Requested range */ + __u32 reserved[13]; +}; + #endif #endif /* __ARM_KVM_H__ */ diff --git a/include/linux/kvm.h b/include/linux/kvm.h index 13065dd..211b86d 100644 --- a/include/linux/kvm.h +++ b/include/linux/kvm.h @@ -264,6 +264,7 @@ struct kvm_xen_exit { #define KVM_EXIT_RISCV_SBI 35 #define KVM_EXIT_RISCV_CSR 36 #define KVM_EXIT_NOTIFY 37 +#define KVM_EXIT_LOONGARCH_IOCSR 38 /* For KVM_EXIT_INTERNAL_ERROR */ /* Emulate instruction failed. */ @@ -336,6 +337,13 @@ struct kvm_run { __u32 len; __u8 is_write; } mmio; + /* KVM_EXIT_LOONGARCH_IOCSR */ + struct { + __u64 phys_addr; + __u8 data[8]; + __u32 len; + __u8 is_write; + } iocsr_io; /* KVM_EXIT_HYPERCALL */ struct { __u64 nr; @@ -1192,6 +1200,7 @@ struct kvm_ppc_resize_hpt { #define KVM_CAP_COUNTER_OFFSET 227 #define KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE 228 #define KVM_CAP_ARM_SUPPORTED_BLOCK_SIZES 229 +#define KVM_CAP_ARM_SUPPORTED_REG_MASK_RANGES 230 #ifdef KVM_CAP_IRQ_ROUTING @@ -1362,6 +1371,7 @@ struct kvm_dirty_tlb { #define KVM_REG_ARM64 0x6000000000000000ULL #define KVM_REG_MIPS 0x7000000000000000ULL #define KVM_REG_RISCV 0x8000000000000000ULL +#define KVM_REG_LOONGARCH 0x9000000000000000ULL #define KVM_REG_SIZE_SHIFT 52 #define KVM_REG_SIZE_MASK 0x00f0000000000000ULL @@ -1562,6 +1572,7 @@ struct kvm_s390_ucas_mapping { #define KVM_ARM_MTE_COPY_TAGS _IOR(KVMIO, 0xb4, struct kvm_arm_copy_mte_tags) /* Available with KVM_CAP_COUNTER_OFFSET */ #define KVM_ARM_SET_COUNTER_OFFSET _IOW(KVMIO, 0xb5, struct kvm_arm_counter_offset) +#define KVM_ARM_GET_REG_WRITABLE_MASKS _IOR(KVMIO, 0xb6, struct reg_mask_range) /* ioctl for vm fd */ #define KVM_CREATE_DEVICE _IOWR(KVMIO, 0xe0, struct kvm_create_device) diff --git a/include/linux/virtio_config.h b/include/linux/virtio_config.h index 2c712c6..8881aea 100644 --- a/include/linux/virtio_config.h +++ b/include/linux/virtio_config.h @@ -105,6 +105,11 @@ */ #define VIRTIO_F_NOTIFICATION_DATA 38 +/* This feature indicates that the driver uses the data provided by the device + * as a virtqueue identifier in available buffer notifications. + */ +#define VIRTIO_F_NOTIF_CONFIG_DATA 39 + /* * This feature indicates that the driver can reset a queue individually. */ diff --git a/include/linux/virtio_pci.h b/include/linux/virtio_pci.h index f703afc..44f4dd2 100644 --- a/include/linux/virtio_pci.h +++ b/include/linux/virtio_pci.h @@ -166,6 +166,17 @@ struct virtio_pci_common_cfg { __le32 queue_used_hi; /* read-write */ }; +/* + * Warning: do not use sizeof on this: use offsetofend for + * specific fields you need. + */ +struct virtio_pci_modern_common_cfg { + struct virtio_pci_common_cfg cfg; + + __le16 queue_notify_data; /* read-write */ + __le16 queue_reset; /* read-write */ +}; + /* Fields in VIRTIO_PCI_CAP_PCI_CFG: */ struct virtio_pci_cfg_cap { struct virtio_pci_cap cap; diff --git a/riscv/include/asm/kvm.h b/riscv/include/asm/kvm.h index 992c5e4..60d3b21 100644 --- a/riscv/include/asm/kvm.h +++ b/riscv/include/asm/kvm.h @@ -80,6 +80,7 @@ struct kvm_riscv_csr { unsigned long sip; unsigned long satp; unsigned long scounteren; + unsigned long senvcfg; }; /* AIA CSR registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ @@ -93,6 +94,11 @@ struct kvm_riscv_aia_csr { unsigned long iprio2h; }; +/* Smstateen CSR for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ +struct kvm_riscv_smstateen_csr { + unsigned long sstateen0; +}; + /* TIMER registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ struct kvm_riscv_timer { __u64 frequency; @@ -131,6 +137,8 @@ enum KVM_RISCV_ISA_EXT_ID { KVM_RISCV_ISA_EXT_ZICSR, KVM_RISCV_ISA_EXT_ZIFENCEI, KVM_RISCV_ISA_EXT_ZIHPM, + KVM_RISCV_ISA_EXT_SMSTATEEN, + KVM_RISCV_ISA_EXT_ZICOND, KVM_RISCV_ISA_EXT_MAX, }; @@ -148,6 +156,7 @@ enum KVM_RISCV_SBI_EXT_ID { KVM_RISCV_SBI_EXT_PMU, KVM_RISCV_SBI_EXT_EXPERIMENTAL, KVM_RISCV_SBI_EXT_VENDOR, + KVM_RISCV_SBI_EXT_DBCN, KVM_RISCV_SBI_EXT_MAX, }; @@ -178,10 +187,13 @@ enum KVM_RISCV_SBI_EXT_ID { #define KVM_REG_RISCV_CSR (0x03 << KVM_REG_RISCV_TYPE_SHIFT) #define KVM_REG_RISCV_CSR_GENERAL (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT) #define KVM_REG_RISCV_CSR_AIA (0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT) +#define KVM_REG_RISCV_CSR_SMSTATEEN (0x2 << KVM_REG_RISCV_SUBTYPE_SHIFT) #define KVM_REG_RISCV_CSR_REG(name) \ (offsetof(struct kvm_riscv_csr, name) / sizeof(unsigned long)) #define KVM_REG_RISCV_CSR_AIA_REG(name) \ (offsetof(struct kvm_riscv_aia_csr, name) / sizeof(unsigned long)) +#define KVM_REG_RISCV_CSR_SMSTATEEN_REG(name) \ + (offsetof(struct kvm_riscv_smstateen_csr, name) / sizeof(unsigned long)) /* Timer registers are mapped as type 4 */ #define KVM_REG_RISCV_TIMER (0x04 << KVM_REG_RISCV_TYPE_SHIFT) From patchwork Tue Nov 28 14:56:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 13471318 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="nzAQpPBi" Received: from mail-pl1-x62c.google.com (mail-pl1-x62c.google.com [IPv6:2607:f8b0:4864:20::62c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5E55819A4 for ; Tue, 28 Nov 2023 06:56:46 -0800 (PST) Received: by mail-pl1-x62c.google.com with SMTP id d9443c01a7336-1cf89df1eecso38564415ad.3 for ; Tue, 28 Nov 2023 06:56:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1701183406; x=1701788206; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rzvuCYvNDC4WAU9MiwvqT5G+x/uZAqkiyqUofd5JUWM=; b=nzAQpPBiBKviHGQAF6uedXqKC8F7Wx2NSmPgTNIynolMrXnaYwsUy4C+cz9BKBLpjR luK766NDlr4ARb8140s8MkJYZTY4sMhrFNG5ZHHHdlU64LEtbfYtq610kXXWabBdPslC 2ols6tMhdyQMCaGV+noUiMXIovLHdfII5WxO96cD/nlm3Y2xWBuxwrLqCVz0rIebXLCR PSWMdbNvpuFxzeQejgJyc5kvYivUURvdyqd6Rwz/4nZqsy/dqXIhU+bYr4lAQuLxBQgb MR9ZvyUXUA+3msC1e0UsHyWAp3Fz6BJKUlz2peOa1AzQPXOMtmbdM8l08qR8yudHoFub AATA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701183406; x=1701788206; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rzvuCYvNDC4WAU9MiwvqT5G+x/uZAqkiyqUofd5JUWM=; b=GHmHYHcZ0Y9eM9faBcEuYDXtV3Dz0oSk9jf+6Tifp04UD+E9l9xejdywkEx7ov1uxB 8devibuuedR27/UlHN/VF0nsFi8u26ZZ6rk+VuPD+HjRhc8hhez2XbXwFsC27M3qiLva 05pUDSB1CvjLuCtFFt50O4QVb9jQoOR778z0lKoRQe7a0ciNOFRDaZ+8UvGuAul5UiK6 e2i6uc7vKsv4Kqfws+YjOGbKREw/EWHBZXt70lsasDVEB2KqbLYZ8TUyRupHEAsUBJ/c NHBmqj2YhAQiM/Kyf8ERqOctoBImcTsd5TE7jpJCWBSkSxivzUI8QOOiRSK9xW7FSxu0 wsMg== X-Gm-Message-State: AOJu0YyrgY7+5IM0CM7P7HKXz95TiS0ujhLeejtv1O7FTXjaNpk2Speq wYnJKMjTBEpKkloQGg6HixskaQ== X-Google-Smtp-Source: AGHT+IFHabpA9QTBC99zG/ypygFsL3wJdocwojvWfvQDhDg9U7Uo3wdVa1mMxoziBAAenignp4vJfQ== X-Received: by 2002:a17:903:1103:b0:1ce:6312:537c with SMTP id n3-20020a170903110300b001ce6312537cmr15885985plh.10.1701183405740; Tue, 28 Nov 2023 06:56:45 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id j1-20020a170902c08100b001ab39cd875csm9023580pld.133.2023.11.28.06.56.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Nov 2023 06:56:45 -0800 (PST) From: Anup Patel To: Will Deacon , julien.thierry.kdev@gmail.com, maz@kernel.org Cc: Paolo Bonzini , Atish Patra , Andrew Jones , Anup Patel , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Anup Patel Subject: [kvmtool PATCH 02/10] riscv: Improve warning in generate_cpu_nodes() Date: Tue, 28 Nov 2023 20:26:20 +0530 Message-Id: <20231128145628.413414-3-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231128145628.413414-1-apatel@ventanamicro.com> References: <20231128145628.413414-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Let's print name of the ISA extension in warning if generate_cpu_nodes() drops the ISA extension from generated ISA string due to lack of space. Signed-off-by: Anup Patel --- riscv/fdt.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/riscv/fdt.c b/riscv/fdt.c index 9af71b5..b45f731 100644 --- a/riscv/fdt.c +++ b/riscv/fdt.c @@ -108,7 +108,8 @@ static void generate_cpu_nodes(void *fdt, struct kvm *kvm) } if ((strlen(isa_info_arr[i].name) + pos + 1) >= CPU_ISA_MAX_LEN) { - pr_warning("Insufficient space to append ISA exension\n"); + pr_warning("Insufficient space to append ISA exension %s\n", + isa_info_arr[i].name); break; } pos += snprintf(cpu_isa + pos, CPU_ISA_MAX_LEN, "_%s", From patchwork Tue Nov 28 14:56:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 13471319 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="QJz/2YdX" Received: from mail-pl1-x633.google.com (mail-pl1-x633.google.com [IPv6:2607:f8b0:4864:20::633]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C58F91BD1 for ; Tue, 28 Nov 2023 06:56:50 -0800 (PST) Received: by mail-pl1-x633.google.com with SMTP id d9443c01a7336-1ce3084c2d1so46216965ad.3 for ; Tue, 28 Nov 2023 06:56:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1701183410; x=1701788210; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FgjoNrqFDNIe7ian9OPihopZ/0iJ0MZOML4kaPf+Pyw=; b=QJz/2YdX5Lv/5MpohPVnL9WoC//yB/cDdP47e19mbOKkAgtNUF+p6oHE17n7LwjMEq 93l5iy8JgR+ao4VfVxrSL3UuKTlmeFcJnqpCZ5mBvnxko3vH6wr9SwFA8i1Q4lQE7W4D IIL5eQLYTzUEsRgoDcTMeVf+TrV4kEkfHKgZMy/otmUHXNh1SKfwJ7RMKXVI5k1Fs53S HS3WNznxmjEc25tEG2Yfj117Be0ul0CHeoswA0x9kDLYYmrX5MO9N6aVJZAb0lHcuP7C I6sG640XNfG20RhE4oGfshgBGgP7plf7l6oPtz4DaTpRkd65NVmtl5p6wvq+yVlXUxH3 gKaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701183410; x=1701788210; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FgjoNrqFDNIe7ian9OPihopZ/0iJ0MZOML4kaPf+Pyw=; b=liOXFlLTee4osiihGCWePiK04trYZ7zuVmMxbX5V8T9bIVmDO08W1/RHUG0GG3mAP+ kwrREAjxL9j0Ct+RpmtrmkEmE5OIGZlaXNkyzsFDkQ7bECqc0KIKdHqndJA2N2k9XErm CTEsOjYcY6Rq2JTPLPmTS+UFyHUQWUqzG/MEai3GSVqtbyAbevv9xhXWpCkjgXS7BFds 8zqgqXifVDtumLGV8jvIyFtohbpcTjfg/5AlUC+3zJ60GOwALI9AyL93W/WqfmekK9dw UKJNqa5PULLqpbpTuzSIvZeJtg92yI4fCZx9vWz7/YjfCJQtqyBgtG9G7myd8ZnmDxSQ 0GXg== X-Gm-Message-State: AOJu0Yznk9B4gZ9We6y0qcvCqciuoklCbIrONiVPG5oNSi8Ajc3SYsLk ivZtSSOKes+MnpMupGi/S1FrBA== X-Google-Smtp-Source: AGHT+IHgigFZ6pNkcrRyi5Kih3JjvCGjjnKNVK7ixGDK5KkCRRVdCD8e5XtNe/xEko9S/RpSC6SLuw== X-Received: by 2002:a17:902:f64d:b0:1cf:61c8:73e9 with SMTP id m13-20020a170902f64d00b001cf61c873e9mr21345331plg.50.1701183410129; Tue, 28 Nov 2023 06:56:50 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id j1-20020a170902c08100b001ab39cd875csm9023580pld.133.2023.11.28.06.56.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Nov 2023 06:56:49 -0800 (PST) From: Anup Patel To: Will Deacon , julien.thierry.kdev@gmail.com, maz@kernel.org Cc: Paolo Bonzini , Atish Patra , Andrew Jones , Anup Patel , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Anup Patel Subject: [kvmtool PATCH 03/10] riscv: Make CPU_ISA_MAX_LEN depend upon isa_info_arr array size Date: Tue, 28 Nov 2023 20:26:21 +0530 Message-Id: <20231128145628.413414-4-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231128145628.413414-1-apatel@ventanamicro.com> References: <20231128145628.413414-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Currently, the CPU_ISA_MAX_LEN is a fixed value so we will easily run out of space when all possible ISA extensions supported by KVM RISC-V are available. Instead of above, let us make CPU_ISA_MAX_LEN depend upon the isa_info_arr[] array size so that CPU_ISA_MAX_LEN automatically adapts to growing number of ISA extensions. Signed-off-by: Anup Patel --- riscv/fdt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/riscv/fdt.c b/riscv/fdt.c index b45f731..230d1f8 100644 --- a/riscv/fdt.c +++ b/riscv/fdt.c @@ -44,7 +44,6 @@ static void dump_fdt(const char *dtb_file, void *fdt) } #define CPU_NAME_MAX_LEN 15 -#define CPU_ISA_MAX_LEN 128 static void generate_cpu_nodes(void *fdt, struct kvm *kvm) { int cpu, pos, i, index, valid_isa_len; @@ -60,6 +59,7 @@ static void generate_cpu_nodes(void *fdt, struct kvm *kvm) for (cpu = 0; cpu < kvm->nrcpus; ++cpu) { char cpu_name[CPU_NAME_MAX_LEN]; +#define CPU_ISA_MAX_LEN (ARRAY_SIZE(isa_info_arr) * 16) char cpu_isa[CPU_ISA_MAX_LEN]; struct kvm_cpu *vcpu = kvm->cpus[cpu]; struct kvm_one_reg reg; From patchwork Tue Nov 28 14:56:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 13471320 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="MREn/27x" Received: from mail-pl1-x62a.google.com (mail-pl1-x62a.google.com [IPv6:2607:f8b0:4864:20::62a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EF14510C1 for ; Tue, 28 Nov 2023 06:56:54 -0800 (PST) Received: by mail-pl1-x62a.google.com with SMTP id d9443c01a7336-1cfc2d03b3aso19333565ad.1 for ; Tue, 28 Nov 2023 06:56:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1701183414; x=1701788214; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=d0zuXKCmA/fCwgVtEEggMd6l7hk0jdC/LhoPoNgdg+I=; b=MREn/27xkqfj8iFU7xESUbYI4OKjPrxXq4CP3i9nF5F908CF72kotDwj+wHkT03irI vkSp4/7wFMiNbrDlHn8yvFnfe8bPb+4dXAjzp/GSWxmsrmhr0zHcy/fBOteY5haf0lcb x3L5X2o0Qw72k7kdmFWAODSTY5ImbenJJ5h2hnwA7uwFzgw1Holb+ClEAlr8GdKZQYNx MopptGtYln6iH8PQNEKrK55q9dMUaqOZ6CAZ/98O1oZzxq5DLf6LLvyHeAXbV/CP5z8C 5oTkM0CV3E25rqZwtobZwy60/8w9YOlrCNTNR692xbsW1ydaUMRPtvPodZfo062VMhuT ZwPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701183414; x=1701788214; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=d0zuXKCmA/fCwgVtEEggMd6l7hk0jdC/LhoPoNgdg+I=; b=astqgqXnKtdcPSbDIGAP+oqGvbHCwkGTMQ4a6S56fngsDHy7RFoRmFOZs/XMaw6iYY AMbLKuxzjDBQmqsMsXFLraO/W/bVKAzyziUiUL9GXNF0Bwlo3ipxh7U0jPQzmvbT7OeV DwPcMm7QiKPS1VWuoe9+2ix+xjgxBmqd789SRHc5ElW3xXXcnel7DlqC6WNdKov18wtb 36e24z34bA0kjLeVRx6MITq3MHp7wjQ9U/zZXEVyGbcFrGhDoiNm5ppPDIghGrf386bW vo6J+eqeYYoaUyo44aPB+/Lrk3Sn6J7ivp1ugrfWeC91EhUzvHYP0dylyBRxFwmcmD5T meXg== X-Gm-Message-State: AOJu0Yw+4R5AdIHfUIMJBkvH2WaiPjVu4cRhaQyzBJUuZ0euccX8LLXV pfXKyK5kNslV2I5s++vIMN/I8w== X-Google-Smtp-Source: AGHT+IFMvTCBlHbh81wYN3s3G7OgL1J0aZlGcfQICX60Aedc8bG47talciVsG9wOml2AbCSK9ZGjpg== X-Received: by 2002:a17:902:ce8a:b0:1cf:df4f:30d9 with SMTP id f10-20020a170902ce8a00b001cfdf4f30d9mr6152725plg.29.1701183414313; Tue, 28 Nov 2023 06:56:54 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id j1-20020a170902c08100b001ab39cd875csm9023580pld.133.2023.11.28.06.56.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Nov 2023 06:56:53 -0800 (PST) From: Anup Patel To: Will Deacon , julien.thierry.kdev@gmail.com, maz@kernel.org Cc: Paolo Bonzini , Atish Patra , Andrew Jones , Anup Patel , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Anup Patel Subject: [kvmtool PATCH 04/10] riscv: Add Zba and Zbs extension support Date: Tue, 28 Nov 2023 20:26:22 +0530 Message-Id: <20231128145628.413414-5-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231128145628.413414-1-apatel@ventanamicro.com> References: <20231128145628.413414-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 When the Zba and Zbs extension is available expose it to the guest via device tree so that guest can use it. Signed-off-by: Anup Patel --- riscv/fdt.c | 2 ++ riscv/include/kvm/kvm-config-arch.h | 6 ++++++ 2 files changed, 8 insertions(+) diff --git a/riscv/fdt.c b/riscv/fdt.c index 230d1f8..cfe4678 100644 --- a/riscv/fdt.c +++ b/riscv/fdt.c @@ -21,7 +21,9 @@ struct isa_ext_info isa_info_arr[] = { {"svinval", KVM_RISCV_ISA_EXT_SVINVAL}, {"svnapot", KVM_RISCV_ISA_EXT_SVNAPOT}, {"svpbmt", KVM_RISCV_ISA_EXT_SVPBMT}, + {"zba", KVM_RISCV_ISA_EXT_ZBA}, {"zbb", KVM_RISCV_ISA_EXT_ZBB}, + {"zbs", KVM_RISCV_ISA_EXT_ZBS}, {"zicbom", KVM_RISCV_ISA_EXT_ZICBOM}, {"zicboz", KVM_RISCV_ISA_EXT_ZICBOZ}, {"zihintpause", KVM_RISCV_ISA_EXT_ZIHINTPAUSE}, diff --git a/riscv/include/kvm/kvm-config-arch.h b/riscv/include/kvm/kvm-config-arch.h index 863baea..978037a 100644 --- a/riscv/include/kvm/kvm-config-arch.h +++ b/riscv/include/kvm/kvm-config-arch.h @@ -40,9 +40,15 @@ struct kvm_config_arch { OPT_BOOLEAN('\0', "disable-svpbmt", \ &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_SVPBMT], \ "Disable Svpbmt Extension"), \ + OPT_BOOLEAN('\0', "disable-zba", \ + &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZBA], \ + "Disable Zba Extension"), \ OPT_BOOLEAN('\0', "disable-zbb", \ &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZBB], \ "Disable Zbb Extension"), \ + OPT_BOOLEAN('\0', "disable-zbs", \ + &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZBS], \ + "Disable Zbs Extension"), \ OPT_BOOLEAN('\0', "disable-zicbom", \ &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZICBOM], \ "Disable Zicbom Extension"), \ From patchwork Tue Nov 28 14:56:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 13471321 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="nFLP5A7l" Received: from mail-pl1-x62c.google.com (mail-pl1-x62c.google.com [IPv6:2607:f8b0:4864:20::62c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 11F68111 for ; Tue, 28 Nov 2023 06:56:59 -0800 (PST) Received: by mail-pl1-x62c.google.com with SMTP id d9443c01a7336-1cfb3ee8bc7so27950605ad.1 for ; Tue, 28 Nov 2023 06:56:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1701183418; x=1701788218; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tdili8BtTS1M3baU+hZ81RVV3W9O2cLJnQYpN2vMBOw=; b=nFLP5A7lte2k7NeqbrSkEk+a5NTsRJ9NLb8nKTohITc+iQhd/nm3ERn291YxyMgj7i RXfRDKnMm9X/3xArNKXnc9LjZ1ZkqXBytECVIwGg/5qluKFNZFx21ZTRG8HsLpb1TjsP +9pZWGa8d7plZoIwbwqAhdTFReymfkrhk6sv+ZkeYJ7Wbdcq2rYDjdJytlEftqS05ayO b6DKiqIzRbeuRfrW0ngeke/9KBxCXGQ7tKk+acKqBSbGuFYKGJhCdTReTaH5g7gAOJlC FPtjy2FQ/UEqlsNjxugrUTNFAOn7zEBeZzKHtU4TtcbFDymdSScv4VKIrMQ6DCgl9cXZ jL0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701183418; x=1701788218; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tdili8BtTS1M3baU+hZ81RVV3W9O2cLJnQYpN2vMBOw=; b=YGruW4jses8QpDpA8lr45zMP8a5hHxIqxBkqHeS6bsu1x7WW7dTEJmtA6HLZMO7xo4 dIKLAZB0b4RKgD76/Ky0jsTVNA5uJO99VaSq3fdTzywo7hPV8UeqN1VhwDdTtB2+pYQ9 OGeUbWHnf1LM8P5pjryWFjOSmHQ8FrDT9wjqTuzEE9zUH2wDNFgdZmW4EaWlE9zr5xZ6 qqX3HmX+Gme3BEqrOcmCEHaR3ntzWAv/+D4nS7NLrgdAoYTrYJWAijrezsWbycVHxpfC 3UsUo8BTDu7nrYEU3G+OXi6lDXMsVIpVq619z/okNHxnGQa1trsxuUI3YuCoFJHvCuN8 +HrQ== X-Gm-Message-State: AOJu0YzWDhOythvEzsWqQQd13D2SWdaK1w5jL114RCg3WyUrzikg9+EJ sCeJHM3euvcI1PakqmtzJ66X/g== X-Google-Smtp-Source: AGHT+IHtOsF59+XMv3bPjl1d2IV98iItNDJlb3ZNbUY8c97idQ/4fFYABVJErS8fwmJJiAW/nQHLiw== X-Received: by 2002:a17:902:bf02:b0:1cf:ca03:a221 with SMTP id bi2-20020a170902bf0200b001cfca03a221mr8585431plb.24.1701183418467; Tue, 28 Nov 2023 06:56:58 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id j1-20020a170902c08100b001ab39cd875csm9023580pld.133.2023.11.28.06.56.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Nov 2023 06:56:58 -0800 (PST) From: Anup Patel To: Will Deacon , julien.thierry.kdev@gmail.com, maz@kernel.org Cc: Paolo Bonzini , Atish Patra , Andrew Jones , Anup Patel , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Anup Patel Subject: [kvmtool PATCH 05/10] riscv: Add Zicntr and Zihpm extension support Date: Tue, 28 Nov 2023 20:26:23 +0530 Message-Id: <20231128145628.413414-6-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231128145628.413414-1-apatel@ventanamicro.com> References: <20231128145628.413414-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 When the Zicntr and Zihpm extension is available expose it to the guest via device tree so that guest can use it. Signed-off-by: Anup Patel --- riscv/fdt.c | 2 ++ riscv/include/kvm/kvm-config-arch.h | 6 ++++++ 2 files changed, 8 insertions(+) diff --git a/riscv/fdt.c b/riscv/fdt.c index cfe4678..19786af 100644 --- a/riscv/fdt.c +++ b/riscv/fdt.c @@ -26,7 +26,9 @@ struct isa_ext_info isa_info_arr[] = { {"zbs", KVM_RISCV_ISA_EXT_ZBS}, {"zicbom", KVM_RISCV_ISA_EXT_ZICBOM}, {"zicboz", KVM_RISCV_ISA_EXT_ZICBOZ}, + {"zicntr", KVM_RISCV_ISA_EXT_ZICNTR}, {"zihintpause", KVM_RISCV_ISA_EXT_ZIHINTPAUSE}, + {"zihpm", KVM_RISCV_ISA_EXT_ZIHPM}, }; static void dump_fdt(const char *dtb_file, void *fdt) diff --git a/riscv/include/kvm/kvm-config-arch.h b/riscv/include/kvm/kvm-config-arch.h index 978037a..af5c4b8 100644 --- a/riscv/include/kvm/kvm-config-arch.h +++ b/riscv/include/kvm/kvm-config-arch.h @@ -55,9 +55,15 @@ struct kvm_config_arch { OPT_BOOLEAN('\0', "disable-zicboz", \ &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZICBOZ], \ "Disable Zicboz Extension"), \ + OPT_BOOLEAN('\0', "disable-zicntr", \ + &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZICNTR], \ + "Disable Zicntr Extension"), \ OPT_BOOLEAN('\0', "disable-zihintpause", \ &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZIHINTPAUSE],\ "Disable Zihintpause Extension"), \ + OPT_BOOLEAN('\0', "disable-zihpm", \ + &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZIHPM], \ + "Disable Zihpm Extension"), \ OPT_BOOLEAN('\0', "disable-sbi-legacy", \ &(cfg)->sbi_ext_disabled[KVM_RISCV_SBI_EXT_V01], \ "Disable SBI Legacy Extensions"), \ From patchwork Tue Nov 28 14:56:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 13471322 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="ave2lSuu" Received: from mail-pl1-x62e.google.com (mail-pl1-x62e.google.com [IPv6:2607:f8b0:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BD4F1127 for ; Tue, 28 Nov 2023 06:57:03 -0800 (PST) Received: by mail-pl1-x62e.google.com with SMTP id d9443c01a7336-1cf89e31773so38022185ad.0 for ; Tue, 28 Nov 2023 06:57:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1701183423; x=1701788223; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kbUuA57ruEhi2ahjuA8C/2BffQFp958wQ651hhrhePw=; b=ave2lSuuLQFF0CjPlBJU/TkLyIwND+Unhkmvxo6lgUBeE89VmqmlrmcrQwGkJP1ZED MZjn3BiifmepmTsvhAnx0w1U02OT/QQrVvmObFXF+Mv4GmXNQpWnJcg867yxq9P4rnKJ bVPzubxTh5uZ9n6J33O9zF6PnlR9hkPJnynM3RgnQ58SVRv30ZyU3+xRi7k3upf5TCjV WMGPLlv4O8iiqLmSxzSezOwQ/WSa2MCLn2dMcQYKMNu6wA/CsgRd8JaskzpGzNmuxjMZ iTbaElTg1BTHxl1PVYYxpKftFuPknQry4IvixtAQX4xNiPc4JXVXp5NSgMAcvjnV0fwd fCXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701183423; x=1701788223; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kbUuA57ruEhi2ahjuA8C/2BffQFp958wQ651hhrhePw=; b=VHNALWiu1Qikv8k9afhDxlvev6PbLtBwleh4AyUH0IXW8XJWjlpUtkS5j5yYAvM35F xW50DJf/+Ok7ZIl6LKOaCJ6feiHS6Rlr+sxHC7/ByyotuvEz+wF0Rx30S2yZnJwiydBj WpYgcN0CZA2U5i7lIisQ7kLIPJ2At7h/lB2mqpdQqMXdiXmzmjor+5lIQ1LLOBvNoBwf sNvKCIWIFcEdcyrV/tN2xuKsO3g3oX5kBoGoMU6yvEGP75h6+0jaC252UWbz7TLuJuE/ 8CxjUWEtVKKczJ40woqsViMcNmaLFQUBEBEZZAphB37dxZCfVrsnnSYQlTjiStpI/Dhi BucA== X-Gm-Message-State: AOJu0Yzffa1Y6m4HiRDT8ctrdwRiu9D4yrqqbW9Y0VMgKax0q/O/FrOt BUomOYCpuQYMMyXEA6rm5KN7ew== X-Google-Smtp-Source: AGHT+IH+Ebdv/W0b+4+opaX2MitG1Qm7BXPcUPvE32hQyY7M4XQ5KEKJq/an9OAS+JCfWK4gxs+DOQ== X-Received: by 2002:a17:902:988b:b0:1cf:b130:e9af with SMTP id s11-20020a170902988b00b001cfb130e9afmr10972906plp.20.1701183423144; Tue, 28 Nov 2023 06:57:03 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id j1-20020a170902c08100b001ab39cd875csm9023580pld.133.2023.11.28.06.56.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Nov 2023 06:57:02 -0800 (PST) From: Anup Patel To: Will Deacon , julien.thierry.kdev@gmail.com, maz@kernel.org Cc: Paolo Bonzini , Atish Patra , Andrew Jones , Anup Patel , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Anup Patel Subject: [kvmtool PATCH 06/10] riscv: Add Zicsr and Zifencei extension support Date: Tue, 28 Nov 2023 20:26:24 +0530 Message-Id: <20231128145628.413414-7-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231128145628.413414-1-apatel@ventanamicro.com> References: <20231128145628.413414-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 When the Zicsr and Zifencei extension is available expose it to the guest via device tree so that guest can use it. Signed-off-by: Anup Patel --- riscv/fdt.c | 2 ++ riscv/include/kvm/kvm-config-arch.h | 6 ++++++ 2 files changed, 8 insertions(+) diff --git a/riscv/fdt.c b/riscv/fdt.c index 19786af..a4d54eb 100644 --- a/riscv/fdt.c +++ b/riscv/fdt.c @@ -27,6 +27,8 @@ struct isa_ext_info isa_info_arr[] = { {"zicbom", KVM_RISCV_ISA_EXT_ZICBOM}, {"zicboz", KVM_RISCV_ISA_EXT_ZICBOZ}, {"zicntr", KVM_RISCV_ISA_EXT_ZICNTR}, + {"zicsr", KVM_RISCV_ISA_EXT_ZICSR}, + {"zifencei", KVM_RISCV_ISA_EXT_ZIFENCEI}, {"zihintpause", KVM_RISCV_ISA_EXT_ZIHINTPAUSE}, {"zihpm", KVM_RISCV_ISA_EXT_ZIHPM}, }; diff --git a/riscv/include/kvm/kvm-config-arch.h b/riscv/include/kvm/kvm-config-arch.h index af5c4b8..c524771 100644 --- a/riscv/include/kvm/kvm-config-arch.h +++ b/riscv/include/kvm/kvm-config-arch.h @@ -58,6 +58,12 @@ struct kvm_config_arch { OPT_BOOLEAN('\0', "disable-zicntr", \ &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZICNTR], \ "Disable Zicntr Extension"), \ + OPT_BOOLEAN('\0', "disable-zicsr", \ + &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZICSR], \ + "Disable Zicsr Extension"), \ + OPT_BOOLEAN('\0', "disable-zifencei", \ + &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZIFENCEI], \ + "Disable Zifencei Extension"), \ OPT_BOOLEAN('\0', "disable-zihintpause", \ &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZIHINTPAUSE],\ "Disable Zihintpause Extension"), \ From patchwork Tue Nov 28 14:56:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 13471323 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="R5eUFLd1" Received: from mail-pl1-x634.google.com (mail-pl1-x634.google.com [IPv6:2607:f8b0:4864:20::634]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3BBB1111 for ; Tue, 28 Nov 2023 06:57:08 -0800 (PST) Received: by mail-pl1-x634.google.com with SMTP id d9443c01a7336-1ce28faa92dso42843925ad.2 for ; Tue, 28 Nov 2023 06:57:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1701183428; x=1701788228; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cM+iyx3HzV6Q0lhdkwsJZGfIeyqwEQZL5+dROw33NYg=; b=R5eUFLd18vglNoLmRuiu28eJIHQJpwpLKXAfQhk00+um5bUbnQuPh5bSmzH9Erxu/5 wFIfdUP3vX6TwY9uWA+6bLQ3l2sFj4oanC4XpwLrFxHGCLfe2t2H1RCBvsdpk0ySG3Hg /ZhucgLKvAaIjxXOssFmtOXgDXiOirjuG2pmlgNapt3wWFqvcoQo/bnASlMgYmjoDtBu UKRqwcWgJUETgH7DuOGRur0JBhciXedpz544q+cdzVSBfjTjrx4zR0BRE6Ze9uzspyYw kuEBIn5dTIEXUHYjORzRttiiglh7isVMWXp+Ih58L9k1+4qzTfx77bhTFHcHW3GhFJl0 uHKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701183428; x=1701788228; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cM+iyx3HzV6Q0lhdkwsJZGfIeyqwEQZL5+dROw33NYg=; b=TFMxWXIofhhuWgPZXOEid5h7UM0vwLWVYUz+audkjeZd9qeIUXNt1CYsyvq+zvoRXC RhCvInmCmrSE+sufdNLvX54zIJJbhT0QheGRN0xhFC6e45E9l20a0dUrmjgg6n/5hC2C ckH3qhNZ945M0Hm3nOwI01qWxWAe2qP/GRARk2nr+jHi9mH5JvDOfhhTFRm7hrpDiS8s Vtk/l2KijcQH4oZw8pUJIcabbh9gEXbv23HrVP3c2VJpta0KmSZa+2bqRMDMGcZOMLH3 RoDVzCyd5dnrFzwQNIwwddNf9B58y0wClN+CfmWoU2lfxKsEes5NlqMbx51CsZFeRTeQ lIsQ== X-Gm-Message-State: AOJu0Yw+KVwZZFnFKHIrE+FIH5SAAL1CTpdoREn1ro+W2OwOOTB4dRty VBgq/LYxupTqzFpDES1djxrq7w== X-Google-Smtp-Source: AGHT+IG2Giid5R0skwB+Jt13gqXafpEZhJYgvRusyq4PgzHNzsOI9MZxpjGMI2cqqBeg3wiP22haAw== X-Received: by 2002:a17:902:d508:b0:1cf:d597:194c with SMTP id b8-20020a170902d50800b001cfd597194cmr6879024plg.49.1701183427550; Tue, 28 Nov 2023 06:57:07 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id j1-20020a170902c08100b001ab39cd875csm9023580pld.133.2023.11.28.06.57.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Nov 2023 06:57:07 -0800 (PST) From: Anup Patel To: Will Deacon , julien.thierry.kdev@gmail.com, maz@kernel.org Cc: Paolo Bonzini , Atish Patra , Andrew Jones , Anup Patel , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Anup Patel Subject: [kvmtool PATCH 07/10] riscv: Add Smstateen extension support Date: Tue, 28 Nov 2023 20:26:25 +0530 Message-Id: <20231128145628.413414-8-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231128145628.413414-1-apatel@ventanamicro.com> References: <20231128145628.413414-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 When the Smstateen extension is available expose it to the guest via device tree so that guest can use it. Signed-off-by: Anup Patel --- riscv/fdt.c | 1 + riscv/include/kvm/kvm-config-arch.h | 3 +++ 2 files changed, 4 insertions(+) diff --git a/riscv/fdt.c b/riscv/fdt.c index a4d54eb..0fe0f0b 100644 --- a/riscv/fdt.c +++ b/riscv/fdt.c @@ -16,6 +16,7 @@ struct isa_ext_info { struct isa_ext_info isa_info_arr[] = { /* sorted alphabetically */ + {"smstateen", KVM_RISCV_ISA_EXT_SMSTATEEN}, {"ssaia", KVM_RISCV_ISA_EXT_SSAIA}, {"sstc", KVM_RISCV_ISA_EXT_SSTC}, {"svinval", KVM_RISCV_ISA_EXT_SVINVAL}, diff --git a/riscv/include/kvm/kvm-config-arch.h b/riscv/include/kvm/kvm-config-arch.h index c524771..49eb3e6 100644 --- a/riscv/include/kvm/kvm-config-arch.h +++ b/riscv/include/kvm/kvm-config-arch.h @@ -25,6 +25,9 @@ struct kvm_config_arch { OPT_U64('\0', "custom-mimpid", \ &(cfg)->custom_mimpid, \ "Show custom mimpid to Guest VCPU"), \ + OPT_BOOLEAN('\0', "disable-smstateen", \ + &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_SMSTATEEN], \ + "Disable Smstateen Extension"), \ OPT_BOOLEAN('\0', "disable-ssaia", \ &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_SSAIA], \ "Disable Ssaia Extension"), \ From patchwork Tue Nov 28 14:56:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 13471324 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="EIvAmC+q" Received: from mail-pg1-x532.google.com (mail-pg1-x532.google.com [IPv6:2607:f8b0:4864:20::532]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 66C81111 for ; Tue, 28 Nov 2023 06:57:12 -0800 (PST) Received: by mail-pg1-x532.google.com with SMTP id 41be03b00d2f7-5aa481d53e5so3981914a12.1 for ; Tue, 28 Nov 2023 06:57:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1701183432; x=1701788232; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1GaZLArS4uEWR7hS0+LMZr4tSCm8f/wfXv0BlFAD2A4=; b=EIvAmC+qvAEcJdIyQxIuygqOI/iLrZilV7UY33H+Xa7jaJiXYRkLAkVkbFdX3bwND+ A8b5NeMj+c+YsYJ98bgoxth4bsod1SdC0AHEstbv0I+kKoo3gtqj9RJPmYaGdYQx1w8L kkZ4zdIKm0U7LndEFEooa99p5lgBfxIM0xasAPBtKA0vycD1Wq3/aL1fZ9ewMrsVqKAQ yNSrm7J7PiE73GoIoPDqcCpt81hkgPykFb1L5Y8wFmFYVBCBX/3dD5qGVpNwX0NJ8P3W kWt+pJmGo+jCIk9Ehqnxv3kvpTb9ct8G8IhIk0xV1fvoZYSQVTFyrI146nmiIuZGmXi5 rU2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701183432; x=1701788232; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1GaZLArS4uEWR7hS0+LMZr4tSCm8f/wfXv0BlFAD2A4=; b=B0tLDpnd1SwMHmXF0i9Us2TxH1sNOTvjeJj6tvBgrYn/x0TJ3JWWy5HZc3IMKnR3MB HkM7mSMp71kw/tO9CSyes5Zu0gdkPfQV/i3/9PE7qAE+jpaEAcRDYwVJsC6upLlIOqTH QhDXOghd1pxc+bNPS/aDRTy2sFJHkcq3+hzNosFzMQXn8dUOGWGvV88AHCgwtEncr9JD ZSc8NfjUPGKIOHiqIC59/ms4fkXol56tW+WRQhSRlh9EKB38CnRPgNDiI7cn9iBhP7kP SOr+Gxzi2TT85WflPWZ0T1qdVQUFPAbAr0I7BXBJ/VlePJmqZZMjt8noYrVYSxdFR52j YA0A== X-Gm-Message-State: AOJu0YyBVku/2GO0rp4NfOOafoB8n1yj7j6XpPv4YoNp0YS312XUYi3P u45m+YXJoe1hwa0SIqTGFuaqyw== X-Google-Smtp-Source: AGHT+IG7bgWXf62BmYjAlTTPfyIqGJJN77eb7QgJcUohI3jWVxZ4PVOdEsRVUkiPfOmmG6tfo2UwwQ== X-Received: by 2002:a17:90b:390e:b0:285:da91:69e8 with SMTP id ob14-20020a17090b390e00b00285da9169e8mr7059326pjb.47.1701183431732; Tue, 28 Nov 2023 06:57:11 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id j1-20020a170902c08100b001ab39cd875csm9023580pld.133.2023.11.28.06.57.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Nov 2023 06:57:11 -0800 (PST) From: Anup Patel To: Will Deacon , julien.thierry.kdev@gmail.com, maz@kernel.org Cc: Paolo Bonzini , Atish Patra , Andrew Jones , Anup Patel , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Anup Patel Subject: [kvmtool PATCH 08/10] riscv: Add Zicond extension support Date: Tue, 28 Nov 2023 20:26:26 +0530 Message-Id: <20231128145628.413414-9-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231128145628.413414-1-apatel@ventanamicro.com> References: <20231128145628.413414-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 When the Zicond extension is available expose it to the guest via device tree so that guest can use it. Signed-off-by: Anup Patel --- riscv/fdt.c | 1 + riscv/include/kvm/kvm-config-arch.h | 3 +++ 2 files changed, 4 insertions(+) diff --git a/riscv/fdt.c b/riscv/fdt.c index 0fe0f0b..1124fa1 100644 --- a/riscv/fdt.c +++ b/riscv/fdt.c @@ -28,6 +28,7 @@ struct isa_ext_info isa_info_arr[] = { {"zicbom", KVM_RISCV_ISA_EXT_ZICBOM}, {"zicboz", KVM_RISCV_ISA_EXT_ZICBOZ}, {"zicntr", KVM_RISCV_ISA_EXT_ZICNTR}, + {"zicond", KVM_RISCV_ISA_EXT_ZICOND}, {"zicsr", KVM_RISCV_ISA_EXT_ZICSR}, {"zifencei", KVM_RISCV_ISA_EXT_ZIFENCEI}, {"zihintpause", KVM_RISCV_ISA_EXT_ZIHINTPAUSE}, diff --git a/riscv/include/kvm/kvm-config-arch.h b/riscv/include/kvm/kvm-config-arch.h index 49eb3e6..48d0770 100644 --- a/riscv/include/kvm/kvm-config-arch.h +++ b/riscv/include/kvm/kvm-config-arch.h @@ -61,6 +61,9 @@ struct kvm_config_arch { OPT_BOOLEAN('\0', "disable-zicntr", \ &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZICNTR], \ "Disable Zicntr Extension"), \ + OPT_BOOLEAN('\0', "disable-zicond", \ + &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZICOND], \ + "Disable Zicond Extension"), \ OPT_BOOLEAN('\0', "disable-zicsr", \ &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZICSR], \ "Disable Zicsr Extension"), \ From patchwork Tue Nov 28 14:56:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 13471325 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="GVsmJRCA" Received: from mail-pl1-x634.google.com (mail-pl1-x634.google.com [IPv6:2607:f8b0:4864:20::634]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A08DD127 for ; Tue, 28 Nov 2023 06:57:16 -0800 (PST) Received: by mail-pl1-x634.google.com with SMTP id d9443c01a7336-1cfafe3d46bso31772065ad.0 for ; Tue, 28 Nov 2023 06:57:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1701183436; x=1701788236; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=O7BCkDlEadkuDM5M9mJaJ5lnCVNpUbfkuweY2LH7cKc=; b=GVsmJRCAtoR3MQi+OtiL3wfp4Y+FxWb9RXhWhx71hUFI4nYmCuae6lQvyTPVpCa2Sa Y7m3sZ/UmAs56n+GG4bb3UnicNwHRMwA+2BrVeYRP43GeS4VPJPjJn6r+YZLmt946cl1 1j8gUEStnV/U2qXbZGV0lbwY6SWsnDMRpeethyW8tXvowvadnOQPA9gTHhWjNtRSKpFH nXqHxxMhNWm/UBxfvbxE7fErscPaY9QRB2Oh7NxwvVMkctWU+u1+XErRCXaLHh29MTpQ DhzjUTskXlHVd6OmbTzIRIqFI7nzRbk6ZoyDzyyixE/s5tdmAJWOrZEb7IoBoiGxJTpm zvlg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701183436; x=1701788236; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=O7BCkDlEadkuDM5M9mJaJ5lnCVNpUbfkuweY2LH7cKc=; b=gTJO6CrcBdr/45EpsATC4s5uCiQH/GYnzxK5bBkbrM5l31eAwiB5TshrDpCo0F9D0/ IIKZpn8Pv0CQEkWGRTNI+3XysKDaQA2woaSZr7nC3/P5fMNzXye0hF6Kkr2DXIGk08lF FhO+uOCqrqfTAUanU1Ki3xAPxM/71th+JUT35PxD6h+KvIXQGGeN0JzEmk1m0oEaa6PA bcTTMigoXwXZt/6uZh+WhWA1kjO8IUQGTYGOyXAKeTQ7xIPmpM/EwGO9MiDXFI1YKDcI g2ya/MKueXQKXKmvYSUcmPzRHusXqRzsWqy9wF+WdPmabvwlrjNXd28zEmSHTZvCnGO0 hSaw== X-Gm-Message-State: AOJu0Yy46RJlYrnZDqJ+VxWA8ErTclBOktXkVfoR5Gt7Si4zALKK6AuN qfFedSPA6IGvUCpLj26g+faLqg== X-Google-Smtp-Source: AGHT+IEddxVCpbDyl7DSz4+wlRdml0wvPHO0ZR3csY2RtvrNL6EiXNiXdE42jWS5zvFJZJPvZKBDuQ== X-Received: by 2002:a17:902:bb8c:b0:1cf:a8ef:df8f with SMTP id m12-20020a170902bb8c00b001cfa8efdf8fmr13087800pls.68.1701183436017; Tue, 28 Nov 2023 06:57:16 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id j1-20020a170902c08100b001ab39cd875csm9023580pld.133.2023.11.28.06.57.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Nov 2023 06:57:15 -0800 (PST) From: Anup Patel To: Will Deacon , julien.thierry.kdev@gmail.com, maz@kernel.org Cc: Paolo Bonzini , Atish Patra , Andrew Jones , Anup Patel , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Anup Patel Subject: [kvmtool PATCH 09/10] riscv: Set mmu-type DT property based on satp_mode ONE_REG interface Date: Tue, 28 Nov 2023 20:26:27 +0530 Message-Id: <20231128145628.413414-10-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231128145628.413414-1-apatel@ventanamicro.com> References: <20231128145628.413414-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Instead of hard-coding the mmu-type DT property, we should set it based on satp_mode ONE_REG interface. Signed-off-by: Anup Patel --- riscv/fdt.c | 44 +++++++++++++++++++++++++++++++++++++------- 1 file changed, 37 insertions(+), 7 deletions(-) diff --git a/riscv/fdt.c b/riscv/fdt.c index 1124fa1..8485acf 100644 --- a/riscv/fdt.c +++ b/riscv/fdt.c @@ -57,7 +57,7 @@ static void generate_cpu_nodes(void *fdt, struct kvm *kvm) int cpu, pos, i, index, valid_isa_len; const char *valid_isa_order = "IEMAFDQCLBJTPVNSUHKORWXYZG"; int arr_sz = ARRAY_SIZE(isa_info_arr); - unsigned long cbom_blksz = 0, cboz_blksz = 0; + unsigned long cbom_blksz = 0, cboz_blksz = 0, satp_mode = 0; _FDT(fdt_begin_node(fdt, "cpus")); _FDT(fdt_property_cell(fdt, "#address-cells", 0x1)); @@ -125,15 +125,45 @@ static void generate_cpu_nodes(void *fdt, struct kvm *kvm) } cpu_isa[pos] = '\0'; + reg.id = RISCV_CONFIG_REG(satp_mode); + reg.addr = (unsigned long)&satp_mode; + if (ioctl(vcpu->vcpu_fd, KVM_GET_ONE_REG, ®) < 0) + satp_mode = (vcpu->riscv_xlen == 64) ? 8 : 1; + _FDT(fdt_begin_node(fdt, cpu_name)); _FDT(fdt_property_string(fdt, "device_type", "cpu")); _FDT(fdt_property_string(fdt, "compatible", "riscv")); - if (vcpu->riscv_xlen == 64) - _FDT(fdt_property_string(fdt, "mmu-type", - "riscv,sv48")); - else - _FDT(fdt_property_string(fdt, "mmu-type", - "riscv,sv32")); + if (vcpu->riscv_xlen == 64) { + switch (satp_mode) { + case 10: + _FDT(fdt_property_string(fdt, "mmu-type", + "riscv,sv57")); + break; + case 9: + _FDT(fdt_property_string(fdt, "mmu-type", + "riscv,sv48")); + break; + case 8: + _FDT(fdt_property_string(fdt, "mmu-type", + "riscv,sv39")); + break; + default: + _FDT(fdt_property_string(fdt, "mmu-type", + "riscv,none")); + break; + } + } else { + switch (satp_mode) { + case 1: + _FDT(fdt_property_string(fdt, "mmu-type", + "riscv,sv32")); + break; + default: + _FDT(fdt_property_string(fdt, "mmu-type", + "riscv,none")); + break; + } + } _FDT(fdt_property_string(fdt, "riscv,isa", cpu_isa)); if (cbom_blksz) _FDT(fdt_property_cell(fdt, "riscv,cbom-block-size", cbom_blksz)); From patchwork Tue Nov 28 14:56:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 13471326 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="T5euO1eV" Received: from mail-pl1-x62b.google.com (mail-pl1-x62b.google.com [IPv6:2607:f8b0:4864:20::62b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9F4C9127 for ; Tue, 28 Nov 2023 06:57:20 -0800 (PST) Received: by mail-pl1-x62b.google.com with SMTP id d9443c01a7336-1cfb83211b9so25373025ad.3 for ; Tue, 28 Nov 2023 06:57:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1701183440; x=1701788240; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xwIs8nEfIc4H0x0tyu7MTp0Kuhb4OwEwEqgm1x28cAE=; b=T5euO1eVi2NgiishN0SfMSQRbKyuF0fdOTklxf3dSFRHxQ6twtOp4Da6nPaBo40cy0 Of8oB0FQHx5+e5VkqwiGbXxT5x69bPwuhrVvzc7VhGUlN5JSX61gAJirHVHhfM+XiE7B kWn4TnMIl047ZjyossbE97JOf8zO1eI/vIbkvePuXOnKgm06SXosyNlfSXr4EPzkWefA YrkG7RlDgYAGgBR6TTNbDDKTVIPK9K27zEOkFmmWk7hLH1XlrJdfF3FQ7tG0GpMteHxv YpDTXKCcsTMLUkGzU0I8Q0ss1GOGaF1W7JwpGBWobGnJHPYZPPnt669yErg5k1KPyzMS A9GQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701183440; x=1701788240; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xwIs8nEfIc4H0x0tyu7MTp0Kuhb4OwEwEqgm1x28cAE=; b=NYUVGdSTX8nqxcWBhQt+2fdPwzcm7Qox+nh9+B+txC02XL7lJ7lvnsd18k0xPwKvT2 LJiNS6x5QCb5Mx9G/tDsRiF3F0gKEaXkKfmt9ooJVomRHclmYF/KHsQ2cLC/scyD+uGH abjymozPsUadIfMtn5ZWntvOKtsVPbzNPGrmXkr9DzI+QPdd2tLEA8np7l4JiH1OH19w anQ7F8+/sRFKl1UVh4FPLfbdYmuqRoMehVn+y8EyW44Ot+K/k1pNtBeXpOn/AYkWsIYj 6xrCQIvty8+Hh9UT8h3IPFeb/4V2/IixKALjHai38Ni5S9KRA+UYDkP9OA14uBy/q8so mzIA== X-Gm-Message-State: AOJu0YzcWkau+p5mzy0zYkpy1hzAVWjOTIo2BsS0IsbzWoCTwRpef4Ig vGJfkQ8JQVf8QxjMtkc9XsTRHg== X-Google-Smtp-Source: AGHT+IEoUvv3uxivYOxvLpY+oK4D/unmsQkf8bsG9mjdi57Yky23KzPLLC35z99Y2pc7vzOhucbR0w== X-Received: by 2002:a17:902:db07:b0:1cf:c37f:7160 with SMTP id m7-20020a170902db0700b001cfc37f7160mr8898046plx.63.1701183439914; Tue, 28 Nov 2023 06:57:19 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id j1-20020a170902c08100b001ab39cd875csm9023580pld.133.2023.11.28.06.57.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Nov 2023 06:57:19 -0800 (PST) From: Anup Patel To: Will Deacon , julien.thierry.kdev@gmail.com, maz@kernel.org Cc: Paolo Bonzini , Atish Patra , Andrew Jones , Anup Patel , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Anup Patel Subject: [kvmtool PATCH 10/10] riscv: Handle SBI DBCN calls from Guest/VM Date: Tue, 28 Nov 2023 20:26:28 +0530 Message-Id: <20231128145628.413414-11-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231128145628.413414-1-apatel@ventanamicro.com> References: <20231128145628.413414-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The new SBI DBCN functions are forwarded by in-kernel KVM RISC-V module to user-space so let us handle these calls in kvm_cpu_riscv_sbi() function. Signed-off-by: Anup Patel --- riscv/include/kvm/kvm-config-arch.h | 5 ++- riscv/include/kvm/sbi.h | 14 ++++++- riscv/kvm-cpu.c | 57 +++++++++++++++++++++++++++++ 3 files changed, 73 insertions(+), 3 deletions(-) diff --git a/riscv/include/kvm/kvm-config-arch.h b/riscv/include/kvm/kvm-config-arch.h index 48d0770..d2fc2d4 100644 --- a/riscv/include/kvm/kvm-config-arch.h +++ b/riscv/include/kvm/kvm-config-arch.h @@ -102,6 +102,9 @@ struct kvm_config_arch { "Disable SBI Experimental Extensions"), \ OPT_BOOLEAN('\0', "disable-sbi-vendor", \ &(cfg)->sbi_ext_disabled[KVM_RISCV_SBI_EXT_VENDOR], \ - "Disable SBI Vendor Extensions"), + "Disable SBI Vendor Extensions"), \ + OPT_BOOLEAN('\0', "disable-sbi-dbcn", \ + &(cfg)->sbi_ext_disabled[KVM_RISCV_SBI_EXT_DBCN], \ + "Disable SBI DBCN Extension"), #endif /* KVM__KVM_CONFIG_ARCH_H */ diff --git a/riscv/include/kvm/sbi.h b/riscv/include/kvm/sbi.h index f4b4182..a0f2c70 100644 --- a/riscv/include/kvm/sbi.h +++ b/riscv/include/kvm/sbi.h @@ -20,6 +20,7 @@ enum sbi_ext_id { SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID = 0x7, SBI_EXT_0_1_SHUTDOWN = 0x8, SBI_EXT_BASE = 0x10, + SBI_EXT_DBCN = 0x4442434E, }; enum sbi_ext_base_fid { @@ -32,6 +33,12 @@ enum sbi_ext_base_fid { SBI_BASE_GET_MIMPID, }; +enum sbi_ext_dbcn_fid { + SBI_EXT_DBCN_CONSOLE_WRITE = 0, + SBI_EXT_DBCN_CONSOLE_READ = 1, + SBI_EXT_DBCN_CONSOLE_WRITE_BYTE = 2, +}; + #define SBI_SPEC_VERSION_DEFAULT 0x1 #define SBI_SPEC_VERSION_MAJOR_OFFSET 24 #define SBI_SPEC_VERSION_MAJOR_MASK 0x7f @@ -41,8 +48,11 @@ enum sbi_ext_base_fid { #define SBI_SUCCESS 0 #define SBI_ERR_FAILURE -1 #define SBI_ERR_NOT_SUPPORTED -2 -#define SBI_ERR_INVALID_PARAM -3 +#define SBI_ERR_INVALID_PARAM -3 #define SBI_ERR_DENIED -4 -#define SBI_ERR_INVALID_ADDRESS -5 +#define SBI_ERR_INVALID_ADDRESS -5 +#define SBI_ERR_ALREADY_AVAILABLE -6 +#define SBI_ERR_ALREADY_STARTED -7 +#define SBI_ERR_ALREADY_STOPPED -8 #endif diff --git a/riscv/kvm-cpu.c b/riscv/kvm-cpu.c index 540baec..c4e83c4 100644 --- a/riscv/kvm-cpu.c +++ b/riscv/kvm-cpu.c @@ -105,6 +105,17 @@ struct kvm_cpu *kvm_cpu__arch_init(struct kvm *kvm, unsigned long cpu_id) die("KVM_SET_ONE_REG failed (sbi_ext %d)", i); } + /* Force enable SBI debug console if not disabled from command line */ + if (!kvm->cfg.arch.sbi_ext_disabled[KVM_RISCV_SBI_EXT_DBCN]) { + id = 1; + reg.id = RISCV_SBI_EXT_REG(KVM_REG_RISCV_SBI_SINGLE, + KVM_RISCV_SBI_EXT_DBCN); + reg.addr = (unsigned long)&id; + if (ioctl(vcpu->vcpu_fd, KVM_SET_ONE_REG, ®) < 0) + pr_warning("KVM_SET_ONE_REG failed (sbi_ext %d)", + KVM_RISCV_SBI_EXT_DBCN); + } + /* Populate the vcpu structure. */ vcpu->kvm = kvm; vcpu->cpu_id = cpu_id; @@ -128,7 +139,9 @@ void kvm_cpu__delete(struct kvm_cpu *vcpu) static bool kvm_cpu_riscv_sbi(struct kvm_cpu *vcpu) { char ch; + u64 addr; bool ret = true; + char *str_start, *str_end; int dfd = kvm_cpu__get_debug_fd(); switch (vcpu->kvm_run->riscv_sbi.extension_id) { @@ -144,6 +157,50 @@ static bool kvm_cpu_riscv_sbi(struct kvm_cpu *vcpu) else vcpu->kvm_run->riscv_sbi.ret[0] = SBI_ERR_FAILURE; break; + case SBI_EXT_DBCN: + switch (vcpu->kvm_run->riscv_sbi.function_id) { + case SBI_EXT_DBCN_CONSOLE_WRITE: + case SBI_EXT_DBCN_CONSOLE_READ: + addr = vcpu->kvm_run->riscv_sbi.args[1]; +#if __riscv_xlen == 32 + addr |= (u64)vcpu->kvm_run->riscv_sbi.args[2] << 32; +#endif + if (!vcpu->kvm_run->riscv_sbi.args[0]) + break; + str_start = guest_flat_to_host(vcpu->kvm, addr); + addr += vcpu->kvm_run->riscv_sbi.args[0] - 1; + str_end = guest_flat_to_host(vcpu->kvm, addr); + if (!str_start || !str_end) { + vcpu->kvm_run->riscv_sbi.ret[0] = + SBI_ERR_INVALID_PARAM; + break; + } + vcpu->kvm_run->riscv_sbi.ret[1] = 0; + while (str_start <= str_end) { + if (vcpu->kvm_run->riscv_sbi.function_id == + SBI_EXT_DBCN_CONSOLE_WRITE) { + term_putc(str_start, 1, 0); + } else { + if (!term_readable(0)) + break; + *str_start = term_getc(vcpu->kvm, 0); + } + vcpu->kvm_run->riscv_sbi.ret[1]++; + str_start++; + } + break; + case SBI_EXT_DBCN_CONSOLE_WRITE_BYTE: + ch = vcpu->kvm_run->riscv_sbi.args[0]; + term_putc(&ch, 1, 0); + vcpu->kvm_run->riscv_sbi.ret[0] = 0; + vcpu->kvm_run->riscv_sbi.ret[1] = 0; + break; + default: + vcpu->kvm_run->riscv_sbi.ret[0] = + SBI_ERR_NOT_SUPPORTED; + break; + } + break; default: dprintf(dfd, "Unhandled SBI call\n"); dprintf(dfd, "extension_id=0x%lx function_id=0x%lx\n",