From patchwork Wed Nov 29 21:44:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 13473506 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=nxp.com header.i=@nxp.com header.b="G+fPSZ5G" Received: from EUR02-AM0-obe.outbound.protection.outlook.com (mail-am0eur02on2087.outbound.protection.outlook.com [40.107.247.87]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4829BA8; Wed, 29 Nov 2023 13:44:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=H3aHqkTkwEcB41AUeFTg75xYDwkQwv1XTUCk4UmEH71MTt3RGbpcUO64jiQ9oYzOzMsTnQ4BgHtXE6sph+fS80mSRek2m3TgT0wHlCsmrsIHWIv3kCaFTkgiR6SyaeBxDxpFQxoQj2dxWHFsSvmJ1QrdFHHuc+X/rt6Gr6zHcSph0TWwHJNRNt4IKzTpil4zEo/BgPkXcdRlGoH7lP/ZWqusMYms1srV6K8PmcgkizG4BJBGPlzGvy04AgRKuiYNKzN5mzGPlfYGEzYnMLtfzObACBFXUqfgB8sJj7KnMJVLYhfqdxxip1ZCAM5Gwc41FWXlvYWGNDSf3BnqdOpvGw== ARC-Message-Signature: i=1; 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b=G+fPSZ5Gheya2hVFV2JynlCLyo2+8be+JHIxL48RLbn3yzBCkL7pcownXyFoKHuw/IeKgiXkrHLduUTdz0+GG1MaoPL1mb2ZhAVIJnoJceqpSfFZBDXhiRPUzqTKRJxgPXMk6wOuvlFuRiZP4hWrceob84XkgL//Me+AgbtWHb0= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) by DBAPR04MB7416.eurprd04.prod.outlook.com (2603:10a6:10:1b3::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7068.11; Wed, 29 Nov 2023 21:44:33 +0000 Received: from AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::95f5:5118:258f:ee40]) by AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::95f5:5118:258f:ee40%6]) with mapi id 15.20.7046.015; Wed, 29 Nov 2023 21:44:33 +0000 From: Frank Li To: manivannan.sadhasivam@linaro.org Cc: Frank.Li@nxp.com, bhelgaas@google.com, imx@lists.linux.dev, kw@linux.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, lpieralisi@kernel.org, minghuan.Lian@nxp.com, mingkai.hu@nxp.com, robh@kernel.org, roy.zang@nxp.com Subject: [PATCH v4 1/4] PCI: layerscape: Add function pointer for exit_from_l2() Date: Wed, 29 Nov 2023 16:44:09 -0500 Message-Id: <20231129214412.327633-2-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231129214412.327633-1-Frank.Li@nxp.com> References: <20231129214412.327633-1-Frank.Li@nxp.com> X-ClientProxiedBy: SJ0PR13CA0136.namprd13.prod.outlook.com (2603:10b6:a03:2c6::21) To AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM6PR04MB4838:EE_|DBAPR04MB7416:EE_ X-MS-Office365-Filtering-Correlation-Id: 80f38b58-d0fc-4b2d-c1f9-08dbf1245fa1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: dywSFHG9nYnye8+ZLNH5uHFG20x0To6gW3UUoWUZoLy6Sq8i/8WWbNKIK/SLC3gQRjCxRoTFOQUvlCeTsRb/her6DuuSdCCbK3O856e81m8BWjCko2Hcw1C77USa2ujJ8DeCc4wtSvmaV/Im3EWU9eiRradQctY/Hc/dPEtjraoJwiosQw0Zs56B4osEnsuFAVGZliw1t3VXKSxp9R0w0NIf2Lth/Ut0ayCvLGcZ96Lt+n/kTn5hXRazp7SPQiUfMiSBdo7YoOhjbCI2VwIPkw8CUdsf6d+pCSNAESv51OShlKElu7GKAHStweULM12A1VCW73eqt/oD6jchMfPBdyVQgRJ1loXnocCHP1sOJnt+fs+dMvP16GTjQeHO4rqo2Cz36YYZ0QaZFDxHnl8gLfeBVxf54ji2GxD2rIoXg/rUqU6aaA683UYaJ3Q/KcYIyCRPtJnD3+G4UeugDRxvTwwLHtdS9kynE207w/man7dSzxaf1IPgSE3O0Iy1RMkyaRkj8SdFvuE35qqPV84GKmsfMEdPAwa4+Xl47GH2wvK7j/eNlkWiBzVGG+l+Rd66y/Gv9fuELGSvgxP/3LASw0YTJ+nZHg1XLhtWqk1YrBrrRl3M5Yk6W/LXe/P+Lsumlappfzu+14pDMDFHpvg6aL4Nktf3DLL4DG/O4dh6RSisEvx4pncbTNmpfdTVIU41zrLIrgTNU+0IDL3uqejcHIjaZRtKVC2lE62LZHFeedv+/24EhlxrnQqwOogc143r6jS16gH6xJkMzZk3db10vPvn9vN7lMz4bEvC3S17MGbzfcX31/iHe/1zoQ7Cz61lggUh1+dhYZRmTP1Yzz4ffuV8e+//xt+3vrHQlOATYoyNvpcSra32CRMlRahdmh0Kewn/4af7VqrNnPGwzdwAibQWqTPacPPC8Be97KbzSr55IaB9iZnd69osmb+8wErkv7oxVvJzePvOquYA5jfylZPzQ/BuLGhe096FPXeJWyoJcTsT7nDSQGAbq8/y4G8aiXMfvXWa120kvDCyfX7znTJIdfDTuptPXcI3UDK7UDKIV7Qxn9FPXB7LgzVE2GkwcleRBKffQX50WOdxmzALuajz5YJJvmHfCfKKoh93Pofj1jo6Xyvna9iCvrdFqrmZ2tX7AbhKCuixmKe7QrLCE3heiFm9q4vElZE0PM7++/x517YChINAAyeapKZiMYhH1zQphgQacKSFb5ho3vNp6Qxmb0C2ZKs8s58HRLZ58mRCCMg0ao9cFag6gdcJ0r4o9UvYE8cGeMAQIEMbHgelS5dOBhFUkfobrvQvCu1i4ieuTbcnnk24gU9sd1xEHmKkwtkxA9tleyLP2FDXL4za/A+QjnBFEZwgK0cfxKGnsA1cRh8i71xE/c+MVZpu7kyJr2IiCg4qD7z7qMSwArTt+uiRLsiBnLLiW1S4QUY7Zh9T+UXAT5uxRagctttcg+PpuO7fydJ2timJtOzVYHLzfsFxhxfIJBFvmo6bvPDPuv8GVKTyL2ZLyK9e14uzq4JWuNDfxcQlkDwvZzrFIzOItkk25Pg3oSc97dIAD1BvD7o= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 80f38b58-d0fc-4b2d-c1f9-08dbf1245fa1 X-MS-Exchange-CrossTenant-AuthSource: AM6PR04MB4838.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Nov 2023 21:44:33.0058 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: ovnIhvgycGnHm5mQ7WBhp5iI8DiK9PGm9QlwiE9wf39eNiYWUZOnguSV0dqhndkJl/nqNCg2Ure/zvkn3snxdA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBAPR04MB7416 Since difference SoCs require different sequence for exiting L2, let's add a separate "exit_from_l2()" callback. This callback can be used to execute SoC specific sequence. Change ls_pcie_exit_from_l2() return value from void to int. Return error if exit_from_l2() failure at exit resume flow. Reviewed-by: Manivannan Sadhasivam Signed-off-by: Frank Li --- Notes: Change from v3 to v4 - update commit message Add mani's review by tag Change from v2 to v3 - fixed according to mani's feedback 1. update commit message 2. move dw_pcie_host_ops to next patch 3. check return value from exit_from_l2() Change from v1 to v2 - change subject 'a' to 'A' Change from v1 to v2 - change subject 'a' to 'A' drivers/pci/controller/dwc/pci-layerscape.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-layerscape.c b/drivers/pci/controller/dwc/pci-layerscape.c index 37956e09c65bd..aea89926bcc4f 100644 --- a/drivers/pci/controller/dwc/pci-layerscape.c +++ b/drivers/pci/controller/dwc/pci-layerscape.c @@ -39,6 +39,7 @@ struct ls_pcie_drvdata { const u32 pf_off; + int (*exit_from_l2)(struct dw_pcie_rp *pp); bool pm_support; }; @@ -125,7 +126,7 @@ static void ls_pcie_send_turnoff_msg(struct dw_pcie_rp *pp) dev_err(pcie->pci->dev, "PME_Turn_off timeout\n"); } -static void ls_pcie_exit_from_l2(struct dw_pcie_rp *pp) +static int ls_pcie_exit_from_l2(struct dw_pcie_rp *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct ls_pcie *pcie = to_ls_pcie(pci); @@ -150,6 +151,8 @@ static void ls_pcie_exit_from_l2(struct dw_pcie_rp *pp) 10000); if (ret) dev_err(pcie->pci->dev, "L2 exit timeout\n"); + + return ret; } static int ls_pcie_host_init(struct dw_pcie_rp *pp) @@ -180,6 +183,7 @@ static const struct ls_pcie_drvdata ls1021a_drvdata = { static const struct ls_pcie_drvdata layerscape_drvdata = { .pf_off = 0xc0000, .pm_support = true, + .exit_from_l2 = ls_pcie_exit_from_l2, }; static const struct of_device_id ls_pcie_of_match[] = { @@ -247,11 +251,14 @@ static int ls_pcie_suspend_noirq(struct device *dev) static int ls_pcie_resume_noirq(struct device *dev) { struct ls_pcie *pcie = dev_get_drvdata(dev); + int ret; if (!pcie->drvdata->pm_support) return 0; - ls_pcie_exit_from_l2(&pcie->pci->pp); + ret = pcie->drvdata->exit_from_l2(&pcie->pci->pp); + if (ret) + return ret; return dw_pcie_resume_noirq(pcie->pci); } From patchwork Wed Nov 29 21:44:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 13473507 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=nxp.com header.i=@nxp.com header.b="Ccep8/hg" Received: from EUR02-AM0-obe.outbound.protection.outlook.com (mail-am0eur02on2081.outbound.protection.outlook.com [40.107.247.81]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7AB4F10D0; Wed, 29 Nov 2023 13:44:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=bq8rDZtew6On8My8vGe71UwrPPrAL0JvbeTziozrf0T5+nF9jgu1htXM/6K/hVKt8CIyOFMVw1lBaQmgOgFDVACFFSjGYX7fWc2I2e5jqRQrJDHdg9+e36WQzgHWHeqW2aPc0PR9OJJ7RInmzgRv5XOlDQlteBpy6EIXkuTXGnL0f51mbrpWN91PmEo0+tEkJJVbQIKADEZUmV7kcFZYMUqXLGc6CO3jR9nerran+ioVItoOW61d83mLlON2UpuLTfzhD+ct7mt1DNHY5rJG2thhItdrEqAQleA0GbuBxUKJh0cw5OA5sMXMxvBlvnrWvfOP+wbiy7LUWog1p3mdsA== ARC-Message-Signature: i=1; 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b=Ccep8/hgKEQvatDulHxiD1dbd2hkRt9e9QiMapZ/frrI1BV66XiQiLvQgHQbKqZzN1rrD8V6kp4SqBlzn69ceX4ljzgT81KjkcJBemepXbmAdhQnCqKtSY0DLmPdA/lBhDZoo1lJQRroIRwn0SOzxgRbO4aWNCFgUyiIVcaDhRw= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) by DBAPR04MB7416.eurprd04.prod.outlook.com (2603:10a6:10:1b3::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7068.11; Wed, 29 Nov 2023 21:44:37 +0000 Received: from AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::95f5:5118:258f:ee40]) by AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::95f5:5118:258f:ee40%6]) with mapi id 15.20.7046.015; Wed, 29 Nov 2023 21:44:37 +0000 From: Frank Li To: manivannan.sadhasivam@linaro.org Cc: Frank.Li@nxp.com, bhelgaas@google.com, imx@lists.linux.dev, kw@linux.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, lpieralisi@kernel.org, minghuan.Lian@nxp.com, mingkai.hu@nxp.com, robh@kernel.org, roy.zang@nxp.com Subject: [PATCH v4 2/4] PCI: layerscape: Add suspend/resume for ls1021a Date: Wed, 29 Nov 2023 16:44:10 -0500 Message-Id: <20231129214412.327633-3-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231129214412.327633-1-Frank.Li@nxp.com> References: <20231129214412.327633-1-Frank.Li@nxp.com> X-ClientProxiedBy: SJ0PR13CA0136.namprd13.prod.outlook.com (2603:10b6:a03:2c6::21) To AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM6PR04MB4838:EE_|DBAPR04MB7416:EE_ X-MS-Office365-Filtering-Correlation-Id: 9fb2c528-951d-4f01-d89b-08dbf1246216 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: QQIXzHcnKIpgMT5GsAP1N7Gbbr77yE11RivSPl/MrDdttkzmcjYNl8iOzDVBog5hMMfiO8yikUW95HbaTFZSRP8PrjREZLnKO9rkKKcNT8OGd/K2SzRU+JsOdkIFywM0pnpWHwx+sham+YQ5qOO9gSe3bny+jHOpTiMQOEsRpRMRQOXuw5WcZYIhEmalBhthuNxAAyGHvgoFQXrL/FiaJTXZfsscLGHLOgL4LA1FFoKvEr1WxlBg6gqXNQYAkJdmuPDwWVmHXPJnujpNxRRXjR6OXL2DX593App9xgPCgXUiy7bHRlLTM5YGEQEhLEg+bWq6YPGOgaBtXpcOYdmIVaS7sF6vEiRr4th4c+PR8FnYDjmRinf2NVpY05QgYk/CvuNcwcV2ycg+Bqq4qL9LScVawyX8UZCLUEb0xcgsCcPsoo4bmv8+1XKOLjnP3afhhSju7L/YD2SF49olxlLIIbqqGBAgB1yX8ZlpdtC7pQMaP9aFwLAg4ReLjoJ1mUTdK7oyEnGRTouj/VYrNq5NNiqDoM3waOeIHtGR6CrIVGAv9ScJHguaSfBbIcCdOPc37jcTvT/YFKe+ui1zIpKRhLiKOT4FM1PBQ/gDOo2NU3mYesW7jIVvQ8ntN8sVOZVRQmNbMtapvKfK7pmo/v9nwbi4Q82EJpypcu0uShBi080bSsHwi/Un0E5gLbVKYWBoQDwghddVIW3VD80lfR9yYqzu+QHvVL518Psz9RR0UpXv2QNUP2hjN9AgUSkPZrzjgqcSZ6ycaG6yvxR3qdbragK/hzWDLa+bdB2lPCCPI4JiVxdwcHAH/tiJ7swrLfvZSKB1dzc/szloye0uJdOnWUdVhnsd/rud/kERJqxeJgl9/snH5GCiChzlwtYf08P+3fIrARMF+kIVM5nGNwGMYQNPONK7sOfR/JDGLqwQcSMQNsrJKtxZ6cre0pyJQgmUjhDOoV6MqGVqRImCal9Rel8XFsG6k3f95oB/y/izXqa/wgIoa/70hk2dvRkvApoRPBZ5gh1sr/vcsVbk5iEdH7arCTIYWeOTr740wLKnA0a9M6wv1qIoHsJKIYApwotCzhcnipR+x3s2xA41A71J9CAEw52DmTJBI60PHUEqZlscMF05eNcjOk7FCPfqQW8uN5HV9i4FjntcTS7vr2HugA0ARYqaPV9aFZmpvckuvu7uD4TM+CGeGUYZddkAGIqvqKLXmQ1HzwCr3QXPj3pyDUk/f4hUsFMH7EU8JR+9vd+XFtmhMHEdZPAwHLfJRxC9Xeof9cpKB6otPfw7r1K+N179vie+tDNLYkL7OcpTZcpEuZEnSG7o1qBDaKgAu6zSFZjQeIl0XakZzKTMnfv8/bup/RHgXGzwWi01kW/JaZn308SR3vuTuiOfok22N9kRJKtggDnmo6yaVuOOqMyddw0xL5r564PMlFfffrCzehBDHM6T/ProqRTryzXw0AZX7/Fe7jLtg9zMnvdpB6/WriCuUmCmBPAn+T/Wqa0ZTb1o9fvOaQEmEORbAv7vJfI2fke0zMOyaJrahAdFKGZ0xsw86+6yQpk2GwCRHu4MjwM+d1DngbTA+E0yfs0C8IrT X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 9fb2c528-951d-4f01-d89b-08dbf1246216 X-MS-Exchange-CrossTenant-AuthSource: AM6PR04MB4838.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Nov 2023 21:44:37.1656 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: +89MQHUZpGJc5fmQw6UpVSwTmh++KcHoXi8I9/hpOUP19WU2+B0lZb5FVR8NitOzTjGH32xVIXWNiJXOhK6fMg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBAPR04MB7416 ls1021a add suspend/resume support. In the suspend path, PME_Turn_Off message is sent to the endpoint to transition the link to L2/L3_Ready state. In this SoC, there is no way to check if the controller has received the PME_To_Ack from the endpoint or not. So to be on the safer side, the driver just waits for PCIE_PME_TO_L2_TIMEOUT_US before asserting the SoC specific PMXMTTURNOFF bit to complete the PME_Turn_Off handshake. This link would then enter L2/L3 state depending on the VAUX supply. In the resume path, the link is brought back from L2 to L0 by doing a software reset. Signed-off-by: Frank Li --- Notes: Change from v3 to v4 - update commit message. - it is reset a glue logic part for PCI controller. - use regmap_write_bits() to reduce code change. Change from v2 to v3 - update according to mani's feedback change from v1 to v2 - change subject 'a' to 'A' drivers/pci/controller/dwc/pci-layerscape.c | 83 ++++++++++++++++++++- 1 file changed, 82 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pci-layerscape.c b/drivers/pci/controller/dwc/pci-layerscape.c index aea89926bcc4f..42bca2c3b5c3e 100644 --- a/drivers/pci/controller/dwc/pci-layerscape.c +++ b/drivers/pci/controller/dwc/pci-layerscape.c @@ -35,11 +35,19 @@ #define PF_MCR_PTOMR BIT(0) #define PF_MCR_EXL2S BIT(1) +/* LS1021A PEXn PM Write Control Register */ +#define SCFG_PEXPMWRCR(idx) (0x5c + (idx) * 0x64) +#define PMXMTTURNOFF BIT(31) +#define SCFG_PEXSFTRSTCR 0x190 +#define PEXSR(idx) BIT(idx) + #define PCIE_IATU_NUM 6 struct ls_pcie_drvdata { const u32 pf_off; + const struct dw_pcie_host_ops *ops; int (*exit_from_l2)(struct dw_pcie_rp *pp); + bool scfg_support; bool pm_support; }; @@ -47,6 +55,8 @@ struct ls_pcie { struct dw_pcie *pci; const struct ls_pcie_drvdata *drvdata; void __iomem *pf_base; + struct regmap *scfg; + int index; bool big_endian; }; @@ -171,13 +181,65 @@ static int ls_pcie_host_init(struct dw_pcie_rp *pp) return 0; } +static void scfg_pcie_send_turnoff_msg(struct regmap *scfg, u32 reg, u32 mask) +{ + /* Send PME_Turn_Off message */ + regmap_write_bits(scfg, reg, mask, mask); + + /* + * There is no specific register to check for PME_To_Ack from endpoint. + * So on the safe side, wait for PCIE_PME_TO_L2_TIMEOUT_US. + */ + mdelay(PCIE_PME_TO_L2_TIMEOUT_US/1000); + + /* + * Layerscape hardware reference manual recommends clearing the PMXMTTURNOFF bit + * to complete the PME_Turn_Off handshake. + */ + regmap_write_bits(scfg, reg, mask, 0); +} + +static void ls1021a_pcie_send_turnoff_msg(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct ls_pcie *pcie = to_ls_pcie(pci); + + scfg_pcie_send_turnoff_msg(pcie->scfg, SCFG_PEXPMWRCR(pcie->index), PMXMTTURNOFF); +} + +static int scfg_pcie_exit_from_l2(struct regmap *scfg, u32 reg, u32 mask) +{ + /* Only way exit from l2 is that do software reset */ + regmap_write_bits(scfg, reg, mask, mask); + + regmap_write_bits(scfg, reg, mask, 0); + + return 0; +} + +static int ls1021a_pcie_exit_from_l2(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct ls_pcie *pcie = to_ls_pcie(pci); + + return scfg_pcie_exit_from_l2(pcie->scfg, SCFG_PEXSFTRSTCR, PEXSR(pcie->index)); +} + static const struct dw_pcie_host_ops ls_pcie_host_ops = { .host_init = ls_pcie_host_init, .pme_turn_off = ls_pcie_send_turnoff_msg, }; +static const struct dw_pcie_host_ops ls1021a_pcie_host_ops = { + .host_init = ls_pcie_host_init, + .pme_turn_off = ls1021a_pcie_send_turnoff_msg, +}; + static const struct ls_pcie_drvdata ls1021a_drvdata = { - .pm_support = false, + .pm_support = true, + .scfg_support = true, + .ops = &ls1021a_pcie_host_ops, + .exit_from_l2 = ls1021a_pcie_exit_from_l2, }; static const struct ls_pcie_drvdata layerscape_drvdata = { @@ -205,6 +267,8 @@ static int ls_pcie_probe(struct platform_device *pdev) struct dw_pcie *pci; struct ls_pcie *pcie; struct resource *dbi_base; + u32 index[2]; + int ret; pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); if (!pcie) @@ -220,6 +284,7 @@ static int ls_pcie_probe(struct platform_device *pdev) pci->pp.ops = &ls_pcie_host_ops; pcie->pci = pci; + pci->pp.ops = pcie->drvdata->ops ? pcie->drvdata->ops : &ls_pcie_host_ops; dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs"); pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base); @@ -230,6 +295,22 @@ static int ls_pcie_probe(struct platform_device *pdev) pcie->pf_base = pci->dbi_base + pcie->drvdata->pf_off; + if (pcie->drvdata->scfg_support) { + pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node, "fsl,pcie-scfg"); + if (IS_ERR(pcie->scfg)) { + dev_err(dev, "No syscfg phandle specified\n"); + return PTR_ERR(pcie->scfg); + } + + ret = of_property_read_u32_array(dev->of_node, "fsl,pcie-scfg", index, 2); + if (ret) { + pcie->scfg = NULL; + return ret; + } + + pcie->index = index[1]; + } + if (!ls_pcie_is_bridge(pcie)) return -ENODEV; From patchwork Wed Nov 29 21:44:11 2023 Content-Type: text/plain; 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Received: from AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) by DBAPR04MB7416.eurprd04.prod.outlook.com (2603:10a6:10:1b3::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7068.11; Wed, 29 Nov 2023 21:44:41 +0000 Received: from AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::95f5:5118:258f:ee40]) by AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::95f5:5118:258f:ee40%6]) with mapi id 15.20.7046.015; Wed, 29 Nov 2023 21:44:41 +0000 From: Frank Li To: manivannan.sadhasivam@linaro.org Cc: Frank.Li@nxp.com, bhelgaas@google.com, imx@lists.linux.dev, kw@linux.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, lpieralisi@kernel.org, minghuan.Lian@nxp.com, mingkai.hu@nxp.com, robh@kernel.org, roy.zang@nxp.com Subject: [PATCH v4 3/4] PCI: layerscape: Rename pf_* as pf_lut_* Date: Wed, 29 Nov 2023 16:44:11 -0500 Message-Id: <20231129214412.327633-4-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231129214412.327633-1-Frank.Li@nxp.com> References: <20231129214412.327633-1-Frank.Li@nxp.com> X-ClientProxiedBy: SJ0PR13CA0136.namprd13.prod.outlook.com (2603:10b6:a03:2c6::21) To AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM6PR04MB4838:EE_|DBAPR04MB7416:EE_ X-MS-Office365-Filtering-Correlation-Id: 7c8bcb84-09f6-4a76-02bf-08dbf1246447 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Rename it to avoid duplicate pf_* and lut_* in driver. Signed-off-by: Frank Li Reviewed-by: Manivannan Sadhasivam --- Notes: pf_lut is better than pf_* or lut* because some chip use 'pf', some chip use 'lut'. change from v1 to v4 - new patch at v3 drivers/pci/controller/dwc/pci-layerscape.c | 34 ++++++++++----------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-layerscape.c b/drivers/pci/controller/dwc/pci-layerscape.c index 42bca2c3b5c3e..590e07bb27002 100644 --- a/drivers/pci/controller/dwc/pci-layerscape.c +++ b/drivers/pci/controller/dwc/pci-layerscape.c @@ -44,7 +44,7 @@ #define PCIE_IATU_NUM 6 struct ls_pcie_drvdata { - const u32 pf_off; + const u32 pf_lut_off; const struct dw_pcie_host_ops *ops; int (*exit_from_l2)(struct dw_pcie_rp *pp); bool scfg_support; @@ -54,13 +54,13 @@ struct ls_pcie_drvdata { struct ls_pcie { struct dw_pcie *pci; const struct ls_pcie_drvdata *drvdata; - void __iomem *pf_base; + void __iomem *pf_lut_base; struct regmap *scfg; int index; bool big_endian; }; -#define ls_pcie_pf_readl_addr(addr) ls_pcie_pf_readl(pcie, addr) +#define ls_pcie_pf_lut_readl_addr(addr) ls_pcie_pf_lut_readl(pcie, addr) #define to_ls_pcie(x) dev_get_drvdata((x)->dev) static bool ls_pcie_is_bridge(struct ls_pcie *pcie) @@ -101,20 +101,20 @@ static void ls_pcie_fix_error_response(struct ls_pcie *pcie) iowrite32(PCIE_ABSERR_SETTING, pci->dbi_base + PCIE_ABSERR); } -static u32 ls_pcie_pf_readl(struct ls_pcie *pcie, u32 off) +static u32 ls_pcie_pf_lut_readl(struct ls_pcie *pcie, u32 off) { if (pcie->big_endian) - return ioread32be(pcie->pf_base + off); + return ioread32be(pcie->pf_lut_base + off); - return ioread32(pcie->pf_base + off); + return ioread32(pcie->pf_lut_base + off); } -static void ls_pcie_pf_writel(struct ls_pcie *pcie, u32 off, u32 val) +static void ls_pcie_pf_lut_writel(struct ls_pcie *pcie, u32 off, u32 val) { if (pcie->big_endian) - iowrite32be(val, pcie->pf_base + off); + iowrite32be(val, pcie->pf_lut_base + off); else - iowrite32(val, pcie->pf_base + off); + iowrite32(val, pcie->pf_lut_base + off); } static void ls_pcie_send_turnoff_msg(struct dw_pcie_rp *pp) @@ -124,11 +124,11 @@ static void ls_pcie_send_turnoff_msg(struct dw_pcie_rp *pp) u32 val; int ret; - val = ls_pcie_pf_readl(pcie, LS_PCIE_PF_MCR); + val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_PF_MCR); val |= PF_MCR_PTOMR; - ls_pcie_pf_writel(pcie, LS_PCIE_PF_MCR, val); + ls_pcie_pf_lut_writel(pcie, LS_PCIE_PF_MCR, val); - ret = readx_poll_timeout(ls_pcie_pf_readl_addr, LS_PCIE_PF_MCR, + ret = readx_poll_timeout(ls_pcie_pf_lut_readl_addr, LS_PCIE_PF_MCR, val, !(val & PF_MCR_PTOMR), PCIE_PME_TO_L2_TIMEOUT_US/10, PCIE_PME_TO_L2_TIMEOUT_US); @@ -147,15 +147,15 @@ static int ls_pcie_exit_from_l2(struct dw_pcie_rp *pp) * Set PF_MCR_EXL2S bit in LS_PCIE_PF_MCR register for the link * to exit L2 state. */ - val = ls_pcie_pf_readl(pcie, LS_PCIE_PF_MCR); + val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_PF_MCR); val |= PF_MCR_EXL2S; - ls_pcie_pf_writel(pcie, LS_PCIE_PF_MCR, val); + ls_pcie_pf_lut_writel(pcie, LS_PCIE_PF_MCR, val); /* * L2 exit timeout of 10ms is not defined in the specifications, * it was chosen based on empirical observations. */ - ret = readx_poll_timeout(ls_pcie_pf_readl_addr, LS_PCIE_PF_MCR, + ret = readx_poll_timeout(ls_pcie_pf_lut_readl_addr, LS_PCIE_PF_MCR, val, !(val & PF_MCR_EXL2S), 1000, 10000); @@ -243,7 +243,7 @@ static const struct ls_pcie_drvdata ls1021a_drvdata = { }; static const struct ls_pcie_drvdata layerscape_drvdata = { - .pf_off = 0xc0000, + .pf_lut_off = 0xc0000, .pm_support = true, .exit_from_l2 = ls_pcie_exit_from_l2, }; @@ -293,7 +293,7 @@ static int ls_pcie_probe(struct platform_device *pdev) pcie->big_endian = of_property_read_bool(dev->of_node, "big-endian"); - pcie->pf_base = pci->dbi_base + pcie->drvdata->pf_off; + pcie->pf_lut_base = pci->dbi_base + pcie->drvdata->pf_lut_off; if (pcie->drvdata->scfg_support) { pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node, "fsl,pcie-scfg"); From patchwork Wed Nov 29 21:44:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 13473509 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=nxp.com header.i=@nxp.com header.b="hbTT5bX7" Received: from EUR02-AM0-obe.outbound.protection.outlook.com (mail-am0eur02on2082.outbound.protection.outlook.com [40.107.247.82]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3A0091709; Wed, 29 Nov 2023 13:44:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; 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Wed, 29 Nov 2023 21:44:44 +0000 From: Frank Li To: manivannan.sadhasivam@linaro.org Cc: Frank.Li@nxp.com, bhelgaas@google.com, imx@lists.linux.dev, kw@linux.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, lpieralisi@kernel.org, minghuan.Lian@nxp.com, mingkai.hu@nxp.com, robh@kernel.org, roy.zang@nxp.com Subject: [PATCH v4 4/4] PCI: layerscape: Add suspend/resume for ls1043a Date: Wed, 29 Nov 2023 16:44:12 -0500 Message-Id: <20231129214412.327633-5-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231129214412.327633-1-Frank.Li@nxp.com> References: <20231129214412.327633-1-Frank.Li@nxp.com> X-ClientProxiedBy: SJ0PR13CA0136.namprd13.prod.outlook.com (2603:10b6:a03:2c6::21) To AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM6PR04MB4838:EE_|DBAPR04MB7416:EE_ X-MS-Office365-Filtering-Correlation-Id: 120f70b8-0948-486f-8230-08dbf1246699 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: kNZvkY6D0WUb3GEAGFwtxIMo5lWLFN/XWWmeXHR4ce+FPq8n7jgKxFLODjiOHO7XgpSSgBiuIkuCT/0V6gdHqroQ53Dn423odSpF/4S+gRRUtmHg916rWloTpRYcnb/iT59+xko5E0yE/apAPPYhZDRPk6zQt3ALomrA4sl8jLjq33K7/cufg8k4sq1MCa76qiJJrSTemzERCIeEeAg7fuWj5a80nqFJC23ohFNJ5LM8V/3hL9j52JMN6VwrbQnUTqeaWZpXnop5gFM4DOIkD9wvPsk6+0+mGzcQQQm1F7NYElExAolhOvsbPXm6niRS0uy7dzUOhzlzTzvG7wl4Y/dv0kgUT8SPyWJ/VXoFl0UwSxExiDAWhdaxFNsst8m0dcQlNifMiuPW8cNlHuTXUTiz7doMcMIIuGzJtQBY4X4DrgUuEF5uDnknPUznAOtF6q1FjlXiQs/Sfp7ZVXb20sY8LgD51p1bXIjVs3t3vm1480LQcim0v/Y/ba/wIAKP/jZZj11+ZX+63v0rvJnfxAuRCZmzLq73oUFgKfVb0dNzRAop//2VD8iG9MVbvwiogHWXj89rdaIYk4c39GpFxO+JRgZ/ZPKS6dCQL8VG5EQYqBUXf/EKc0GJpWAiW/h6dm7L1Xpzcpqed6blbLroQWIybsmL6+JjaYL9Q23/cNkacCsEv5RKkM9FgUjTRM6TJykYxF6WtJlfjdW8rNOw9yAtAJGVr5Oe9T+J4vq4W6mOmeLTjs4XXuZ+1111K7oXZgaGZIpIYivjwU8rR61TNZ4w0qJNTib5jUwG9ec9ljoqzFWT54ejnCxjy6A4VJMGghU4Z64V9gNIro6SR9MinedCMTkFtv8U/YwqotEiPaoqEwgY4ZUaNcGcPdtpnwM+L2N0eWnf5Sx/TFkd3HmLswOH+wR3sjn5y4Di3dncWc76VwFMW0N8gseVZwISCJA+jdQvBhbEUlFWxd38Qd/9WxlG3SqwLVpIGvRM97XCPJnL5AQj0AsYu3E5EDBG3/3MAd0pjkRkExluWWctSWV9fuHI4hM9TqjN7XaAkq2dydwt4alrfOtrLZfB2L05nAHcCrBh7uE01NgkwC/xFf0bhPp85/ZFYE8jKwvBGxWkACuEcTCG1HdDcOnMSnnc+IHoyiQoNKdTgAsclNLL1xfDrr5fVXP882wOlcW2TPnD0GOOgq4xBjDfY5BjgbFMiYFbfyLl2I+dnPaytGQbR7rs4rLAU1YuqW2mly4CeYlyb/C3DYGrz6GAVcCog4WnMAoAmzl1B7TdyNHPhU21EliQOzdBOWjdmcEID+74lLmf/F3VOq/cKQg7aEaWtsDmVpb0X5p+cmWk9ZzuZ9+x/FqNHquGXHxx8A0n+Fpn79ym9DKpE06G7J1CxlvutuqmkRKQPXVG0NfpTZQU3bvIaX+Ryq/GGAr+G7dEDrEdC9OvZHGi3kRxJaSfwEzQwLvuDSSujZ5iHKmXBGehrcjxqGAfPNbaEMESGPK8bACBgJe3CXLtRtzXnLuq/6zm5/GY3+8ezWDsjqim/kysLbcYx4pAs2mEG+hXmc2/+PBf5gnDidU= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 120f70b8-0948-486f-8230-08dbf1246699 X-MS-Exchange-CrossTenant-AuthSource: AM6PR04MB4838.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Nov 2023 21:44:44.7864 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: voDQ3O9v9pgZu8BNm+qpB0oJNKiiE3jMn//dnOK7nPpiUkhU9I6Bb9y7C/ybrMkL1s/gvD0LXI0HqUf9Om6wqw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBAPR04MB7416 In the suspend path, PME_Turn_Off message is sent to the endpoint to transition the link to L2/L3_Ready state. In this SoC, there is no way to check if the controller has received the PME_To_Ack from the endpoint or not. So to be on the safer side, the driver just waits for PCIE_PME_TO_L2_TIMEOUT_US before asserting the SoC specific PMXMTTURNOFF bit to complete the PME_Turn_Off handshake. This link would then enter L2/L3 state depending on the VAUX supply. In the resume path, the link is brought back from L2 to L0 by doing a software reset. Signed-off-by: Frank Li --- Notes: Change from v3 to v4 - Call scfg_pcie_send_turnoff_msg() shared with ls1021a - update commit message Change from v2 to v3 - Remove ls_pcie_lut_readl(writel) function Change from v1 to v2 - Update subject 'a' to 'A' drivers/pci/controller/dwc/pci-layerscape.c | 63 ++++++++++++++++++++- 1 file changed, 62 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pci-layerscape.c b/drivers/pci/controller/dwc/pci-layerscape.c index 590e07bb27002..d39700b3afaaa 100644 --- a/drivers/pci/controller/dwc/pci-layerscape.c +++ b/drivers/pci/controller/dwc/pci-layerscape.c @@ -41,6 +41,15 @@ #define SCFG_PEXSFTRSTCR 0x190 #define PEXSR(idx) BIT(idx) +/* LS1043A PEX PME control register */ +#define SCFG_PEXPMECR 0x144 +#define PEXPME(idx) BIT(31 - (idx) * 4) + +/* LS1043A PEX LUT debug register */ +#define LS_PCIE_LDBG 0x7fc +#define LDBG_SR BIT(30) +#define LDBG_WE BIT(31) + #define PCIE_IATU_NUM 6 struct ls_pcie_drvdata { @@ -225,6 +234,45 @@ static int ls1021a_pcie_exit_from_l2(struct dw_pcie_rp *pp) return scfg_pcie_exit_from_l2(pcie->scfg, SCFG_PEXSFTRSTCR, PEXSR(pcie->index)); } +static void ls1043a_pcie_send_turnoff_msg(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct ls_pcie *pcie = to_ls_pcie(pci); + + scfg_pcie_send_turnoff_msg(pcie->scfg, SCFG_PEXPMECR, PEXPME(pcie->index)); +} + +static int ls1043a_pcie_exit_from_l2(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct ls_pcie *pcie = to_ls_pcie(pci); + u32 val; + + /* + * Only way let PEX module exit L2 is do a software reset. + * LDBG_WE: allows the user to have write access to the PEXDBG[SR] for both setting and + * clearing the soft reset on the PEX module. + * LDBG_SR: When SR is set to 1, the PEX module enters soft reset. + */ + val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_LDBG); + val |= LDBG_WE; + ls_pcie_pf_lut_writel(pcie, LS_PCIE_LDBG, val); + + val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_LDBG); + val |= LDBG_SR; + ls_pcie_pf_lut_writel(pcie, LS_PCIE_LDBG, val); + + val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_LDBG); + val &= ~LDBG_SR; + ls_pcie_pf_lut_writel(pcie, LS_PCIE_LDBG, val); + + val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_LDBG); + val &= ~LDBG_WE; + ls_pcie_pf_lut_writel(pcie, LS_PCIE_LDBG, val); + + return 0; +} + static const struct dw_pcie_host_ops ls_pcie_host_ops = { .host_init = ls_pcie_host_init, .pme_turn_off = ls_pcie_send_turnoff_msg, @@ -242,6 +290,19 @@ static const struct ls_pcie_drvdata ls1021a_drvdata = { .exit_from_l2 = ls1021a_pcie_exit_from_l2, }; +static const struct dw_pcie_host_ops ls1043a_pcie_host_ops = { + .host_init = ls_pcie_host_init, + .pme_turn_off = ls1043a_pcie_send_turnoff_msg, +}; + +static const struct ls_pcie_drvdata ls1043a_drvdata = { + .pf_lut_off = 0x10000, + .pm_support = true, + .scfg_support = true, + .ops = &ls1043a_pcie_host_ops, + .exit_from_l2 = ls1043a_pcie_exit_from_l2, +}; + static const struct ls_pcie_drvdata layerscape_drvdata = { .pf_lut_off = 0xc0000, .pm_support = true, @@ -252,7 +313,7 @@ static const struct of_device_id ls_pcie_of_match[] = { { .compatible = "fsl,ls1012a-pcie", .data = &layerscape_drvdata }, { .compatible = "fsl,ls1021a-pcie", .data = &ls1021a_drvdata }, { .compatible = "fsl,ls1028a-pcie", .data = &layerscape_drvdata }, - { .compatible = "fsl,ls1043a-pcie", .data = &ls1021a_drvdata }, + { .compatible = "fsl,ls1043a-pcie", .data = &ls1043a_drvdata }, { .compatible = "fsl,ls1046a-pcie", .data = &layerscape_drvdata }, { .compatible = "fsl,ls2080a-pcie", .data = &layerscape_drvdata }, { .compatible = "fsl,ls2085a-pcie", .data = &layerscape_drvdata },