From patchwork Wed Nov 29 22:21:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "David E. Box" X-Patchwork-Id: 13473606 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="bI+BVPTi" Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6A3D5C1; Wed, 29 Nov 2023 14:21:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1701296500; x=1732832500; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=/oyzykdSt+VTIrV0ILfyr4YDLUq4rAc6Mhdr6VxDMvw=; b=bI+BVPTi03S0ruJulXVDE7POVOktWBXYEOrEdVWuXvqjcn6cYPjbl1nJ Oi/Wc7VkOyJBhXJbnbZFa4HbBwWw3f3HZKi2Zd2uv9uvqNGsdJaFpakpr 1D1JORkiBpIMA+eHMhs1qvZakpI1qgv3W+wK5dwkYqDFPGNtYiAqDGzEC u3WmF9KvdXWAFStNUYjEQyUmJOV/VezdeGtJUo8a2dxAZHIH/DYgPpjSe VY5F16oY21+zZFf/hRt68+42nYTO7u61mDQ2lO5HltAChluqAc8ajxpWz jymMkpN5nH0xLeYWLySLSngG6bosEdi7qRM9NoFsYMw5+I0sDRRdggp8r g==; X-IronPort-AV: E=McAfee;i="6600,9927,10909"; a="11936990" X-IronPort-AV: E=Sophos;i="6.04,237,1695711600"; d="scan'208";a="11936990" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2023 14:21:35 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10909"; a="798070410" X-IronPort-AV: E=Sophos;i="6.04,237,1695711600"; d="scan'208";a="798070410" Received: from linux.intel.com ([10.54.29.200]) by orsmga008.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2023 14:21:32 -0800 Received: from debox1-desk4.lan (unknown [10.209.108.167]) by linux.intel.com (Postfix) with ESMTP id B8254580BF8; Wed, 29 Nov 2023 14:21:32 -0800 (PST) From: "David E. Box" To: linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, ilpo.jarvinen@linux.intel.com, rajvi.jingar@linux.intel.com Subject: [PATCH V6 01/20] platform/x86/intel/vsec: Fix xa_alloc memory leak Date: Wed, 29 Nov 2023 14:21:13 -0800 Message-Id: <20231129222132.2331261-2-david.e.box@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231129222132.2331261-1-david.e.box@linux.intel.com> References: <20231129222132.2331261-1-david.e.box@linux.intel.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Commit 936874b77dd0 ("platform/x86/intel/vsec: Add PCI error recovery support to Intel PMT") added an xarray to track the list of vsec devices to be recovered after a PCI error. But it did not provide cleanup for the list leading to a memory leak that was caught by kmemleak. Do xa_alloc() before devm_add_action_or_reset() so that the list may be cleaned up with xa_erase() in the release function. Fixes: 936874b77dd0 ("platform/x86/intel/vsec: Add PCI error recovery support to Intel PMT") Signed-off-by: David E. Box Reviewed-by: Ilpo Järvinen --- V6 - Move xa_alloc() before ida_alloc() to reduce mutex use during error recovery. - Fix return value after id_alloc() fail - Add Fixes tag - Add more detail to changelog V5 - New patch drivers/platform/x86/intel/vsec.c | 24 ++++++++++++++---------- drivers/platform/x86/intel/vsec.h | 1 + 2 files changed, 15 insertions(+), 10 deletions(-) diff --git a/drivers/platform/x86/intel/vsec.c b/drivers/platform/x86/intel/vsec.c index c1f9e4471b28..2d568466b4e2 100644 --- a/drivers/platform/x86/intel/vsec.c +++ b/drivers/platform/x86/intel/vsec.c @@ -120,6 +120,8 @@ static void intel_vsec_dev_release(struct device *dev) { struct intel_vsec_device *intel_vsec_dev = dev_to_ivdev(dev); + xa_erase(&auxdev_array, intel_vsec_dev->id); + mutex_lock(&vsec_ida_lock); ida_free(intel_vsec_dev->ida, intel_vsec_dev->auxdev.id); mutex_unlock(&vsec_ida_lock); @@ -135,19 +137,27 @@ int intel_vsec_add_aux(struct pci_dev *pdev, struct device *parent, struct auxiliary_device *auxdev = &intel_vsec_dev->auxdev; int ret, id; - mutex_lock(&vsec_ida_lock); - ret = ida_alloc(intel_vsec_dev->ida, GFP_KERNEL); - mutex_unlock(&vsec_ida_lock); + ret = xa_alloc(&auxdev_array, &intel_vsec_dev->id, intel_vsec_dev, + PMT_XA_LIMIT, GFP_KERNEL); if (ret < 0) { kfree(intel_vsec_dev->resource); kfree(intel_vsec_dev); return ret; } + mutex_lock(&vsec_ida_lock); + id = ida_alloc(intel_vsec_dev->ida, GFP_KERNEL); + mutex_unlock(&vsec_ida_lock); + if (id < 0) { + kfree(intel_vsec_dev->resource); + kfree(intel_vsec_dev); + return id; + } + if (!parent) parent = &pdev->dev; - auxdev->id = ret; + auxdev->id = id; auxdev->name = name; auxdev->dev.parent = parent; auxdev->dev.release = intel_vsec_dev_release; @@ -169,12 +179,6 @@ int intel_vsec_add_aux(struct pci_dev *pdev, struct device *parent, if (ret < 0) return ret; - /* Add auxdev to list */ - ret = xa_alloc(&auxdev_array, &id, intel_vsec_dev, PMT_XA_LIMIT, - GFP_KERNEL); - if (ret) - return ret; - return 0; } EXPORT_SYMBOL_NS_GPL(intel_vsec_add_aux, INTEL_VSEC); diff --git a/drivers/platform/x86/intel/vsec.h b/drivers/platform/x86/intel/vsec.h index 0fd042c171ba..0a6201b4a0e9 100644 --- a/drivers/platform/x86/intel/vsec.h +++ b/drivers/platform/x86/intel/vsec.h @@ -45,6 +45,7 @@ struct intel_vsec_device { struct ida *ida; struct intel_vsec_platform_info *info; int num_resources; + int id; /* xa */ void *priv_data; size_t priv_data_size; }; From patchwork Wed Nov 29 22:21:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "David E. Box" X-Patchwork-Id: 13473601 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="c+1kLW1Q" Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BE181B2; Wed, 29 Nov 2023 14:21:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1701296497; x=1732832497; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=cJyfY54HPBudYrh68xzafpqw9C8nqcKlO72JEQ0kcdQ=; b=c+1kLW1Q9nQ2+9S8LBddcdKvHkMpOHLz8I3T2NdGi1SGFij3Co0DvqDT h5HMpZKRaFpGdxAOLXdybmjybizZDj1hvZPcCqSdxXC64DVvOTz3pXy2k CV2RVqiiuSQMMH4IxKHotbXCHAzsLHwDrcShN9tKxbEIm181+6yrg8+VY msDuA0n/soiO4xvKHcly2klKZHGsf31tv3hgnJM4dUtS3v9uP7aYpqnlN qrVIHJfguXDayCZvqfYdPo+RWW4fTvGq4xcbcQk6OE0bU4SGH6UKBLfOW Z8J44vpm0b7+D6+jrGqTQyOek01uWE2+wGlS90bVrtghtFleOiKf+v4vQ w==; X-IronPort-AV: E=McAfee;i="6600,9927,10909"; a="11936986" X-IronPort-AV: E=Sophos;i="6.04,237,1695711600"; d="scan'208";a="11936986" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2023 14:21:35 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10909"; a="798070411" X-IronPort-AV: E=Sophos;i="6.04,237,1695711600"; d="scan'208";a="798070411" Received: from linux.intel.com ([10.54.29.200]) by orsmga008.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2023 14:21:33 -0800 Received: from debox1-desk4.lan (unknown [10.209.108.167]) by linux.intel.com (Postfix) with ESMTP id E0A485807E2; Wed, 29 Nov 2023 14:21:32 -0800 (PST) From: "David E. Box" To: linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, ilpo.jarvinen@linux.intel.com, rajvi.jingar@linux.intel.com Subject: [PATCH V6 02/20] platform/x86/intel/vsec: Remove unnecessary return Date: Wed, 29 Nov 2023 14:21:14 -0800 Message-Id: <20231129222132.2331261-3-david.e.box@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231129222132.2331261-1-david.e.box@linux.intel.com> References: <20231129222132.2331261-1-david.e.box@linux.intel.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 In intel_vsec_add_aux(), just return from the last call to devm_add_action_or_reset() instead of checking its return value. Suggested-by: Ilpo Järvinen Signed-off-by: David E. Box Reviewed-by: Ilpo Järvinen --- V6 - New patch drivers/platform/x86/intel/vsec.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/platform/x86/intel/vsec.c b/drivers/platform/x86/intel/vsec.c index 2d568466b4e2..340562ae2041 100644 --- a/drivers/platform/x86/intel/vsec.c +++ b/drivers/platform/x86/intel/vsec.c @@ -174,12 +174,8 @@ int intel_vsec_add_aux(struct pci_dev *pdev, struct device *parent, return ret; } - ret = devm_add_action_or_reset(parent, intel_vsec_remove_aux, + return devm_add_action_or_reset(parent, intel_vsec_remove_aux, auxdev); - if (ret < 0) - return ret; - - return 0; } EXPORT_SYMBOL_NS_GPL(intel_vsec_add_aux, INTEL_VSEC); From patchwork Wed Nov 29 22:21:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "David E. Box" X-Patchwork-Id: 13473609 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="XiM14tSx" Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4F5D2B2; Wed, 29 Nov 2023 14:21:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1701296501; x=1732832501; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=2MI25wU4ULmrwW6oRa0ViaqII4h2lvJfng37DWryzFY=; b=XiM14tSxIKuKD9spzl3nEcU9x386y2HmdO7XfdNXnWgt5MGcagL5Njo+ nqAJF3ZdLyKW03iJ45gLIcqE8ax84qGB8EpmvbDXnVN29H3r0eyMV/LJo BLJqhFhbwp+tUvynDlnNwQGSNWoA1LMIM6kvxj2AbldRgJnyEFSp0R1h1 G6/tlE88nJDXcX2D4WBWqxqFo6GbxdtkUOdBHE3sfH7Sa+cshb5gqOai9 YrAFtOpQb8x8utN2rJKFeq1qIszsHNNe4NLXT0JyHYdVSQHN6Smh1hqTI PfLxaldbMSioyROj16CiQvNRBjx9vcZGxid1RjwixyV7vFx97UDcLZ8uJ w==; X-IronPort-AV: E=McAfee;i="6600,9927,10909"; a="11937005" X-IronPort-AV: E=Sophos;i="6.04,237,1695711600"; d="scan'208";a="11937005" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2023 14:21:35 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10909"; a="798070412" X-IronPort-AV: E=Sophos;i="6.04,237,1695711600"; d="scan'208";a="798070412" Received: from linux.intel.com ([10.54.29.200]) by orsmga008.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2023 14:21:33 -0800 Received: from debox1-desk4.lan (unknown [10.209.108.167]) by linux.intel.com (Postfix) with ESMTP id 1313A580BF8; Wed, 29 Nov 2023 14:21:33 -0800 (PST) From: "David E. Box" To: linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, ilpo.jarvinen@linux.intel.com, rajvi.jingar@linux.intel.com Subject: [PATCH V6 03/20] platform/x86/intel/vsec: Move structures to header Date: Wed, 29 Nov 2023 14:21:15 -0800 Message-Id: <20231129222132.2331261-4-david.e.box@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231129222132.2331261-1-david.e.box@linux.intel.com> References: <20231129222132.2331261-1-david.e.box@linux.intel.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 In preparation for exporting an API to register Intel Vendor Specific Extended Capabilities (VSEC) from other drivers, move needed structures to the header file. Signed-off-by: David E. Box Reviewed-by: Ilpo Järvinen --- V6 - No change V5 - No change V4 - No change V3 - No change V2 - New patch splitting previous PATCH 1 drivers/platform/x86/intel/vsec.c | 35 ------------------------------ drivers/platform/x86/intel/vsec.h | 36 +++++++++++++++++++++++++++++++ 2 files changed, 36 insertions(+), 35 deletions(-) diff --git a/drivers/platform/x86/intel/vsec.c b/drivers/platform/x86/intel/vsec.c index 340562ae2041..c83e2c549fc7 100644 --- a/drivers/platform/x86/intel/vsec.c +++ b/drivers/platform/x86/intel/vsec.c @@ -24,13 +24,6 @@ #include "vsec.h" -/* Intel DVSEC offsets */ -#define INTEL_DVSEC_ENTRIES 0xA -#define INTEL_DVSEC_SIZE 0xB -#define INTEL_DVSEC_TABLE 0xC -#define INTEL_DVSEC_TABLE_BAR(x) ((x) & GENMASK(2, 0)) -#define INTEL_DVSEC_TABLE_OFFSET(x) ((x) & GENMASK(31, 3)) -#define TABLE_OFFSET_SHIFT 3 #define PMT_XA_START 0 #define PMT_XA_MAX INT_MAX #define PMT_XA_LIMIT XA_LIMIT(PMT_XA_START, PMT_XA_MAX) @@ -39,34 +32,6 @@ static DEFINE_IDA(intel_vsec_ida); static DEFINE_IDA(intel_vsec_sdsi_ida); static DEFINE_XARRAY_ALLOC(auxdev_array); -/** - * struct intel_vsec_header - Common fields of Intel VSEC and DVSEC registers. - * @rev: Revision ID of the VSEC/DVSEC register space - * @length: Length of the VSEC/DVSEC register space - * @id: ID of the feature - * @num_entries: Number of instances of the feature - * @entry_size: Size of the discovery table for each feature - * @tbir: BAR containing the discovery tables - * @offset: BAR offset of start of the first discovery table - */ -struct intel_vsec_header { - u8 rev; - u16 length; - u16 id; - u8 num_entries; - u8 entry_size; - u8 tbir; - u32 offset; -}; - -enum intel_vsec_id { - VSEC_ID_TELEMETRY = 2, - VSEC_ID_WATCHER = 3, - VSEC_ID_CRASHLOG = 4, - VSEC_ID_SDSI = 65, - VSEC_ID_TPMI = 66, -}; - static const char *intel_vsec_name(enum intel_vsec_id id) { switch (id) { diff --git a/drivers/platform/x86/intel/vsec.h b/drivers/platform/x86/intel/vsec.h index 0a6201b4a0e9..c242c07ea69c 100644 --- a/drivers/platform/x86/intel/vsec.h +++ b/drivers/platform/x86/intel/vsec.h @@ -11,9 +11,45 @@ #define VSEC_CAP_SDSI BIT(3) #define VSEC_CAP_TPMI BIT(4) +/* Intel DVSEC offsets */ +#define INTEL_DVSEC_ENTRIES 0xA +#define INTEL_DVSEC_SIZE 0xB +#define INTEL_DVSEC_TABLE 0xC +#define INTEL_DVSEC_TABLE_BAR(x) ((x) & GENMASK(2, 0)) +#define INTEL_DVSEC_TABLE_OFFSET(x) ((x) & GENMASK(31, 3)) +#define TABLE_OFFSET_SHIFT 3 + struct pci_dev; struct resource; +enum intel_vsec_id { + VSEC_ID_TELEMETRY = 2, + VSEC_ID_WATCHER = 3, + VSEC_ID_CRASHLOG = 4, + VSEC_ID_SDSI = 65, + VSEC_ID_TPMI = 66, +}; + +/** + * struct intel_vsec_header - Common fields of Intel VSEC and DVSEC registers. + * @rev: Revision ID of the VSEC/DVSEC register space + * @length: Length of the VSEC/DVSEC register space + * @id: ID of the feature + * @num_entries: Number of instances of the feature + * @entry_size: Size of the discovery table for each feature + * @tbir: BAR containing the discovery tables + * @offset: BAR offset of start of the first discovery table + */ +struct intel_vsec_header { + u8 rev; + u16 length; + u16 id; + u8 num_entries; + u8 entry_size; + u8 tbir; + u32 offset; +}; + enum intel_vsec_quirks { /* Watcher feature not supported */ VSEC_QUIRK_NO_WATCHER = BIT(0), From patchwork Wed Nov 29 22:21:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "David E. Box" X-Patchwork-Id: 13473604 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Tx0dKP7K" Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 90457BD; Wed, 29 Nov 2023 14:21:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1701296499; x=1732832499; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=pE3sub0j+/JrDbkd6ddVl6W0ILnvFOW3qKEc09tjz0w=; b=Tx0dKP7KkB2ZOvlefKh5ECao2OxG5NQHQ33TYcjMt6qkgg2NqePv0yxl lhPyDtlznobP8cEXbR6aDJ2zH2W5ABSfYk4PoP7sfduM+oYKK5CiNImrc J6xCkhPTKPxFpWE4YRa8kTFnptJk7Eic2ilQ5x9OW/SX1eXpTMzD+O2Ud exmmsQQWTExcSyRdFdGlX8+GNr0FdfMK05m3I8Yuo/rz87BL2Y+MLA/Ea 007q4Zvr7tZzlPgLzDbI3aDULObl26h80JusamsDM3rYme6eEMb24Tj4D oMQeZI+0xr91UhT8ZJlWYhGwRf0rhm9RUSs7EJeb0NF/70wO2mXObvcsQ w==; X-IronPort-AV: E=McAfee;i="6600,9927,10909"; a="11937002" X-IronPort-AV: E=Sophos;i="6.04,237,1695711600"; d="scan'208";a="11937002" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2023 14:21:35 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10909"; a="798070413" X-IronPort-AV: E=Sophos;i="6.04,237,1695711600"; d="scan'208";a="798070413" Received: from linux.intel.com ([10.54.29.200]) by orsmga008.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2023 14:21:33 -0800 Received: from debox1-desk4.lan (unknown [10.209.108.167]) by linux.intel.com (Postfix) with ESMTP id 2FA445807E2; Wed, 29 Nov 2023 14:21:33 -0800 (PST) From: "David E. Box" To: linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, ilpo.jarvinen@linux.intel.com, rajvi.jingar@linux.intel.com Subject: [PATCH V6 04/20] platform/x86/intel/vsec: remove platform_info from vsec device structure Date: Wed, 29 Nov 2023 14:21:16 -0800 Message-Id: <20231129222132.2331261-5-david.e.box@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231129222132.2331261-1-david.e.box@linux.intel.com> References: <20231129222132.2331261-1-david.e.box@linux.intel.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 In preparation for exporting an API to register Intel Vendor Specific Extended Capabilities (VSEC) from other drivers, remove the pointer to platform_info from intel_vsec_device. This prevents a potential page fault when auxiliary drivers probe and attempt to dereference this pointer to access the needed quirks field. Instead, just add the quirks to intel_vsec_device. Signed-off-by: David E. Box Reviewed-by: Ilpo Järvinen --- V6 - No change V5 - No change V4 - No change V3 - No change V2 - New patch splitting previous PATCH 1 drivers/platform/x86/intel/pmt/class.c | 2 +- drivers/platform/x86/intel/vsec.c | 2 +- drivers/platform/x86/intel/vsec.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/platform/x86/intel/pmt/class.c b/drivers/platform/x86/intel/pmt/class.c index f32a233470de..2ad91d2fd954 100644 --- a/drivers/platform/x86/intel/pmt/class.c +++ b/drivers/platform/x86/intel/pmt/class.c @@ -31,7 +31,7 @@ bool intel_pmt_is_early_client_hw(struct device *dev) * differences from the server platforms (which use the Out Of Band * Management Services Module OOBMSM). */ - return !!(ivdev->info->quirks & VSEC_QUIRK_EARLY_HW); + return !!(ivdev->quirks & VSEC_QUIRK_EARLY_HW); } EXPORT_SYMBOL_NS_GPL(intel_pmt_is_early_client_hw, INTEL_PMT); diff --git a/drivers/platform/x86/intel/vsec.c b/drivers/platform/x86/intel/vsec.c index c83e2c549fc7..ba352af65dde 100644 --- a/drivers/platform/x86/intel/vsec.c +++ b/drivers/platform/x86/intel/vsec.c @@ -193,7 +193,7 @@ static int intel_vsec_add_dev(struct pci_dev *pdev, struct intel_vsec_header *he intel_vsec_dev->pcidev = pdev; intel_vsec_dev->resource = res; intel_vsec_dev->num_resources = header->num_entries; - intel_vsec_dev->info = info; + intel_vsec_dev->quirks = info->quirks; if (header->id == VSEC_ID_SDSI) intel_vsec_dev->ida = &intel_vsec_sdsi_ida; diff --git a/drivers/platform/x86/intel/vsec.h b/drivers/platform/x86/intel/vsec.h index c242c07ea69c..8b9fad170503 100644 --- a/drivers/platform/x86/intel/vsec.h +++ b/drivers/platform/x86/intel/vsec.h @@ -79,11 +79,11 @@ struct intel_vsec_device { struct pci_dev *pcidev; struct resource *resource; struct ida *ida; - struct intel_vsec_platform_info *info; int num_resources; int id; /* xa */ void *priv_data; size_t priv_data_size; + unsigned long quirks; }; int intel_vsec_add_aux(struct pci_dev *pdev, struct device *parent, From patchwork Wed Nov 29 22:21:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "David E. Box" X-Patchwork-Id: 13473615 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="SYdFi688" Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CF692D5E; Wed, 29 Nov 2023 14:21:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1701296504; x=1732832504; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=7NVpmNIbGkzNR5bKws5rMhWK4Hzsb6NBLKtyScjr2do=; b=SYdFi688ISdGeQXwsSKB3H5KLNAy5DEoxbCP6rWTUOPlvID8rWDmAu/u LIsf7xonVJWD+0Yd09YnMtEeSb1/jdQsnAHkgeNkJnJcTNJ+3R35C2EJx ac/hGRWJWg7YOgSKDQRS3AR+UHBgGexRzdbDvLAgvfBbqW5CGRO6XIDHI WGFVzWGhtGDLMb8qJPi75eCT0vhzKZ3jdCpwtc3DwKIidmhYexLsaYxRv C2iTi+n2NTSrtHUttS2+CgBuYO1mAIIDtbG5rcwoyJrwtCZ0at+GRTF+T LlnhgfUN76K/rAWmNyIyZu6IG2za1FQNSK5JZk9BTm9XIK+Yk0jGQQezJ A==; X-IronPort-AV: E=McAfee;i="6600,9927,10909"; a="11936999" X-IronPort-AV: E=Sophos;i="6.04,237,1695711600"; d="scan'208";a="11936999" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2023 14:21:35 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10909"; a="798070415" X-IronPort-AV: E=Sophos;i="6.04,237,1695711600"; d="scan'208";a="798070415" Received: from linux.intel.com ([10.54.29.200]) by orsmga008.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2023 14:21:33 -0800 Received: from debox1-desk4.lan (unknown [10.209.108.167]) by linux.intel.com (Postfix) with ESMTP id 4E0B4580BF8; Wed, 29 Nov 2023 14:21:33 -0800 (PST) From: "David E. Box" To: linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, ilpo.jarvinen@linux.intel.com, rajvi.jingar@linux.intel.com Subject: [PATCH V6 05/20] platform/x86/intel/vsec: Use cleanup.h Date: Wed, 29 Nov 2023 14:21:17 -0800 Message-Id: <20231129222132.2331261-6-david.e.box@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231129222132.2331261-1-david.e.box@linux.intel.com> References: <20231129222132.2331261-1-david.e.box@linux.intel.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Use cleanup.h helpers to handle cleanup of resources in intel_vsec_add_dev() after failures. Signed-off-by: David E. Box Reviewed-by: Ilpo Järvinen --- V6 - No change V5 - Assign no_free_ptr(res) to resource member. This fixes __must_check_fn warning. - Remove unsed ret variable. V4 - Do no_free_ptr() before and in call to intel_vsec_add_aux(). - Add resource cleanup in this patch. V3 - New patch. drivers/platform/x86/intel/vsec.c | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/drivers/platform/x86/intel/vsec.c b/drivers/platform/x86/intel/vsec.c index ba352af65dde..27e8698ebe5e 100644 --- a/drivers/platform/x86/intel/vsec.c +++ b/drivers/platform/x86/intel/vsec.c @@ -15,6 +15,7 @@ #include #include +#include #include #include #include @@ -147,8 +148,9 @@ EXPORT_SYMBOL_NS_GPL(intel_vsec_add_aux, INTEL_VSEC); static int intel_vsec_add_dev(struct pci_dev *pdev, struct intel_vsec_header *header, struct intel_vsec_platform_info *info) { - struct intel_vsec_device *intel_vsec_dev; - struct resource *res, *tmp; + struct intel_vsec_device __free(kfree) *intel_vsec_dev = NULL; + struct resource __free(kfree) *res = NULL; + struct resource *tmp; unsigned long quirks = info->quirks; int i; @@ -170,10 +172,8 @@ static int intel_vsec_add_dev(struct pci_dev *pdev, struct intel_vsec_header *he return -ENOMEM; res = kcalloc(header->num_entries, sizeof(*res), GFP_KERNEL); - if (!res) { - kfree(intel_vsec_dev); + if (!res) return -ENOMEM; - } if (quirks & VSEC_QUIRK_TABLE_SHIFT) header->offset >>= TABLE_OFFSET_SHIFT; @@ -191,7 +191,7 @@ static int intel_vsec_add_dev(struct pci_dev *pdev, struct intel_vsec_header *he } intel_vsec_dev->pcidev = pdev; - intel_vsec_dev->resource = res; + intel_vsec_dev->resource = no_free_ptr(res); intel_vsec_dev->num_resources = header->num_entries; intel_vsec_dev->quirks = info->quirks; @@ -200,7 +200,11 @@ static int intel_vsec_add_dev(struct pci_dev *pdev, struct intel_vsec_header *he else intel_vsec_dev->ida = &intel_vsec_ida; - return intel_vsec_add_aux(pdev, NULL, intel_vsec_dev, + /* + * Pass the ownership of intel_vsec_dev and resource within it to + * intel_vsec_add_aux() + */ + return intel_vsec_add_aux(pdev, NULL, no_free_ptr(intel_vsec_dev), intel_vsec_name(header->id)); } From patchwork Wed Nov 29 22:21:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "David E. Box" X-Patchwork-Id: 13473607 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="m8dYxSsW" Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A6143C9; Wed, 29 Nov 2023 14:21:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1701296500; x=1732832500; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=xvZYvHgO1aPnYX1bisLdg94DIXjNqrQoBT9Flv01IZY=; b=m8dYxSsWIwKIM1Ut0G6DiiMx9x4clXiFz9UO57FSFUUL4jUar7GMXJbK jlgpNqK28yqq/qOxb/SW5fe3REWjgRperIQ2YXEvVHxToM7Nw4ujAMaKj qTQoMw16EfmUIgZzlBc+Wduy/vJJOQc43MTPJBAxDLJ/Zb12R2fHZ+QUe JK2aYUy8rEVVrZN2PV1OQrn5AiciVN0KejrVp5QRFxLu5/Sa6h3HmK71n dYjROWCwJ2jS0BRkhT/WJMhwjvHPqwo8+XImD6dxhhXNPReNgDPurccyR vZua7d8WfiKi4w8Ex/l2Y7q2lbn7S5jvnenLOz++dqWVyqxLE293lu4dl g==; X-IronPort-AV: E=McAfee;i="6600,9927,10909"; a="11937000" X-IronPort-AV: E=Sophos;i="6.04,237,1695711600"; d="scan'208";a="11937000" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2023 14:21:35 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10909"; a="798070417" X-IronPort-AV: E=Sophos;i="6.04,237,1695711600"; d="scan'208";a="798070417" Received: from linux.intel.com ([10.54.29.200]) by orsmga008.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2023 14:21:33 -0800 Received: from debox1-desk4.lan (unknown [10.209.108.167]) by linux.intel.com (Postfix) with ESMTP id 686685807E2; Wed, 29 Nov 2023 14:21:33 -0800 (PST) From: "David E. Box" To: linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, ilpo.jarvinen@linux.intel.com, rajvi.jingar@linux.intel.com Subject: [PATCH V6 06/20] platform/x86/intel/vsec: Assign auxdev parent by argument Date: Wed, 29 Nov 2023 14:21:18 -0800 Message-Id: <20231129222132.2331261-7-david.e.box@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231129222132.2331261-1-david.e.box@linux.intel.com> References: <20231129222132.2331261-1-david.e.box@linux.intel.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Instead of checking for a NULL parent argument in intel_vsec_add_aux() and then assigning it to the probed device, remove this check and just pass the device in the call. Since this function is exported, return -EINVAL if the parent is not specified. Signed-off-by: David E. Box Reviewed-by: Ilpo Järvinen --- V6 - No change V5 - New patch drivers/platform/x86/intel/vsec.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/platform/x86/intel/vsec.c b/drivers/platform/x86/intel/vsec.c index 27e8698ebe5e..329ba03a6da0 100644 --- a/drivers/platform/x86/intel/vsec.c +++ b/drivers/platform/x86/intel/vsec.c @@ -103,6 +103,9 @@ int intel_vsec_add_aux(struct pci_dev *pdev, struct device *parent, struct auxiliary_device *auxdev = &intel_vsec_dev->auxdev; int ret, id; + if (!parent) + return -EINVAL; + ret = xa_alloc(&auxdev_array, &intel_vsec_dev->id, intel_vsec_dev, PMT_XA_LIMIT, GFP_KERNEL); if (ret < 0) { @@ -120,9 +123,6 @@ int intel_vsec_add_aux(struct pci_dev *pdev, struct device *parent, return id; } - if (!parent) - parent = &pdev->dev; - auxdev->id = id; auxdev->name = name; auxdev->dev.parent = parent; @@ -204,7 +204,7 @@ static int intel_vsec_add_dev(struct pci_dev *pdev, struct intel_vsec_header *he * Pass the ownership of intel_vsec_dev and resource within it to * intel_vsec_add_aux() */ - return intel_vsec_add_aux(pdev, NULL, no_free_ptr(intel_vsec_dev), + return intel_vsec_add_aux(pdev, &pdev->dev, no_free_ptr(intel_vsec_dev), intel_vsec_name(header->id)); } From patchwork Wed Nov 29 22:21:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "David E. Box" X-Patchwork-Id: 13473603 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="VxLHpjwZ" Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 18CD2B6; Wed, 29 Nov 2023 14:21:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1701296499; x=1732832499; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=CEKwCDyzAKtF9bU/ZF6jhZZ1ki4rh3e/SCTBNX3kgIw=; b=VxLHpjwZiH0nUWburbOzDvXuooFzCK3BbXeKU8iT08iYRZDzJSL+DAZE HEMNwCTZvskssr1WbX0KLfd8SKAUYoslZmrSFY0NGT9UZan5Afiaf8vXm cOpiMlfl8vVOXto98etKQ5/S738QTgB5t0b5xCJpEAkoUDqeGzlDUJWN6 bPqA47yU2npSzqykoWbK/NSgLUrQNiManjstMC1zcOCjngoOJUuFkpejt 5aWV1jItm9/endvA7ZlkvpA1yEyC6cnO41VcWpYTNDmYSPXdn/E1e7AhO KdKPOxvJGpLUyHnhOPLPPbEX3SBGiPOxr2w0v1c1ea8yHfA2STB1HEmCJ w==; X-IronPort-AV: E=McAfee;i="6600,9927,10909"; a="11936995" X-IronPort-AV: E=Sophos;i="6.04,237,1695711600"; d="scan'208";a="11936995" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2023 14:21:35 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10909"; a="798070421" X-IronPort-AV: E=Sophos;i="6.04,237,1695711600"; d="scan'208";a="798070421" Received: from linux.intel.com ([10.54.29.200]) by orsmga008.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2023 14:21:33 -0800 Received: from debox1-desk4.lan (unknown [10.209.108.167]) by linux.intel.com (Postfix) with ESMTP id 84146580BF8; Wed, 29 Nov 2023 14:21:33 -0800 (PST) From: "David E. Box" To: linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, ilpo.jarvinen@linux.intel.com, rajvi.jingar@linux.intel.com Subject: [PATCH V6 07/20] platform/x86/intel/vsec: Add intel_vsec_register Date: Wed, 29 Nov 2023 14:21:19 -0800 Message-Id: <20231129222132.2331261-8-david.e.box@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231129222132.2331261-1-david.e.box@linux.intel.com> References: <20231129222132.2331261-1-david.e.box@linux.intel.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Gayatri Kammela Add and export intel_vsec_register() to allow the registration of Intel extended capabilities from other drivers. Add check to look for memory conflicts before registering a new capability. Since the vsec provider may not be a PCI device, add a parent field to intel_vsec_platform_info() to allow specifying the parent device for device managed cleanup. Signed-off-by: Gayatri Kammela Signed-off-by: David E. Box Reviewed-by: Ilpo Järvinen --- V6 - In changelog, explain need for the parent field V5 - Add parent variable in intel_vsec_add_dev() and set parent to the pci device if info->parent is not set. V4 - Move res cleanup to previous patch V3 - Replace kfree on request_mem_region fail with use of cleanup.h helper. V2 - New patch splitting previous PATCH 1 drivers/platform/x86/intel/vsec.c | 24 +++++++++++++++++++++++- drivers/platform/x86/intel/vsec.h | 4 ++++ 2 files changed, 27 insertions(+), 1 deletion(-) diff --git a/drivers/platform/x86/intel/vsec.c b/drivers/platform/x86/intel/vsec.c index 329ba03a6da0..2978d4e95bb0 100644 --- a/drivers/platform/x86/intel/vsec.c +++ b/drivers/platform/x86/intel/vsec.c @@ -151,9 +151,15 @@ static int intel_vsec_add_dev(struct pci_dev *pdev, struct intel_vsec_header *he struct intel_vsec_device __free(kfree) *intel_vsec_dev = NULL; struct resource __free(kfree) *res = NULL; struct resource *tmp; + struct device *parent; unsigned long quirks = info->quirks; int i; + if (info->parent) + parent = info->parent; + else + parent = &pdev->dev; + if (!intel_vsec_supported(header->id, info->caps)) return -EINVAL; @@ -188,6 +194,12 @@ static int intel_vsec_add_dev(struct pci_dev *pdev, struct intel_vsec_header *he header->offset + i * (header->entry_size * sizeof(u32)); tmp->end = tmp->start + (header->entry_size * sizeof(u32)) - 1; tmp->flags = IORESOURCE_MEM; + + /* Check resource is not in use */ + if (!request_mem_region(tmp->start, resource_size(tmp), "")) + return -EBUSY; + + release_mem_region(tmp->start, resource_size(tmp)); } intel_vsec_dev->pcidev = pdev; @@ -204,7 +216,7 @@ static int intel_vsec_add_dev(struct pci_dev *pdev, struct intel_vsec_header *he * Pass the ownership of intel_vsec_dev and resource within it to * intel_vsec_add_aux() */ - return intel_vsec_add_aux(pdev, &pdev->dev, no_free_ptr(intel_vsec_dev), + return intel_vsec_add_aux(pdev, parent, no_free_ptr(intel_vsec_dev), intel_vsec_name(header->id)); } @@ -322,6 +334,16 @@ static bool intel_vsec_walk_vsec(struct pci_dev *pdev, return have_devices; } +void intel_vsec_register(struct pci_dev *pdev, + struct intel_vsec_platform_info *info) +{ + if (!pdev || !info) + return; + + intel_vsec_walk_header(pdev, info); +} +EXPORT_SYMBOL_NS_GPL(intel_vsec_register, INTEL_VSEC); + static int intel_vsec_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) { struct intel_vsec_platform_info *info; diff --git a/drivers/platform/x86/intel/vsec.h b/drivers/platform/x86/intel/vsec.h index 8b9fad170503..bb8b6452df70 100644 --- a/drivers/platform/x86/intel/vsec.h +++ b/drivers/platform/x86/intel/vsec.h @@ -69,6 +69,7 @@ enum intel_vsec_quirks { /* Platform specific data */ struct intel_vsec_platform_info { + struct device *parent; struct intel_vsec_header **headers; unsigned long caps; unsigned long quirks; @@ -99,4 +100,7 @@ static inline struct intel_vsec_device *auxdev_to_ivdev(struct auxiliary_device { return container_of(auxdev, struct intel_vsec_device, auxdev); } + +void intel_vsec_register(struct pci_dev *pdev, + struct intel_vsec_platform_info *info); #endif From patchwork Wed Nov 29 22:21:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "David E. Box" X-Patchwork-Id: 13473610 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="PL6uyjrY" Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 879BFD1; Wed, 29 Nov 2023 14:21:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1701296501; x=1732832501; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=hucH4KP50LXX2Kh5Iz88BOSFqM6zBFgUJz7knousSUg=; b=PL6uyjrY0XAW8WTTHb5NlPKacI2RLv+nNPap4IsudQFlGqkanyfnDUHp zkRZvnhvfRRZQr3KcOGV5zV0cdkmdjIJoP/+OO7ENEgRGN6oE0y/X5QG8 WMcXbpBfLaJd10zUlRy/iD7qF1lg9FazSGshx2AWTBajDVjJVVOjVmBFl RXkBU1Qlvn4/KbkDoq+aJYpfdfrQFgLoMBX1OXNEDjnfg6MCpiINRoFjI ec1A+g7lLYvGY3XyeCQcBdFhEnwYHp63Ebhz9wPHkmMxppUJXbzTXSSdZ HouWaDMeT3Vmmo+egb9cnAj3vn2pTTwexAmc9XRgfJKyIfuGIoRlLHxG9 w==; X-IronPort-AV: E=McAfee;i="6600,9927,10909"; a="11937004" X-IronPort-AV: E=Sophos;i="6.04,237,1695711600"; d="scan'208";a="11937004" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2023 14:21:35 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10909"; a="798070422" X-IronPort-AV: E=Sophos;i="6.04,237,1695711600"; d="scan'208";a="798070422" Received: from linux.intel.com ([10.54.29.200]) by orsmga008.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2023 14:21:33 -0800 Received: from debox1-desk4.lan (unknown [10.209.108.167]) by linux.intel.com (Postfix) with ESMTP id A094C5807E2; Wed, 29 Nov 2023 14:21:33 -0800 (PST) From: "David E. Box" To: linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, ilpo.jarvinen@linux.intel.com, rajvi.jingar@linux.intel.com Subject: [PATCH V6 08/20] platform/x86/intel/vsec: Add base address field Date: Wed, 29 Nov 2023 14:21:20 -0800 Message-Id: <20231129222132.2331261-9-david.e.box@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231129222132.2331261-1-david.e.box@linux.intel.com> References: <20231129222132.2331261-1-david.e.box@linux.intel.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Some devices may emulate PCI VSEC capabilities in MMIO. In such cases the BAR is not readable from a config space. Provide a field for drivers to indicate the base address to be used. Signed-off-by: David E. Box Reviewed-by: Ilpo Järvinen --- V6 - No change V5 - No change V4 - No change V3 - No change V2 - No change drivers/platform/x86/intel/pmt/class.c | 14 +++++++++++--- drivers/platform/x86/intel/vsec.c | 10 ++++++++-- drivers/platform/x86/intel/vsec.h | 2 ++ 3 files changed, 21 insertions(+), 5 deletions(-) diff --git a/drivers/platform/x86/intel/pmt/class.c b/drivers/platform/x86/intel/pmt/class.c index 2ad91d2fd954..32608baaa56c 100644 --- a/drivers/platform/x86/intel/pmt/class.c +++ b/drivers/platform/x86/intel/pmt/class.c @@ -160,10 +160,11 @@ static struct class intel_pmt_class = { static int intel_pmt_populate_entry(struct intel_pmt_entry *entry, struct intel_pmt_header *header, - struct device *dev, + struct intel_vsec_device *ivdev, struct resource *disc_res) { - struct pci_dev *pci_dev = to_pci_dev(dev->parent); + struct pci_dev *pci_dev = ivdev->pcidev; + struct device *dev = &ivdev->auxdev.dev; u8 bir; /* @@ -215,6 +216,13 @@ static int intel_pmt_populate_entry(struct intel_pmt_entry *entry, break; case ACCESS_BARID: + /* Use the provided base address if it exists */ + if (ivdev->base_addr) { + entry->base_addr = ivdev->base_addr + + GET_ADDRESS(header->base_offset); + break; + } + /* * If another BAR was specified then the base offset * represents the offset within that BAR. SO retrieve the @@ -319,7 +327,7 @@ int intel_pmt_dev_create(struct intel_pmt_entry *entry, struct intel_pmt_namespa if (ret) return ret; - ret = intel_pmt_populate_entry(entry, &header, dev, disc_res); + ret = intel_pmt_populate_entry(entry, &header, intel_vsec_dev, disc_res); if (ret) return ret; diff --git a/drivers/platform/x86/intel/vsec.c b/drivers/platform/x86/intel/vsec.c index 2978d4e95bb0..648ee842d413 100644 --- a/drivers/platform/x86/intel/vsec.c +++ b/drivers/platform/x86/intel/vsec.c @@ -153,6 +153,7 @@ static int intel_vsec_add_dev(struct pci_dev *pdev, struct intel_vsec_header *he struct resource *tmp; struct device *parent; unsigned long quirks = info->quirks; + u64 base_addr; int i; if (info->parent) @@ -184,14 +185,18 @@ static int intel_vsec_add_dev(struct pci_dev *pdev, struct intel_vsec_header *he if (quirks & VSEC_QUIRK_TABLE_SHIFT) header->offset >>= TABLE_OFFSET_SHIFT; + if (info->base_addr) + base_addr = info->base_addr; + else + base_addr = pdev->resource[header->tbir].start; + /* * The DVSEC/VSEC contains the starting offset and count for a block of * discovery tables. Create a resource array of these tables to the * auxiliary device driver. */ for (i = 0, tmp = res; i < header->num_entries; i++, tmp++) { - tmp->start = pdev->resource[header->tbir].start + - header->offset + i * (header->entry_size * sizeof(u32)); + tmp->start = base_addr + header->offset + i * (header->entry_size * sizeof(u32)); tmp->end = tmp->start + (header->entry_size * sizeof(u32)) - 1; tmp->flags = IORESOURCE_MEM; @@ -206,6 +211,7 @@ static int intel_vsec_add_dev(struct pci_dev *pdev, struct intel_vsec_header *he intel_vsec_dev->resource = no_free_ptr(res); intel_vsec_dev->num_resources = header->num_entries; intel_vsec_dev->quirks = info->quirks; + intel_vsec_dev->base_addr = info->base_addr; if (header->id == VSEC_ID_SDSI) intel_vsec_dev->ida = &intel_vsec_sdsi_ida; diff --git a/drivers/platform/x86/intel/vsec.h b/drivers/platform/x86/intel/vsec.h index bb8b6452df70..e23e76129691 100644 --- a/drivers/platform/x86/intel/vsec.h +++ b/drivers/platform/x86/intel/vsec.h @@ -73,6 +73,7 @@ struct intel_vsec_platform_info { struct intel_vsec_header **headers; unsigned long caps; unsigned long quirks; + u64 base_addr; }; struct intel_vsec_device { @@ -85,6 +86,7 @@ struct intel_vsec_device { void *priv_data; size_t priv_data_size; unsigned long quirks; + u64 base_addr; }; int intel_vsec_add_aux(struct pci_dev *pdev, struct device *parent, From patchwork Wed Nov 29 22:21:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "David E. Box" X-Patchwork-Id: 13473613 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="dVBoKhq5" Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 956E7F4; Wed, 29 Nov 2023 14:21:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1701296502; x=1732832502; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=kJYw8Sg4jWhmxTchdwmX18j6/kfRum1qXopwd4av18s=; b=dVBoKhq5WH1YiaRdicUQUOeA1BOmQj3y6gD1ExDzrEFfOzV3S7q+AEP8 doDSmoenV9voHULVA3lM8DXzDpu2ADRCpvqTjcZegIYoIZU5x+RuTa8fc 9FIMzJ7E3keoe8ATGVANyMpaTVn4XtWddySFVfa0kcXw2d0jP0IZqw15m C5edSZOQVbOfGY005sZVVi+/eWX5cjCeWF71nb2XYBJxrfuIeX8X1fjy8 8TxtanRU5AVvVUGVaf5H4BpxxVhr5pOHU/fy8Tg3iMySjTbgKyLfUIM+U 7h/u7Dbjy6/7T4L7MZWZYqdF1UT8apdYwIzYqSVaqZMZsStTPN2sIbxwp A==; X-IronPort-AV: E=McAfee;i="6600,9927,10909"; a="11937007" X-IronPort-AV: E=Sophos;i="6.04,237,1695711600"; d="scan'208";a="11937007" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2023 14:21:35 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10909"; a="798070424" X-IronPort-AV: E=Sophos;i="6.04,237,1695711600"; d="scan'208";a="798070424" Received: from linux.intel.com ([10.54.29.200]) by orsmga008.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2023 14:21:33 -0800 Received: from debox1-desk4.lan (unknown [10.209.108.167]) by linux.intel.com (Postfix) with ESMTP id BCE1D580BF8; Wed, 29 Nov 2023 14:21:33 -0800 (PST) From: "David E. Box" To: linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, ilpo.jarvinen@linux.intel.com, rajvi.jingar@linux.intel.com Subject: [PATCH V6 09/20] platform/x86/intel/pmt: Add header to struct intel_pmt_entry Date: Wed, 29 Nov 2023 14:21:21 -0800 Message-Id: <20231129222132.2331261-10-david.e.box@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231129222132.2331261-1-david.e.box@linux.intel.com> References: <20231129222132.2331261-1-david.e.box@linux.intel.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The PMT header is passed to several functions. Instead, store the header in struct intel_pmt_entry which is also passed to these functions and shorten the argument list. This simplifies the calls in preparation for later changes. While here also perform a newline cleanup. Signed-off-by: David E. Box Reviewed-by: Ilpo Järvinen --- V6 - No change V5 - Mention newline cleanup in changelog V4 - No change V3 - No change V2 - No change drivers/platform/x86/intel/pmt/class.c | 8 +++----- drivers/platform/x86/intel/pmt/class.h | 16 ++++++++-------- drivers/platform/x86/intel/pmt/crashlog.c | 2 +- drivers/platform/x86/intel/pmt/telemetry.c | 2 +- 4 files changed, 13 insertions(+), 15 deletions(-) diff --git a/drivers/platform/x86/intel/pmt/class.c b/drivers/platform/x86/intel/pmt/class.c index 32608baaa56c..142a24e3727d 100644 --- a/drivers/platform/x86/intel/pmt/class.c +++ b/drivers/platform/x86/intel/pmt/class.c @@ -159,12 +159,12 @@ static struct class intel_pmt_class = { }; static int intel_pmt_populate_entry(struct intel_pmt_entry *entry, - struct intel_pmt_header *header, struct intel_vsec_device *ivdev, struct resource *disc_res) { struct pci_dev *pci_dev = ivdev->pcidev; struct device *dev = &ivdev->auxdev.dev; + struct intel_pmt_header *header = &entry->header; u8 bir; /* @@ -313,7 +313,6 @@ int intel_pmt_dev_create(struct intel_pmt_entry *entry, struct intel_pmt_namespa struct intel_vsec_device *intel_vsec_dev, int idx) { struct device *dev = &intel_vsec_dev->auxdev.dev; - struct intel_pmt_header header; struct resource *disc_res; int ret; @@ -323,16 +322,15 @@ int intel_pmt_dev_create(struct intel_pmt_entry *entry, struct intel_pmt_namespa if (IS_ERR(entry->disc_table)) return PTR_ERR(entry->disc_table); - ret = ns->pmt_header_decode(entry, &header, dev); + ret = ns->pmt_header_decode(entry, dev); if (ret) return ret; - ret = intel_pmt_populate_entry(entry, &header, intel_vsec_dev, disc_res); + ret = intel_pmt_populate_entry(entry, intel_vsec_dev, disc_res); if (ret) return ret; return intel_pmt_dev_register(entry, ns, dev); - } EXPORT_SYMBOL_NS_GPL(intel_pmt_dev_create, INTEL_PMT); diff --git a/drivers/platform/x86/intel/pmt/class.h b/drivers/platform/x86/intel/pmt/class.h index db11d58867ce..e477a19f6700 100644 --- a/drivers/platform/x86/intel/pmt/class.h +++ b/drivers/platform/x86/intel/pmt/class.h @@ -18,7 +18,15 @@ #define GET_BIR(v) ((v) & GENMASK(2, 0)) #define GET_ADDRESS(v) ((v) & GENMASK(31, 3)) +struct intel_pmt_header { + u32 base_offset; + u32 size; + u32 guid; + u8 access_type; +}; + struct intel_pmt_entry { + struct intel_pmt_header header; struct bin_attribute pmt_bin_attr; struct kobject *kobj; void __iomem *disc_table; @@ -29,19 +37,11 @@ struct intel_pmt_entry { int devid; }; -struct intel_pmt_header { - u32 base_offset; - u32 size; - u32 guid; - u8 access_type; -}; - struct intel_pmt_namespace { const char *name; struct xarray *xa; const struct attribute_group *attr_grp; int (*pmt_header_decode)(struct intel_pmt_entry *entry, - struct intel_pmt_header *header, struct device *dev); }; diff --git a/drivers/platform/x86/intel/pmt/crashlog.c b/drivers/platform/x86/intel/pmt/crashlog.c index bbb3d61d09f4..4014c02cafdb 100644 --- a/drivers/platform/x86/intel/pmt/crashlog.c +++ b/drivers/platform/x86/intel/pmt/crashlog.c @@ -223,10 +223,10 @@ static const struct attribute_group pmt_crashlog_group = { }; static int pmt_crashlog_header_decode(struct intel_pmt_entry *entry, - struct intel_pmt_header *header, struct device *dev) { void __iomem *disc_table = entry->disc_table; + struct intel_pmt_header *header = &entry->header; struct crashlog_entry *crashlog; if (!pmt_crashlog_supported(entry)) diff --git a/drivers/platform/x86/intel/pmt/telemetry.c b/drivers/platform/x86/intel/pmt/telemetry.c index 39cbc87cc28a..f86080e8bebd 100644 --- a/drivers/platform/x86/intel/pmt/telemetry.c +++ b/drivers/platform/x86/intel/pmt/telemetry.c @@ -58,10 +58,10 @@ static bool pmt_telem_region_overlaps(struct intel_pmt_entry *entry, } static int pmt_telem_header_decode(struct intel_pmt_entry *entry, - struct intel_pmt_header *header, struct device *dev) { void __iomem *disc_table = entry->disc_table; + struct intel_pmt_header *header = &entry->header; if (pmt_telem_region_overlaps(entry, dev)) return 1; From patchwork Wed Nov 29 22:21:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "David E. Box" X-Patchwork-Id: 13473617 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="cY9k0MH8" Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D624F1A5; Wed, 29 Nov 2023 14:21:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1701296503; x=1732832503; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=mTQKeEGqkVwZBu8K10JaBFk2T1W2h9axZYcKX97t0UU=; b=cY9k0MH8cN9AzZrB4VWd0C9RA8JsEiV8z9UIp9CY29hUeQkkJohUtJi7 mak0+uC1WxnBpYVgiQ6RMchd7Z/0q5jovad1bNzJNQP1x95mv6s1yQJeS VYQm2icgwlMt8PRysyp50vCpjN4E8jxTCg5i2GW58K7q1+VhE7fMLfZqs VQciKeh7XzO4X2IKWR67iHs+4GzoINfnfCV0ZjzQDKSp/WjVpW7bN3NgH 1N3CtKbJ28e7Qnq3pk9mdaAu/H+husUhb2/pCCekry6JtE1N8pvXcffzk YkuRZbrYXtwkWVa8Sn736wjl2JzwRGmOU/Aub7o9Bsg7RLhKARbf+RvGP A==; X-IronPort-AV: E=McAfee;i="6600,9927,10909"; a="11937013" X-IronPort-AV: E=Sophos;i="6.04,237,1695711600"; d="scan'208";a="11937013" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2023 14:21:35 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10909"; a="798070425" X-IronPort-AV: E=Sophos;i="6.04,237,1695711600"; d="scan'208";a="798070425" Received: from linux.intel.com ([10.54.29.200]) by orsmga008.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2023 14:21:34 -0800 Received: from debox1-desk4.lan (unknown [10.209.108.167]) by linux.intel.com (Postfix) with ESMTP id DAA855807E2; Wed, 29 Nov 2023 14:21:33 -0800 (PST) From: "David E. Box" To: linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, ilpo.jarvinen@linux.intel.com, rajvi.jingar@linux.intel.com Subject: [PATCH V6 10/20] platform/x86/intel/pmt: telemetry: Export API to read telemetry Date: Wed, 29 Nov 2023 14:21:22 -0800 Message-Id: <20231129222132.2331261-11-david.e.box@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231129222132.2331261-1-david.e.box@linux.intel.com> References: <20231129222132.2331261-1-david.e.box@linux.intel.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Export symbols to allow access to Intel PMT Telemetry data on available devices. Provides APIs to search, register, and read telemetry using a kref managed pointer that serves as a handle to a telemetry endpoint. To simplify searching for present devices, have the IDA start at 1 instead of 0 so that 0 can be used to indicate end of search. Signed-off-by: David E. Box Reviewed-by: Ilpo Järvinen --- V6 - No change V5 - No change V4 - No change V3 - Add comment for mutex lock - Fix multiline comments - Fix line lengths - Fix space/tab inconsistences in header doc V2 - Add explanation of PMT_XA_START change in changelog - change return and argument type of pmt_telem_get_next_endpoint() to unsigned long - style fixes drivers/platform/x86/intel/pmt/class.c | 21 ++- drivers/platform/x86/intel/pmt/class.h | 14 ++ drivers/platform/x86/intel/pmt/telemetry.c | 191 ++++++++++++++++++++- drivers/platform/x86/intel/pmt/telemetry.h | 126 ++++++++++++++ 4 files changed, 344 insertions(+), 8 deletions(-) create mode 100644 drivers/platform/x86/intel/pmt/telemetry.h diff --git a/drivers/platform/x86/intel/pmt/class.c b/drivers/platform/x86/intel/pmt/class.c index 142a24e3727d..4b53940a64e2 100644 --- a/drivers/platform/x86/intel/pmt/class.c +++ b/drivers/platform/x86/intel/pmt/class.c @@ -17,7 +17,7 @@ #include "../vsec.h" #include "class.h" -#define PMT_XA_START 0 +#define PMT_XA_START 1 #define PMT_XA_MAX INT_MAX #define PMT_XA_LIMIT XA_LIMIT(PMT_XA_START, PMT_XA_MAX) #define GUID_SPR_PUNIT 0x9956f43f @@ -247,6 +247,7 @@ static int intel_pmt_dev_register(struct intel_pmt_entry *entry, struct intel_pmt_namespace *ns, struct device *parent) { + struct intel_vsec_device *ivdev = dev_to_ivdev(parent); struct resource res = {0}; struct device *dev; int ret; @@ -270,7 +271,7 @@ static int intel_pmt_dev_register(struct intel_pmt_entry *entry, if (ns->attr_grp) { ret = sysfs_create_group(entry->kobj, ns->attr_grp); if (ret) - goto fail_sysfs; + goto fail_sysfs_create_group; } /* if size is 0 assume no data buffer, so no file needed */ @@ -295,13 +296,23 @@ static int intel_pmt_dev_register(struct intel_pmt_entry *entry, entry->pmt_bin_attr.size = entry->size; ret = sysfs_create_bin_file(&dev->kobj, &entry->pmt_bin_attr); - if (!ret) - return 0; + if (ret) + goto fail_ioremap; + if (ns->pmt_add_endpoint) { + ret = ns->pmt_add_endpoint(entry, ivdev->pcidev); + if (ret) + goto fail_add_endpoint; + } + + return 0; + +fail_add_endpoint: + sysfs_remove_bin_file(entry->kobj, &entry->pmt_bin_attr); fail_ioremap: if (ns->attr_grp) sysfs_remove_group(entry->kobj, ns->attr_grp); -fail_sysfs: +fail_sysfs_create_group: device_unregister(dev); fail_dev_create: xa_erase(ns->xa, entry->devid); diff --git a/drivers/platform/x86/intel/pmt/class.h b/drivers/platform/x86/intel/pmt/class.h index e477a19f6700..d23c63b73ab7 100644 --- a/drivers/platform/x86/intel/pmt/class.h +++ b/drivers/platform/x86/intel/pmt/class.h @@ -9,6 +9,7 @@ #include #include "../vsec.h" +#include "telemetry.h" /* PMT access types */ #define ACCESS_BARID 2 @@ -18,6 +19,16 @@ #define GET_BIR(v) ((v) & GENMASK(2, 0)) #define GET_ADDRESS(v) ((v) & GENMASK(31, 3)) +struct pci_dev; + +struct telem_endpoint { + struct pci_dev *pcidev; + struct telem_header header; + void __iomem *base; + bool present; + struct kref kref; +}; + struct intel_pmt_header { u32 base_offset; u32 size; @@ -26,6 +37,7 @@ struct intel_pmt_header { }; struct intel_pmt_entry { + struct telem_endpoint *ep; struct intel_pmt_header header; struct bin_attribute pmt_bin_attr; struct kobject *kobj; @@ -43,6 +55,8 @@ struct intel_pmt_namespace { const struct attribute_group *attr_grp; int (*pmt_header_decode)(struct intel_pmt_entry *entry, struct device *dev); + int (*pmt_add_endpoint)(struct intel_pmt_entry *entry, + struct pci_dev *pdev); }; bool intel_pmt_is_early_client_hw(struct device *dev); diff --git a/drivers/platform/x86/intel/pmt/telemetry.c b/drivers/platform/x86/intel/pmt/telemetry.c index f86080e8bebd..09258564dfc4 100644 --- a/drivers/platform/x86/intel/pmt/telemetry.c +++ b/drivers/platform/x86/intel/pmt/telemetry.c @@ -30,6 +30,15 @@ /* Used by client hardware to identify a fixed telemetry entry*/ #define TELEM_CLIENT_FIXED_BLOCK_GUID 0x10000000 +#define NUM_BYTES_QWORD(v) ((v) << 3) +#define SAMPLE_ID_OFFSET(v) ((v) << 3) + +#define NUM_BYTES_DWORD(v) ((v) << 2) +#define SAMPLE_ID_OFFSET32(v) ((v) << 2) + +/* Protects access to the xarray of telemetry endpoint handles */ +static DEFINE_MUTEX(ep_lock); + enum telem_type { TELEM_TYPE_PUNIT = 0, TELEM_TYPE_CRASHLOG, @@ -84,21 +93,195 @@ static int pmt_telem_header_decode(struct intel_pmt_entry *entry, return 0; } +static int pmt_telem_add_endpoint(struct intel_pmt_entry *entry, + struct pci_dev *pdev) +{ + struct telem_endpoint *ep; + + /* Endpoint lifetimes are managed by kref, not devres */ + entry->ep = kzalloc(sizeof(*(entry->ep)), GFP_KERNEL); + if (!entry->ep) + return -ENOMEM; + + ep = entry->ep; + ep->pcidev = pdev; + ep->header.access_type = entry->header.access_type; + ep->header.guid = entry->header.guid; + ep->header.base_offset = entry->header.base_offset; + ep->header.size = entry->header.size; + ep->base = entry->base; + ep->present = true; + + kref_init(&ep->kref); + + return 0; +} + static DEFINE_XARRAY_ALLOC(telem_array); static struct intel_pmt_namespace pmt_telem_ns = { .name = "telem", .xa = &telem_array, .pmt_header_decode = pmt_telem_header_decode, + .pmt_add_endpoint = pmt_telem_add_endpoint, }; +/* Called when all users unregister and the device is removed */ +static void pmt_telem_ep_release(struct kref *kref) +{ + struct telem_endpoint *ep; + + ep = container_of(kref, struct telem_endpoint, kref); + kfree(ep); +} + +unsigned long pmt_telem_get_next_endpoint(unsigned long start) +{ + struct intel_pmt_entry *entry; + unsigned long found_idx; + + mutex_lock(&ep_lock); + xa_for_each_start(&telem_array, found_idx, entry, start) { + /* + * Return first found index after start. + * 0 is not valid id. + */ + if (found_idx > start) + break; + } + mutex_unlock(&ep_lock); + + return found_idx == start ? 0 : found_idx; +} +EXPORT_SYMBOL_NS_GPL(pmt_telem_get_next_endpoint, INTEL_PMT_TELEMETRY); + +struct telem_endpoint *pmt_telem_register_endpoint(int devid) +{ + struct intel_pmt_entry *entry; + unsigned long index = devid; + + mutex_lock(&ep_lock); + entry = xa_find(&telem_array, &index, index, XA_PRESENT); + if (!entry) { + mutex_unlock(&ep_lock); + return ERR_PTR(-ENXIO); + } + + kref_get(&entry->ep->kref); + mutex_unlock(&ep_lock); + + return entry->ep; +} +EXPORT_SYMBOL_NS_GPL(pmt_telem_register_endpoint, INTEL_PMT_TELEMETRY); + +void pmt_telem_unregister_endpoint(struct telem_endpoint *ep) +{ + kref_put(&ep->kref, pmt_telem_ep_release); +} +EXPORT_SYMBOL_NS_GPL(pmt_telem_unregister_endpoint, INTEL_PMT_TELEMETRY); + +int pmt_telem_get_endpoint_info(int devid, struct telem_endpoint_info *info) +{ + struct intel_pmt_entry *entry; + unsigned long index = devid; + int err = 0; + + if (!info) + return -EINVAL; + + mutex_lock(&ep_lock); + entry = xa_find(&telem_array, &index, index, XA_PRESENT); + if (!entry) { + err = -ENXIO; + goto unlock; + } + + info->pdev = entry->ep->pcidev; + info->header = entry->ep->header; + +unlock: + mutex_unlock(&ep_lock); + return err; + +} +EXPORT_SYMBOL_NS_GPL(pmt_telem_get_endpoint_info, INTEL_PMT_TELEMETRY); + +int pmt_telem_read(struct telem_endpoint *ep, u32 id, u64 *data, u32 count) +{ + u32 offset, size; + + if (!ep->present) + return -ENODEV; + + offset = SAMPLE_ID_OFFSET(id); + size = ep->header.size; + + if (offset + NUM_BYTES_QWORD(count) > size) + return -EINVAL; + + memcpy_fromio(data, ep->base + offset, NUM_BYTES_QWORD(count)); + + return ep->present ? 0 : -EPIPE; +} +EXPORT_SYMBOL_NS_GPL(pmt_telem_read, INTEL_PMT_TELEMETRY); + +int pmt_telem_read32(struct telem_endpoint *ep, u32 id, u32 *data, u32 count) +{ + u32 offset, size; + + if (!ep->present) + return -ENODEV; + + offset = SAMPLE_ID_OFFSET32(id); + size = ep->header.size; + + if (offset + NUM_BYTES_DWORD(count) > size) + return -EINVAL; + + memcpy_fromio(data, ep->base + offset, NUM_BYTES_DWORD(count)); + + return ep->present ? 0 : -EPIPE; +} +EXPORT_SYMBOL_NS_GPL(pmt_telem_read32, INTEL_PMT_TELEMETRY); + +struct telem_endpoint * +pmt_telem_find_and_register_endpoint(struct pci_dev *pcidev, u32 guid, u16 pos) +{ + int devid = 0; + int inst = 0; + int err = 0; + + while ((devid = pmt_telem_get_next_endpoint(devid))) { + struct telem_endpoint_info ep_info; + + err = pmt_telem_get_endpoint_info(devid, &ep_info); + if (err) + return ERR_PTR(err); + + if (ep_info.header.guid == guid && ep_info.pdev == pcidev) { + if (inst == pos) + return pmt_telem_register_endpoint(devid); + ++inst; + } + } + + return ERR_PTR(-ENXIO); +} +EXPORT_SYMBOL_NS_GPL(pmt_telem_find_and_register_endpoint, INTEL_PMT_TELEMETRY); + static void pmt_telem_remove(struct auxiliary_device *auxdev) { struct pmt_telem_priv *priv = auxiliary_get_drvdata(auxdev); int i; - for (i = 0; i < priv->num_entries; i++) - intel_pmt_dev_destroy(&priv->entry[i], &pmt_telem_ns); -} + mutex_lock(&ep_lock); + for (i = 0; i < priv->num_entries; i++) { + struct intel_pmt_entry *entry = &priv->entry[i]; + + kref_put(&entry->ep->kref, pmt_telem_ep_release); + intel_pmt_dev_destroy(entry, &pmt_telem_ns); + } + mutex_unlock(&ep_lock); +}; static int pmt_telem_probe(struct auxiliary_device *auxdev, const struct auxiliary_device_id *id) { @@ -117,7 +300,9 @@ static int pmt_telem_probe(struct auxiliary_device *auxdev, const struct auxilia for (i = 0; i < intel_vsec_dev->num_resources; i++) { struct intel_pmt_entry *entry = &priv->entry[priv->num_entries]; + mutex_lock(&ep_lock); ret = intel_pmt_dev_create(entry, &pmt_telem_ns, intel_vsec_dev, i); + mutex_unlock(&ep_lock); if (ret < 0) goto abort_probe; if (ret) diff --git a/drivers/platform/x86/intel/pmt/telemetry.h b/drivers/platform/x86/intel/pmt/telemetry.h new file mode 100644 index 000000000000..d45af5512b4e --- /dev/null +++ b/drivers/platform/x86/intel/pmt/telemetry.h @@ -0,0 +1,126 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _TELEMETRY_H +#define _TELEMETRY_H + +/* Telemetry types */ +#define PMT_TELEM_TELEMETRY 0 +#define PMT_TELEM_CRASHLOG 1 + +struct telem_endpoint; +struct pci_dev; + +struct telem_header { + u8 access_type; + u16 size; + u32 guid; + u32 base_offset; +}; + +struct telem_endpoint_info { + struct pci_dev *pdev; + struct telem_header header; +}; + +/** + * pmt_telem_get_next_endpoint() - Get next device id for a telemetry endpoint + * @start: starting devid to look from + * + * This functions can be used in a while loop predicate to retrieve the devid + * of all available telemetry endpoints. Functions pmt_telem_get_next_endpoint() + * and pmt_telem_register_endpoint() can be used inside of the loop to examine + * endpoint info and register to receive a pointer to the endpoint. The pointer + * is then usable in the telemetry read calls to access the telemetry data. + * + * Return: + * * devid - devid of the next present endpoint from start + * * 0 - when no more endpoints are present after start + */ +unsigned long pmt_telem_get_next_endpoint(unsigned long start); + +/** + * pmt_telem_register_endpoint() - Register a telemetry endpoint + * @devid: device id/handle of the telemetry endpoint + * + * Increments the kref usage counter for the endpoint. + * + * Return: + * * endpoint - On success returns pointer to the telemetry endpoint + * * -ENXIO - telemetry endpoint not found + */ +struct telem_endpoint *pmt_telem_register_endpoint(int devid); + +/** + * pmt_telem_unregister_endpoint() - Unregister a telemetry endpoint + * @ep: ep structure to populate. + * + * Decrements the kref usage counter for the endpoint. + */ +void pmt_telem_unregister_endpoint(struct telem_endpoint *ep); + +/** + * pmt_telem_get_endpoint_info() - Get info for an endpoint from its devid + * @devid: device id/handle of the telemetry endpoint + * @info: Endpoint info structure to be populated + * + * Return: + * * 0 - Success + * * -ENXIO - telemetry endpoint not found for the devid + * * -EINVAL - @info is NULL + */ +int pmt_telem_get_endpoint_info(int devid, struct telem_endpoint_info *info); + +/** + * pmt_telem_find_and_register_endpoint() - Get a telemetry endpoint from + * pci_dev device, guid and pos + * @pdev: PCI device inside the Intel vsec + * @guid: GUID of the telemetry space + * @pos: Instance of the guid + * + * Return: + * * endpoint - On success returns pointer to the telemetry endpoint + * * -ENXIO - telemetry endpoint not found + */ +struct telem_endpoint *pmt_telem_find_and_register_endpoint(struct pci_dev *pcidev, + u32 guid, u16 pos); + +/** + * pmt_telem_read() - Read qwords from counter sram using sample id + * @ep: Telemetry endpoint to be read + * @id: The beginning sample id of the metric(s) to be read + * @data: Allocated qword buffer + * @count: Number of qwords requested + * + * Callers must ensure reads are aligned. When the call returns -ENODEV, + * the device has been removed and callers should unregister the telemetry + * endpoint. + * + * Return: + * * 0 - Success + * * -ENODEV - The device is not present. + * * -EINVAL - The offset is out bounds + * * -EPIPE - The device was removed during the read. Data written + * but should be considered invalid. + */ +int pmt_telem_read(struct telem_endpoint *ep, u32 id, u64 *data, u32 count); + +/** + * pmt_telem_read32() - Read qwords from counter sram using sample id + * @ep: Telemetry endpoint to be read + * @id: The beginning sample id of the metric(s) to be read + * @data: Allocated dword buffer + * @count: Number of dwords requested + * + * Callers must ensure reads are aligned. When the call returns -ENODEV, + * the device has been removed and callers should unregister the telemetry + * endpoint. + * + * Return: + * * 0 - Success + * * -ENODEV - The device is not present. + * * -EINVAL - The offset is out bounds + * * -EPIPE - The device was removed during the read. Data written + * but should be considered invalid. + */ +int pmt_telem_read32(struct telem_endpoint *ep, u32 id, u32 *data, u32 count); + +#endif From patchwork Wed Nov 29 22:21:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "David E. Box" X-Patchwork-Id: 13473619 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="gjz6VCvq" Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2CCE810CE; Wed, 29 Nov 2023 14:21:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1701296505; x=1732832505; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=7abKeGBqWJoe/utqW0SXcd0dRfgRj7nppTOamC8y3RM=; b=gjz6VCvqTvUkSKOLrGx2TmuOVmwV7rUl2nG3O1MoUio7JKgtp2HKT9Eh 3IBOShVrRAhLEWQLhw7E8uHliBbqBG068+/qte8E7AxpaSEzsc6CN/yZV H4DHmtebT/OeeZWwPjPe2bbgl5DndFMWF4J5vrhbpIN/C7VY41+8qL1pP WuBJyNVtP0/59cUoLZNh+JjP0MHDauBB+biialodhoOTUXBDi902TnY+Z pi7HkF0qIbqT2WkjG/R9JfVl07zEeU0urmMMvT8/KNPuUL+IM63F4D0Jf wiUG3LtwwDS+QtyenR75WFasH42z0boYzz+75VjEx79TQBVYvbqjXdbyd w==; X-IronPort-AV: E=McAfee;i="6600,9927,10909"; a="11937008" X-IronPort-AV: E=Sophos;i="6.04,237,1695711600"; d="scan'208";a="11937008" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2023 14:21:35 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10909"; a="798070431" X-IronPort-AV: E=Sophos;i="6.04,237,1695711600"; d="scan'208";a="798070431" Received: from linux.intel.com ([10.54.29.200]) by orsmga008.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2023 14:21:34 -0800 Received: from debox1-desk4.lan (unknown [10.209.108.167]) by linux.intel.com (Postfix) with ESMTP id 04192580BF8; Wed, 29 Nov 2023 14:21:34 -0800 (PST) From: "David E. Box" To: linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, ilpo.jarvinen@linux.intel.com, rajvi.jingar@linux.intel.com Subject: [PATCH V6 11/20] platform/x86:intel/pmc: Call pmc_get_low_power_modes from platform init Date: Wed, 29 Nov 2023 14:21:23 -0800 Message-Id: <20231129222132.2331261-12-david.e.box@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231129222132.2331261-1-david.e.box@linux.intel.com> References: <20231129222132.2331261-1-david.e.box@linux.intel.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Xi Pardee In order to setup a table of low power mode requirements for Meteor Lake, pmc_core_get_low_power_modes() will need to be run from platform init code so that the enabled modes are known, allowing the use of the pmc_for_each_mode helper. Make the function global and call it from the platform init code. Signed-off-by: Xi Pardee Signed-off-by: David E. Box Reviewed-by: Ilpo Järvinen --- V6 - No change V5 - No change V4 - No change V3 - No change V2 - Added clearer explanation for the change in the changelog drivers/platform/x86/intel/pmc/adl.c | 2 ++ drivers/platform/x86/intel/pmc/cnp.c | 2 ++ drivers/platform/x86/intel/pmc/core.c | 7 +++---- drivers/platform/x86/intel/pmc/core.h | 1 + drivers/platform/x86/intel/pmc/icl.c | 10 +++++++++- drivers/platform/x86/intel/pmc/mtl.c | 4 +++- drivers/platform/x86/intel/pmc/spt.c | 10 +++++++++- drivers/platform/x86/intel/pmc/tgl.c | 1 + 8 files changed, 30 insertions(+), 7 deletions(-) diff --git a/drivers/platform/x86/intel/pmc/adl.c b/drivers/platform/x86/intel/pmc/adl.c index 5006008e01be..64c492391ede 100644 --- a/drivers/platform/x86/intel/pmc/adl.c +++ b/drivers/platform/x86/intel/pmc/adl.c @@ -319,6 +319,8 @@ int adl_core_init(struct pmc_dev *pmcdev) if (ret) return ret; + pmc_core_get_low_power_modes(pmcdev); + /* Due to a hardware limitation, the GBE LTR blocks PC10 * when a cable is attached. Tell the PMC to ignore it. */ diff --git a/drivers/platform/x86/intel/pmc/cnp.c b/drivers/platform/x86/intel/pmc/cnp.c index 420aaa1d7c76..59298f184d0e 100644 --- a/drivers/platform/x86/intel/pmc/cnp.c +++ b/drivers/platform/x86/intel/pmc/cnp.c @@ -214,6 +214,8 @@ int cnp_core_init(struct pmc_dev *pmcdev) if (ret) return ret; + pmc_core_get_low_power_modes(pmcdev); + /* Due to a hardware limitation, the GBE LTR blocks PC10 * when a cable is attached. Tell the PMC to ignore it. */ diff --git a/drivers/platform/x86/intel/pmc/core.c b/drivers/platform/x86/intel/pmc/core.c index 84c175b9721a..3894119d61b0 100644 --- a/drivers/platform/x86/intel/pmc/core.c +++ b/drivers/platform/x86/intel/pmc/core.c @@ -966,9 +966,8 @@ static bool pmc_core_pri_verify(u32 lpm_pri, u8 *mode_order) return true; } -static void pmc_core_get_low_power_modes(struct platform_device *pdev) +void pmc_core_get_low_power_modes(struct pmc_dev *pmcdev) { - struct pmc_dev *pmcdev = platform_get_drvdata(pdev); struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN]; u8 pri_order[LPM_MAX_NUM_MODES] = LPM_DEFAULT_PRI; u8 mode_order[LPM_MAX_NUM_MODES]; @@ -1000,7 +999,8 @@ static void pmc_core_get_low_power_modes(struct platform_device *pdev) for (mode = 0; mode < LPM_MAX_NUM_MODES; mode++) pri_order[mode_order[mode]] = mode; else - dev_warn(&pdev->dev, "Assuming a default substate order for this platform\n"); + dev_warn(&pmcdev->pdev->dev, + "Assuming a default substate order for this platform\n"); /* * Loop through all modes from lowest to highest priority, @@ -1250,7 +1250,6 @@ static int pmc_core_probe(struct platform_device *pdev) } pmcdev->pmc_xram_read_bit = pmc_core_check_read_lock_bit(primary_pmc); - pmc_core_get_low_power_modes(pdev); pmc_core_do_dmi_quirks(primary_pmc); pmc_core_dbgfs_register(pmcdev); diff --git a/drivers/platform/x86/intel/pmc/core.h b/drivers/platform/x86/intel/pmc/core.h index 0729f593c6a7..ccf24e0f5e50 100644 --- a/drivers/platform/x86/intel/pmc/core.h +++ b/drivers/platform/x86/intel/pmc/core.h @@ -490,6 +490,7 @@ extern int pmc_core_send_ltr_ignore(struct pmc_dev *pmcdev, u32 value); int pmc_core_resume_common(struct pmc_dev *pmcdev); int get_primary_reg_base(struct pmc *pmc); +extern void pmc_core_get_low_power_modes(struct pmc_dev *pmcdev); extern void pmc_core_ssram_init(struct pmc_dev *pmcdev); diff --git a/drivers/platform/x86/intel/pmc/icl.c b/drivers/platform/x86/intel/pmc/icl.c index d08e3174230d..71b0fd6cb7d8 100644 --- a/drivers/platform/x86/intel/pmc/icl.c +++ b/drivers/platform/x86/intel/pmc/icl.c @@ -53,7 +53,15 @@ const struct pmc_reg_map icl_reg_map = { int icl_core_init(struct pmc_dev *pmcdev) { struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN]; + int ret; pmc->map = &icl_reg_map; - return get_primary_reg_base(pmc); + + ret = get_primary_reg_base(pmc); + if (ret) + return ret; + + pmc_core_get_low_power_modes(pmcdev); + + return ret; } diff --git a/drivers/platform/x86/intel/pmc/mtl.c b/drivers/platform/x86/intel/pmc/mtl.c index 2204bc666980..c3b5f4fe01d1 100644 --- a/drivers/platform/x86/intel/pmc/mtl.c +++ b/drivers/platform/x86/intel/pmc/mtl.c @@ -985,7 +985,7 @@ static int mtl_resume(struct pmc_dev *pmcdev) int mtl_core_init(struct pmc_dev *pmcdev) { struct pmc *pmc = pmcdev->pmcs[PMC_IDX_SOC]; - int ret = 0; + int ret; mtl_d3_fixup(); @@ -1002,6 +1002,8 @@ int mtl_core_init(struct pmc_dev *pmcdev) return ret; } + pmc_core_get_low_power_modes(pmcdev); + /* Due to a hardware limitation, the GBE LTR blocks PC10 * when a cable is attached. Tell the PMC to ignore it. */ diff --git a/drivers/platform/x86/intel/pmc/spt.c b/drivers/platform/x86/intel/pmc/spt.c index 4b6f5cbda16c..ab993a69e33e 100644 --- a/drivers/platform/x86/intel/pmc/spt.c +++ b/drivers/platform/x86/intel/pmc/spt.c @@ -137,7 +137,15 @@ const struct pmc_reg_map spt_reg_map = { int spt_core_init(struct pmc_dev *pmcdev) { struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN]; + int ret; pmc->map = &spt_reg_map; - return get_primary_reg_base(pmc); + + ret = get_primary_reg_base(pmc); + if (ret) + return ret; + + pmc_core_get_low_power_modes(pmcdev); + + return ret; } diff --git a/drivers/platform/x86/intel/pmc/tgl.c b/drivers/platform/x86/intel/pmc/tgl.c index 2449940102db..d5f1d2223c5a 100644 --- a/drivers/platform/x86/intel/pmc/tgl.c +++ b/drivers/platform/x86/intel/pmc/tgl.c @@ -263,6 +263,7 @@ int tgl_core_init(struct pmc_dev *pmcdev) if (ret) return ret; + pmc_core_get_low_power_modes(pmcdev); pmc_core_get_tgl_lpm_reqs(pmcdev->pdev); /* Due to a hardware limitation, the GBE LTR blocks PC10 * when a cable is attached. Tell the PMC to ignore it. From patchwork Wed Nov 29 22:21:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "David E. Box" X-Patchwork-Id: 13473611 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="PybWZ381" Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8C58DB6; Wed, 29 Nov 2023 14:21:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1701296502; x=1732832502; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=O5UBa7jU0JUDTCsfFNwlMZwtV0vDNoS2o3XqsF3gJ6A=; b=PybWZ381m5LLu6R2opu6ez21tIPR9EpTUoeTZ/ln1DHas6cqYtBybASX AgBmqgSMg44meJ5ttNIcv1lSm1mHCFKGBnGyB061fzRF175s9CG0tDAvl hSaVP5u5xMFQMub56JoU+tuDAa5aZBeFZiYG8vkFYOXNNh5qwfn+4yR3N ZnQyjbTG6PvFxK0Oxjl8N1KkrrvT9uQydVHLltA0tJz2GO130ouyiU2M/ Ry+CxiFA7ki8a9k9/6X6SM7Q5xrT8brgXILv8+zGPL129HXKVl+9acoIz c2LUGDHN7M6g7S3WM8UrN9tIok7SJjWUTJxcVA5LkXZE5L6IeDTjqrPiA Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10909"; a="11937006" X-IronPort-AV: E=Sophos;i="6.04,237,1695711600"; d="scan'208";a="11937006" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2023 14:21:35 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10909"; a="798070434" X-IronPort-AV: E=Sophos;i="6.04,237,1695711600"; d="scan'208";a="798070434" Received: from linux.intel.com ([10.54.29.200]) by orsmga008.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2023 14:21:34 -0800 Received: from debox1-desk4.lan (unknown [10.209.108.167]) by linux.intel.com (Postfix) with ESMTP id 1E7495807E2; Wed, 29 Nov 2023 14:21:34 -0800 (PST) From: "David E. Box" To: linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, ilpo.jarvinen@linux.intel.com, rajvi.jingar@linux.intel.com Subject: [PATCH V6 12/20] platform/x86/intel/pmc: Allow pmc_core_ssram_init to fail Date: Wed, 29 Nov 2023 14:21:24 -0800 Message-Id: <20231129222132.2331261-13-david.e.box@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231129222132.2331261-1-david.e.box@linux.intel.com> References: <20231129222132.2331261-1-david.e.box@linux.intel.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Currently, if the PMC SSRAM initialization fails, no error is returned and the only indication is that a PMC device has not been created. Instead, allow an error to be returned and handled directly by the caller. Signed-off-by: David E. Box Reviewed-by: Ilpo Järvinen --- V6 - No change V5 - No change V4 - Remove return value check in mtl.c. Proper use of the value would require returning an error status from pmc_core_add_pmc(). But the function that calls it will be removed in the next patch so wait to use it then. V3 - New patch split from V2 PATCH 9 - Add dev_warn on pmc_core_ssram_init fail drivers/platform/x86/intel/pmc/core.h | 2 +- drivers/platform/x86/intel/pmc/core_ssram.c | 21 +++++++++++++-------- 2 files changed, 14 insertions(+), 9 deletions(-) diff --git a/drivers/platform/x86/intel/pmc/core.h b/drivers/platform/x86/intel/pmc/core.h index ccf24e0f5e50..edaa70067e41 100644 --- a/drivers/platform/x86/intel/pmc/core.h +++ b/drivers/platform/x86/intel/pmc/core.h @@ -492,7 +492,7 @@ int pmc_core_resume_common(struct pmc_dev *pmcdev); int get_primary_reg_base(struct pmc *pmc); extern void pmc_core_get_low_power_modes(struct pmc_dev *pmcdev); -extern void pmc_core_ssram_init(struct pmc_dev *pmcdev); +extern int pmc_core_ssram_init(struct pmc_dev *pmcdev); int spt_core_init(struct pmc_dev *pmcdev); int cnp_core_init(struct pmc_dev *pmcdev); diff --git a/drivers/platform/x86/intel/pmc/core_ssram.c b/drivers/platform/x86/intel/pmc/core_ssram.c index 13fa16f0d52e..815950713e25 100644 --- a/drivers/platform/x86/intel/pmc/core_ssram.c +++ b/drivers/platform/x86/intel/pmc/core_ssram.c @@ -35,20 +35,20 @@ static inline u64 get_base(void __iomem *addr, u32 offset) return lo_hi_readq(addr + offset) & GENMASK_ULL(63, 3); } -static void +static int pmc_core_pmc_add(struct pmc_dev *pmcdev, u64 pwrm_base, const struct pmc_reg_map *reg_map, int pmc_index) { struct pmc *pmc = pmcdev->pmcs[pmc_index]; if (!pwrm_base) - return; + return -ENODEV; /* Memory for primary PMC has been allocated in core.c */ if (!pmc) { pmc = devm_kzalloc(&pmcdev->pdev->dev, sizeof(*pmc), GFP_KERNEL); if (!pmc) - return; + return -ENOMEM; } pmc->map = reg_map; @@ -57,10 +57,12 @@ pmc_core_pmc_add(struct pmc_dev *pmcdev, u64 pwrm_base, if (!pmc->regbase) { devm_kfree(&pmcdev->pdev->dev, pmc); - return; + return -ENOMEM; } pmcdev->pmcs[pmc_index] = pmc; + + return 0; } static void @@ -96,7 +98,7 @@ pmc_core_ssram_get_pmc(struct pmc_dev *pmcdev, void __iomem *ssram, u32 offset, iounmap(ssram); } -void pmc_core_ssram_init(struct pmc_dev *pmcdev) +int pmc_core_ssram_init(struct pmc_dev *pmcdev) { void __iomem *ssram; struct pci_dev *pcidev; @@ -105,7 +107,7 @@ void pmc_core_ssram_init(struct pmc_dev *pmcdev) pcidev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(20, 2)); if (!pcidev) - goto out; + return -ENODEV; ret = pcim_enable_device(pcidev); if (ret) @@ -123,11 +125,14 @@ void pmc_core_ssram_init(struct pmc_dev *pmcdev) pmc_core_ssram_get_pmc(pmcdev, ssram, SSRAM_PCH_OFFSET, PMC_IDX_PCH); iounmap(ssram); -out: - return; + + return 0; disable_dev: + pmcdev->ssram_pcidev = NULL; pci_disable_device(pcidev); release_dev: pci_dev_put(pcidev); + + return ret; } From patchwork Wed Nov 29 22:21:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "David E. Box" X-Patchwork-Id: 13473602 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Sk7D/fIm" Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 90D5DA8; Wed, 29 Nov 2023 14:21:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1701296498; x=1732832498; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=nb3VedcwG3zdZSHIcLy4eRGg0Oi6buv/79ezprDIXEo=; b=Sk7D/fImxnXI6Q1/nFNsi4roG6uHyNu8/uyyYDDu2jB3sDbtSo6mXsHC qNfGzk6Y730hDuQxAamK/XbCHiZ1vjys2FF0YP6jOxL2whBDdvRWNlHdx /sjKMkW4n0NRJBYk75xgJk8gVn5ZHOOGwcfyDcctJhVbymUH+7bR6vNha Dv/B42mSUcVet1kLA/YGCS97LOTDcvyhfrvAzd4vb7hRBgA8TBTylhthY HFRaOQZInaI82fY2ZlXuUy7008RzaAfgRzuQe5p23Gfr/dM3lZod5xNSG yqsJSREc6IzmDMrKS0/lkOKyGKmY/6C8Rtc9JIW0PcLl/PrqBiER3fMG/ A==; X-IronPort-AV: E=McAfee;i="6600,9927,10909"; a="11937003" X-IronPort-AV: E=Sophos;i="6.04,237,1695711600"; d="scan'208";a="11937003" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2023 14:21:35 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10909"; a="798070429" X-IronPort-AV: E=Sophos;i="6.04,237,1695711600"; d="scan'208";a="798070429" Received: from linux.intel.com ([10.54.29.200]) by orsmga008.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2023 14:21:34 -0800 Received: from debox1-desk4.lan (unknown [10.209.108.167]) by linux.intel.com (Postfix) with ESMTP id 39C33580C4B; Wed, 29 Nov 2023 14:21:34 -0800 (PST) From: "David E. Box" To: linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, ilpo.jarvinen@linux.intel.com, rajvi.jingar@linux.intel.com Subject: [PATCH V6 13/20] platform/x86/intel/pmc: Cleanup SSRAM discovery Date: Wed, 29 Nov 2023 14:21:25 -0800 Message-Id: <20231129222132.2331261-14-david.e.box@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231129222132.2331261-1-david.e.box@linux.intel.com> References: <20231129222132.2331261-1-david.e.box@linux.intel.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Clean up the code handling SSRAM discovery. Handle all resource allocation and cleanup in pmc_core_ssram_get_pmc(). Return the error status from this function but only fail the init if we fail to discover the primary PMC. Signed-off-by: David E. Box Reviewed-by: Ilpo Järvinen --- V6 - Drops patch adding cleanup helpers for iounmap() and ioport_unmap() to io.h until s390 build issue is resolved. Add pmc_core specific DEFINE_FREE helper for iounmap() for now. V5 - Use single function to handle SSRAM discovery of all PMCs. V4 - Add checking the return value from pmc_core_sram_init() to mtl.c - Use iounmap cleanup from io.h V3 - New patch split from previous PATCH 2 - Update changelog - Use cleanup.h to cleanup ioremap V2 - no change drivers/platform/x86/intel/pmc/core_ssram.c | 62 +++++++++++---------- 1 file changed, 33 insertions(+), 29 deletions(-) diff --git a/drivers/platform/x86/intel/pmc/core_ssram.c b/drivers/platform/x86/intel/pmc/core_ssram.c index 815950713e25..c1b984255571 100644 --- a/drivers/platform/x86/intel/pmc/core_ssram.c +++ b/drivers/platform/x86/intel/pmc/core_ssram.c @@ -8,6 +8,7 @@ * */ +#include #include #include @@ -21,6 +22,8 @@ #define SSRAM_IOE_OFFSET 0x68 #define SSRAM_DEVID_OFFSET 0x70 +DEFINE_FREE(pmc_core_iounmap, void __iomem *, iounmap(_T)); + static const struct pmc_reg_map *pmc_core_find_regmap(struct pmc_info *list, u16 devid) { for (; list->map; ++list) @@ -65,44 +68,49 @@ pmc_core_pmc_add(struct pmc_dev *pmcdev, u64 pwrm_base, return 0; } -static void -pmc_core_ssram_get_pmc(struct pmc_dev *pmcdev, void __iomem *ssram, u32 offset, - int pmc_idx) +static int +pmc_core_ssram_get_pmc(struct pmc_dev *pmcdev, int pmc_idx, u32 offset) { - u64 pwrm_base; + struct pci_dev *ssram_pcidev = pmcdev->ssram_pcidev; + void __iomem __free(pmc_core_iounmap) *tmp_ssram = NULL; + void __iomem __free(pmc_core_iounmap) *ssram = NULL; + const struct pmc_reg_map *map; + u64 ssram_base, pwrm_base; u16 devid; - if (pmc_idx != PMC_IDX_SOC) { - u64 ssram_base = get_base(ssram, offset); + if (!pmcdev->regmap_list) + return -ENOENT; - if (!ssram_base) - return; + ssram_base = ssram_pcidev->resource[0].start; + tmp_ssram = ioremap(ssram_base, SSRAM_HDR_SIZE); + if (pmc_idx != PMC_IDX_MAIN) { + /* + * The secondary PMC BARS (which are behind hidden PCI devices) + * are read from fixed offsets in MMIO of the primary PMC BAR. + */ + ssram_base = get_base(tmp_ssram, offset); ssram = ioremap(ssram_base, SSRAM_HDR_SIZE); if (!ssram) - return; + return -ENOMEM; + + } else { + ssram = no_free_ptr(tmp_ssram); } pwrm_base = get_base(ssram, SSRAM_PWRM_OFFSET); devid = readw(ssram + SSRAM_DEVID_OFFSET); - if (pmcdev->regmap_list) { - const struct pmc_reg_map *map; + map = pmc_core_find_regmap(pmcdev->regmap_list, devid); + if (!map) + return -ENODEV; - map = pmc_core_find_regmap(pmcdev->regmap_list, devid); - if (map) - pmc_core_pmc_add(pmcdev, pwrm_base, map, pmc_idx); - } - - if (pmc_idx != PMC_IDX_SOC) - iounmap(ssram); + return pmc_core_pmc_add(pmcdev, pwrm_base, map, PMC_IDX_MAIN); } int pmc_core_ssram_init(struct pmc_dev *pmcdev) { - void __iomem *ssram; struct pci_dev *pcidev; - u64 ssram_base; int ret; pcidev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(20, 2)); @@ -113,18 +121,14 @@ int pmc_core_ssram_init(struct pmc_dev *pmcdev) if (ret) goto release_dev; - ssram_base = pcidev->resource[0].start; - ssram = ioremap(ssram_base, SSRAM_HDR_SIZE); - if (!ssram) - goto disable_dev; - pmcdev->ssram_pcidev = pcidev; - pmc_core_ssram_get_pmc(pmcdev, ssram, 0, PMC_IDX_SOC); - pmc_core_ssram_get_pmc(pmcdev, ssram, SSRAM_IOE_OFFSET, PMC_IDX_IOE); - pmc_core_ssram_get_pmc(pmcdev, ssram, SSRAM_PCH_OFFSET, PMC_IDX_PCH); + ret = pmc_core_ssram_get_pmc(pmcdev, PMC_IDX_MAIN, 0); + if (ret) + goto disable_dev; - iounmap(ssram); + pmc_core_ssram_get_pmc(pmcdev, PMC_IDX_IOE, SSRAM_IOE_OFFSET); + pmc_core_ssram_get_pmc(pmcdev, PMC_IDX_PCH, SSRAM_PCH_OFFSET); return 0; From patchwork Wed Nov 29 22:21:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "David E. Box" X-Patchwork-Id: 13473608 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="bhTyLuFc" Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A42C7DC; Wed, 29 Nov 2023 14:21:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1701296501; x=1732832501; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=nE/Fz9/Og+Wogrm3SSh3ppiII4ChSXaZ/7QfluPgCK0=; b=bhTyLuFcE2wblHWZayKwr42Ozk6+tSlOcacKukJN5+K0+I6FHH9aKo4u ImucKErp1ST7zjQvt/Eywn6e8gRTL5Zk8JT3YpE655QdahbB2Hm3SntTs oae6ZkHMAy+0H4xyKQHSeWJCgWSB8z9oL+gEGJOq7ZAOOUnzZvKbHbtrd vT9z9ukhFUDIDc75D5iXkY3C+Kb27EzJUXr0fSNqwo4Jns+gT0k80i45T O2MuQbP0zEYc0CS1ySYPugiKxGCArMf+08VrpZ4c6MZIiw4ikXU8g0HcF +4Nw4vZbDDhLfH1O34ACg52Rft/FBauYSnnL83OGfR2ZWWWNcZ5kBb/d4 Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10909"; a="11937001" X-IronPort-AV: E=Sophos;i="6.04,237,1695711600"; d="scan'208";a="11937001" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2023 14:21:35 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10909"; a="798070430" X-IronPort-AV: E=Sophos;i="6.04,237,1695711600"; d="scan'208";a="798070430" Received: from linux.intel.com ([10.54.29.200]) by orsmga008.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2023 14:21:34 -0800 Received: from debox1-desk4.lan (unknown [10.209.108.167]) by linux.intel.com (Postfix) with ESMTP id 57C08580CB8; Wed, 29 Nov 2023 14:21:34 -0800 (PST) From: "David E. Box" To: linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, ilpo.jarvinen@linux.intel.com, rajvi.jingar@linux.intel.com Subject: [PATCH V6 14/20] platform/x86/intel/pmc/mtl: Use return value from pmc_core_ssram_init() Date: Wed, 29 Nov 2023 14:21:26 -0800 Message-Id: <20231129222132.2331261-15-david.e.box@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231129222132.2331261-1-david.e.box@linux.intel.com> References: <20231129222132.2331261-1-david.e.box@linux.intel.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Instead of checking for a NULL regbase, use the return value from pmc_core_ssram_init() to check if PMC discovery was successful. If not, use the legacy enumeration method (which only works for the primary PMC). Signed-off-by: David E. Box Reviewed-by: Ilpo Järvinen --- V6 - No change V5 - New patch. Split from previous. drivers/platform/x86/intel/pmc/mtl.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/platform/x86/intel/pmc/mtl.c b/drivers/platform/x86/intel/pmc/mtl.c index c3b5f4fe01d1..d1d3d33fb4b8 100644 --- a/drivers/platform/x86/intel/pmc/mtl.c +++ b/drivers/platform/x86/intel/pmc/mtl.c @@ -990,12 +990,16 @@ int mtl_core_init(struct pmc_dev *pmcdev) mtl_d3_fixup(); pmcdev->resume = mtl_resume; - pmcdev->regmap_list = mtl_pmc_info_list; - pmc_core_ssram_init(pmcdev); - /* If regbase not assigned, set map and discover using legacy method */ - if (!pmc->regbase) { + /* + * If ssram init fails use legacy method to at least get the + * primary PMC + */ + ret = pmc_core_ssram_init(pmcdev); + if (ret) { + dev_warn(&pmcdev->pdev->dev, + "ssram init failed, %d, using legacy init\n", ret); pmc->map = &mtl_socm_reg_map; ret = get_primary_reg_base(pmc); if (ret) From patchwork Wed Nov 29 22:21:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "David E. Box" X-Patchwork-Id: 13473614 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Lx27ZCfa" Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7DAD6193; Wed, 29 Nov 2023 14:21:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1701296503; x=1732832503; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=5UoZQm+5mlrVi2iED5gw7GUDbpPxS++v3tW390wcYxA=; b=Lx27ZCfasTNeE20rYeXWujjuEiSQeiUUyxguIz3YM6xmrjhflixiIx1D gYr1RH8hU5NTN4KVTrfc/GeQQiFT9RiKcuWvlc7maNddgl/0bMf7TMc4H ZG2bAz951Cf6EZ73aFtby4yRbpg38aIXHjMvk83vWvHtPPImPJNroTK7w QLrEi529sMxYsSQP9GnvtPdJp2MEfgWqp7Ono1/ZikSx/ppb5smniZrjM D0Jo5ZWyXr0w1ORTTXQO0nweP6JkVMiaJ1J3Miqf0jLIdE4Yl1FNQGaAD ry8v6jn82SVeLPrwAY9defvj+UcemXoq4sDqFdc3jm2V+bwh4VHqrcDIp w==; X-IronPort-AV: E=McAfee;i="6600,9927,10909"; a="11937015" X-IronPort-AV: E=Sophos;i="6.04,237,1695711600"; d="scan'208";a="11937015" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2023 14:21:35 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10909"; a="798070438" X-IronPort-AV: E=Sophos;i="6.04,237,1695711600"; d="scan'208";a="798070438" Received: from linux.intel.com ([10.54.29.200]) by orsmga008.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2023 14:21:34 -0800 Received: from debox1-desk4.lan (unknown [10.209.108.167]) by linux.intel.com (Postfix) with ESMTP id 74964580ABB; Wed, 29 Nov 2023 14:21:34 -0800 (PST) From: "David E. Box" To: linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, ilpo.jarvinen@linux.intel.com, rajvi.jingar@linux.intel.com Subject: [PATCH V6 15/20] platform/x86/intel/pmc: Find and register PMC telemetry entries Date: Wed, 29 Nov 2023 14:21:27 -0800 Message-Id: <20231129222132.2331261-16-david.e.box@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231129222132.2331261-1-david.e.box@linux.intel.com> References: <20231129222132.2331261-1-david.e.box@linux.intel.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The PMC SSRAM device contains counters that are structured in Intel Platform Monitoring Technology (PMT) telemetry regions. Look for and register these telemetry regions from the driver so that they may be read using the Intel PMT ABI. Signed-off-by: David E. Box Reviewed-by: Ilpo Järvinen --- V6 - No change V5 - no change V4 - no change V3 - no change V2 - no change drivers/platform/x86/intel/pmc/Kconfig | 1 + drivers/platform/x86/intel/pmc/core_ssram.c | 49 +++++++++++++++++++++ 2 files changed, 50 insertions(+) diff --git a/drivers/platform/x86/intel/pmc/Kconfig b/drivers/platform/x86/intel/pmc/Kconfig index b526597e4deb..d2f651fbec2c 100644 --- a/drivers/platform/x86/intel/pmc/Kconfig +++ b/drivers/platform/x86/intel/pmc/Kconfig @@ -7,6 +7,7 @@ config INTEL_PMC_CORE tristate "Intel PMC Core driver" depends on PCI depends on ACPI + depends on INTEL_PMT_TELEMETRY help The Intel Platform Controller Hub for Intel Core SoCs provides access to Power Management Controller registers via various interfaces. This diff --git a/drivers/platform/x86/intel/pmc/core_ssram.c b/drivers/platform/x86/intel/pmc/core_ssram.c index c1b984255571..9ca720f9cbb2 100644 --- a/drivers/platform/x86/intel/pmc/core_ssram.c +++ b/drivers/platform/x86/intel/pmc/core_ssram.c @@ -13,6 +13,8 @@ #include #include "core.h" +#include "../vsec.h" +#include "../pmt/telemetry.h" #define SSRAM_HDR_SIZE 0x100 #define SSRAM_PWRM_OFFSET 0x14 @@ -24,6 +26,49 @@ DEFINE_FREE(pmc_core_iounmap, void __iomem *, iounmap(_T)); +static void +pmc_add_pmt(struct pmc_dev *pmcdev, u64 ssram_base, void __iomem *ssram) +{ + struct pci_dev *pcidev = pmcdev->ssram_pcidev; + struct intel_vsec_platform_info info = {}; + struct intel_vsec_header *headers[2] = {}; + struct intel_vsec_header header; + void __iomem *dvsec; + u32 dvsec_offset; + u32 table, hdr; + + ssram = ioremap(ssram_base, SSRAM_HDR_SIZE); + if (!ssram) + return; + + dvsec_offset = readl(ssram + SSRAM_DVSEC_OFFSET); + iounmap(ssram); + + dvsec = ioremap(ssram_base + dvsec_offset, SSRAM_DVSEC_SIZE); + if (!dvsec) + return; + + hdr = readl(dvsec + PCI_DVSEC_HEADER1); + header.id = readw(dvsec + PCI_DVSEC_HEADER2); + header.rev = PCI_DVSEC_HEADER1_REV(hdr); + header.length = PCI_DVSEC_HEADER1_LEN(hdr); + header.num_entries = readb(dvsec + INTEL_DVSEC_ENTRIES); + header.entry_size = readb(dvsec + INTEL_DVSEC_SIZE); + + table = readl(dvsec + INTEL_DVSEC_TABLE); + header.tbir = INTEL_DVSEC_TABLE_BAR(table); + header.offset = INTEL_DVSEC_TABLE_OFFSET(table); + iounmap(dvsec); + + headers[0] = &header; + info.caps = VSEC_CAP_TELEMETRY; + info.headers = headers; + info.base_addr = ssram_base; + info.parent = &pmcdev->pdev->dev; + + intel_vsec_register(pcidev, &info); +} + static const struct pmc_reg_map *pmc_core_find_regmap(struct pmc_info *list, u16 devid) { for (; list->map; ++list) @@ -101,6 +146,9 @@ pmc_core_ssram_get_pmc(struct pmc_dev *pmcdev, int pmc_idx, u32 offset) pwrm_base = get_base(ssram, SSRAM_PWRM_OFFSET); devid = readw(ssram + SSRAM_DEVID_OFFSET); + /* Find and register and PMC telemetry entries */ + pmc_add_pmt(pmcdev, ssram_base, ssram); + map = pmc_core_find_regmap(pmcdev->regmap_list, devid); if (!map) return -ENODEV; @@ -140,3 +188,4 @@ int pmc_core_ssram_init(struct pmc_dev *pmcdev) return ret; } +MODULE_IMPORT_NS(INTEL_VSEC); From patchwork Wed Nov 29 22:21:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "David E. Box" X-Patchwork-Id: 13473612 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="VYCIn3qp" Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 422EFA8; Wed, 29 Nov 2023 14:21:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1701296502; x=1732832502; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=XwhfWuy+bq1RolUlxjYZAzfBQKpo5+rwImS6TwTG/Zg=; b=VYCIn3qpfDmjw/wAgXj74Qvb2LPBg5HJmAJSwjwv6H+NdKrAfwguH13L oUyMMVZ1q4w0XNRl7x5YUtuxIZ1BPQI9woQTHSHeAOuHS/6U0T9Vx4O3a Q1UxS/Sn89yh8v3xiSdXoRFjRE/EWvJlKFwP8jjrggtQs1gDehVIbKJ1m U47E2FbkwinqCOaKsSYcBHCnE8ZrSPEfCyYD5Wrl//G0DzHUlEFPvt7e6 gGxJBISlXWS1tD5/yRNmS3Yf7ZJ/AguATZOlrJkFbeBxHiuzoCytCX4ow dcZJ/SL04R7iMX5b6fG+WQlLvF3UOEAqw8fqgieF/iyql7U9toFbz7iQQ Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10909"; a="11937009" X-IronPort-AV: E=Sophos;i="6.04,237,1695711600"; d="scan'208";a="11937009" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2023 14:21:35 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10909"; a="798070441" X-IronPort-AV: E=Sophos;i="6.04,237,1695711600"; d="scan'208";a="798070441" Received: from linux.intel.com ([10.54.29.200]) by orsmga008.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2023 14:21:34 -0800 Received: from debox1-desk4.lan (unknown [10.209.108.167]) by linux.intel.com (Postfix) with ESMTP id 977E5580BF8; Wed, 29 Nov 2023 14:21:34 -0800 (PST) From: "David E. Box" To: linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, ilpo.jarvinen@linux.intel.com, rajvi.jingar@linux.intel.com Subject: [PATCH V6 16/20] platform/x86/intel/pmc: Display LPM requirements for multiple PMCs Date: Wed, 29 Nov 2023 14:21:28 -0800 Message-Id: <20231129222132.2331261-17-david.e.box@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231129222132.2331261-1-david.e.box@linux.intel.com> References: <20231129222132.2331261-1-david.e.box@linux.intel.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Rajvi Jingar Update the substate_requirements attribute to display the requirements for all the PMCs on a package. Signed-off-by: Rajvi Jingar Signed-off-by: David E. Box Reviewed-by: Ilpo Järvinen --- V6 - Add comment to document reason to check lpm_req_regs for NULL again V5 - Use conditional instead of if/else to do seq_printf() V4 - No change V3 - Add missing submitter signoff V2 - no change drivers/platform/x86/intel/pmc/core.c | 123 ++++++++++++++------------ 1 file changed, 68 insertions(+), 55 deletions(-) diff --git a/drivers/platform/x86/intel/pmc/core.c b/drivers/platform/x86/intel/pmc/core.c index 3894119d61b0..9d3a1b6ef622 100644 --- a/drivers/platform/x86/intel/pmc/core.c +++ b/drivers/platform/x86/intel/pmc/core.c @@ -728,7 +728,7 @@ static int pmc_core_substate_l_sts_regs_show(struct seq_file *s, void *unused) } DEFINE_SHOW_ATTRIBUTE(pmc_core_substate_l_sts_regs); -static void pmc_core_substate_req_header_show(struct seq_file *s) +static void pmc_core_substate_req_header_show(struct seq_file *s, int pmc_index) { struct pmc_dev *pmcdev = s->private; int i, mode; @@ -743,68 +743,81 @@ static void pmc_core_substate_req_header_show(struct seq_file *s) static int pmc_core_substate_req_regs_show(struct seq_file *s, void *unused) { struct pmc_dev *pmcdev = s->private; - struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN]; - const struct pmc_bit_map **maps = pmc->map->lpm_sts; - const struct pmc_bit_map *map; - const int num_maps = pmc->map->lpm_num_maps; - u32 sts_offset = pmc->map->lpm_status_offset; - u32 *lpm_req_regs = pmc->lpm_req_regs; - int mp; + u32 sts_offset; + u32 *lpm_req_regs; + int num_maps, mp, pmc_index; - /* Display the header */ - pmc_core_substate_req_header_show(s); + for (pmc_index = 0; pmc_index < ARRAY_SIZE(pmcdev->pmcs); ++pmc_index) { + struct pmc *pmc = pmcdev->pmcs[pmc_index]; + const struct pmc_bit_map **maps; - /* Loop over maps */ - for (mp = 0; mp < num_maps; mp++) { - u32 req_mask = 0; - u32 lpm_status; - int mode, idx, i, len = 32; + if (!pmc) + continue; + + maps = pmc->map->lpm_sts; + num_maps = pmc->map->lpm_num_maps; + sts_offset = pmc->map->lpm_status_offset; + lpm_req_regs = pmc->lpm_req_regs; /* - * Capture the requirements and create a mask so that we only - * show an element if it's required for at least one of the - * enabled low power modes + * When there are multiple PMCs, though the PMC may exist, the + * requirement register discovery could have failed so check + * before accessing. */ - pmc_for_each_mode(idx, mode, pmcdev) - req_mask |= lpm_req_regs[mp + (mode * num_maps)]; - - /* Get the last latched status for this map */ - lpm_status = pmc_core_reg_read(pmc, sts_offset + (mp * 4)); - - /* Loop over elements in this map */ - map = maps[mp]; - for (i = 0; map[i].name && i < len; i++) { - u32 bit_mask = map[i].bit_mask; - - if (!(bit_mask & req_mask)) - /* - * Not required for any enabled states - * so don't display - */ - continue; - - /* Display the element name in the first column */ - seq_printf(s, "%30s |", map[i].name); - - /* Loop over the enabled states and display if required */ - pmc_for_each_mode(idx, mode, pmcdev) { - if (lpm_req_regs[mp + (mode * num_maps)] & bit_mask) - seq_printf(s, " %9s |", - "Required"); - else - seq_printf(s, " %9s |", " "); + if (!lpm_req_regs) + continue; + + /* Display the header */ + pmc_core_substate_req_header_show(s, pmc_index); + + /* Loop over maps */ + for (mp = 0; mp < num_maps; mp++) { + u32 req_mask = 0; + u32 lpm_status; + const struct pmc_bit_map *map; + int mode, idx, i, len = 32; + + /* + * Capture the requirements and create a mask so that we only + * show an element if it's required for at least one of the + * enabled low power modes + */ + pmc_for_each_mode(idx, mode, pmcdev) + req_mask |= lpm_req_regs[mp + (mode * num_maps)]; + + /* Get the last latched status for this map */ + lpm_status = pmc_core_reg_read(pmc, sts_offset + (mp * 4)); + + /* Loop over elements in this map */ + map = maps[mp]; + for (i = 0; map[i].name && i < len; i++) { + u32 bit_mask = map[i].bit_mask; + + if (!(bit_mask & req_mask)) { + /* + * Not required for any enabled states + * so don't display + */ + continue; + } + + /* Display the element name in the first column */ + seq_printf(s, "pmc%d: %26s |", pmc_index, map[i].name); + + /* Loop over the enabled states and display if required */ + pmc_for_each_mode(idx, mode, pmcdev) { + bool required = lpm_req_regs[mp + (mode * num_maps)] & + bit_mask; + seq_printf(s, " %9s |", required ? "Required" : " "); + } + + /* In Status column, show the last captured state of this agent */ + seq_printf(s, " %9s |", lpm_status & bit_mask ? "Yes" : " "); + + seq_puts(s, "\n"); } - - /* In Status column, show the last captured state of this agent */ - if (lpm_status & bit_mask) - seq_printf(s, " %9s |", "Yes"); - else - seq_printf(s, " %9s |", " "); - - seq_puts(s, "\n"); } } - return 0; } DEFINE_SHOW_ATTRIBUTE(pmc_core_substate_req_regs); From patchwork Wed Nov 29 22:21:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "David E. Box" X-Patchwork-Id: 13473621 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="C7ij0lyd" Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 206BE10E6; Wed, 29 Nov 2023 14:21:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1701296506; x=1732832506; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=cUaNFCRzY0WgtBRcu6J9Bq4TnaUOe6SPpfBzkDLbR18=; b=C7ij0lydHDRv9j4Pw27SGw5WYeKnR7rDOGKhKxYRPkQ8gcXMxLXgXwMp DpCd5GuKPZfm/+LxJfnuWA5nX1YZtjkeDFuc1O310mRss14qMCB+h2yb+ vq3edVdF4kyk3RMGk07GdDU/CfhqL5dmBeRaUWZprfsf+MkDwfm0duqkL fLZcoshmCmBdhzzb8hORBkcocnCr7F8+eDvFlYVUqoT80xKCgfWrAe47O De1aIbikmnCucXtjOuG4HyvlqBviD6pMQCQ8JiSY+rNo09ZDEmwNlrcWa MnrvYV/YZVU5X0DFhZSK6U5R1nuPgafllVW4ZyM+6ca65WvFpH1gxNdIT g==; X-IronPort-AV: E=McAfee;i="6600,9927,10909"; a="11937012" X-IronPort-AV: E=Sophos;i="6.04,237,1695711600"; d="scan'208";a="11937012" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2023 14:21:35 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10909"; a="798070442" X-IronPort-AV: E=Sophos;i="6.04,237,1695711600"; d="scan'208";a="798070442" Received: from linux.intel.com ([10.54.29.200]) by orsmga008.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2023 14:21:35 -0800 Received: from debox1-desk4.lan (unknown [10.209.108.167]) by linux.intel.com (Postfix) with ESMTP id C3AD3580ABB; Wed, 29 Nov 2023 14:21:34 -0800 (PST) From: "David E. Box" To: linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, ilpo.jarvinen@linux.intel.com, rajvi.jingar@linux.intel.com Subject: [PATCH V6 17/20] platform/x86/intel/pmc: Retrieve LPM information using Intel PMT Date: Wed, 29 Nov 2023 14:21:29 -0800 Message-Id: <20231129222132.2331261-18-david.e.box@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231129222132.2331261-1-david.e.box@linux.intel.com> References: <20231129222132.2331261-1-david.e.box@linux.intel.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Xi Pardee On supported platforms, the low power mode (LPM) requirements for entering each idle substate are described in Platform Monitoring Technology (PMT) telemetry entries. Provide a function for platform code to attempt to find and read the requirements from the telemetry entries. Signed-off-by: Xi Pardee Signed-off-by: David E. Box Reviewed-by: Ilpo Järvinen --- V6 - no change V5 - no change V4 - no change V3 - no change V2 - remove extra parens drivers/platform/x86/intel/pmc/core.h | 3 + drivers/platform/x86/intel/pmc/core_ssram.c | 135 ++++++++++++++++++++ 2 files changed, 138 insertions(+) diff --git a/drivers/platform/x86/intel/pmc/core.h b/drivers/platform/x86/intel/pmc/core.h index edaa70067e41..85b6f6ae4995 100644 --- a/drivers/platform/x86/intel/pmc/core.h +++ b/drivers/platform/x86/intel/pmc/core.h @@ -320,6 +320,7 @@ struct pmc_reg_map { const u32 lpm_status_offset; const u32 lpm_live_status_offset; const u32 etr3_offset; + const u8 *lpm_reg_index; }; /** @@ -329,6 +330,7 @@ struct pmc_reg_map { * specific attributes */ struct pmc_info { + u32 guid; u16 devid; const struct pmc_reg_map *map; }; @@ -486,6 +488,7 @@ extern const struct pmc_bit_map *mtl_ioem_lpm_maps[]; extern const struct pmc_reg_map mtl_ioem_reg_map; extern void pmc_core_get_tgl_lpm_reqs(struct platform_device *pdev); +extern int pmc_core_ssram_get_lpm_reqs(struct pmc_dev *pmcdev); extern int pmc_core_send_ltr_ignore(struct pmc_dev *pmcdev, u32 value); int pmc_core_resume_common(struct pmc_dev *pmcdev); diff --git a/drivers/platform/x86/intel/pmc/core_ssram.c b/drivers/platform/x86/intel/pmc/core_ssram.c index 9ca720f9cbb2..3501c7bd6b33 100644 --- a/drivers/platform/x86/intel/pmc/core_ssram.c +++ b/drivers/platform/x86/intel/pmc/core_ssram.c @@ -24,8 +24,142 @@ #define SSRAM_IOE_OFFSET 0x68 #define SSRAM_DEVID_OFFSET 0x70 +/* PCH query */ +#define LPM_HEADER_OFFSET 1 +#define LPM_REG_COUNT 28 +#define LPM_MODE_OFFSET 1 + DEFINE_FREE(pmc_core_iounmap, void __iomem *, iounmap(_T)); +static u32 pmc_core_find_guid(struct pmc_info *list, const struct pmc_reg_map *map) +{ + for (; list->map; ++list) + if (list->map == map) + return list->guid; + + return 0; +} + +static int pmc_core_get_lpm_req(struct pmc_dev *pmcdev, struct pmc *pmc) +{ + struct telem_endpoint *ep; + const u8 *lpm_indices; + int num_maps, mode_offset = 0; + int ret, mode, i; + int lpm_size; + u32 guid; + + lpm_indices = pmc->map->lpm_reg_index; + num_maps = pmc->map->lpm_num_maps; + lpm_size = LPM_MAX_NUM_MODES * num_maps; + + guid = pmc_core_find_guid(pmcdev->regmap_list, pmc->map); + if (!guid) + return -ENXIO; + + ep = pmt_telem_find_and_register_endpoint(pmcdev->ssram_pcidev, guid, 0); + if (IS_ERR(ep)) { + dev_dbg(&pmcdev->pdev->dev, "couldn't get telem endpoint %ld", + PTR_ERR(ep)); + return -EPROBE_DEFER; + } + + pmc->lpm_req_regs = devm_kzalloc(&pmcdev->pdev->dev, + lpm_size * sizeof(u32), + GFP_KERNEL); + if (!pmc->lpm_req_regs) { + ret = -ENOMEM; + goto unregister_ep; + } + + /* + * PMC Low Power Mode (LPM) table + * + * In telemetry space, the LPM table contains a 4 byte header followed + * by 8 consecutive mode blocks (one for each LPM mode). Each block + * has a 4 byte header followed by a set of registers that describe the + * IP state requirements for the given mode. The IP mapping is platform + * specific but the same for each block, making for easy analysis. + * Platforms only use a subset of the space to track the requirements + * for their IPs. Callers provide the requirement registers they use as + * a list of indices. Each requirement register is associated with an + * IP map that's maintained by the caller. + * + * Header + * +----+----------------------------+----------------------------+ + * | 0 | REVISION | ENABLED MODES | + * +----+--------------+-------------+-------------+--------------+ + * + * Low Power Mode 0 Block + * +----+--------------+-------------+-------------+--------------+ + * | 1 | SUB ID | SIZE | MAJOR | MINOR | + * +----+--------------+-------------+-------------+--------------+ + * | 2 | LPM0 Requirements 0 | + * +----+---------------------------------------------------------+ + * | | ... | + * +----+---------------------------------------------------------+ + * | 29 | LPM0 Requirements 27 | + * +----+---------------------------------------------------------+ + * + * ... + * + * Low Power Mode 7 Block + * +----+--------------+-------------+-------------+--------------+ + * | | SUB ID | SIZE | MAJOR | MINOR | + * +----+--------------+-------------+-------------+--------------+ + * | 60 | LPM7 Requirements 0 | + * +----+---------------------------------------------------------+ + * | | ... | + * +----+---------------------------------------------------------+ + * | 87 | LPM7 Requirements 27 | + * +----+---------------------------------------------------------+ + * + */ + mode_offset = LPM_HEADER_OFFSET + LPM_MODE_OFFSET; + pmc_for_each_mode(i, mode, pmcdev) { + u32 *req_offset = pmc->lpm_req_regs + (mode * num_maps); + int m; + + for (m = 0; m < num_maps; m++) { + u8 sample_id = lpm_indices[m] + mode_offset; + + ret = pmt_telem_read32(ep, sample_id, req_offset, 1); + if (ret) { + dev_err(&pmcdev->pdev->dev, + "couldn't read Low Power Mode requirements: %d\n", ret); + devm_kfree(&pmcdev->pdev->dev, pmc->lpm_req_regs); + goto unregister_ep; + } + ++req_offset; + } + mode_offset += LPM_REG_COUNT + LPM_MODE_OFFSET; + } + +unregister_ep: + pmt_telem_unregister_endpoint(ep); + + return ret; +} + +int pmc_core_ssram_get_lpm_reqs(struct pmc_dev *pmcdev) +{ + int ret, i; + + if (!pmcdev->ssram_pcidev) + return -ENODEV; + + for (i = 0; i < ARRAY_SIZE(pmcdev->pmcs); ++i) { + if (!pmcdev->pmcs[i]) + continue; + + ret = pmc_core_get_lpm_req(pmcdev, pmcdev->pmcs[i]); + if (ret) + return ret; + } + + return 0; +} + static void pmc_add_pmt(struct pmc_dev *pmcdev, u64 ssram_base, void __iomem *ssram) { @@ -189,3 +323,4 @@ int pmc_core_ssram_init(struct pmc_dev *pmcdev) return ret; } MODULE_IMPORT_NS(INTEL_VSEC); +MODULE_IMPORT_NS(INTEL_PMT_TELEMETRY); From patchwork Wed Nov 29 22:21:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "David E. Box" X-Patchwork-Id: 13473618 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="LIN5Twb9" Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B0AC710D3; Wed, 29 Nov 2023 14:21:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1701296505; x=1732832505; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=tF3n+VCff3GUz8CRsrRcnikQq6XWJjByBScXPFkh73k=; b=LIN5Twb9Z+flX+YGmHelooCy4junM2d3u9fOb/PnGc2ssJP9XAuoeMS7 RatOwcXXHsTWTWH3Og9HFn1yRZ3SV2SXIrLy0M+TOc4w1ujqbMmCtzilU jnKq9QLzlUstYY5Zx3IZbUp7TN5j3CLbmfYhnM2Uy4PVLweTKgdodbHFK 81l/SrkMXGQ/LvX7lE5QZJ/r6vuJAgvXEqxffWhTBoob8mG/xGQioGoP4 +YI7Vm+PFmtGJQ1GDpISAf9vh2pkbYom7dbxXeBbL+DUqSHt22InqytqF DwHbgT0529AlTPi7kGHE2a8327RXZk1d3Cb7OLOiBfd5GaRu7N/LYwKLR A==; X-IronPort-AV: E=McAfee;i="6600,9927,10909"; a="11937010" X-IronPort-AV: E=Sophos;i="6.04,237,1695711600"; d="scan'208";a="11937010" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2023 14:21:35 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10909"; a="798070444" X-IronPort-AV: E=Sophos;i="6.04,237,1695711600"; d="scan'208";a="798070444" Received: from linux.intel.com ([10.54.29.200]) by orsmga008.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2023 14:21:35 -0800 Received: from debox1-desk4.lan (unknown [10.209.108.167]) by linux.intel.com (Postfix) with ESMTP id E5E665807E2; Wed, 29 Nov 2023 14:21:34 -0800 (PST) From: "David E. Box" To: linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, ilpo.jarvinen@linux.intel.com, rajvi.jingar@linux.intel.com Subject: [PATCH V6 18/20] platform/x86/intel/pmc: Read low power mode requirements for MTL-M and MTL-P Date: Wed, 29 Nov 2023 14:21:30 -0800 Message-Id: <20231129222132.2331261-19-david.e.box@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231129222132.2331261-1-david.e.box@linux.intel.com> References: <20231129222132.2331261-1-david.e.box@linux.intel.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Xi Pardee Add support to read the low power mode requirements for Meteor Lake M and Meteor Lake P. Signed-off-by: Xi Pardee Signed-off-by: David E. Box Reviewed-by: Ilpo Järvinen --- V6 - no change V5 - no change V4 - no change V3 - directly return value from pmc_core_ssram_get_lpm_reqs() V2 - fixed unused return value drivers/platform/x86/intel/pmc/mtl.c | 39 +++++++++++++++++++++++----- 1 file changed, 32 insertions(+), 7 deletions(-) diff --git a/drivers/platform/x86/intel/pmc/mtl.c b/drivers/platform/x86/intel/pmc/mtl.c index d1d3d33fb4b8..7ceeae507f4c 100644 --- a/drivers/platform/x86/intel/pmc/mtl.c +++ b/drivers/platform/x86/intel/pmc/mtl.c @@ -11,6 +11,13 @@ #include #include "core.h" +/* PMC SSRAM PMT Telemetry GUIDS */ +#define SOCP_LPM_REQ_GUID 0x2625030 +#define IOEM_LPM_REQ_GUID 0x4357464 +#define IOEP_LPM_REQ_GUID 0x5077612 + +static const u8 MTL_LPM_REG_INDEX[] = {0, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16, 20}; + /* * Die Mapping to Product. * Product SOCDie IOEDie PCHDie @@ -465,6 +472,7 @@ const struct pmc_reg_map mtl_socm_reg_map = { .lpm_sts = mtl_socm_lpm_maps, .lpm_status_offset = MTL_LPM_STATUS_OFFSET, .lpm_live_status_offset = MTL_LPM_LIVE_STATUS_OFFSET, + .lpm_reg_index = MTL_LPM_REG_INDEX, }; const struct pmc_bit_map mtl_ioep_pfear_map[] = { @@ -782,6 +790,13 @@ const struct pmc_reg_map mtl_ioep_reg_map = { .ltr_show_sts = mtl_ioep_ltr_show_map, .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET, .ltr_ignore_max = ADL_NUM_IP_IGN_ALLOWED, + .lpm_num_maps = ADL_LPM_NUM_MAPS, + .lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2, + .lpm_residency_offset = MTL_LPM_RESIDENCY_OFFSET, + .lpm_priority_offset = MTL_LPM_PRI_OFFSET, + .lpm_en_offset = MTL_LPM_EN_OFFSET, + .lpm_sts_latch_en_offset = MTL_LPM_STATUS_LATCH_EN_OFFSET, + .lpm_reg_index = MTL_LPM_REG_INDEX, }; const struct pmc_bit_map mtl_ioem_pfear_map[] = { @@ -922,6 +937,13 @@ const struct pmc_reg_map mtl_ioem_reg_map = { .ltr_show_sts = mtl_ioep_ltr_show_map, .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET, .ltr_ignore_max = ADL_NUM_IP_IGN_ALLOWED, + .lpm_sts_latch_en_offset = MTL_LPM_STATUS_LATCH_EN_OFFSET, + .lpm_num_maps = ADL_LPM_NUM_MAPS, + .lpm_priority_offset = MTL_LPM_PRI_OFFSET, + .lpm_en_offset = MTL_LPM_EN_OFFSET, + .lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2, + .lpm_residency_offset = MTL_LPM_RESIDENCY_OFFSET, + .lpm_reg_index = MTL_LPM_REG_INDEX, }; #define PMC_DEVID_SOCM 0x7e7f @@ -929,16 +951,19 @@ const struct pmc_reg_map mtl_ioem_reg_map = { #define PMC_DEVID_IOEM 0x7ebf static struct pmc_info mtl_pmc_info_list[] = { { - .devid = PMC_DEVID_SOCM, - .map = &mtl_socm_reg_map, + .guid = SOCP_LPM_REQ_GUID, + .devid = PMC_DEVID_SOCM, + .map = &mtl_socm_reg_map, }, { - .devid = PMC_DEVID_IOEP, - .map = &mtl_ioep_reg_map, + .guid = IOEP_LPM_REQ_GUID, + .devid = PMC_DEVID_IOEP, + .map = &mtl_ioep_reg_map, }, { - .devid = PMC_DEVID_IOEM, - .map = &mtl_ioem_reg_map + .guid = IOEM_LPM_REQ_GUID, + .devid = PMC_DEVID_IOEM, + .map = &mtl_ioem_reg_map }, {} }; @@ -1014,5 +1039,5 @@ int mtl_core_init(struct pmc_dev *pmcdev) dev_dbg(&pmcdev->pdev->dev, "ignoring GBE LTR\n"); pmc_core_send_ltr_ignore(pmcdev, 3); - return 0; + return pmc_core_ssram_get_lpm_reqs(pmcdev); } From patchwork Wed Nov 29 22:21:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "David E. Box" X-Patchwork-Id: 13473616 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Wq3Wxo6q" Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8398A197; Wed, 29 Nov 2023 14:21:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1701296503; x=1732832503; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=3uctqsFvdPRcO1F5mxpmLxaCC0IWGt+HEDKUw/EKGHQ=; b=Wq3Wxo6qfwv0PARXauAbAanewRzIglax0bJRmuCO9v2r5OqTcSQWcr6N ntQNeWTYKt3tNJS2i19OmmEJ0HZ1wjdgRkHOh9cEq0lJrwhsfsIGymTdd 4HtCGT2mHdw2YC16GOfzuWzGyYSN5ZFrzDtO8beE57xZ0GPgFjCq6Y6sU Y/74NTS3oCZ0AhaAVdjg1n3w/d/o9Qh8VPssKvTBAb4hDrLxceyAJoIRP ww57wN1w7TJ4cE6ZwAp5BWGZIMKXBoUjbeWM4VxUU1dRCKd+sHg+918aa MhxeST9zNse90QE8m6cj0iu+XB/P5S+hVBVGjDjgSmkgo5JiM+pRnMsX5 g==; X-IronPort-AV: E=McAfee;i="6600,9927,10909"; a="11937014" X-IronPort-AV: E=Sophos;i="6.04,237,1695711600"; d="scan'208";a="11937014" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2023 14:21:35 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10909"; a="798070446" X-IronPort-AV: E=Sophos;i="6.04,237,1695711600"; d="scan'208";a="798070446" Received: from linux.intel.com ([10.54.29.200]) by orsmga008.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2023 14:21:35 -0800 Received: from debox1-desk4.lan (unknown [10.209.108.167]) by linux.intel.com (Postfix) with ESMTP id 1136F580C4B; Wed, 29 Nov 2023 14:21:35 -0800 (PST) From: "David E. Box" To: linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, ilpo.jarvinen@linux.intel.com, rajvi.jingar@linux.intel.com Subject: [PATCH V6 19/20] platform/x86/intel/pmc: Add debug attribute for Die C6 counter Date: Wed, 29 Nov 2023 14:21:31 -0800 Message-Id: <20231129222132.2331261-20-david.e.box@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231129222132.2331261-1-david.e.box@linux.intel.com> References: <20231129222132.2331261-1-david.e.box@linux.intel.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add a "die_c6_us_show" debugfs attribute. Reads the counter value using Intel Platform Monitoring Technology (PMT) driver API. This counter is useful for determining the idle residency of CPUs in the compute tile. Also adds a missing forward declaration for punit_ep which was declared in an earlier upstream commit but only used for the first time in this one. Signed-off-by: David E. Box Reviewed-by: Ilpo Järvinen --- V6 - No change V5 - Change comment for crystal error and return value V4 - no change V3 - Split previous PATCH V2 13. Separates implementation (this patch) from platform specific use (next patch) V2 - Remove use of __func__ - Use HZ_PER_MHZ - Fix missing newlines in printks drivers/platform/x86/intel/pmc/core.c | 55 +++++++++++++++++++++++++++ drivers/platform/x86/intel/pmc/core.h | 4 ++ 2 files changed, 59 insertions(+) diff --git a/drivers/platform/x86/intel/pmc/core.c b/drivers/platform/x86/intel/pmc/core.c index 9d3a1b6ef622..983e3a8f4910 100644 --- a/drivers/platform/x86/intel/pmc/core.c +++ b/drivers/platform/x86/intel/pmc/core.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include @@ -27,6 +28,7 @@ #include #include "core.h" +#include "../pmt/telemetry.h" /* Maximum number of modes supported by platfoms that has low power mode capability */ const char *pmc_lpm_modes[] = { @@ -822,6 +824,47 @@ static int pmc_core_substate_req_regs_show(struct seq_file *s, void *unused) } DEFINE_SHOW_ATTRIBUTE(pmc_core_substate_req_regs); +static unsigned int pmc_core_get_crystal_freq(void) +{ + unsigned int eax_denominator, ebx_numerator, ecx_hz, edx; + + if (boot_cpu_data.cpuid_level < 0x15) + return 0; + + eax_denominator = ebx_numerator = ecx_hz = edx = 0; + + /* CPUID 15H TSC/Crystal ratio, plus optionally Crystal Hz */ + cpuid(0x15, &eax_denominator, &ebx_numerator, &ecx_hz, &edx); + + if (ebx_numerator == 0 || eax_denominator == 0) + return 0; + + return ecx_hz; +} + +static int pmc_core_die_c6_us_show(struct seq_file *s, void *unused) +{ + struct pmc_dev *pmcdev = s->private; + u64 die_c6_res, count; + int ret; + + if (!pmcdev->crystal_freq) { + dev_warn_once(&pmcdev->pdev->dev, "Crystal frequency unavailable\n"); + return -ENXIO; + } + + ret = pmt_telem_read(pmcdev->punit_ep, pmcdev->die_c6_offset, + &count, 1); + if (ret) + return ret; + + die_c6_res = div64_u64(count * HZ_PER_MHZ, pmcdev->crystal_freq); + seq_printf(s, "%llu\n", die_c6_res); + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(pmc_core_die_c6_us); + static int pmc_core_lpm_latch_mode_show(struct seq_file *s, void *unused) { struct pmc_dev *pmcdev = s->private; @@ -1118,6 +1161,12 @@ static void pmc_core_dbgfs_register(struct pmc_dev *pmcdev) pmcdev->dbgfs_dir, pmcdev, &pmc_core_substate_req_regs_fops); } + + if (pmcdev->has_die_c6) { + debugfs_create_file("die_c6_us_show", 0444, + pmcdev->dbgfs_dir, pmcdev, + &pmc_core_die_c6_us_fops); + } } static const struct x86_cpu_id intel_pmc_core_ids[] = { @@ -1212,6 +1261,10 @@ static void pmc_core_clean_structure(struct platform_device *pdev) pci_dev_put(pmcdev->ssram_pcidev); pci_disable_device(pmcdev->ssram_pcidev); } + + if (pmcdev->punit_ep) + pmt_telem_unregister_endpoint(pmcdev->punit_ep); + platform_set_drvdata(pdev, NULL); mutex_destroy(&pmcdev->lock); } @@ -1232,6 +1285,8 @@ static int pmc_core_probe(struct platform_device *pdev) if (!pmcdev) return -ENOMEM; + pmcdev->crystal_freq = pmc_core_get_crystal_freq(); + platform_set_drvdata(pdev, pmcdev); pmcdev->pdev = pdev; diff --git a/drivers/platform/x86/intel/pmc/core.h b/drivers/platform/x86/intel/pmc/core.h index 85b6f6ae4995..6d7673145f90 100644 --- a/drivers/platform/x86/intel/pmc/core.h +++ b/drivers/platform/x86/intel/pmc/core.h @@ -16,6 +16,8 @@ #include #include +struct telem_endpoint; + #define SLP_S0_RES_COUNTER_MASK GENMASK(31, 0) #define PMC_BASE_ADDR_DEFAULT 0xFE000000 @@ -357,6 +359,7 @@ struct pmc { * @devs: pointer to an array of pmc pointers * @pdev: pointer to platform_device struct * @ssram_pcidev: pointer to pci device struct for the PMC SSRAM + * @crystal_freq: crystal frequency from cpuid * @dbgfs_dir: path to debugfs interface * @pmc_xram_read_bit: flag to indicate whether PMC XRAM shadow registers * used to read MPHY PG and PLL status are available @@ -374,6 +377,7 @@ struct pmc_dev { struct dentry *dbgfs_dir; struct platform_device *pdev; struct pci_dev *ssram_pcidev; + unsigned int crystal_freq; int pmc_xram_read_bit; struct mutex lock; /* generic mutex lock for PMC Core */ From patchwork Wed Nov 29 22:21:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "David E. Box" X-Patchwork-Id: 13473620 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="k/7rIKVP" Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E21CE10F3; Wed, 29 Nov 2023 14:21:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1701296507; x=1732832507; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=bHXqITvvls58rwPqWf3sWqsK4WQUOUNsGHTtQSWEOes=; b=k/7rIKVPgofovhq0P3Udz4bnDq8NKVjUEL256r1yJWUP1DKNloQ91nZY l8tr4TqxDuZjXs51u3yGeDWJbB/23b33dv5hlRXqDOa5IWrQN8V5zS6jY HRdCwYyra3iu4CTPmL1lkx7177g4Z0C+8eRx1otzR5Rdu6PIzK1lfV8Ak 0iqYVH5xV/agJp1R7UZMaeDSDZF6AGcMpLjiO84WIfuXOnPgbkJtLYMit IRdt9//TkWwswURlGPxXBm0yOVjXznq/GUZaCW+DM410dkjDMJNZz9mjF 5DE4kzoCXdyFJJze2KXPod3s8PQbD3IcuTFyQAwIbv+HMF1pVIriU/ScJ g==; X-IronPort-AV: E=McAfee;i="6600,9927,10909"; a="11937011" X-IronPort-AV: E=Sophos;i="6.04,237,1695711600"; d="scan'208";a="11937011" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2023 14:21:35 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10909"; a="798070447" X-IronPort-AV: E=Sophos;i="6.04,237,1695711600"; d="scan'208";a="798070447" Received: from linux.intel.com ([10.54.29.200]) by orsmga008.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2023 14:21:35 -0800 Received: from debox1-desk4.lan (unknown [10.209.108.167]) by linux.intel.com (Postfix) with ESMTP id 338AD580ABB; Wed, 29 Nov 2023 14:21:35 -0800 (PST) From: "David E. Box" To: linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, ilpo.jarvinen@linux.intel.com, rajvi.jingar@linux.intel.com Subject: [PATCH V6 20/20] platform/x86/intel/pmc: Show Die C6 counter on Meteor Lake Date: Wed, 29 Nov 2023 14:21:32 -0800 Message-Id: <20231129222132.2331261-21-david.e.box@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231129222132.2331261-1-david.e.box@linux.intel.com> References: <20231129222132.2331261-1-david.e.box@linux.intel.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Expose the Die C6 counter on Meteor Lake. Signed-off-by: David E. Box Reviewed-by: Ilpo Järvinen --- V6 - no change V5 - no change V4 - no change V3 - Split PATCH V2 13. Separates implementation (previous patch) from platform specific use (this patch) drivers/platform/x86/intel/pmc/mtl.c | 32 ++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/platform/x86/intel/pmc/mtl.c b/drivers/platform/x86/intel/pmc/mtl.c index 7ceeae507f4c..38c2f946ec23 100644 --- a/drivers/platform/x86/intel/pmc/mtl.c +++ b/drivers/platform/x86/intel/pmc/mtl.c @@ -10,12 +10,17 @@ #include #include "core.h" +#include "../pmt/telemetry.h" /* PMC SSRAM PMT Telemetry GUIDS */ #define SOCP_LPM_REQ_GUID 0x2625030 #define IOEM_LPM_REQ_GUID 0x4357464 #define IOEP_LPM_REQ_GUID 0x5077612 +/* Die C6 from PUNIT telemetry */ +#define MTL_PMT_DMU_DIE_C6_OFFSET 15 +#define MTL_PMT_DMU_GUID 0x1A067102 + static const u8 MTL_LPM_REG_INDEX[] = {0, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16, 20}; /* @@ -968,6 +973,32 @@ static struct pmc_info mtl_pmc_info_list[] = { {} }; +static void mtl_punit_pmt_init(struct pmc_dev *pmcdev) +{ + struct telem_endpoint *ep; + struct pci_dev *pcidev; + + pcidev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(10, 0)); + if (!pcidev) { + dev_err(&pmcdev->pdev->dev, "PUNIT PMT device not found.\n"); + return; + } + + ep = pmt_telem_find_and_register_endpoint(pcidev, MTL_PMT_DMU_GUID, 0); + if (IS_ERR(ep)) { + dev_err(&pmcdev->pdev->dev, + "pmc_core: couldn't get DMU telem endpoint, %ld\n", + PTR_ERR(ep)); + return; + } + + pci_dev_put(pcidev); + pmcdev->punit_ep = ep; + + pmcdev->has_die_c6 = true; + pmcdev->die_c6_offset = MTL_PMT_DMU_DIE_C6_OFFSET; +} + #define MTL_GNA_PCI_DEV 0x7e4c #define MTL_IPU_PCI_DEV 0x7d19 #define MTL_VPU_PCI_DEV 0x7d1d @@ -1032,6 +1063,7 @@ int mtl_core_init(struct pmc_dev *pmcdev) } pmc_core_get_low_power_modes(pmcdev); + mtl_punit_pmt_init(pmcdev); /* Due to a hardware limitation, the GBE LTR blocks PC10 * when a cable is attached. Tell the PMC to ignore it.