From patchwork Thu Nov 30 01:10:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 13473762 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="jkbVXW+I" Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2082.outbound.protection.outlook.com [40.107.243.82]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3467510A; Wed, 29 Nov 2023 17:10:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=QdZphUtFo5f7+HshrnrVT2ElTpdEX3piZXWQU9e91QuvpueItNGgqWOMQpUufqEOwHs+fna8OP9sRP8P5WZ+r9O30UQySwKq6x5UK/x2PT0HXS0n9GHugj5l7+RHKBVgSh9ZG1OZ4DsJok8AMz1fDhwgAo7aI+EM8sruQCtlE6Zm2upN2fJfh4+Uo5DDbo/GM1dqUrNOTYBeyKwP0HAIpuEaNSu9PSU+jj+MB5EZH+cJ8ZoCHfFWqxsBoKhrWXRqXzAF0bRS2JlHFgwEu85ByaAnHzJ5Y9mAndsuDxMytD+YXovmwbM/zaQAfNNvzjT1RsZRGxJ56T3cwp1Hjeaasw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=jd6rraoB++P6AMiBToFZHHrXvI/RmL6YR5zTlW3nQ/A=; b=UUV8mbcVuZfDpNwsQYFFY5sVApaQRGkSiBbcM6q6ixW01LgDBoUZ02UQFW5NGlCGXV/3gZkgPIHCqIvgY4M8s6dvjFTN2dgf78dz5TIoQPGQVAW6P1usobX42DXUVOsZsp+0vuOSBw/0JqNRoTIq9pOkCpwMzEb1eEassg2h3XHcSA9V6bHV+od8NIvcAt+mpz4kCpr0u+KQPa7QEpe9zSJhkp+gkZH+VS4fMMVKgA+QBU9OELrcMroMS37DueDGZB/wCAZOU8isAx1vtpoD3kchf6mNrjhVAc9Wdbmswe0njvQqPVcVBxWvGLyHX30PGieugicHjMbasChwc5giGw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=jd6rraoB++P6AMiBToFZHHrXvI/RmL6YR5zTlW3nQ/A=; b=jkbVXW+I36uEb7RpaYsXBgPfJclZ2J1G8rwVEJ6ikOne1prRFU3VT2iVC250MZMhbmrCrw6Ce5i7T7CWazdH5rCepvzoenjVkMZ1KieO8TEEVZJXdVC5FJ/tp0j3JAr0Jeq81CJxn+pP0NJoe9RAhuPdhhpQsIeb/VOpEfmEO0Tom7P6ps5evoRB+SRAcbzLKoWgYTggGI+ctUrCWI+xgT77cHR5wi9eudQbjNrINhxySQ9ioeile8ZtGhMyiRXfjC202+0V8Z7aLFtZnfXzJrJy44DYwPfgYY3FLvbWSY4qvavcO5lsRViHm8uoiaRTvlYXv+Y+RSS4W1pvPvC42A== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by PH0PR12MB5484.namprd12.prod.outlook.com (2603:10b6:510:eb::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.24; Thu, 30 Nov 2023 01:10:45 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.7046.015; Thu, 30 Nov 2023 01:10:44 +0000 From: Jason Gunthorpe To: acpica-devel@lists.linux.dev, Andy Gross , Alim Akhtar , Alyssa Rosenzweig , Bjorn Andersson , AngeloGioacchino Del Regno , asahi@lists.linux.dev, Baolin Wang , devicetree@vger.kernel.org, Frank Rowand , Hanjun Guo , "Gustavo A. R. Silva" , Heiko Stuebner , iommu@lists.linux.dev, Jean-Philippe Brucker , Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kees Cook , Konrad Dybcio , Krzysztof Kozlowski , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Lorenzo Pieralisi , Marek Szyprowski , Hector Martin , Matthias Brugger , Orson Zhai , "Rafael J. Wysocki" , Rob Clark , Robert Moore , Rob Herring , Robin Murphy , Samuel Holland , Sudeep Holla , Sven Peter , Thierry Reding , Krishna Reddy , virtualization@lists.linux.dev, Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: =?utf-8?q?Andr=C3=A9_Draszik?= , patches@lists.linux.dev Subject: [PATCH 01/30] iommu/of: Make a of_iommu_for_each_id() Date: Wed, 29 Nov 2023 21:10:08 -0400 Message-ID: <1-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> In-Reply-To: <0-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> References: X-ClientProxiedBy: SN6PR16CA0052.namprd16.prod.outlook.com (2603:10b6:805:ca::29) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|PH0PR12MB5484:EE_ X-MS-Office365-Filtering-Correlation-Id: 761ff352-228f-423a-dff5-08dbf1412b18 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: dF5RqqeD+DfHp5aKbbhPoFkoVOqcUsijVbfeew9+x8rzSMGkdUAfIzodZB9dX9DJQC2YjhOHU5FTb/CLsxaW2GLnQHMGbujbteTiQwO4yWRWPQu8ZCIYpcw5Cj5ZIYdeVFfxF0Gpqw1L9/Wo0yyaH5LjhTrO23LjRstBHio9BaBnPjaiYcONy30a8S7TGUblkiW8wbatsQQ4603DrkcX22XCY6u+y9jMHL9JiRq/dJPwP0iRY0AZJNTwczM+psAKOZ3dKXwvDnS+5zSnIe/Ah9YjtEBnsWtfAAYbHPjqxPfz4/JLaoBqob6KfOQQjbesYvMkdrtcawRwjHQFhQ2l24XfBDhav0TXLAmy8soT9d5Rpy+rZq4WNcXiDKkQd7+Mzh2KGKI/qH3ax6r84w+IeIyYDsUDIez4JYJJQIHkb9tAJLB6LNub9kPMiT3iynefh6DopagtpkECR1xq/mz9AV6RXBelYJcH/oyfP+rUO9/xrbH39J2RpryZ9TwayPsjOBuKfJzOYmECSx4TWOLPRof2177pk4x6MYPFWq3Xs7gsOHJ+6xpO9RAri85SNJItnaAvupPpan814AWkquC/k/mUNGFyOrbvqqTsI8UV+2VzgsjH7dxaNvWmrklE4IelrqBa5rHBqXJpLlyBPBhqlUCTb+Eld8Yjw3AMe0p6xZ4= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:LV2PR12MB5869.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(366004)(346002)(136003)(396003)(39860400002)(376002)(230922051799003)(451199024)(1800799012)(186009)(64100799003)(1191002)(8936002)(110136005)(8676002)(316002)(66556008)(4326008)(86362001)(66476007)(6486002)(478600001)(66946007)(41300700001)(36756003)(921008)(7416002)(7366002)(2906002)(7406005)(5660300002)(38100700002)(2616005)(6512007)(6506007)(6666004)(83380400001)(26005)(202311291699003)(4216001);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 7GboM41ZeDYsHWH1VFgz5aZUzKHpZLODWUia5EldzFmgi28B/JSnY3iScioXrcaZQ4o7KDnLsOWE8KhHqZcAGg9Sw2E06FHdf+rzSB80OKICSvHmLSB8Cm6S6o1639PsfP4T09LffkPimgOD9sI2EEITlgNVlTPPJK0b5auWQ0mrT0QbqmBrTG9p3Avlm8I0AkVNX1TjyWqVwIILQweO2TRruY1IPKfDD9MdnfZeC+QOOQ4QSlhwqJKv8CwR1AFNe32R/D6c/DPxMRr4ymP2qw0N/KnUtHIe6v7WyYaoyMtKtUqA+3y822q5+R3GSbziRyrJIwZ2epxLm1VpzFoHz8OTFm0OZPUsflla7A3nO7wUeHRG/my1yQM1kMJKIOYg9zu9+rgxPn7ZDG61seOhhamy25qADDQ2ddakMeDP4O2+VM//LvTe6Kry2+Flgr9pUYiS53LY/LubMDdQB/iHdEcjQuiYKge73FGELwEJLxDC/Jj7mhTpdIAgj81AgTrgMX/qzlkV8bjggdNOF0i9+WhTuVu1rki3Ipunz1d1WFQnE+ya5/RDvZZP8D6n4py+f+0sfC0xHPzEa80U1ahyUY5kFW/bG2VwURu7JV1LRQ+X4rVFHZ0evwVlYKdVyoUdI8NmFqIIHecBCZR8NBtEJ4IZyPqrTr31RgcvXvQpIGFUJojWfF9Z5Hw+q0Rx57iF0mOgws830Dnfok2MFStUiGm5CSy0CE6pTK3fz3Oqmn5LLkIO1I8k3Fgr/HjUV7fzSzyASgMzwvgWL157sx3b5sJyrXYC5u4jOTuZdljnUyUdao7BbuJzmaBpIycMGYNmmjYqes3g4rEWZN1ceej7UZpnVCO/r5WFkTeMQuvSgdiJeozNvFCdkwAbFK0cQeh8fCa/2l+8IB6nOtUIKFDFAx34Q2SqF8WRzWg964O9Yi+WTea3rSbILkcpVn1uwk69UE7xu0LAMzYOYY80mQt227GDYp6OKo4gL1WEAlXhHOXXODDU9BydRgmZTs5ndGh1fLKQO03BkvGZvsq0TXQWwO9ZaLqLTcvqVQgg2lrZJzAUyl9vI6gURxzuhPYEaja1bCnpynqadlTOSQnUnd3pflUDps2y4qgbI/XPopUpqbmRbRHVjimGWWSH/bs/y6oXrwoaM64i4k10Mghtm6czO03GettDtsJWg2eZRk6q3YByqbhKpGxK7fUtmfJfXMtwR4hwGBJ9TsHrYy0NQahmU7LsSWOAnQNXBaNhsS0nUUheqMsZ1eAeD89zoFd2Jpqfq8tfWZPrbetvmvnmWMZm2SioKE/R4o+v47rEMS5wl+y56N7SH3YpqGPXt4T8JLMSxsJOodov6cr0cLaKF6MLTEfaAiomRg7aL2pnWl+KxISHewbjEdnoAgLHTNSGJd4ogpP/je9YepV8Q2rk88dXVpnFY7uPfoLf7vLfM5zvk4W/RcAqTsmh2qO5nWk6Ar1p1V3tyGOL8i+jeoQcs1lBSIHNoj1swiFaK/7yG7FhgvTkXns5/bum+aM3q/FIqqrJ6stn3AN3IYD4wDQGkkDYt8702myM9mhPICq/6F5VevtnaGDE/ckgAc1viNl3lGlt X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 761ff352-228f-423a-dff5-08dbf1412b18 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2023 01:10:40.2229 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: AckvpZbtNsA7bKWlureRMMN8ajHkKkPruqCt1LQrkOtA7SIQ09cRozP0XupBMFvX X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5484 Take the existing machinery that was wired to invoking of_xlate on each id through the various maps and aliases and allow it to call a function pointer with an opaque. Call of_iommu_xlate() using the existing of_iommu_for_each_id(). Signed-off-by: Jason Gunthorpe --- drivers/iommu/of_iommu.c | 82 ++++++++++++++++++++++------------------ 1 file changed, 46 insertions(+), 36 deletions(-) diff --git a/drivers/iommu/of_iommu.c b/drivers/iommu/of_iommu.c index 164317bfb8a81f..3d4580f1fbb378 100644 --- a/drivers/iommu/of_iommu.c +++ b/drivers/iommu/of_iommu.c @@ -17,9 +17,9 @@ #include #include -static int of_iommu_xlate(struct device *dev, - struct of_phandle_args *iommu_spec) +static int of_iommu_xlate(struct of_phandle_args *iommu_spec, void *info) { + struct device *dev = info; const struct iommu_ops *ops; struct fwnode_handle *fwnode = &iommu_spec->np->fwnode; int ret; @@ -48,26 +48,27 @@ static int of_iommu_xlate(struct device *dev, return ret; } -static int of_iommu_configure_dev_id(struct device_node *master_np, - struct device *dev, - const u32 *id) +typedef int (*of_for_each_fn)(struct of_phandle_args *args, void *info); + +static int __for_each_map_id(struct device_node *master_np, u32 id, + of_for_each_fn fn, void *info) { struct of_phandle_args iommu_spec = { .args_count = 1 }; int err; - err = of_map_id(master_np, *id, "iommu-map", + err = of_map_id(master_np, id, "iommu-map", "iommu-map-mask", &iommu_spec.np, iommu_spec.args); if (err) return err; - err = of_iommu_xlate(dev, &iommu_spec); + err = fn(&iommu_spec, info); of_node_put(iommu_spec.np); return err; } -static int of_iommu_configure_dev(struct device_node *master_np, - struct device *dev) +static int __for_each_iommus(struct device_node *master_np, of_for_each_fn fn, + void *info) { struct of_phandle_args iommu_spec; int err = -ENODEV, idx = 0; @@ -75,7 +76,7 @@ static int of_iommu_configure_dev(struct device_node *master_np, while (!of_parse_phandle_with_args(master_np, "iommus", "#iommu-cells", idx, &iommu_spec)) { - err = of_iommu_xlate(dev, &iommu_spec); + err = fn(&iommu_spec, info); of_node_put(iommu_spec.np); idx++; if (err) @@ -86,23 +87,46 @@ static int of_iommu_configure_dev(struct device_node *master_np, } struct of_pci_iommu_alias_info { - struct device *dev; struct device_node *np; + of_for_each_fn fn; + void *info; }; -static int of_pci_iommu_init(struct pci_dev *pdev, u16 alias, void *data) +static int __for_each_map_pci(struct pci_dev *pdev, u16 alias, void *data) { - struct of_pci_iommu_alias_info *info = data; - u32 input_id = alias; + struct of_pci_iommu_alias_info *pci_info = data; - return of_iommu_configure_dev_id(info->np, info->dev, &input_id); + return __for_each_map_id(pci_info->np, alias, pci_info->fn, + pci_info->info); } -static int of_iommu_configure_device(struct device_node *master_np, - struct device *dev, const u32 *id) +static int of_iommu_for_each_id(struct device *dev, + struct device_node *master_np, const u32 *id, + of_for_each_fn fn, void *info) { - return (id) ? of_iommu_configure_dev_id(master_np, dev, id) : - of_iommu_configure_dev(master_np, dev); + /* + * We don't currently walk up the tree looking for a parent IOMMU. + * See the `Notes:' section of + * Documentation/devicetree/bindings/iommu/iommu.txt + */ + if (dev_is_pci(dev)) { + struct of_pci_iommu_alias_info pci_info = { + .np = master_np, + .fn = fn, + .info = info, + }; + + /* In PCI mode the ID comes from the RID */ + if (WARN_ON(id)) + return -EINVAL; + + return pci_for_each_dma_alias(to_pci_dev(dev), + __for_each_map_pci, &pci_info); + } + + if (id) + return __for_each_map_id(master_np, *id, fn, info); + return __for_each_iommus(master_np, fn, info); } /* @@ -133,25 +157,11 @@ int of_iommu_configure(struct device *dev, struct device_node *master_np, iommu_fwspec_free(dev); } - /* - * We don't currently walk up the tree looking for a parent IOMMU. - * See the `Notes:' section of - * Documentation/devicetree/bindings/iommu/iommu.txt - */ - if (dev_is_pci(dev)) { - struct of_pci_iommu_alias_info info = { - .dev = dev, - .np = master_np, - }; - + if (dev_is_pci(dev)) pci_request_acs(); - err = pci_for_each_dma_alias(to_pci_dev(dev), - of_pci_iommu_init, &info); - } else { - err = of_iommu_configure_device(master_np, dev, id); - } - mutex_unlock(&iommu_probe_device_lock); + err = of_iommu_for_each_id(dev, master_np, id, of_iommu_xlate, dev); + mutex_unlock(&iommu_probe_device_lock); if (err == -ENODEV || err == -EPROBE_DEFER) return err; if (err) From patchwork Thu Nov 30 01:10:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 13473774 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="doEttS/l" Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2053.outbound.protection.outlook.com [40.107.243.53]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DA1D110CB; Wed, 29 Nov 2023 17:11:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=HORhBOqFrxfTFHe3FuDPVTyBPEWQkdsesYUlMZPPB/PV1+nha7Sx3tZqUEDwqK/RyTn/VvDUfNXbMh4O2Y3MS4q3HAb+CLMQhrGuHubL3GLcAreTh1+iE/3CIrje6cyH65XJ3zvhfE2rKmstu179fGH5CmPzXEhE3Z/3/slbLpTpaz1SyCuD3RThDLXOV8Uwg8i1QYl2jztVJIpSfHMb8Q93HpPF5y0x6FrXqypHabLyDWRPTgWsV6MdDqMuLJolcN9j/nHHZCnMBQ99LNLxvm3RJthe36g9B3XrnJiVBGEfyTveNU2GI3Abx2gqZrhLfk9pcxuPZlOMSU0d3lRlWA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=1otHA+LIL3W1WZMWhBTV+rqHH68xzfh1OFbgeJsyAew=; b=dIzx2Ow2yuwP8iT0OWYVSHQEpkPqxbjqRm2Cn0wg3J13QvBEAJjFA2iaXJK15n612Gm+EMQRd3TY13xWecpUctJHJUm+M+H8o1WjVa1twVae21ulKjyqsm7L8Mf78R0r5+DYnVyypPYpxoEXXRdeEREiHSUnPSt6wapzXeeAcfTrdp77z0m04b1tR5B6kMNrExIYgrHlzz/8ifB892SmyyakxdlK+3IbrnmqoCvmBsB7uSgxZL/4VXV5Rvz5ktR4bcq/ynEMl2LT83B9yRRJ3uzd5B0QCXKs0h4397I4mFfdRk+W8aTXizj+Q9NTqHIhANvbifhfuR0U696EDoMtEw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=1otHA+LIL3W1WZMWhBTV+rqHH68xzfh1OFbgeJsyAew=; b=doEttS/lS7F+WQ093rXr+f1jzMGxAYZ/ZFHsN0NuBff5/S67oZASEaVROX1bTDHL2faxMu9E/W7Fcl7wXUzFw7b0vR8RPM1NimFG94/Qcyo/5TT6PBsvKylYx3MaypZOrZGa0BPQ/MAa9VBM/UErjL4SQtc5fOQ6CpqWlIyjtEbSsQC84neUevIH1P5AaG6wDmplLuAjGbSM363ruUoNCanwqpxK7M67qrfp48EhTwmSrFWklUMvxNJUvG3wgD9UMz9zsxA8f/W4vVQcpbvENRDHvYKW8bY0y7HIqhbF/k1N6290ZmqjZWf+3BsFhWuBv8kmrBp23yNggPQbsA6EkQ== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by PH0PR12MB5484.namprd12.prod.outlook.com (2603:10b6:510:eb::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.24; Thu, 30 Nov 2023 01:10:52 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.7046.015; Thu, 30 Nov 2023 01:10:52 +0000 From: Jason Gunthorpe To: acpica-devel@lists.linux.dev, Andy Gross , Alim Akhtar , Alyssa Rosenzweig , Bjorn Andersson , AngeloGioacchino Del Regno , asahi@lists.linux.dev, Baolin Wang , devicetree@vger.kernel.org, Frank Rowand , Hanjun Guo , "Gustavo A. R. Silva" , Heiko Stuebner , iommu@lists.linux.dev, Jean-Philippe Brucker , Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kees Cook , Konrad Dybcio , Krzysztof Kozlowski , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Lorenzo Pieralisi , Marek Szyprowski , Hector Martin , Matthias Brugger , Orson Zhai , "Rafael J. Wysocki" , Rob Clark , Robert Moore , Rob Herring , Robin Murphy , Samuel Holland , Sudeep Holla , Sven Peter , Thierry Reding , Krishna Reddy , virtualization@lists.linux.dev, Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: =?utf-8?q?Andr=C3=A9_Draszik?= , patches@lists.linux.dev Subject: [PATCH 02/30] ACPI: VIOT: Make a viot_iommu_for_each_id() Date: Wed, 29 Nov 2023 21:10:09 -0400 Message-ID: <2-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> In-Reply-To: <0-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> References: X-ClientProxiedBy: SN6PR08CA0011.namprd08.prod.outlook.com (2603:10b6:805:66::24) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|PH0PR12MB5484:EE_ X-MS-Office365-Filtering-Correlation-Id: 3b7c2a46-bde1-43ba-de9f-08dbf1412c2b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 2i71bxGKun33R1DeXVHUpr3CXstj44PRyf0JQC09JOqxra+4rpqi5V/a+/WNw06/dj83EGkjEtD9uRBPznXeSDDkNdiSHgywYfHFohfJfP5b4rz7XPeQjq9TcVX9mDGt1dEHDjb0iasrFInbtiy7uLqrvF3BfAh/nQqbR5aEWR/lmLQoDZEiu3TUE8unhP/ke6+ROgtIBc/402OUrVaT5sn4QOgTnOAOctotEwEkLjyyh3IjWXYFRh+aBAV/94KDX6IUP8AGOGvnVOvMSmj8UWwnH6bZFKZcCddZBBxbb11988ipr7g7OlpVTCplEPjQj2GAyLjdL26mzDwDi7+FqE1dYFb7uZmb0cgcf0Nmd9dcI9FZOjs/qlRwk+m0CQ0XlMVu2WvTh9o4YVkntL2HGmFrNPEK01LJc0rtP/hUGEgdVJuqdhLr6akwU3miEWqKf5QGHKUhvRYdLUBNhVbblfanJ0na3Z/TL4VY9SLfFNvfR6z0I29DRgxucRw+JF1oP8gv1fBVfNUFRWM8qHkySEglkzkqh8mV/m0sg929hf/Rux4IUzNyRAuu4q+WRIzPGBGmIYbFwvAm6le49EmunEZVWerPmJYb+CGZZBkheEqksA/whO/VlZDCoH+wheChpCp9NkzpFNPFDAIG8aJgQaKelX7TxfkNz45ZEVkrcGo= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:LV2PR12MB5869.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(366004)(346002)(136003)(396003)(39860400002)(376002)(230922051799003)(451199024)(1800799012)(186009)(64100799003)(1191002)(8936002)(110136005)(8676002)(316002)(66556008)(4326008)(86362001)(66476007)(6486002)(478600001)(66946007)(41300700001)(36756003)(921008)(7416002)(7366002)(2906002)(7406005)(5660300002)(38100700002)(2616005)(6512007)(6506007)(6666004)(83380400001)(26005)(202311291699003)(4216001);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: o93vOzgPifG1P4VbkFhWTGFFahkhlARUTrm73NWNXsXUnTuxLZ6yq8GJaBMtRGwqFGsGLuWRFp2q4YQM+9D6gQ2MePrzhiz3/gU5Tz7/NS2z6BpVbDiAE96w35u0Or/eXUXm7Xzcm66fLtslM1UNp/ABFr1THw/JegH0NWolq9xqMS/B9eKUvF42pJnrTnWuXpMPEh/0ho4iEbriw+9e97QbTc7u9ChjUxcuyWqjOsaNUWM7QkDTq6renXotM9hzoq8AYz079eSg/zH3WlZxVmGM9Q8pTWPOoU7JmBQUMBgb9ScqzzwZEDu8Jb+sOTGlw5v0/SGatkYAof4EaHSJRcLg10NyzoGR5/BxOtZDt5AhVtdK29nbvqsA9/b1YaVDJB+crL7vk9KHdCW5MsJ9BxDv8DBnX7phfHXtU/CP+v8bwACV1XYaqxLdnvrhqHGZeoQjFdTnRZQ9T1AUVFybd0E7i6ZOyPyTZ/lEh9Eww4cvKsifl0XR9CITk+a2HNLdoQoCZXiyddBKcgzN5Fk3TAN1uAnCZLr/+imCvCuj+GYyja5AMJODWY23umKFYSXk1+k9P2S3E4vWYZ94ORdethA5gzpFfcwui0/4PH8ZV065Ab7oxpqMLEoEMEnM9fVFiwEKLXiBnMZKCBGatPCFiHo5DwA+/dZzYuC79TNgGZV2sdYy8DM9L2HYn8qbFGtwkGfrXOr+6yeMyVrd4RP2ZcgQn1Xos4hD09ifvRxnlNFlfLVTHfcARbXWOKB+58PNw67IoAfRCyJipaIjfyYlP89rG7CAzERtn3z/Zawhmxz+rzvGQ74acndrk5d8IKMcQWk2xBiXRMNQLsfTvGfYfswXq5Eu3m85TH75mJpP6g4me/zdldZWhhnNg0zyBY+PgSd5sMErvND4/es1Mfs5LcrawXiZgf+eGoDU8/e9tekzm9nOLsGPIMnNi3ToMJm8qO1f/LvCu3NM0jAYkwQngplTWjNLO9M+ntuwb3gIGIok4S5qFVjuyorrRSlsVeXH++qLaQH1K9ECUvEWvl5wInCKkuVlknqJSXTzpi+BMmQRb0jPIX7Kh4u86A1cBehBlgFKUSYguRzYsIdXOnl8ZoYgm3YEzhxikhb+z5Q2L5ym33IWUAN78djx5V7kye2dMNgxdEQ2fDn1ilL0+hzS6iCS4h4wCHOkAogroJvChs/vYvEFosBnG4/9YwZ0D6NcdyPBGV3OgKjxGSG0F8ka1V7wNuImt6rDWS+6o7BOz74Q7kpmKCjTUANR+WtMC8pgtquDAa2sA72tJoDK3u4QNN/4wWok5W4iwD4KbFUPolUV0qqSQAB8+v2fZBNRwpwohOJO/CKMXug58RFtgNjr78jkLMLFFf2k34bczjUkiG637PQFFk0Di7IA7p8VWD2Yoadii1L+fg/yoDNZKQftOFxt8d+6yMGOFeVLUoXg7W7pfWz8UghOhbZw+BwvmmNayRhwoKZx9VvkzeifYv5vOL7UxN7ykuTl/OFazFw4QI4R9nCU5aDUSB2IjT2XfOsHZEPfShSoSsAv4nhyziF9zCGBM7GJztsQySxonQWwzySNF2zDj+GDqo1w+/1oVIOb X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 3b7c2a46-bde1-43ba-de9f-08dbf1412c2b X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2023 01:10:42.0115 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: rKRdU3xUv0YfjqjwVjOiGYZpIlTC16NPNlmHBn1LiMBDSU/VmIXb/gDGNS0ISUvI X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5484 Similar to of_iommu_for_each_id() this parses the VIOT ACPI description and invokes a function over each entry in the table. Have viot_iommu_configure() use the new function to call viot_dev_iommu_init(). Signed-off-by: Jason Gunthorpe Acked-by: Rafael J. Wysocki --- drivers/acpi/viot.c | 54 +++++++++++++++++++++++---------------- include/linux/acpi_viot.h | 11 ++++++++ 2 files changed, 43 insertions(+), 22 deletions(-) diff --git a/drivers/acpi/viot.c b/drivers/acpi/viot.c index c8025921c129b2..7ab35ef05c84e0 100644 --- a/drivers/acpi/viot.c +++ b/drivers/acpi/viot.c @@ -25,13 +25,6 @@ #include #include -struct viot_iommu { - /* Node offset within the table */ - unsigned int offset; - struct fwnode_handle *fwnode; - struct list_head list; -}; - struct viot_endpoint { union { /* PCI range */ @@ -304,10 +297,10 @@ void __init acpi_viot_init(void) acpi_put_table(hdr); } -static int viot_dev_iommu_init(struct device *dev, struct viot_iommu *viommu, - u32 epid) +static int viot_dev_iommu_init(struct viot_iommu *viommu, u32 epid, void *info) { const struct iommu_ops *ops; + struct device *dev = info; if (!viommu) return -ENODEV; @@ -324,11 +317,17 @@ static int viot_dev_iommu_init(struct device *dev, struct viot_iommu *viommu, return acpi_iommu_fwspec_init(dev, epid, viommu->fwnode, ops); } -static int viot_pci_dev_iommu_init(struct pci_dev *pdev, u16 dev_id, void *data) +struct viot_pci_iommu_alias_info { + struct device *dev; + viot_for_each_fn fn; + void *info; +}; + +static int __for_each_pci_alias(struct pci_dev *pdev, u16 dev_id, void *data) { u32 epid; struct viot_endpoint *ep; - struct device *aliased_dev = data; + struct viot_pci_iommu_alias_info *info = data; u32 domain_nr = pci_domain_nr(pdev->bus); list_for_each_entry(ep, &viot_pci_ranges, list) { @@ -339,14 +338,14 @@ static int viot_pci_dev_iommu_init(struct pci_dev *pdev, u16 dev_id, void *data) epid = ((domain_nr - ep->segment_start) << 16) + dev_id - ep->bdf_start + ep->endpoint_id; - return viot_dev_iommu_init(aliased_dev, ep->viommu, - epid); + return info->fn(ep->viommu, epid, info->info); } } return -ENODEV; } -static int viot_mmio_dev_iommu_init(struct platform_device *pdev) +static int __for_each_platform(struct platform_device *pdev, + viot_for_each_fn fn, void *info) { struct resource *mem; struct viot_endpoint *ep; @@ -357,12 +356,28 @@ static int viot_mmio_dev_iommu_init(struct platform_device *pdev) list_for_each_entry(ep, &viot_mmio_endpoints, list) { if (ep->address == mem->start) - return viot_dev_iommu_init(&pdev->dev, ep->viommu, - ep->endpoint_id); + return fn(ep->viommu, ep->endpoint_id, info); } return -ENODEV; } +int viot_iommu_for_each_id(struct device *dev, viot_for_each_fn fn, void *info) +{ + if (dev_is_pci(dev)) { + struct viot_pci_iommu_alias_info pci_info = { + .dev = dev, + .fn = fn, + .info = info, + }; + return pci_for_each_dma_alias(to_pci_dev(dev), + __for_each_pci_alias, &pci_info); + } + + if (dev_is_platform(dev)) + return __for_each_platform(to_platform_device(dev), fn, info); + return -ENODEV; +} + /** * viot_iommu_configure - Setup IOMMU ops for an endpoint described by VIOT * @dev: the endpoint @@ -371,10 +386,5 @@ static int viot_mmio_dev_iommu_init(struct platform_device *pdev) */ int viot_iommu_configure(struct device *dev) { - if (dev_is_pci(dev)) - return pci_for_each_dma_alias(to_pci_dev(dev), - viot_pci_dev_iommu_init, dev); - else if (dev_is_platform(dev)) - return viot_mmio_dev_iommu_init(to_platform_device(dev)); - return -ENODEV; + return viot_iommu_for_each_id(dev, viot_dev_iommu_init, dev); } diff --git a/include/linux/acpi_viot.h b/include/linux/acpi_viot.h index a5a12243156377..fce4eefcae4aad 100644 --- a/include/linux/acpi_viot.h +++ b/include/linux/acpi_viot.h @@ -5,6 +5,17 @@ #include +struct viot_iommu { + /* Node offset within the table */ + unsigned int offset; + struct fwnode_handle *fwnode; + struct list_head list; +}; + +typedef int (*viot_for_each_fn)(struct viot_iommu *viommu, u32 epid, + void *info); +int viot_iommu_for_each_id(struct device *dev, viot_for_each_fn fn, void *info); + #ifdef CONFIG_ACPI_VIOT void __init acpi_viot_early_init(void); void __init acpi_viot_init(void); From patchwork Thu Nov 30 01:10:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 13473772 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="RPbLdFCJ" Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2070.outbound.protection.outlook.com [40.107.244.70]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2D9A8D7F; Wed, 29 Nov 2023 17:10:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=XXFEYKsOQXGSHNx/lvA5mDO//TOdy7bfcifppRBhtOk3lMlTDZXyLuLUyQOM0sInG48Z1OH8gbAkvmd60w3QitMNrobafMPtoRw0PPwpX4p33zTo8QxaXbEFi226AxFq/kiv4luxEAOZ4WkOd3jIlFMZJRUwn6/Q9ULPtirlOCof6oPb9P4kHsFc9+RL4YDUCWA8Qytcrwyfkf+/bxw3LffLrYW7fYBK5qJS+ZlkZK95hhwxEj1a+jHXEjXfZ6DIsBEfMvpMUNw+xSPNslmMfFCAAZwDhTcyDmi71Ys1Ofz5o0T1N7M1xB4S/y+IlUY9gmEOEDre/Hwm5tX2eIHDdg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=TeNlyomNkLn0vDrMhnXRZEG4tXI6kjRAm58pilBJJWY=; b=J9v0skXnxpK9wrcH0+M+LX/agrU7B+TBYzOCgWwnrkMPJ2GSxp1CeR90bsQSa63Laebo8gZpo36vDmvI8FS1C0ZMfyc7zcLPSZV4nEfBW7HRuIN83wHvlx+QXgOpXWEQXAjcAugw8q+hLl6mkhYMKUmzmiC69zBv/UYCiDpIRasdfpqolxiE6i8zF9++cvyiDZfBg7T1q7q3F8cCwRKpDjsz2jwWKXoJ75G8TzFy/izBfNPP56tXwAHjDpjJDP/lILvMdDmNqnY7Ucz2XdM+OBVu1/cFv5lfbJf9hxhjtQxShGfD6sBSkvkrQP2/wQRVkewrz8sEbJJ9T1PWnVEhWg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=TeNlyomNkLn0vDrMhnXRZEG4tXI6kjRAm58pilBJJWY=; b=RPbLdFCJzmrVks0WTIxkHSvZFDRokh9D3A7VdSiGc2sYySwYag6Kfpx6OI7CAo3CqIn6jXsG21Y8YRvyXFy+tdLhxLrOHdwOttpmFN2k3hgwf4gmYYCzFHkgR6cMhMkJb4lZjoNRvphOb5NpNAC83xrXtFPs6WphKkcWll8pTgm1KKuquyWYvBVWG4e234AsGUGQ1Sq+wrQlXJhmeWlU+bzrrzkbiydliXllW2XLkRA35Ukrffo3A6F7mna9xp8ko5K3ztkX1chvOAy2y9gvwBL4TTxIajqFkVUt5ypfeQpAaOgaGp8X+9uhO/4FoIF53ojtO2Bo+d8NLuTNq2gYTA== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by DM6PR12MB4484.namprd12.prod.outlook.com (2603:10b6:5:28f::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.23; Thu, 30 Nov 2023 01:10:56 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.7046.015; Thu, 30 Nov 2023 01:10:55 +0000 From: Jason Gunthorpe To: acpica-devel@lists.linux.dev, Andy Gross , Alim Akhtar , Alyssa Rosenzweig , Bjorn Andersson , AngeloGioacchino Del Regno , asahi@lists.linux.dev, Baolin Wang , devicetree@vger.kernel.org, Frank Rowand , Hanjun Guo , "Gustavo A. R. Silva" , Heiko Stuebner , iommu@lists.linux.dev, Jean-Philippe Brucker , Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kees Cook , Konrad Dybcio , Krzysztof Kozlowski , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Lorenzo Pieralisi , Marek Szyprowski , Hector Martin , Matthias Brugger , Orson Zhai , "Rafael J. Wysocki" , Rob Clark , Robert Moore , Rob Herring , Robin Murphy , Samuel Holland , Sudeep Holla , Sven Peter , Thierry Reding , Krishna Reddy , virtualization@lists.linux.dev, Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: =?utf-8?q?Andr=C3=A9_Draszik?= , patches@lists.linux.dev Subject: [PATCH 03/30] ACPI: IORT: Make a iort_iommu_for_each_id() Date: Wed, 29 Nov 2023 21:10:10 -0400 Message-ID: <3-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> In-Reply-To: <0-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> References: X-ClientProxiedBy: SA0PR11CA0128.namprd11.prod.outlook.com (2603:10b6:806:131::13) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|DM6PR12MB4484:EE_ X-MS-Office365-Filtering-Correlation-Id: 2d5393b6-bc80-4b4e-b90c-08dbf1412d33 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: WACztOEs8ClSQyQdofD6SX2bBXzfuSg2e7e3+uDtfk99ONwwvVbPkCjQh7TK2zT3OKVQESNy+e3Z51zhWf81cOrl5Nu3GL5sNi79w7k59rEbqA/JAmG5Vm2LmlvvBgBZz0HQsoc2FPIh0dnp5AdiZaPFjFf7RmKKjldH/SQCrDt+2VWUFGj/vL2oMzXtI3GD+KFiX8KXxwCq7cTLou4caG3KSGsVuLRswSfT3CZw+2BdW2kNB6SDpjw4yTSizCpVsXSF90tNhXTBLEJ25WXYjfRhXkgy/7XZWBs3jXJxucSdcjN488G0WclTa0TqryykNvp1Y+bZBzwpeEFxLZPzeZcpetiH+2EPn8f2Uj3KihUdoxyrmqvkkopqrexACNFWjcl5lnv+7sZHAZGGFnT9B2nbKyR4oGHkf/1azWtq2rVxEPnIGkeY6DSMShC58tqlrfcsq5NHsQd+eKj0CHP3EWJSvo9Yg0b3g0GMoqGpRgwhjBfS+G6rX9+1t/ru1JQNVT4oGTUybHWfS7gbOiHzn7hvaWbhHVHyP8WCOqsrwdbMIRO6wzJNPKGiODXjHBpDcNaq9dQQO6u00YNzR1hGvc+6jdHppRN7yorUJl8bBf5QcfUhih0WFb8koHc2LtjqtBQRuuRnW7Uh6d1dYzJsl0bhk5jFOJJlnTLNdUpn9U0= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:LV2PR12MB5869.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(376002)(366004)(396003)(136003)(346002)(39860400002)(230922051799003)(1800799012)(451199024)(186009)(64100799003)(83380400001)(1191002)(2616005)(26005)(921008)(66476007)(66946007)(66556008)(7406005)(7366002)(7416002)(110136005)(2906002)(8676002)(4326008)(8936002)(86362001)(5660300002)(41300700001)(6506007)(6666004)(6512007)(36756003)(316002)(478600001)(6486002)(202311291699003)(38100700002)(4216001);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: jbOz4qPPEyiOOTp5vSMtAdERSp4SLZpY5rsvqdaXGkZetG8bfl5rmfpr/jibgOqs/O+W3tXSVdFUlV7d52t8GJt7XGeakPRSsUutrfHLe/HReDathpx+nlzHTnV8Nr+O1L25XeMDMFb2/JP82vgQ07DF/uV76YUZUW8KTPqsh9CdgzJRG4GNCk9OBf5YLuFynV7gr+HInimMfbobXW8UfD7p3q4zUapr6rArgHsn6KAwPL7UzZrwvOx1vsXnkcxEkKKqW27tHYGj/MKNJaALJpDDyJk9HZ19BvmAyybXsSpsfLqGjezKayT+3VagLHNtMdyVeed0ux857Ymg5k/xU9bHUluBx374QGxoPaPvsWJi/k87uw/N+AgouafHOObrLrmW2TW1U9pDMnCCo6pU7upfHWHxu7ZY2DBNyaLkb0EusqHviqde9tq+uPhjhc6NNrTuSkyEMc1dPnzANU6WFiJlFdW1ZaNxpLJAUJ0nnUqRTCZ1+f2AVkbBn7tyta8cKWvM343hDQNy8q6MKICys+bp5JzL30camvF8studYCoGEvG9hi7iRVFRuShf7Yu8XHfQv45ftoW2KhO7oxiX2MeIwWSUPK89byMgXH6EGaRuDgEYNAFAQHY7FHMaB+jOCGY+2EUWtpFm+lPZy0C5WD6I64CjmNm5SPXuhckTmqOMMOdVoIELYZQWJTvspap4uLY5wILPfaqMg7C/lPiQbEx1pxZ4W+GinXfKom4ou43Kk/19ZQFtZKog6Zr7SvUo/uaNaP/D5bC13IOOD/+qGmD7kHxpeSvnZs+lVkgMUXRDYd8XGoR2meMKKERnXxS+o9674npHTmS6yzEZTOgU5Dkw7xOCj0mwa7trt1YAK/8bDRcOUxNhhztSlYXDB9lNJAH0SzOSkxf9U+A2vWEVtgIZ+2uGeWIyis33W6ifAolk6goH+3sqLRGV77psDnrVbcm8GJsuxmnSC+QtzUMDGoBsdKUIFuxS9Dmf++6UWY+K+zAnsw2ToF3vzE+HOOL23bkDVxVZhnjyi+fOZl+/G3YDTQkxWPLGdrZbTCOtSy1fqqCHkhLAy+gO7FpmJrN3SOfCdk9Cgx3SEHdqGDNqZirux0idGI2EXnev8Av4c5vAvDk22LMBzGFg39qsbJlpZm5vueasytknE2aL+nyF2d4FzTei2bg301kupvqwynViN5PFUUH2+QJBodisS/dwZRWeYoqnE8RV+AcsSlRbAH6jvSoHyFrcl8Nl6LIXd9ya7qKyLjahOuoim4ME3oBJKPXxCO2q0oRVNqtnUD3LhUmd1FK2KoAOMVdmlEHdT9a7Ek25F22/K3T4CLTDaKWR6pq8deXZyMsqZBAI0NY1sBC4QI5pf+T5i3AQyB7EhJRyDtSYeN/B74YWRTsGjyXZ4K+HqopGBtEzaDK3GtpABJOGXFDFqRzjRHkhnSnAmsduT4eHtuQVLYIGavpxwJQ1kvnkDeqo0ICuKWqwjXtlgiEflWWJh/V3AcDk8NHzd0NZwq4iQEQDAU0nLX/FzAMRIVgIxQGgI/PArMr6ak81G1VI9PftkTde/kUz8rIuTaXCYLK1O+KyX+0kSGwLRp6Q X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2d5393b6-bc80-4b4e-b90c-08dbf1412d33 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2023 01:10:43.8387 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: pF7veoymWuGvxp3HCnmKxo4u/Evh7vjWDzMhm1eLL0GoG6jimlV8Bbu2oexvxU3B X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4484 Similar to of_iommu_for_each_id() this parses the IORT ACPI description and invokes a function over each entry in the table. Have iort_iommu_configure_id() use the new function to call iort_iommu_xlate(). Signed-off-by: Jason Gunthorpe Acked-by: Rafael J. Wysocki --- drivers/acpi/arm64/iort.c | 118 ++++++++++++++++++++++++-------------- include/linux/acpi_iort.h | 12 ++++ 2 files changed, 86 insertions(+), 44 deletions(-) diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c index bdaf9256870d92..5c9b4c23f96a87 100644 --- a/drivers/acpi/arm64/iort.c +++ b/drivers/acpi/arm64/iort.c @@ -1218,9 +1218,10 @@ static bool iort_pci_rc_supports_ats(struct acpi_iort_node *node) return pci_rc->ats_attribute & ACPI_IORT_ATS_SUPPORTED; } -static int iort_iommu_xlate(struct device *dev, struct acpi_iort_node *node, - u32 streamid) +static int iort_iommu_xlate(struct acpi_iort_node *node, u32 streamid, + void *info) { + struct device *dev = info; const struct iommu_ops *ops; struct fwnode_handle *iort_fwnode; @@ -1250,9 +1251,11 @@ static int iort_iommu_xlate(struct device *dev, struct acpi_iort_node *node, struct iort_pci_alias_info { struct device *dev; struct acpi_iort_node *node; + iort_for_each_fn fn; + void *info; }; -static int iort_pci_iommu_init(struct pci_dev *pdev, u16 alias, void *data) +static int __for_each_pci_alias(struct pci_dev *pdev, u16 alias, void *data) { struct iort_pci_alias_info *info = data; struct acpi_iort_node *parent; @@ -1260,7 +1263,7 @@ static int iort_pci_iommu_init(struct pci_dev *pdev, u16 alias, void *data) parent = iort_node_map_id(info->node, alias, &streamid, IORT_IOMMU_TYPE); - return iort_iommu_xlate(info->dev, parent, streamid); + return info->fn(parent, streamid, info->info); } static void iort_named_component_init(struct device *dev, @@ -1280,7 +1283,8 @@ static void iort_named_component_init(struct device *dev, dev_warn(dev, "Could not add device properties\n"); } -static int iort_nc_iommu_map(struct device *dev, struct acpi_iort_node *node) +static int __for_each_platform(struct acpi_iort_node *node, iort_for_each_fn fn, + void *info) { struct acpi_iort_node *parent; int err = -ENODEV, i = 0; @@ -1293,27 +1297,71 @@ static int iort_nc_iommu_map(struct device *dev, struct acpi_iort_node *node) i++); if (parent) - err = iort_iommu_xlate(dev, parent, streamid); + err = fn(parent, streamid, info); } while (parent && !err); return err; } -static int iort_nc_iommu_map_id(struct device *dev, - struct acpi_iort_node *node, - const u32 *in_id) +int iort_iommu_for_each_id(struct device *dev, const u32 *id_in, + struct iort_params *params, iort_for_each_fn fn, + void *info) { - struct acpi_iort_node *parent; - u32 streamid; + struct acpi_iort_named_component *nc; + struct acpi_iort_node *node; + int err = -ENODEV; - parent = iort_node_map_id(node, *in_id, &streamid, IORT_IOMMU_TYPE); - if (parent) - return iort_iommu_xlate(dev, parent, streamid); + memset(params, 0, sizeof(*params)); + if (dev_is_pci(dev)) { + struct pci_bus *bus = to_pci_dev(dev)->bus; + struct iort_pci_alias_info pci_info = { .dev = dev, + .fn = fn, + .info = info }; - return -ENODEV; + node = iort_scan_node(ACPI_IORT_NODE_PCI_ROOT_COMPLEX, + iort_match_node_callback, &bus->dev); + if (!node) + return -ENODEV; + + pci_info.node = node; + err = pci_for_each_dma_alias(to_pci_dev(dev), + __for_each_pci_alias, &pci_info); + + if (iort_pci_rc_supports_ats(node)) + params->pci_rc_ats = true; + return 0; + } + + node = iort_scan_node(ACPI_IORT_NODE_NAMED_COMPONENT, + iort_match_node_callback, dev); + if (!node) + return -ENODEV; + + if (id_in) { + struct acpi_iort_node *parent; + u32 streamid; + + parent = iort_node_map_id(node, *id_in, &streamid, + IORT_IOMMU_TYPE); + if (!parent) + return -ENODEV; + err = fn(parent, streamid, info); + } else { + err = __for_each_platform(node, fn, info); + } + if (err) + return err; + + nc = (struct acpi_iort_named_component *)node->node_data; + params->pasid_num_bits = FIELD_GET(ACPI_IORT_NC_PASID_BITS, + nc->node_flags); + if (nc->node_flags & ACPI_IORT_NC_STALL_SUPPORTED) + params->dma_can_stall = true; + + iort_named_component_init(dev, node); + return 0; } - /** * iort_iommu_configure_id - Set-up IOMMU configuration for a device. * @@ -1324,40 +1372,22 @@ static int iort_nc_iommu_map_id(struct device *dev, */ int iort_iommu_configure_id(struct device *dev, const u32 *id_in) { - struct acpi_iort_node *node; - int err = -ENODEV; + struct iort_params params; + int err; - if (dev_is_pci(dev)) { + err = iort_iommu_for_each_id(dev, id_in, ¶ms, &iort_iommu_xlate, + dev); + if (err) + return err; + + if (params.pci_rc_ats) { struct iommu_fwspec *fwspec; - struct pci_bus *bus = to_pci_dev(dev)->bus; - struct iort_pci_alias_info info = { .dev = dev }; - - node = iort_scan_node(ACPI_IORT_NODE_PCI_ROOT_COMPLEX, - iort_match_node_callback, &bus->dev); - if (!node) - return -ENODEV; - - info.node = node; - err = pci_for_each_dma_alias(to_pci_dev(dev), - iort_pci_iommu_init, &info); fwspec = dev_iommu_fwspec_get(dev); - if (fwspec && iort_pci_rc_supports_ats(node)) + if (fwspec) fwspec->flags |= IOMMU_FWSPEC_PCI_RC_ATS; - } else { - node = iort_scan_node(ACPI_IORT_NODE_NAMED_COMPONENT, - iort_match_node_callback, dev); - if (!node) - return -ENODEV; - - err = id_in ? iort_nc_iommu_map_id(dev, node, id_in) : - iort_nc_iommu_map(dev, node); - - if (!err) - iort_named_component_init(dev, node); } - - return err; + return 0; } #else diff --git a/include/linux/acpi_iort.h b/include/linux/acpi_iort.h index 1cb65592c95dd3..5423abff9b6b09 100644 --- a/include/linux/acpi_iort.h +++ b/include/linux/acpi_iort.h @@ -29,6 +29,18 @@ void iort_deregister_domain_token(int trans_id); struct fwnode_handle *iort_find_domain_token(int trans_id); int iort_pmsi_get_dev_id(struct device *dev, u32 *dev_id); +struct iort_params { + unsigned int pasid_num_bits; + bool dma_can_stall : 1; + bool pci_rc_ats : 1; +}; + +typedef int (*iort_for_each_fn)(struct acpi_iort_node *iommu, u32 streamid, + void *info); +int iort_iommu_for_each_id(struct device *dev, const u32 *id_in, + struct iort_params *params, iort_for_each_fn fn, + void *info); + #ifdef CONFIG_ACPI_IORT u32 iort_msi_map_id(struct device *dev, u32 id); struct irq_domain *iort_get_device_domain(struct device *dev, u32 id, From patchwork Thu Nov 30 01:10:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 13473756 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="Wd3GQfKU" Received: from NAM04-DM6-obe.outbound.protection.outlook.com (mail-dm6nam04on2060.outbound.protection.outlook.com [40.107.102.60]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 526FFD54; Wed, 29 Nov 2023 17:10:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Z5DU661SRsmHA8CiOKQdRZ8DbqSu8OFEE48kOA0RmlerWUfsoDXE4Y1joDpaacFrU6oNTdY2nCTJK89W/CZ8vH9Q6Ly8AxR0pFqRf3zQNKM/1h5Nn9wGNuRQEI4QQ72l/oNnAN/BHiUsKRfQc7vk+uRCiMVyhGfY94+Xu1alXjoSpik/KoHPdPR9AGFzVTYj1WEcwEO+GcJNyQlxghvu8iyETHaQ+SszAJL2xu8B2x0Yy4JZ6Okec1cdNo/fIyA2wij6pvorVhnRU2cQI7AFZkchjOMpXkXNGS/l9mFhP+mAn5w2gMAMZEgzkKfNOPf6fR+N8B1ZL8nAncATf4ubaQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=S1/2RwZb1BvcKrWpjq41xk6R0wcBobygbj+9IidcnE8=; b=Agd/dlrnkFVoUeVayIt9ibYudFujJ5s2Kj4hTuKT1d0gPI1h32WyOi7zFfhRJIFQ27Vtu3YlX1z0RCimsbH5Sz62fzeA2b7/RmSjT2chrxICujq6mQfF4mrBZOaXlHoywtxxTCOxlpXzHy/Exj2/7k8Ppb5gpCYaLVJ5efAwQMl7RheN+cYXqRlYtY8Hc+WvgOowWb3m4bDGbWW0Mvy4QARQc+TysrE3dgmnoB2eNINK9P0/jsZDayBiFuWEjY0B3I1mYMrLDtt7omW68VedFZzoSuwFz1JUWBp5SU22O5IMd1FFkpL9EyBDpZs9aEnaX2YjGNIDAot0rq+mnBkM2w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=S1/2RwZb1BvcKrWpjq41xk6R0wcBobygbj+9IidcnE8=; b=Wd3GQfKUtdMv1PJC8DKrRfs1e1pu+1GrORDA9mw/Xe/WjUmrRFKlPjsn1CrCx+g73L4uWk9ZJRpMClkXk0lJFRuCa5ZlbBRJZFbBO001T28yQsXTqUYF7Z9wr0v66t6vKDf1sleW5b/vmbpgXG4LdU30EpuWv5+qLI1H3OkOeakQd3sA+8NN86eVYHny5ylOVA3PUjlhGK24/viXa76WZAB9SQM/VhnuYL0yCl2hjsHGZtWZnbZd6lirHoRnDOIvgM3O0yDZS3qNFp1r4TgDjbwvCN8dHhxZC28VFu+hSjEWjQYbBhDTYf2hvL4BzfbWWdMJ+ymvvf279JY7Pkor7w== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by DS0PR12MB7607.namprd12.prod.outlook.com (2603:10b6:8:13f::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.22; Thu, 30 Nov 2023 01:10:39 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.7046.015; Thu, 30 Nov 2023 01:10:39 +0000 From: Jason Gunthorpe To: acpica-devel@lists.linux.dev, Andy Gross , Alim Akhtar , Alyssa Rosenzweig , Bjorn Andersson , AngeloGioacchino Del Regno , asahi@lists.linux.dev, Baolin Wang , devicetree@vger.kernel.org, Frank Rowand , Hanjun Guo , "Gustavo A. R. Silva" , Heiko Stuebner , iommu@lists.linux.dev, Jean-Philippe Brucker , Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kees Cook , Konrad Dybcio , Krzysztof Kozlowski , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Lorenzo Pieralisi , Marek Szyprowski , Hector Martin , Matthias Brugger , Orson Zhai , "Rafael J. Wysocki" , Rob Clark , Robert Moore , Rob Herring , Robin Murphy , Samuel Holland , Sudeep Holla , Sven Peter , Thierry Reding , Krishna Reddy , virtualization@lists.linux.dev, Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: =?utf-8?q?Andr=C3=A9_Draszik?= , patches@lists.linux.dev Subject: [PATCH 04/30] ACPI: IORT: Remove fwspec from the reserved region code Date: Wed, 29 Nov 2023 21:10:11 -0400 Message-ID: <4-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> In-Reply-To: <0-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> References: X-ClientProxiedBy: SN7PR04CA0162.namprd04.prod.outlook.com (2603:10b6:806:125::17) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|DS0PR12MB7607:EE_ X-MS-Office365-Filtering-Correlation-Id: 799948c1-d494-4ba0-9962-08dbf1412a25 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: HOwkopNGa0CBJ1OiokLpJXaWRObisYdz9OliU1tDVjJR2EnhrrKcMvn/tZ83zBYOOidiSi8ak9+LyDk0jrjNScorLATqTch+cK3eZEvCvHa9OJoe5YHgi5ryCfuHinCcJG8s5XKJSBolN6DMZl5JG3dM9HvzzfGFcFAZs6iV5V+QD3MdcEzrkWle7chIpMx3D3uJG33V1z2xUdcxzRxOA6bBKQRvTzJUJRCZ10g1HuL5tIFYzqGdsCv+MezcXMViedA2D2f/dkVQqD7s+QElsnFAS3QsMbsnhLcbguhk7k9fziOPCgn3B/kqidMU2YZorqB95rHis9lRV1uCshslD8buIhDwtYviVktRpgsJZgXGW89iPbJi7GEFipUARuQVyBUqisXCxncXwRVW8RhjpJkret/3sHfo76HuN+mj9HfKQa+rccIWWT9NqG3fhFuklkM9i6H+ysP2p047dM/5L5W+fGt+KDLyRY/eLHbTPYiBv/jZ6Esvw4h+gwP8dK7Qq1uEu1WtSXjrEorgJpM+ZiKsrE+FD1KMABgO+J7O5sg5CvDJAA7uCirdJRXqOL6qOiXaF8q0zMBZMUx6YMbFoI5tdk3RhlBthpaxCd53dhMdIssQl62wLdeMF8zQqr/zMgPYaZUM2YzPfbRig3Hcw2QxVxeWSr0HzzwrHGkMjk8= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:LV2PR12MB5869.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(396003)(39860400002)(346002)(136003)(366004)(376002)(230922051799003)(186009)(451199024)(64100799003)(1800799012)(38100700002)(202311291699003)(83380400001)(1191002)(5660300002)(110136005)(2906002)(86362001)(4326008)(8676002)(8936002)(66556008)(7366002)(7406005)(7416002)(66476007)(66946007)(6486002)(478600001)(6666004)(316002)(36756003)(6506007)(41300700001)(6512007)(921008)(26005)(2616005)(4216001);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 2mhjeIC9kP2zwjJ3vrYUZ3jAaoHBX2IY3xBPl32LW6cQIx4sFAdbPZhmnG4FuurHu6p3/dvANUAkZDtE0qDPN/ou7YhPs2tsbok7mpuaXMcMfO0M7bPh2A1fz3T9E6fJegXZa+VGcrfhLiKA+jZ1fvOie0oeI24UrywXgLEvy9hKFky4LgxovLqk+BfisoJ6k/bwUbt8HNn8j7mcwjVMqBLC1Mw2z8zYA5HeoThE2HMrRqb/kYRYE/nGY5+VghO/EJ/FyJ1PUmgPonmaL+Hng6hRhEZEshsd4k+BCVryJtnlrqQdQbNzqZ9+k/6kHfBir1tuwTV/Y1xQs6tqFRKw7LZCv9U1i3jqtRW+Fj0ACuaX5q9QkXG47MKP1qC2Hd0IBYb8lXYczGiWDp3Jq8LQHe7DhOvMJtZX3ImlfvrqcjIMhjx1LrFK/DIafD+7Wd/YRY/uaYyVFQseOvBsoPapUNoa1Qj5O3KELLC6x4avNE2/HIR2EXaav1KvNkU7c7gCrEmnoVeEdbxzKHbLv2VjJCbP22IT97ChwhkZUSYdvOw34KlafoIMGRDv85ONLD9vAuF7pfIRBwvTDqjeMmwES+rEAmUMyzlwieNm4DCpX1Ea8yKKkbJlz0CriJQwsfFTncnBtlHLna74Vk4+u5xtpvX64DJLMgg1XAVJ0JORy92xnyC7+UkgX19i6PYaWlkKhcxq4QGf4hYC7nzZ1oS5Pp5GEwMmkp2GEjFNs3cgFawMlWAWCZ2iwkHfGy44qxaptAZWc07/kMbmFqEbkAHPYFkpyCJKmPv7tYsAiPJJ3tErJIbT00MvmLZ48jtfiYiAtnwqDBEe4FqQQSryvmb/5E8mHCbXWNWQNPJp87DNTCX2ve0mvEp/VytaRQSrgaMhcPV5D6Hqc9HCNLyJpmeUyT7r8K3k6F/Mh7qpYaCn4mgiEQ3wjzWctJHnLEdT8iQCDYmV3QIDp492oWMRyl7u082Jr4tU6fBOgtBHUb5YVoAMOUEpieV+cf3sfB4c/yyw3i51kX/t8PkwNrgBGoaLtgXID4g/XFV2q2WpS3rUAe12l2QBr7rz0uSC02jcAA+C/NwqWcsyIAT4p39aYlDAgnkJA/CJqy39gJoye6JJdN8oVmTjamQpXfouVPGCX5WnC9DbXNl7QyhY2OEZCPW2q/ybiZmpni6jiwMqKaCA9vqgFVSoK/hD0MWCZCgUsUN5SdiTLxjc6j31/FUortrzLHg+K/8kiAnxrLpb0c3vdxVnJ4QDTj3fJJnO4ItGF7nZOKRV0jPbsWbWGfB4BKXmbdE5K6KJ+y2eKtHJcIz3mq12uyq5AstKy6Ci2Xw7V37Bdq2e4kufxiE7s7cFf7YC8E0/8S5hll+U/9KAXsWsCQFhIg33RhYxdEnQz5IYeHc6PrmbffrrQfqoMz3SXtyAKT9Wy0DHKmD6a74EDs4xwTpZa95ZgScZVVRXkoJt/ocLubU9iM7yTus6mwV4jn1kKEI9pyad9Wcb4vjV02TEj6LJ5wNQ3Te0SKYbTb4hapAl3cCabqW5+WgszKOoMDPTKI9NV+v3CMATwO3SJvm8uXDPHDgRo5qRDg6XL5qKBYxI X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 799948c1-d494-4ba0-9962-08dbf1412a25 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2023 01:10:38.8211 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: xmL1HXjHi6e5JgKpBsPqhhRc8AtQttGvFiUIYyPn2GmuaV9VgchKVr2DtiYJqBGB X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7607 iort_iommu_get_resv_regions() needs access to the parsed id array that is currently stored in the iommu_fwspec. Instead of getting this from the fwspec inside the iort code have the caller pass it in. Signed-off-by: Jason Gunthorpe Acked-by: Rafael J. Wysocki --- drivers/acpi/arm64/iort.c | 88 ++++++++++++++++++++++++--------------- drivers/iommu/dma-iommu.c | 7 +++- include/linux/acpi_iort.h | 8 +++- 3 files changed, 65 insertions(+), 38 deletions(-) diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c index 5c9b4c23f96a87..93e30f2f5004f0 100644 --- a/drivers/acpi/arm64/iort.c +++ b/drivers/acpi/arm64/iort.c @@ -946,11 +946,19 @@ static u32 *iort_rmr_alloc_sids(u32 *sids, u32 count, u32 id_start, return new_sids; } -static bool iort_rmr_has_dev(struct device *dev, u32 id_start, +struct iort_resv_args { + struct device *dev; + struct list_head *head; + struct fwnode_handle *iommu_fwnode; + const u32 *fw_ids; + unsigned int fw_num_ids; +}; + +static bool iort_rmr_has_dev(struct iort_resv_args *args, u32 id_start, u32 id_count) { + struct device *dev = args->dev; int i; - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); /* * Make sure the kernel has preserved the boot firmware PCIe @@ -965,18 +973,18 @@ static bool iort_rmr_has_dev(struct device *dev, u32 id_start, return false; } - for (i = 0; i < fwspec->num_ids; i++) { - if (fwspec->ids[i] >= id_start && - fwspec->ids[i] <= id_start + id_count) + for (i = 0; i < args->fw_num_ids; i++) { + if (args->fw_ids[i] >= id_start && + args->fw_ids[i] <= id_start + id_count) return true; } return false; } -static void iort_node_get_rmr_info(struct acpi_iort_node *node, - struct acpi_iort_node *iommu, - struct device *dev, struct list_head *head) +static void iort_node_get_rmr_info(struct iort_resv_args *args, + struct acpi_iort_node *node, + struct acpi_iort_node *iommu) { struct acpi_iort_node *smmu = NULL; struct acpi_iort_rmr *rmr; @@ -1013,8 +1021,8 @@ static void iort_node_get_rmr_info(struct acpi_iort_node *node, continue; /* If dev is valid, check RMR node corresponds to the dev SID */ - if (dev && !iort_rmr_has_dev(dev, map->output_base, - map->id_count)) + if (args->dev && + !iort_rmr_has_dev(args, map->output_base, map->id_count)) continue; /* Retrieve SIDs associated with the Node. */ @@ -1029,12 +1037,12 @@ static void iort_node_get_rmr_info(struct acpi_iort_node *node, if (!sids) return; - iort_get_rmrs(node, smmu, sids, num_sids, head); + iort_get_rmrs(node, smmu, sids, num_sids, args->head); kfree(sids); } -static void iort_find_rmrs(struct acpi_iort_node *iommu, struct device *dev, - struct list_head *head) +static void iort_find_rmrs(struct iort_resv_args *args, + struct acpi_iort_node *iommu) { struct acpi_table_iort *iort; struct acpi_iort_node *iort_node, *iort_end; @@ -1057,7 +1065,7 @@ static void iort_find_rmrs(struct acpi_iort_node *iommu, struct device *dev, return; if (iort_node->type == ACPI_IORT_NODE_RMR) - iort_node_get_rmr_info(iort_node, iommu, dev, head); + iort_node_get_rmr_info(args, iort_node, iommu); iort_node = ACPI_ADD_PTR(struct acpi_iort_node, iort_node, iort_node->length); @@ -1069,25 +1077,23 @@ static void iort_find_rmrs(struct acpi_iort_node *iommu, struct device *dev, * If dev is NULL, the function populates all the RMRs associated with the * given IOMMU. */ -static void iort_iommu_rmr_get_resv_regions(struct fwnode_handle *iommu_fwnode, - struct device *dev, - struct list_head *head) +static void iort_iommu_rmr_get_resv_regions(struct iort_resv_args *args) { struct acpi_iort_node *iommu; - iommu = iort_get_iort_node(iommu_fwnode); + iommu = iort_get_iort_node(args->iommu_fwnode); if (!iommu) return; - iort_find_rmrs(iommu, dev, head); + iort_find_rmrs(args, iommu); } -static struct acpi_iort_node *iort_get_msi_resv_iommu(struct device *dev) +static struct acpi_iort_node * +iort_get_msi_resv_iommu(struct iort_resv_args *args) { struct acpi_iort_node *iommu; - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); - iommu = iort_get_iort_node(fwspec->iommu_fwnode); + iommu = iort_get_iort_node(args->iommu_fwnode); if (iommu && (iommu->type == ACPI_IORT_NODE_SMMU_V3)) { struct acpi_iort_smmu_v3 *smmu; @@ -1105,15 +1111,13 @@ static struct acpi_iort_node *iort_get_msi_resv_iommu(struct device *dev) * The ITS interrupt translation spaces (ITS_base + SZ_64K, SZ_64K) * associated with the device are the HW MSI reserved regions. */ -static void iort_iommu_msi_get_resv_regions(struct device *dev, - struct list_head *head) +static void iort_iommu_msi_get_resv_regions(struct iort_resv_args *args) { - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); struct acpi_iort_its_group *its; struct acpi_iort_node *iommu_node, *its_node = NULL; int i; - iommu_node = iort_get_msi_resv_iommu(dev); + iommu_node = iort_get_msi_resv_iommu(args); if (!iommu_node) return; @@ -1126,9 +1130,9 @@ static void iort_iommu_msi_get_resv_regions(struct device *dev, * a given PCI or named component may map IDs to. */ - for (i = 0; i < fwspec->num_ids; i++) { + for (i = 0; i < args->fw_num_ids; i++) { its_node = iort_node_map_id(iommu_node, - fwspec->ids[i], + args->fw_ids[i], NULL, IORT_MSI_TYPE); if (its_node) break; @@ -1151,7 +1155,7 @@ static void iort_iommu_msi_get_resv_regions(struct device *dev, prot, IOMMU_RESV_MSI, GFP_KERNEL); if (region) - list_add_tail(®ion->list, head); + list_add_tail(®ion->list, args->head); } } } @@ -1160,13 +1164,24 @@ static void iort_iommu_msi_get_resv_regions(struct device *dev, * iort_iommu_get_resv_regions - Generic helper to retrieve reserved regions. * @dev: Device from iommu_get_resv_regions() * @head: Reserved region list from iommu_get_resv_regions() + * @iommu_fwnode: fwnode that describes the iommu connection for the device + * @fw_ids: Parsed IDs + * @fw_num_ids: Length of fw_ids */ -void iort_iommu_get_resv_regions(struct device *dev, struct list_head *head) +void iort_iommu_get_resv_regions(struct device *dev, struct list_head *head, + struct fwnode_handle *iommu_fwnode, + const u32 *fw_ids, unsigned int fw_num_ids) { - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); + struct iort_resv_args args = { + .dev = dev, + .head = head, + .iommu_fwnode = iommu_fwnode, + .fw_ids = fw_ids, + .fw_num_ids = fw_num_ids, + }; - iort_iommu_msi_get_resv_regions(dev, head); - iort_iommu_rmr_get_resv_regions(fwspec->iommu_fwnode, dev, head); + iort_iommu_msi_get_resv_regions(&args); + iort_iommu_rmr_get_resv_regions(&args); } /** @@ -1178,7 +1193,12 @@ void iort_iommu_get_resv_regions(struct device *dev, struct list_head *head) void iort_get_rmr_sids(struct fwnode_handle *iommu_fwnode, struct list_head *head) { - iort_iommu_rmr_get_resv_regions(iommu_fwnode, NULL, head); + struct iort_resv_args args = { + .head = head, + .iommu_fwnode = iommu_fwnode, + }; + + iort_iommu_rmr_get_resv_regions(&args); } EXPORT_SYMBOL_GPL(iort_get_rmr_sids); diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c index 85163a83df2f68..d644b0502ef48e 100644 --- a/drivers/iommu/dma-iommu.c +++ b/drivers/iommu/dma-iommu.c @@ -468,9 +468,12 @@ void iommu_put_dma_cookie(struct iommu_domain *domain) */ void iommu_dma_get_resv_regions(struct device *dev, struct list_head *list) { + struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); - if (!is_of_node(dev_iommu_fwspec_get(dev)->iommu_fwnode)) - iort_iommu_get_resv_regions(dev, list); + if (!is_of_node(fwspec->iommu_fwnode)) { + iort_iommu_get_resv_regions(dev, list, fwspec->iommu_fwnode, + fwspec->ids, fwspec->num_ids); + } if (dev->of_node) of_iommu_get_resv_regions(dev, list); diff --git a/include/linux/acpi_iort.h b/include/linux/acpi_iort.h index 5423abff9b6b09..13f0cefb930693 100644 --- a/include/linux/acpi_iort.h +++ b/include/linux/acpi_iort.h @@ -53,7 +53,9 @@ void iort_put_rmr_sids(struct fwnode_handle *iommu_fwnode, /* IOMMU interface */ int iort_dma_get_ranges(struct device *dev, u64 *size); int iort_iommu_configure_id(struct device *dev, const u32 *id_in); -void iort_iommu_get_resv_regions(struct device *dev, struct list_head *head); +void iort_iommu_get_resv_regions(struct device *dev, struct list_head *head, + struct fwnode_handle *iommu_fwnode, + const u32 *fw_ids, unsigned int fw_num_ids); phys_addr_t acpi_iort_dma_get_max_cpu_address(void); #else static inline u32 iort_msi_map_id(struct device *dev, u32 id) @@ -72,7 +74,9 @@ static inline int iort_dma_get_ranges(struct device *dev, u64 *size) static inline int iort_iommu_configure_id(struct device *dev, const u32 *id_in) { return -ENODEV; } static inline -void iort_iommu_get_resv_regions(struct device *dev, struct list_head *head) +void iort_iommu_get_resv_regions(struct device *dev, struct list_head *head, + struct fwnode_handle *iommu_fwnode, + const u32 *fw_ids, unsigned int fw_num_ids) { } static inline phys_addr_t acpi_iort_dma_get_max_cpu_address(void) From patchwork Thu Nov 30 01:10:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 13473758 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="IQjX7i/l" Received: from NAM04-DM6-obe.outbound.protection.outlook.com (mail-dm6nam04on2060.outbound.protection.outlook.com [40.107.102.60]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DA4F010A; Wed, 29 Nov 2023 17:10:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=HNwgJ9M0f7NHybi2UuKUbLbc/hViKCX0JdfFD4LKzmJEg6s+LP8Y9AZUuKbRNOl7yDPWwcHU1nLAi0/9wk0tqyTyShrSZGfs8teEaS7F1gURJZdlLOLIxtTtOh82QtnTbjnjD8KSdefGkuKXVvmUFcitXnfPXDyH5s1mRVgVOpADG1fzrKOXwFmUjV1EaA3NjT1ALgL2VE17RJaf4XiAMIEW9RH6DOynB3ERhCNusPdvYlWj18Eaoajekj97s/SDd2J9Hsta+77QUj163kPqcUhz8Q653OXSApzTaLoNj2XfOMaxNQVIiGGf3vcTqpEeH5jidNlKKhggxHqfm7VYiQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Z7r48HdaFD2m3FjojzyB3owyxRtlpeFZA78h2PReCEE=; b=k7uIMreIE5QccI3QJKd8el4wYJ+423L2GNMZq/rj2mSAo6QgcxrgtW+wu/JZTPPlh5jH+GqwImX+Xn7Vr/Y0kIZD2/DIfPE92/5NtSLiBVzNy7gjXAdOaRLoDdlVaTNphnhRdmWous/Z7L3BzoF0THBSBY2bP/uvArmeMtrdCUdBRABQqBEhM6/UTG2A2FMwIHQZAlA/SmKzczDzEzh/RmCls2f77HkdECDH2KeZiaSfyMDqhoPpikcEeHwwg4Wn+hjFCdzL78tNJrvDR1vRE1HZBQQ8i2Ujfq2QjH+BHZkk+E02fAo2okPZaaOpin8/XG119qtPPKD1PE5UxJQvAQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Z7r48HdaFD2m3FjojzyB3owyxRtlpeFZA78h2PReCEE=; b=IQjX7i/lv+Z8mK2447t1yUT/Sna9CuJqhyRNXlZjIfjeLlhVKevGVzk0bHpEF3wADhFGrWz1o/yO3ZAD5UFOVqVPDZo/CnvwdGhSvmEqFrtdE+JLCBD7Y27mzk6jfrkHWlyyvG3eUusL2mY+GGR6Hbcl0OkA9YAakzZw1Nmffbhat/ylH+gIV5wpkjz5IB6K+Us4L9ZHTsHint02NxqaJYuXvJ5MKzBADQwNLKCEn58whZ3YGCX8nNUXOcwP2yssEwwn1+5VpDLOG5/aVaplgBIXv6VBHka0k3F3rnXYdVdNB52CYIJUVxe3N9OhindYi9JY7B0MhZbmFHVXSQTs5Q== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by DS0PR12MB7607.namprd12.prod.outlook.com (2603:10b6:8:13f::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.22; Thu, 30 Nov 2023 01:10:40 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.7046.015; Thu, 30 Nov 2023 01:10:40 +0000 From: Jason Gunthorpe To: acpica-devel@lists.linux.dev, Andy Gross , Alim Akhtar , Alyssa Rosenzweig , Bjorn Andersson , AngeloGioacchino Del Regno , asahi@lists.linux.dev, Baolin Wang , devicetree@vger.kernel.org, Frank Rowand , Hanjun Guo , "Gustavo A. R. Silva" , Heiko Stuebner , iommu@lists.linux.dev, Jean-Philippe Brucker , Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kees Cook , Konrad Dybcio , Krzysztof Kozlowski , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Lorenzo Pieralisi , Marek Szyprowski , Hector Martin , Matthias Brugger , Orson Zhai , "Rafael J. Wysocki" , Rob Clark , Robert Moore , Rob Herring , Robin Murphy , Samuel Holland , Sudeep Holla , Sven Peter , Thierry Reding , Krishna Reddy , virtualization@lists.linux.dev, Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: =?utf-8?q?Andr=C3=A9_Draszik?= , patches@lists.linux.dev Subject: [PATCH 05/30] iommu: Add iommu_probe_info Date: Wed, 29 Nov 2023 21:10:12 -0400 Message-ID: <5-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> In-Reply-To: <0-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> References: X-ClientProxiedBy: SN1PR12CA0106.namprd12.prod.outlook.com (2603:10b6:802:21::41) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|DS0PR12MB7607:EE_ X-MS-Office365-Filtering-Correlation-Id: 2f2d4ae6-9622-4cea-e3f7-08dbf1412a4d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: /wWspF/FaTgWBVwC3jzSZmwVrg9el1WqTPJImdRwDrEM/jzXqgmhaJE0/icD4hBsG3L0Ez+/ZJyR1WRs5YMcYFZD9Ck+7ls/9OJoF4odI2zvRSTUFA+aCYVn1vcz7NvpeMUgYE9do2TydLJIkJBawiz0zMENmQalX3Jm0rUKKSys48D8AXC68dUUGYZ53oDxF39YC5eiNMbjwJ4STl4ha0+dfeK/7F5vJ0BzzBxhUXJADiuTGutv1oOfTrClckCOC4+3q075y0M6SUQwTSLr285vcTTTrHJ9j9vYQAnnLBfh5zzA39o4fJD9IemL3IiN58iM7bggWCPA5p5Kuy4Fu53f/FE5veH11LlmSOL/k9fp5kZAijrbe1iWY57ESPKTOuTSt39spVJM/IV3YXslnTRlG15IHh237t9V+rwwroo71q4qIJGfvnkNKlaVmC5+DrqaOkY8Jz79dtTfWyDDbgH/mJlEhglQ+Go0qMLYbWtHJczbSjzf/VYhXLom5rftjcUGCaPdEFh0lU2IoMPPLma11BZHvtlXQxoZ5WGPTKRQJIKxIjcMBCGq/l6jfshgKxQdOxYU9SP+RqctYqqSfsYxPDQo79jKMtWGRwBVgrpm7SVmk4Z4Kfb2gIMezmwuXXS64EvJvTzr2xmQroKgBDUlxBWwXQG56UcHd0N2v4A= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:LV2PR12MB5869.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(396003)(39860400002)(346002)(136003)(366004)(376002)(230922051799003)(186009)(451199024)(64100799003)(1800799012)(38100700002)(202311291699003)(83380400001)(1191002)(5660300002)(110136005)(2906002)(86362001)(4326008)(8676002)(8936002)(66556008)(7366002)(7406005)(7416002)(66476007)(66946007)(6486002)(478600001)(6666004)(316002)(36756003)(6506007)(41300700001)(6512007)(921008)(26005)(2616005)(4216001);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 6MU0MdKuBSJB3CE4W+zHAs8QPocLSd6QOFhUd8whfIz7Mlq/5Fejr99reHWiyA2kd1cqZ6t2Z65rMpvmH3hfSRO8fC9m28Ub3rfzTmcwP9rAzn3A70SdPHRDKuFzOKBRPR1wkQtkVyOgj4QXwaH8wo63bKL7nOjg0LMRXUC/F9Ml4zK8oFdFamK4OR16dRiCFljG/V/CPhRGDsIOyeaa9AQNehwXshKGTsmO6P7iisHLiwKSKxsD9SFB/POLtRg6lv7SNl3lu25gcqnq48X/OHeImwCPCC1qa0bxWphcCHxO1PJPwALXCZBIqEdH93lIz2pQ7d4Q6y4xoiniUACBMwtbumDkwYEf8zegp70OZWPzc+IyV9icqaceQyl0XY6zp3SVphMfswzB5YMRlc4Lbv+NyAnHuzkj50Gfap5PqYjzBDee99GXAEcWV2O98+rxLBIyOaVh2/EZoI2MBGDQG88ZAFq8LbC9J/GOZmN1C62KMRYH5gwTrsIMyaw/3KoigyGyu8HhPBV42MjG3sJpeZ+38PD6ungFH1K3DIS0K23vq7alpwSNDL5oyMwR52yPuy2lQT48oofpyp5yHR82dgysnenKCSr3gmi+0RDpoaWoVwA4G1wHQFsOAJdz3nQ9AQLNZDsnguEOleXoMCLiW0R/h7mPc3EAByu/RExa3o6fd3zJ0vhQHDn+sYRpwvjGM7BrrxvjX44nih5IR7C/w+p5WkVd8UsIUOuiJvq+yFYj0DmbLdgJTPlPmEQrAwZuW8hY3KT64DUwqjHI3cSYB0t/3X85jgvAyR21PHqBoF/eDmPkTlcCOGp8VZ71Xk+wt5AwAoOOa80PokXg+GaaFyIigPAIluAzY746OtjADWvD7LURjnyqtSGzzi97SxIzbcABo1+JmjBgPqIUBnbTgFcPJyWgtRwY8oH1186cXU+jSsBLi5F1Kg1Vc0WK4fSfJVcBj+UONUimzsUSgRPb5MukNlBXeen7bH3Q8ef4ygHG6Izk/mUpdy5BMBEmFtmwzzk6K/rVKE1mceHaYd07YipN/cRDcf2RXVQpFQiwbfcLclotGN6ExPjlYmN/VcsTHVikLqaZQRtYiYwaQs8dwFWGIgznDmUbczWzn/3K0DCGpEfK5ZNEI+JgCXfPk8MANZ5+oVLlo2Qa1W8CU1fa9KlUSMvKuAKStpfg1TQOdQrPV6tJbWMf0b/hqHDHfwCgB4BVbiv0tYH68MbjNflQXFx7Q04iV0/hyzX4gFmBYQanuMZEkfr7UQkvw67g1XL2MALRSbimigZXoxpBCFmYFHXErNLMS/bGe6e6rqhQiSMj/jTj5C0L1P2VKc0+Qn0t7d+KfMNZz6qGmzjizdTs9QkJGZ80Weyp5owMkhZCl2aqzy6jY1jl0wLKI80Dc4i+9JxwjR0kvrLaZ03Zji8KFsIfZziEFyzx7ifhlzcs+1GbAbpouNxdKXVv86rqUB/s540n4dQdVgFMvZUWH5HfpxarlciQttRKQUNdeRWxKlkJYCOL42Ztrihw/6cxe4NrXBKEMSVNPyxE5BlK7bkrn555NPUZgnVrN7mzoG6dGtRY6mdWNW8Wmy69Iu8jtOyv X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2f2d4ae6-9622-4cea-e3f7-08dbf1412a4d X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2023 01:10:39.0035 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: xrLki78ZDAKoF/Un4eAP9aiZ8Zf66eXHu3kHgx7W0YNmcQQ64OceHRTRzbybAF6o X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7607 This is a stack structure that is passed around all the parts of probe to allow them to exchange data. With the new design this will be a place for the FW logic to cache data to avoid reparsing and a to convey the currently active call path for probe while we work on restructuring parts of it. Place this in a new header "iommu-driver.h" which is intended to help isolate APIs that are only for use by the drivers away from the consumers of the IOMMU API. Signed-off-by: Jason Gunthorpe --- drivers/acpi/scan.c | 7 +++++- drivers/iommu/iommu.c | 42 ++++++++++++++++++++++++++---------- drivers/iommu/of_iommu.c | 6 +++++- include/linux/iommu-driver.h | 25 +++++++++++++++++++++ include/linux/iommu.h | 3 +++ 5 files changed, 70 insertions(+), 13 deletions(-) create mode 100644 include/linux/iommu-driver.h diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c index 340ba720c72129..9c13df632aa5e0 100644 --- a/drivers/acpi/scan.c +++ b/drivers/acpi/scan.c @@ -1543,6 +1543,8 @@ int acpi_dma_get_range(struct device *dev, const struct bus_dma_region **map) } #ifdef CONFIG_IOMMU_API +#include + int acpi_iommu_fwspec_init(struct device *dev, u32 id, struct fwnode_handle *fwnode, const struct iommu_ops *ops) @@ -1566,6 +1568,9 @@ static int acpi_iommu_configure_id(struct device *dev, const u32 *id_in) { int err; const struct iommu_ops *ops; + struct iommu_probe_info pinf = { + .dev = dev, + }; /* Serialise to make dev->iommu stable under our potential fwspec */ mutex_lock(&iommu_probe_device_lock); @@ -1589,7 +1594,7 @@ static int acpi_iommu_configure_id(struct device *dev, const u32 *id_in) * iommu_probe_device() call for dev, replay it to get things in order. */ if (!err && dev->bus) - err = iommu_probe_device(dev); + err = iommu_probe_device_pinf(&pinf); /* Ignore all other errors apart from EPROBE_DEFER */ if (err == -EPROBE_DEFER) { diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index 9557c2ec08d915..76b245973cfafc 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -399,8 +400,10 @@ EXPORT_SYMBOL_GPL(dev_iommu_priv_set); * Init the dev->iommu and dev->iommu_group in the struct device and get the * driver probed */ -static int iommu_init_device(struct device *dev, const struct iommu_ops *ops) +static int iommu_init_device(struct iommu_probe_info *pinf, + const struct iommu_ops *ops) { + struct device *dev = pinf->dev; struct iommu_device *iommu_dev; struct iommu_group *group; int ret; @@ -413,7 +416,10 @@ static int iommu_init_device(struct device *dev, const struct iommu_ops *ops) goto err_free; } - iommu_dev = ops->probe_device(dev); + if (ops->probe_device_pinf) + iommu_dev = ops->probe_device_pinf(pinf); + else + iommu_dev = ops->probe_device(dev); if (IS_ERR(iommu_dev)) { ret = PTR_ERR(iommu_dev); goto err_module_put; @@ -496,8 +502,9 @@ static void iommu_deinit_device(struct device *dev) DEFINE_MUTEX(iommu_probe_device_lock); -static int __iommu_probe_device(struct device *dev, struct list_head *group_list) +static int __iommu_probe_device(struct iommu_probe_info *pinf) { + struct device *dev = pinf->dev; const struct iommu_ops *ops; struct iommu_fwspec *fwspec; struct iommu_group *group; @@ -533,7 +540,7 @@ static int __iommu_probe_device(struct device *dev, struct list_head *group_list if (dev->iommu_group) return 0; - ret = iommu_init_device(dev, ops); + ret = iommu_init_device(pinf, ops); if (ret) return ret; @@ -557,7 +564,7 @@ static int __iommu_probe_device(struct device *dev, struct list_head *group_list ret = __iommu_device_set_domain(group, dev, group->domain, 0); if (ret) goto err_remove_gdev; - } else if (!group->default_domain && !group_list) { + } else if (!group->default_domain && !pinf->defer_setup) { ret = iommu_setup_default_domain(group, 0); if (ret) goto err_remove_gdev; @@ -568,7 +575,7 @@ static int __iommu_probe_device(struct device *dev, struct list_head *group_list * that need further setup. */ if (list_empty(&group->entry)) - list_add_tail(&group->entry, group_list); + list_add_tail(&group->entry, pinf->deferred_group_list); } mutex_unlock(&group->mutex); @@ -588,13 +595,14 @@ static int __iommu_probe_device(struct device *dev, struct list_head *group_list return ret; } -int iommu_probe_device(struct device *dev) +int iommu_probe_device_pinf(struct iommu_probe_info *pinf) { + struct device *dev = pinf->dev; const struct iommu_ops *ops; int ret; mutex_lock(&iommu_probe_device_lock); - ret = __iommu_probe_device(dev, NULL); + ret = __iommu_probe_device(pinf); mutex_unlock(&iommu_probe_device_lock); if (ret) return ret; @@ -606,6 +614,13 @@ int iommu_probe_device(struct device *dev) return 0; } +int iommu_probe_device(struct device *dev) +{ + struct iommu_probe_info pinf = {.dev = dev}; + + return iommu_probe_device_pinf(&pinf); +} + static void __iommu_group_free_device(struct iommu_group *group, struct group_device *grp_dev) { @@ -1830,11 +1845,12 @@ struct iommu_domain *iommu_group_default_domain(struct iommu_group *group) static int probe_iommu_group(struct device *dev, void *data) { - struct list_head *group_list = data; + struct iommu_probe_info *pinf = data; int ret; + pinf->dev = dev; mutex_lock(&iommu_probe_device_lock); - ret = __iommu_probe_device(dev, group_list); + ret = __iommu_probe_device(pinf); mutex_unlock(&iommu_probe_device_lock); if (ret == -ENODEV) ret = 0; @@ -1977,9 +1993,13 @@ int bus_iommu_probe(const struct bus_type *bus) { struct iommu_group *group, *next; LIST_HEAD(group_list); + struct iommu_probe_info pinf = { + .deferred_group_list = &group_list, + .defer_setup = true, + }; int ret; - ret = bus_for_each_dev(bus, NULL, &group_list, probe_iommu_group); + ret = bus_for_each_dev(bus, NULL, &pinf, probe_iommu_group); if (ret) return ret; diff --git a/drivers/iommu/of_iommu.c b/drivers/iommu/of_iommu.c index 3d4580f1fbb378..fb743ddd239e0b 100644 --- a/drivers/iommu/of_iommu.c +++ b/drivers/iommu/of_iommu.c @@ -7,6 +7,7 @@ #include #include +#include #include #include #include @@ -139,6 +140,9 @@ static int of_iommu_for_each_id(struct device *dev, int of_iommu_configure(struct device *dev, struct device_node *master_np, const u32 *id) { + struct iommu_probe_info pinf = { + .dev = dev, + }; struct iommu_fwspec *fwspec; int err; @@ -167,7 +171,7 @@ int of_iommu_configure(struct device *dev, struct device_node *master_np, if (err) goto err_log; - err = iommu_probe_device(dev); + err = iommu_probe_device_pinf(&pinf); if (err) goto err_log; return 0; diff --git a/include/linux/iommu-driver.h b/include/linux/iommu-driver.h new file mode 100644 index 00000000000000..b85c9f15cf478b --- /dev/null +++ b/include/linux/iommu-driver.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES + * + * This file should ONLY be included by iommu drivers. These API + * calls are NOT to be used generally. + */ +#ifndef __LINUX_IOMMU_DRIVER_H +#define __LINUX_IOMMU_DRIVER_H + +#ifndef CONFIG_IOMMU_API +#error "CONFIG_IOMMU_API is not set, should this header be included?" +#endif + +#include + +struct iommu_probe_info { + struct device *dev; + struct list_head *deferred_group_list; + bool defer_setup : 1; +}; + +int iommu_probe_device_pinf(struct iommu_probe_info *pinf); + +#endif diff --git a/include/linux/iommu.h b/include/linux/iommu.h index c24933a1d0d643..cf578b8e0b59a4 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -43,6 +43,7 @@ struct notifier_block; struct iommu_sva; struct iommu_fault_event; struct iommu_dma_cookie; +struct iommu_probe_info; /* iommu fault flags */ #define IOMMU_FAULT_READ 0x0 @@ -347,6 +348,7 @@ static inline int __iommu_copy_struct_from_user( * @domain_alloc_paging: Allocate an iommu_domain that can be used for * UNMANAGED, DMA, and DMA_FQ domain types. * @probe_device: Add device to iommu driver handling + * @probe_device_pinf: New API for probe_device * @release_device: Remove device from iommu driver handling * @probe_finalize: Do final setup work after the device is added to an IOMMU * group and attached to the groups domain @@ -388,6 +390,7 @@ struct iommu_ops { struct iommu_domain *(*domain_alloc_paging)(struct device *dev); struct iommu_device *(*probe_device)(struct device *dev); + struct iommu_device *(*probe_device_pinf)(struct iommu_probe_info *pinf); void (*release_device)(struct device *dev); void (*probe_finalize)(struct device *dev); struct iommu_group *(*device_group)(struct device *dev); From patchwork Thu Nov 30 01:10:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 13473782 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="FZh9rBNd" Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2084.outbound.protection.outlook.com [40.107.243.84]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2DE5310D4; Wed, 29 Nov 2023 17:11:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=m6BT3mC8pRCBcmPjZ3m9iCDlon+xEbfYM9H/MaCfIqpQE85/2unDlBVYRWVf/ST9/1GwgebWWjkzqQH/woMWt6j10jM60GSrN8Tq+FEApFIsmJaOJdwGmooeaX+rQkF5yT9lL7WpfnknLLH2KRzTuAo2Zw3GzmI6RuyqupdOycJRHPIAf8qhpL5nVEnxAyDKInprLxLChYJocqMx7qkbcnUzr5J8QoJlZ5O4MjcrJogp02IcLWhU0/2KsxFPXMclaDszDdBLYt7zJCY45WSrTeWczncIB/y2rmEnc7f0VAc26GYdBL+amNDrEXkhUHr4B9xor00bvNMKnGIUe6t8Xw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=472sQygPvvhZhJ8WiOO2/mkS7+2EbUYdhDQB/DwfKZ8=; b=P3nKEbUEmulvJPr08xzSdAYDQPXj14/iwWuLPobaQhTPJ8Z9NKqzbRyZaQYl8uyvjBOndSI1ZUElx8SxY1Zq4Fk5a2gIlH5fzNLM56RrQ1udYvrvihao3KmAWi6T7eRD6uEWGXwBc9I03FDj/dKA6xKvrbvHFv4VJeR6PHL2h/TXsFFLM/WSVyi+7jXbKWWr6AAXs25ZBg/VDC0z2Hg4GKT7lpyGOJFhRyruFAbrYWVLIcBLjkg5TAMCf7Bs6CKB1f0Y77QbatMUJvxnolCZWzFF8TLjbl7rTAfgTEnBQRq0Yo3ZjC1GpHTcbzH4NwdUlq4KzjxG2FleDoz9Rmk73g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=472sQygPvvhZhJ8WiOO2/mkS7+2EbUYdhDQB/DwfKZ8=; b=FZh9rBNd9QOgiK1jfedV76ae5bGLRy62Sr0iclxKCTOlv8VIxQrF7CC8B8GJqd8QmytVZTjW6ghMXhqtp7/kbwMYER2lt298hf6GFlKngmTN/F58zVqrvCLAQf9GBZDEU7QWvCGZKnGjKgau2xA5L/docGUu9G9j/mZRQVu7gIumCUCFWKni8lCpV0mfqObwWhjgpOCzhJtelH6lT8Vpw8MWwj1a2xOZiCCSSrQIfdB3bAE+Gd0uPeAJBDftSAvfyAqCPqy5rNDsSMXQJ9jCAvbxd2lS6MBi86TpAMLMZc67Wcowgm++O+WEx9cYQ1vPWj/J4TkiWYKULJsihHVqew== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by PH0PR12MB5484.namprd12.prod.outlook.com (2603:10b6:510:eb::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.24; Thu, 30 Nov 2023 01:10:54 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.7046.015; Thu, 30 Nov 2023 01:10:54 +0000 From: Jason Gunthorpe To: acpica-devel@lists.linux.dev, Andy Gross , Alim Akhtar , Alyssa Rosenzweig , Bjorn Andersson , AngeloGioacchino Del Regno , asahi@lists.linux.dev, Baolin Wang , devicetree@vger.kernel.org, Frank Rowand , Hanjun Guo , "Gustavo A. R. Silva" , Heiko Stuebner , iommu@lists.linux.dev, Jean-Philippe Brucker , Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kees Cook , Konrad Dybcio , Krzysztof Kozlowski , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Lorenzo Pieralisi , Marek Szyprowski , Hector Martin , Matthias Brugger , Orson Zhai , "Rafael J. Wysocki" , Rob Clark , Robert Moore , Rob Herring , Robin Murphy , Samuel Holland , Sudeep Holla , Sven Peter , Thierry Reding , Krishna Reddy , virtualization@lists.linux.dev, Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: =?utf-8?q?Andr=C3=A9_Draszik?= , patches@lists.linux.dev Subject: [PATCH 06/30] iommu: Make iommu_ops_from_fwnode() return the iommu_device Date: Wed, 29 Nov 2023 21:10:13 -0400 Message-ID: <6-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> In-Reply-To: <0-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> References: X-ClientProxiedBy: SN7P222CA0015.NAMP222.PROD.OUTLOOK.COM (2603:10b6:806:124::29) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|PH0PR12MB5484:EE_ X-MS-Office365-Filtering-Correlation-Id: bf4423ce-a64b-47d2-71cb-08dbf1412c62 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: BKbzTr8Riy9oQOKVDyyb2L/xUi7wIbXVOt54dMcq2oA4OOhPzsuVXq/ML4UZ1oieEpabslKrnNdm4mb29lPIiJHhw9Qum6GWnTGFjXFWxk0p8vsS9iP11BY+juvk+oyeYloZoXUfdX0TtLYREekrEA5CwNXJ6qmy8wFKTN6Xl+YrDXV0bdjym5yGwQXthCTbujW6URtQ3lqrIoYUCWEXHQajFYSJkINTIRAD+kKGS7r7NzZWhzXDxwZEKjiojn1cov597uFk/bmjbW7Trr6eTtz+myasXaYknKFf0fnMZ8JMFgoEJcyVxFze+8MMG6BVTcESssecPYvVAT9AwhmZ4Waaj3N9wRuqxTYwUnJqnZXcH9Wxe1/ec2y8+naeGzwOGA28XN3bj1zklPC5ZDjxxPmVVkpMVLi0zU9w3W2bSQEwL1l4+QBfEb98LQxDrGCXIp6tohR+0E4klMZYpZ1Ue6hU84mG6nrPsCPvGUn0sB0GimqaORUs/Q+Zcem/iYSOEzABAZShmLoR0CfkE8DOoO2xD3k1qba1mPEwX7P5L1J6NeJ5MS/qb2H2xaF6+TbYc10vQPyGY4wRC8hZgfK249cCx5PZeSRIvdcRgoNYQUyPzAb9nXUlDOyRSsRD6VIOj8F0KkhmjC84czE1J4cSVJSUEJBSnIqSp/3wczJiQKk= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:LV2PR12MB5869.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(366004)(346002)(136003)(396003)(39860400002)(376002)(230922051799003)(451199024)(1800799012)(186009)(64100799003)(1191002)(8936002)(110136005)(8676002)(316002)(66556008)(4326008)(86362001)(66476007)(6486002)(478600001)(66946007)(41300700001)(36756003)(921008)(7416002)(7366002)(2906002)(7406005)(5660300002)(38100700002)(2616005)(6512007)(6506007)(6666004)(83380400001)(26005)(202311291699003)(4216001);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 74u2vI5Qz9MrU+SN3zzghPjql7uGI9iK6HP0c1j9n+r9JMYrfqsjBtZnthyXPmO70BLmE8n9538yYCoNcQYlwRtf5d4G0pLmTr0IWuQa0ZNDcuHbgnSoOPpOBOX/3529vnMXbFe4piANMTQFVu1h7W8L/9VUz/iJUkeL0Mb7X3B7d1THD3nJIfqN5W7JA9M1EmBQhkxkRfWbXiDP+Jnzi+HmRnGWgY8kztv7p9YYTRgw9mok03DX5+ZuhsUmX2UdamFrd0gcEH5Ka05YAJWMCPyIH6qSUBGQl39VZY+FfluuCXYrmz0HVsfqhjrGDJe7y+AUCBnaUUby4GBs4zev/2SKj24QLde4bNNCnJkduP34kIFuuNTQnx3oyXNJDd9t2dfE8SyGSUL3f5xxiPmH5XlMmQ/Ttpye9qpeuwteWPR3fTxVMVE3xRGqaKHZukrBifaZaV7Tm9ZTOYOb29J28iNrqmmA4Twvq7F2mEh0jpt00ZBmgC2i55fMa2sAYuFwEakoShrALQXV92g/92MnAQ3ND4acv7C/gxWucjCWhed6nAX14pl7Lxwv7uI52/Lxeb73fy8+41aOQUPsigkp8DIgC+j/2pYVmss+JOY3xhA1AN33NGbM5N2t/AAI65DUUT9xUUcBI4CfPshRqCYZURugN0c0LVNWEoFncNG6MLib71UGMpxaM+7kxMbUzccE21OyTWCGlto7V+U8x+lBbBNpg48WOGsgy18bp6OJXik6zmBN6HZ2rjAN96wYL7udAnNdtS78f3qXtLzgCiS6pkVWi0exYXpUFAJvLmdZXP4qZMk8c8+Z80+aRyOOLFHUBSiHAA+h0Uz4Vak9wiWUBJqseyNsMMfPUzwRiJbvZzb7KmL1Hz+n8SQormWGQ6msETCkWk7c8DTznTE5HE5rRZXiN9T9a8DhdVxHbOT4VEkf5GzxudDkXtz0L9fbDnYvQkGDZ6uV/fSn/Z7QlrxXqpER9UCwHGLQxp5i2dcZ2Si/GPL6q2TSCm0DD0cAWM53wq3OOeSF+O0HtGDUuvUbQMDrPeSWulCP+40/QwsD27HhlpGZi1bijb3QH4H4qjHt+o9WUotO7ddsVd0lBpi2QlsultTDuKAv2hi59yfl//DQ34g+/py9d92e3CQVhGpzEdJ2AVDD4f/BOIreXihvEstkHLoHFf0Nk0uBrdZUTfENOruOExl6+n2Www1yeyfbyuAmFfuju/EdTgO4wIhAIwgkjQw7+i5gqS0qLJ3dsxG3WYTjFx9lSUoguhhW/IUnVlyiccCwHReU52bQpgmWDktBph45yBAeVsu0+xA2tb3eXXyr3mD6tj4VS2NjC016oRC7yyd2OxIDTuOPqUJxWAtZt/ZPDvR2vZTQM4XG8exvS9/q7FGjUjjE2iakt4lYXOpfcUA2w1VdneYJvNsCvySCmxpJZ0scSINf4QVXF+AxuWOiQWcFbGj0fqhekubkxne6raQ2Kso+tvHW+zxGp02/DCz3fcvs69Ze1jkEaIyZmjIYWAFk1MOmzsZzEyMxIxBX/rqtmu7ZQ8ZhB6BuueIxKOwOHXpS2LifUXGFHEDh/fmWfmzsvNzR42P5PwVq X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: bf4423ce-a64b-47d2-71cb-08dbf1412c62 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2023 01:10:42.4741 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: CC7T+5CVvgnAF99X1JXCvOTjBqexX/mK5SnV2QcR9gngEP0DC2Z/kP6u/tx4iQwE X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5484 Return the entire struct iommu_device instead of just the ops. Name the changed function iommu_device_from_fwnode(). The iommu_device pointer is kept valid because this is always called under the iommu_probe_device_lock. If iommu_device is valid then ops is valid too, the module refcounting is pointless. Remove it. Signed-off-by: Jason Gunthorpe --- drivers/acpi/arm64/iort.c | 12 +++++++----- drivers/acpi/viot.c | 9 +++++---- drivers/iommu/iommu.c | 20 +++++++++++++------- drivers/iommu/of_iommu.c | 16 ++++++---------- include/linux/iommu-driver.h | 3 +++ include/linux/iommu.h | 7 ------- 6 files changed, 34 insertions(+), 33 deletions(-) diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c index 93e30f2f5004f0..798c0b344f4be8 100644 --- a/drivers/acpi/arm64/iort.c +++ b/drivers/acpi/arm64/iort.c @@ -797,6 +797,8 @@ void acpi_configure_pmsi_domain(struct device *dev) } #ifdef CONFIG_IOMMU_API +#include + static void iort_rmr_free(struct device *dev, struct iommu_resv_region *region) { @@ -1242,7 +1244,7 @@ static int iort_iommu_xlate(struct acpi_iort_node *node, u32 streamid, void *info) { struct device *dev = info; - const struct iommu_ops *ops; + struct iommu_device *iommu; struct fwnode_handle *iort_fwnode; if (!node) @@ -1253,19 +1255,19 @@ static int iort_iommu_xlate(struct acpi_iort_node *node, u32 streamid, return -ENODEV; /* - * If the ops look-up fails, this means that either + * If the iommu look-up fails, this means that either * the SMMU drivers have not been probed yet or that * the SMMU drivers are not built in the kernel; * Depending on whether the SMMU drivers are built-in * in the kernel or not, defer the IOMMU configuration * or just abort it. */ - ops = iommu_ops_from_fwnode(iort_fwnode); - if (!ops) + iommu = iommu_device_from_fwnode(iort_fwnode); + if (!iommu) return iort_iommu_driver_enabled(node->type) ? -EPROBE_DEFER : -ENODEV; - return acpi_iommu_fwspec_init(dev, streamid, iort_fwnode, ops); + return acpi_iommu_fwspec_init(dev, streamid, iort_fwnode, iommu->ops); } struct iort_pci_alias_info { diff --git a/drivers/acpi/viot.c b/drivers/acpi/viot.c index 7ab35ef05c84e0..9780b1d477503e 100644 --- a/drivers/acpi/viot.c +++ b/drivers/acpi/viot.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -299,7 +300,7 @@ void __init acpi_viot_init(void) static int viot_dev_iommu_init(struct viot_iommu *viommu, u32 epid, void *info) { - const struct iommu_ops *ops; + struct iommu_device *iommu; struct device *dev = info; if (!viommu) @@ -309,12 +310,12 @@ static int viot_dev_iommu_init(struct viot_iommu *viommu, u32 epid, void *info) if (device_match_fwnode(dev, viommu->fwnode)) return -EINVAL; - ops = iommu_ops_from_fwnode(viommu->fwnode); - if (!ops) + iommu = iommu_device_from_fwnode(viommu->fwnode); + if (!iommu) return IS_ENABLED(CONFIG_VIRTIO_IOMMU) ? -EPROBE_DEFER : -ENODEV; - return acpi_iommu_fwspec_init(dev, epid, viommu->fwnode, ops); + return acpi_iommu_fwspec_init(dev, epid, viommu->fwnode, iommu->ops); } struct viot_pci_iommu_alias_info { diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index 76b245973cfafc..45e6543748fd46 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -520,13 +520,19 @@ static int __iommu_probe_device(struct iommu_probe_info *pinf) * ops for probing, and thus cheekily co-opt the same mechanism. */ fwspec = dev_iommu_fwspec_get(dev); - if (fwspec && fwspec->ops) + if (fwspec && fwspec->ops) { ops = fwspec->ops; - else - ops = iommu_ops_from_fwnode(NULL); + if (!ops) + return -ENODEV; + } else { + struct iommu_device *iommu; + + iommu = iommu_device_from_fwnode(NULL); + if (!iommu) + return -ENODEV; + ops = iommu->ops; + } - if (!ops) - return -ENODEV; /* * Serialise to avoid races between IOMMU drivers registering in * parallel and/or the "replay" calls from ACPI/OF code via client @@ -2997,7 +3003,7 @@ bool iommu_default_passthrough(void) } EXPORT_SYMBOL_GPL(iommu_default_passthrough); -const struct iommu_ops *iommu_ops_from_fwnode(struct fwnode_handle *fwnode) +struct iommu_device *iommu_device_from_fwnode(struct fwnode_handle *fwnode) { struct iommu_device *iommu; @@ -3005,7 +3011,7 @@ const struct iommu_ops *iommu_ops_from_fwnode(struct fwnode_handle *fwnode) list_for_each_entry(iommu, &iommu_device_list, list) if (iommu->fwnode == fwnode) - return iommu->ops; + return iommu; return NULL; } diff --git a/drivers/iommu/of_iommu.c b/drivers/iommu/of_iommu.c index fb743ddd239e0b..cf68cdebc9f318 100644 --- a/drivers/iommu/of_iommu.c +++ b/drivers/iommu/of_iommu.c @@ -21,16 +21,16 @@ static int of_iommu_xlate(struct of_phandle_args *iommu_spec, void *info) { struct device *dev = info; - const struct iommu_ops *ops; + struct iommu_device *iommu; struct fwnode_handle *fwnode = &iommu_spec->np->fwnode; int ret; - ops = iommu_ops_from_fwnode(fwnode); - if ((ops && !ops->of_xlate) || + iommu = iommu_device_from_fwnode(fwnode); + if ((iommu && !iommu->ops->of_xlate) || !of_device_is_available(iommu_spec->np)) return -ENODEV; - ret = iommu_fwspec_init(dev, &iommu_spec->np->fwnode, ops); + ret = iommu_fwspec_init(dev, &iommu_spec->np->fwnode, iommu->ops); if (ret) return ret; /* @@ -38,14 +38,10 @@ static int of_iommu_xlate(struct of_phandle_args *iommu_spec, void *info) * IOMMU device we're waiting for, which will be useful if we ever get * a proper probe-ordering dependency mechanism in future. */ - if (!ops) + if (!iommu) return driver_deferred_probe_check_state(dev); - if (!try_module_get(ops->owner)) - return -ENODEV; - - ret = ops->of_xlate(dev, iommu_spec); - module_put(ops->owner); + ret = iommu->ops->of_xlate(dev, iommu_spec); return ret; } diff --git a/include/linux/iommu-driver.h b/include/linux/iommu-driver.h index b85c9f15cf478b..636b5b5f18f76f 100644 --- a/include/linux/iommu-driver.h +++ b/include/linux/iommu-driver.h @@ -14,6 +14,8 @@ #include +struct fwnode_handle; + struct iommu_probe_info { struct device *dev; struct list_head *deferred_group_list; @@ -21,5 +23,6 @@ struct iommu_probe_info { }; int iommu_probe_device_pinf(struct iommu_probe_info *pinf); +struct iommu_device *iommu_device_from_fwnode(struct fwnode_handle *fwnode); #endif diff --git a/include/linux/iommu.h b/include/linux/iommu.h index cf578b8e0b59a4..f0aaf55db3c09b 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -819,7 +819,6 @@ int iommu_fwspec_init(struct device *dev, struct fwnode_handle *iommu_fwnode, const struct iommu_ops *ops); void iommu_fwspec_free(struct device *dev); int iommu_fwspec_add_ids(struct device *dev, u32 *ids, int num_ids); -const struct iommu_ops *iommu_ops_from_fwnode(struct fwnode_handle *fwnode); static inline struct iommu_fwspec *dev_iommu_fwspec_get(struct device *dev) { @@ -1168,12 +1167,6 @@ static inline int iommu_fwspec_add_ids(struct device *dev, u32 *ids, return -ENODEV; } -static inline -const struct iommu_ops *iommu_ops_from_fwnode(struct fwnode_handle *fwnode) -{ - return NULL; -} - static inline int iommu_dev_enable_feature(struct device *dev, enum iommu_dev_features feat) { From patchwork Thu Nov 30 01:10:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 13473764 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="U9gOcnp5" Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2082.outbound.protection.outlook.com [40.107.243.82]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 94B4E122; Wed, 29 Nov 2023 17:10:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=ZI/VfW3KtQ7EqonoVuReX+ki7gGguNa+xXtb9Ut0viJOYRFTE0+duS7jEYWql0dcE4npCFIWLnHvrUTN7aPDYgop4bkIJcIRnDZNFmQYUp1Y52UOq2WC6kqtrS14AFMTx0Wu2Yfa6oel7TeI/pA1YlgZ4JWipuRs8esiGAefWFpBPe8iqeMXiD566QpiJdLneosJhSC6oS0BdWvAAHC0lrduXJ4+FVcuQtr5ogyES7tj/iaM5ieDtr790OFqujmqN1aPuyO6TnGKL8nH/l0X/sn2CefqHsr7aCfIGKBJtsQxwIL7OdDMAG07poFKXakzuiwwDgvIBJzOsmggV9qhBw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Hq1FeEtZzTGLjMBeHZUc8BYLNkFyjkdrYErvAcq9nLo=; b=hXJDpoI5IYejF7WlvzmfI8OJDgrWDEKPwgs6t25gTIIcSDdoPfv8SOL+/03U3Ji5M5OirW6etXIorCtEXUTjSJZ89cALV8NQ0OxgZKQ/nxrcyGrrGT+1lGGELg33gZ2JWXMaDWMjRrvSHuRN9LAoze8l0zXR2dIzWSkvi/Veun258Wzg4bB3KMoUjGRk7vWoGXY2RLlRzOWg+cGOIfi/oPTLZueAt98/WrBHINfVj5ijMA8g9BwaKSleiaCkkj6Q5ftwAXMBkI9g3PfusOJ2pZSJdTONHKIqKkUsTpLKJa8tCnS+YWbGSX7Iso88hQGUI+GlYFmYDuhKu/0MD9u4EQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Hq1FeEtZzTGLjMBeHZUc8BYLNkFyjkdrYErvAcq9nLo=; b=U9gOcnp5oO9r8HAidfMReXIo1XzhUGE4o3PomWs81JGYy+IdSZhvYv/WNGyxFH4blWT3Self1X0hhgQSGUG+OKKKkp5Nsnl5XY52hvreHHTIsaBmgMW10jDV3nng2OcHf+aBaQYM79cd6P/PJydRHKDtmkck0+7ZJOb6UoqIwPOfrggdaMETncjk4a8m1biciL27uqK6oM/7InRjBZIQyyOb4Puwj8Ngmy6iGVvWR4p3QEzzVRrKfDDWOEbbKD6fYitkOFvBBY4PK6t/dOE66QAhFMbvqnCtIEYYObZQicwiOOiac3AcM35t1+rKvA2BuNSQrGhDdvK++rP3Y+sM3w== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by PH0PR12MB5484.namprd12.prod.outlook.com (2603:10b6:510:eb::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.24; Thu, 30 Nov 2023 01:10:45 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.7046.015; Thu, 30 Nov 2023 01:10:45 +0000 From: Jason Gunthorpe To: acpica-devel@lists.linux.dev, Andy Gross , Alim Akhtar , Alyssa Rosenzweig , Bjorn Andersson , AngeloGioacchino Del Regno , asahi@lists.linux.dev, Baolin Wang , devicetree@vger.kernel.org, Frank Rowand , Hanjun Guo , "Gustavo A. R. Silva" , Heiko Stuebner , iommu@lists.linux.dev, Jean-Philippe Brucker , Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kees Cook , Konrad Dybcio , Krzysztof Kozlowski , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Lorenzo Pieralisi , Marek Szyprowski , Hector Martin , Matthias Brugger , Orson Zhai , "Rafael J. Wysocki" , Rob Clark , Robert Moore , Rob Herring , Robin Murphy , Samuel Holland , Sudeep Holla , Sven Peter , Thierry Reding , Krishna Reddy , virtualization@lists.linux.dev, Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: =?utf-8?q?Andr=C3=A9_Draszik?= , patches@lists.linux.dev Subject: [PATCH 07/30] iommu/of: Call of_iommu_get_resv_regions() directly Date: Wed, 29 Nov 2023 21:10:14 -0400 Message-ID: <7-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> In-Reply-To: <0-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> References: X-ClientProxiedBy: SN6PR16CA0044.namprd16.prod.outlook.com (2603:10b6:805:ca::21) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|PH0PR12MB5484:EE_ X-MS-Office365-Filtering-Correlation-Id: 3ee7532c-6dfb-446f-5483-08dbf1412b1f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: AXq8fYjKL9dbUcjYCNOjj6vXNKTeHyIkdK3aYWhZRReP7duFWnnmKNml6DIQ3iXQdULihAb8beV9w87+ZjSgyINMih1g6nxrYlXjhGPRliw+P0OVZfpxSrlbZ9b4bXTy+/fQUvMmKjJs0QR1mGa0Mi/uH4+qtxtCYAFpb6rAo8Ykmr6iMtNWCaxqvdf23kd/qMC+qBCyIcsM0XgZX6MiJewSCtD5On6icq0rbww/09ITksupiU4gcRflF7D/M9+P8rX+1Jg0JA1KntvOgWAqnOXxjgeMXWIUs/6YfuJulTteCoRI3IAYxsYzoPCjB5/f/Lhy7PktnkCt9qklrxdY1cWemj8rza3BGBUQIzDy2/PZ2of0uTz5UVttSOLxuEtOI1DJLf/4M/eoSEKE+uiclHfvcy7n9VLu36H7QIn55EHPKHuC5VNYWG8DZHm0FMIjae8prmiVzk7JsX01zQNy4Wgzz6jktyvGFrFO8ZSgiQDiXRxZmDD3hPHGCHkmrKqCpnCq+L6skUBinHblKdZlNbkCPsBHT7zDPA9JurwEaXhF3UN4p9box/3W40/MohsatznS6LEnkkMWZQEdb/P4SDNV81PCmDbpLVEaetFdiouvz5z+B81q+HUuksVovxIqoAWc9vU4UkhNNRHdBEKSPo9fmUHQpAgD6rbsoFAOKBk= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:LV2PR12MB5869.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(366004)(346002)(136003)(396003)(39860400002)(376002)(230922051799003)(451199024)(1800799012)(186009)(64100799003)(1191002)(8936002)(110136005)(8676002)(316002)(66556008)(4326008)(86362001)(66476007)(6486002)(478600001)(66946007)(41300700001)(36756003)(921008)(7416002)(7366002)(2906002)(7406005)(5660300002)(38100700002)(2616005)(6512007)(6506007)(6666004)(83380400001)(26005)(202311291699003)(4216001);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: sgcxk6+KWDiWJ1iVCXCRH2MvIRgNTbyE9s38/862qwL+JO52WQtuzdHDyDP6Zl23hu6xcOMNnpAD6AeoJb8ABv85I6oOuTONfpSorlCSC4+A3OTo++lSYKnotWk8LKznWCs+VCOOMSTc3DsBxVD+O4Nj678xlujskfBtMhw4emeHQWpdCK3fJ0AcnNMVohiyIO1OvTTatWlMhMzAXGqyuGiMRSoOCnZiXPHKAMXZ7KPQ1YDBLkpjuzqKTeyMymZNbDmv0Dc0h9/LMO4ZmnDxiUYC7CrRPJlKUxV3qFBVLDJOooZLOcfVvrffnSoZxYI54uQbm3go20oRbRqtOFhXSXvEluSXrjH37ymBBo3ykZdFrb6lcADSEIFFpzmY3xZWLbNbpFPj18rV8Eajlb8vVvxohNqrB4hv2Sa3r8/ej6mseXYltoasEDmAtnuFfU45cq9pO+tdLxQ5/bDmvDSOej4YHEXknA3jpIR88JlAkBOJaKz7B7lJWKnghK3mPcDjrtz4EM4PvGhE3wX8Rpbj+kCO3G3zz5Zll+SvSA/o2aSXiMxQFuEZB5KX/lrzeRNwwSHxdEGmz5YG7gtWBGo5fkn8xlTPL22ZOli14Vetv0tfOnthMdT7Wn1Pao8nIfzoM0Qtist+WInbf8R3kdCvVlguomoP39U7E7vKv4jeUOSt7W0lRqzZGHgCNQXIORP5eiGU9uBLC96FOSkhL9AWGLPoJw/zzwxF+pgzO1EBfboyD3EdzTiipRIqYJgxBio+rEgkq6zbWgmQGBjggbNovwbRq63P0akscaWtJLLkUmNLRIFJGIE4gIICFmRtW/DvqeARYHD11/zvpmJWWO3HRxqBK/yi4uMypz27G5iru6SWZMB2ZR6GFb93Nhfkneo+n6EOtIiQzAyxcEQ7Nm0a8x7pw8GkrWatHpeHanWXh1qWG5MlkvuEKUnODfEMiZRVShu1wUeEYj/VSGP46lCid53edsmrCRDk+LHSmRBXVRuredzOJT8AfmVdVu510f7RmaxWmO/7oTnrb4cYxZw2OoYm0ABcV22bOTCz2g2Fd/ftOdg+PAOCZHhMTgCD2jhEd5mxklOH2B6ExfyJ1IpleHfqjblcdSvB5GLdgK6MDX0AzUGKXs7VEn1zyaLzYB1huCk0PzjdYlgYmQB2TzHZnSMkgqX82AcK55rJd1+jtbiKT8HqyT/5F2WLTr1opNmE9n8K7hPBtYoDG/dJvSGgW0vB2eTYiO+lLYQpFdAuqBBaLHM35fJnSy6dhu9G7vwlVS1NAcLSO6+BuAGNPv7bCNDdd4JYlzTu35yOVEAhB2b0KUgfeR1YZXOydzgINyRE/5mFvscLV9NLfCx+M5zZj/Ss9SD4aml84nezmW2C3b2DulvhOZLXJk/WOl3xvdaI/w/Z3hUHWEAPc/5d/xAGeHWmhyv/jCpBO/PJQ8dPHoY2X8MUdTcwtIMGUDjZGZxzYZiEWyVu/zmT3wuqWlJ4HcpSRJg+leGwXr4pCsPSGdEjP/QZR9J2sfF9+RHK4JW8xYK1QqLBY2kACjCPR+2musJ5flnEMi5E2hIIARDdyspoeiJBFhBxr1THoK4UJQqv X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 3ee7532c-6dfb-446f-5483-08dbf1412b1f X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2023 01:10:40.2800 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: /2/HhoRl557r94rBEGYCPMXl6Q2MU3jnXM/7ruIL9f7tTdYCOp+PY6ONSjmnGbxl X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5484 virtio-iommu and dart already parse the ACPI firmware description in their own get_resv_regions() callback. They just need to parse the OF description. The generic iommu_dma_get_resv_regions() really just knows how to parse the IORT ACPI in addition to OF. Directly call of_iommu_get_resv_regions() instead. Move the declaration of of_iommu_get_resv_regions() to iommu-driver.h since it is now intended to be called by drivers. Signed-off-by: Jason Gunthorpe --- drivers/iommu/apple-dart.c | 5 ++--- drivers/iommu/dma-iommu.c | 5 ++--- drivers/iommu/of_iommu.c | 3 +++ drivers/iommu/virtio-iommu.c | 5 ++--- include/linux/iommu-driver.h | 9 +++++++++ include/linux/of_iommu.h | 8 -------- 6 files changed, 18 insertions(+), 17 deletions(-) diff --git a/drivers/iommu/apple-dart.c b/drivers/iommu/apple-dart.c index 25135440b5dd54..bb0e5a4577fc03 100644 --- a/drivers/iommu/apple-dart.c +++ b/drivers/iommu/apple-dart.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -32,8 +33,6 @@ #include #include -#include "dma-iommu.h" - #define DART_MAX_STREAMS 256 #define DART_MAX_TTBR 4 #define MAX_DARTS_PER_DEVICE 2 @@ -972,7 +971,7 @@ static void apple_dart_get_resv_regions(struct device *dev, list_add_tail(®ion->list, head); } - iommu_dma_get_resv_regions(dev, head); + of_iommu_get_resv_regions(dev, head); } static const struct iommu_ops apple_dart_iommu_ops = { diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c index d644b0502ef48e..5a828c92cd38b2 100644 --- a/drivers/iommu/dma-iommu.c +++ b/drivers/iommu/dma-iommu.c @@ -23,7 +23,7 @@ #include #include #include -#include +#include #include #include #include @@ -475,8 +475,7 @@ void iommu_dma_get_resv_regions(struct device *dev, struct list_head *list) fwspec->ids, fwspec->num_ids); } - if (dev->of_node) - of_iommu_get_resv_regions(dev, list); + of_iommu_get_resv_regions(dev, list); } EXPORT_SYMBOL(iommu_dma_get_resv_regions); diff --git a/drivers/iommu/of_iommu.c b/drivers/iommu/of_iommu.c index cf68cdebc9f318..20266a8edd5c71 100644 --- a/drivers/iommu/of_iommu.c +++ b/drivers/iommu/of_iommu.c @@ -217,6 +217,9 @@ void of_iommu_get_resv_regions(struct device *dev, struct list_head *list) struct of_phandle_iterator it; int err; + if (!dev->of_node) + return; + of_for_each_phandle(&it, err, dev->of_node, "memory-region", NULL, 0) { const __be32 *maps, *end; struct resource phys; diff --git a/drivers/iommu/virtio-iommu.c b/drivers/iommu/virtio-iommu.c index 34db37fd9675cd..b1a7b14a6c7a2f 100644 --- a/drivers/iommu/virtio-iommu.c +++ b/drivers/iommu/virtio-iommu.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -22,8 +23,6 @@ #include -#include "dma-iommu.h" - #define MSI_IOVA_BASE 0x8000000 #define MSI_IOVA_LENGTH 0x100000 @@ -969,7 +968,7 @@ static void viommu_get_resv_regions(struct device *dev, struct list_head *head) list_add_tail(&msi->list, head); } - iommu_dma_get_resv_regions(dev, head); + of_iommu_get_resv_regions(dev, head); } static struct iommu_ops viommu_ops; diff --git a/include/linux/iommu-driver.h b/include/linux/iommu-driver.h index 636b5b5f18f76f..c572620d3069b4 100644 --- a/include/linux/iommu-driver.h +++ b/include/linux/iommu-driver.h @@ -25,4 +25,13 @@ struct iommu_probe_info { int iommu_probe_device_pinf(struct iommu_probe_info *pinf); struct iommu_device *iommu_device_from_fwnode(struct fwnode_handle *fwnode); +#if IS_ENABLED(CONFIG_OF_IOMMU) +void of_iommu_get_resv_regions(struct device *dev, struct list_head *list); +#else +static inline void of_iommu_get_resv_regions(struct device *dev, + struct list_head *list) +{ +} +#endif + #endif diff --git a/include/linux/of_iommu.h b/include/linux/of_iommu.h index e61cbbe12dac6f..9d5532f2f11486 100644 --- a/include/linux/of_iommu.h +++ b/include/linux/of_iommu.h @@ -11,9 +11,6 @@ struct iommu_ops; extern int of_iommu_configure(struct device *dev, struct device_node *master_np, const u32 *id); -extern void of_iommu_get_resv_regions(struct device *dev, - struct list_head *list); - #else static inline int of_iommu_configure(struct device *dev, @@ -23,11 +20,6 @@ static inline int of_iommu_configure(struct device *dev, return -ENODEV; } -static inline void of_iommu_get_resv_regions(struct device *dev, - struct list_head *list) -{ -} - #endif /* CONFIG_OF_IOMMU */ #endif /* __OF_IOMMU_H */ From patchwork Thu Nov 30 01:10:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 13473783 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="XUtkMqgI" Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2053.outbound.protection.outlook.com [40.107.243.53]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B04F910DD; Wed, 29 Nov 2023 17:11:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=M8h+zVuDBdsEtD8H6TCgJA2MwLSAd/FjtymvxTMAqBuGb59SJb8zhULoxjPFymw/rSehI+9F97nRW90sYQl9orND7GYsSev+18N6mSFpbL4hyo9AoCDYHfrvZQrXO0h1U88QGcVw/2G8218vdEaTCv5i1px80jSALeQtnbeUk2Q3H88vwG5G0LO0FAu6o7s0nt3V0yxAC5SdGwS364wkd0HrAdKjqtJZqBZRHNLZw7uesqzKAKYw2aRTbAj2Ieo55XwT6C+JHogQqb7G/ATWBk7OF8qWkRzVwz1LQTcluBHV7JzsBiDO95gS2+jO9cvlXH3jEwuBs1hXzjo7uJ0WIA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=fwf/8BLazV78Ujjm7q8f4RCgFTKfbzZbel/RjT7b+os=; b=DTpFkSYFrAF65h7jTbnVQ4ztMHgT/lA6WKdxLpLCU27OwAo5qKbaeqk6SZzi4vFvpCXYgBR9Q8ZHQCWzl13XCc+3DZeKee6Y//PLgpGgfstRV6S1IXk4598LaAjIvltNSH5KnBRIGN4HEysDYU/xbvd4bTOrnBQ9Dst1/8FVMG+gAscXvoaDFipPgC+KKC+AcPBoLaqgTr9cnOw6SnBPFMpnGk0p8qOW3q8vQtXXI5fpYQl9Hizp5KPfeWl3EjeBxW5skw5ScMprHZzXFIv11Ut/DbGTyaW5jk8iLwEmFsKWCUxyL2Rji+I4s9N6a/lZEIR0l7VDpM2bW7o/Ub3Bzg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=fwf/8BLazV78Ujjm7q8f4RCgFTKfbzZbel/RjT7b+os=; b=XUtkMqgIGrf6ZOF3tXgS5FIQKR92exTcBtJzon6HxXDyLHQEWjyPB8XRh9c0wR1fr0ut4L2lW5IUwH4HEicNey7hsZel1YQxgWV7XgL4JwMloeI+L8SrGlJ4JBuGhMGIjmJLTfXiHsOJnCTfYPEf+h/1v1Hp71XFzqYl4T6IJe0A9KRDucrrFS9DHo61m8US4ZgPjVhGzLLJMPjCs4zgBhbR8rqJ4D4m5Q1+vKywoUMzrf0HVIDQPuyzfQtbpOUs2aTii23iUU1AIsNpoBBkQWj6Xd0wFY47k6rc6DP6fwf4fjweH4/8RKcSWHZzZgCb786HCs2HFl/3BQNUkvyGqw== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by PH0PR12MB5484.namprd12.prod.outlook.com (2603:10b6:510:eb::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.24; Thu, 30 Nov 2023 01:10:54 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.7046.015; Thu, 30 Nov 2023 01:10:54 +0000 From: Jason Gunthorpe To: acpica-devel@lists.linux.dev, Andy Gross , Alim Akhtar , Alyssa Rosenzweig , Bjorn Andersson , AngeloGioacchino Del Regno , asahi@lists.linux.dev, Baolin Wang , devicetree@vger.kernel.org, Frank Rowand , Hanjun Guo , "Gustavo A. R. Silva" , Heiko Stuebner , iommu@lists.linux.dev, Jean-Philippe Brucker , Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kees Cook , Konrad Dybcio , Krzysztof Kozlowski , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Lorenzo Pieralisi , Marek Szyprowski , Hector Martin , Matthias Brugger , Orson Zhai , "Rafael J. Wysocki" , Rob Clark , Robert Moore , Rob Herring , Robin Murphy , Samuel Holland , Sudeep Holla , Sven Peter , Thierry Reding , Krishna Reddy , virtualization@lists.linux.dev, Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: =?utf-8?q?Andr=C3=A9_Draszik?= , patches@lists.linux.dev Subject: [PATCH 08/30] iommu/of: Add iommu_of_get_single_iommu() Date: Wed, 29 Nov 2023 21:10:15 -0400 Message-ID: <8-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> In-Reply-To: <0-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> References: X-ClientProxiedBy: SA0PR13CA0001.namprd13.prod.outlook.com (2603:10b6:806:130::6) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|PH0PR12MB5484:EE_ X-MS-Office365-Filtering-Correlation-Id: 2af03d14-c665-4974-408c-08dbf1412c44 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: /p7yVX5PvhbJhf+jSbA+Lp4ito6qpWC6FnoepOt4fRU5t47ibWxL7mKVhMdvVdnpoEZ4tvcCMBBuwCovgUZ0f6yy6UubmKuhDDnkNcRDIz8fBGQRIEBUoXGtJJt9xLQSux0Ibc28YJGlgt6xPc2xj/xfnJwO7jh2kozedCunqXH5SgULqr6ZiSMgsi8mmeXqJWa+sCWdCWjfa5FR+CPAgQ/S49LH1DSUD/dPBc3r1PbOtCJKjh7DDnpcTHXzPYibyp5OqSJzrrc4PhMdEpzHPL2PBwYMDSuSTtc0T1Kk/zzfBXBU3CL5SQpJJdqBDkwonZkDNbPQq46VIL1Hb0fH3XXWtggoNkuj18bsoy0djpaFs8/yt9DnDfMkw3Iwiwes/K0t76HydzDO1YD0aT6bG/2p+RmgS3SAvCieMkfwPq1JqO+851N8UfIj7wtrtfEoa3B1i62FZyyCL4PWPGHK+L3d78IaclUK6xpwnonmACW4K+ElAx6qcbe1VbI9aMkWGD3RJr1CteN/NLoyfmecgiHSbISPZJOtEgociMYJJrb9SVji974A6yLlEM6aRn4iK+FsCQu8XQv/mBOfDAoCk3o7LJ8qSBjL8SkpWwQfikkLSF/POblBw5gQJLTuaeY355WH64D54M9TbbnogTDG1YDY8sgaLvFfZh0GIpUKF5A= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:LV2PR12MB5869.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(366004)(346002)(136003)(396003)(39860400002)(376002)(230922051799003)(451199024)(1800799012)(186009)(64100799003)(1191002)(8936002)(110136005)(8676002)(316002)(66556008)(4326008)(86362001)(66476007)(6486002)(478600001)(66946007)(41300700001)(36756003)(921008)(7416002)(7366002)(2906002)(7406005)(5660300002)(38100700002)(2616005)(6512007)(6506007)(6666004)(83380400001)(26005)(202311291699003)(4216001);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: QCwBEix9KdHo9LRLkFEksaEnE1WvxAmGv8Vwjg+oX8rpqxnYUNmOHHKN7ILgSBK8kxGJLoT7nh5SJUq1WgXeFsrNQT1O5Jpp2jYvOAwlmyhb2oRxaEc7JGZ/szraGxa4XFHHdvih4kGr3zs5C5jDKRVuFX2RF8/WWqWJJa78ofIqnItMakLoWDAqPs/8NfwCkTGv7UF0zbrntBJNzsYwxmTdl62V+SxDBx1pOQbhKDIougJp8nUMduriGDcKlpkwhZIZs3UlafUgJgrBgTMBIteOb2E2mvBww29l6oxaAmNOOYQ0a6o52wR/FzfoLzze9PgInnbEPYcoAcW0/TWsW2ffbMpbRGFx6NwbmgaRW8Q6Gthmt+JL1ofKxDTlh9J1ON8q30trpwA97USMPKki5HV0d5RAk0XQtKIFNUF5H/KUk3g2MqSG8wi2OSVX6j/uJshVgPdt1LwdClpa4RrleDD/BOs8vOakTS7lIcspopO8ONkBXwki2GDQ0tV9QJxwlUkzZaqh2NaCZwqxTLDK43U/5a++kEpSO8y9zS5bOST43bxMyNBeRYlgdTiQcF8R46BKub8AUK1rNFeckhYyvWqbOhVaiU3Nu9USjkoUI3TVKcYkEurbTqn7pcYhdsj3jVU14U9IJuxKreunOBx3ukKw4s2zhSUPA+ELJ+aBbtfxOX37Tcd1Of3pge3aYt/5c/2F68FPfxXpiv25Jj2eK3/0DMXqGNFpqDElV60E1dF/lV3HiGh9DN2d6xGMDlSmdBnAIMk9Zkd7bHLbnybYltUcgVQ2gkRba1W5TniN9lruGB17YGtgljrE1QJ7SQU5TNJBEe78GAKZ3rtba/p9BHmiYHK66UITBfkFPK2Wrsq17rBEB28lshRb08i9F7OYCkI5EQPjt2qcIZb0m04GFKFYdSx8bKXZ5kXsM7nNhNv1noCbKl5ivgpRS+ppHtN+9CwJpgGhXLg9QEra0iS46pEuG+VutDMPnBgpQU/3U/JcJnv+tAD+U2VmLGamJmu6u55vBR6D7TzdEmu984czixNe/9w8SkWIXEn2twIQTlNSk+dRi28hXN7HOmbxulLkx21utdxfu9F8Gwu3b1s7fQeeBwQCYoOZKptT4GvwrNwjoSE11adzSXvOTF1iemvUzjyNL0KKtGYjja9qLoSUZ1rn5ojrD756zQKFFlbJw2SwTSq6cpkM7PNro/zGhVxbhpyAG7D2sOxo2KQaOMsM9a8CrgjHV1OVaz6p45790y5QGmmNuklwPxOBUXWw0biQzI5P5oOPazXda+bUIRgNCXdLvIKhpTSpOJ34o2CfbhUQYmuBjumFN37hpLt9RkpZoej4+gGNoGZHuF/q25VFdET7/e/F0v58Wxx3PKs4QxHJGUup/bRznmrtiLNOh47htWo0k6cOUMxceiVXzEnhpZwOr56g7stforgZFK5kFWmqRs1Qk7EtHrBxOh36OMcQp1AVOPVa5jKmihDx3rE5+dS4MJnN73z18Y1eIXHb9cFaCT2CkMhRqdA+SqqQNeicHpK0dTrvNIs9eMbmufRDj1deL9qhHSE6eqxxeVijkHJ04Gme0Ap+b0rEgm7Ne1S3 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2af03d14-c665-4974-408c-08dbf1412c44 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2023 01:10:42.2995 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: NR5cfhMwLhdbnNuFdehhk6uCBjt3FpxSFXTHhABOZa+SD093yMXE4FbPKcL1P5sg X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5484 This function can be called by drivers in their probe function to return a single iommu_device instance associated with the current probe. All drivers need a way to get the iommu_device instance the FW says the device should be using. Wrap the function with a macro that does the container_of(). The driver indicates what instances it accepts by passing in its ops. num_cells is provided to validate that the args are correctly sized. This function is all that is required by drivers that only support a single IOMMU instance and no IDs data. Driver's should follow a typical pattern in their probe_device: iommu = iommu_of_get_single_iommu(pinf, &rk_iommu_ops, -1, struct rk_iommu, iommu); if (IS_ERR(iommu)) return ERR_CAST(iommu); data = kzalloc(sizeof(*data), GFP_KERNEL); if (!data) return ERR_PTR(-ENOMEM); [..] dev_iommu_priv_set(dev, data); return &iommu->iommu; Signed-off-by: Jason Gunthorpe --- drivers/acpi/scan.c | 1 + drivers/iommu/iommu.c | 52 ++++++++++++++++++++++ drivers/iommu/of_iommu.c | 59 +++++++++++++++++++++++++ include/linux/iommu-driver.h | 85 ++++++++++++++++++++++++++++++++++++ 4 files changed, 197 insertions(+) diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c index 9c13df632aa5e0..de36299c3b75bf 100644 --- a/drivers/acpi/scan.c +++ b/drivers/acpi/scan.c @@ -1570,6 +1570,7 @@ static int acpi_iommu_configure_id(struct device *dev, const u32 *id_in) const struct iommu_ops *ops; struct iommu_probe_info pinf = { .dev = dev, + .is_dma_configure = true, }; /* Serialise to make dev->iommu stable under our potential fwspec */ diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index 45e6543748fd46..ca411ad14c1182 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -3015,6 +3015,58 @@ struct iommu_device *iommu_device_from_fwnode(struct fwnode_handle *fwnode) return NULL; } +/* + * Helper for FW interfaces to parse the fwnode into an iommu_driver. This + * caches past search results to avoid re-searching the linked list and computes + * if the FW is describing a single or multi-instance ID list. + */ +struct iommu_device * +iommu_device_from_fwnode_pinf(struct iommu_probe_info *pinf, + const struct iommu_ops *ops, + struct fwnode_handle *fwnode) +{ + struct iommu_device *iommu = pinf->cached_iommu; + + if (!pinf->num_ids) + pinf->cached_single_iommu = true; + + if (!iommu || iommu->fwnode != fwnode) { + iommu = iommu_device_from_fwnode(fwnode); + if (!iommu) + return ERR_PTR( + driver_deferred_probe_check_state(pinf->dev)); + pinf->cached_iommu = iommu; + if (pinf->num_ids) + pinf->cached_single_iommu = false; + } + + /* NULL ops is used for the -EPROBE_DEFER check, match everything */ + if (ops && iommu->ops != ops) { + if (!pinf->num_ids) + return ERR_PTR(-ENODEV); + dev_err(pinf->dev, + FW_BUG + "One device in the FW has iommu's with different Linux drivers, expecting %ps FW wants %ps.", + ops, iommu->ops); + return ERR_PTR(-EINVAL); + } + return iommu; +} + +struct iommu_device *iommu_fw_finish_get_single(struct iommu_probe_info *pinf) +{ + if (WARN_ON(!pinf->num_ids || !pinf->cached_iommu)) + return ERR_PTR(-EINVAL); + if (!pinf->cached_single_iommu) { + dev_err(pinf->dev, + FW_BUG + "The iommu driver %ps expects only one iommu instance, the FW has more.\n", + pinf->cached_iommu->ops); + return ERR_PTR(-EINVAL); + } + return pinf->cached_iommu; +} + int iommu_fwspec_init(struct device *dev, struct fwnode_handle *iommu_fwnode, const struct iommu_ops *ops) { diff --git a/drivers/iommu/of_iommu.c b/drivers/iommu/of_iommu.c index 20266a8edd5c71..37af32a6bc84e5 100644 --- a/drivers/iommu/of_iommu.c +++ b/drivers/iommu/of_iommu.c @@ -138,6 +138,9 @@ int of_iommu_configure(struct device *dev, struct device_node *master_np, { struct iommu_probe_info pinf = { .dev = dev, + .of_master_np = master_np, + .of_map_id = id, + .is_dma_configure = true, }; struct iommu_fwspec *fwspec; int err; @@ -277,3 +280,59 @@ void of_iommu_get_resv_regions(struct device *dev, struct list_head *list) #endif } EXPORT_SYMBOL(of_iommu_get_resv_regions); + +struct parse_info { + struct iommu_probe_info *pinf; + const struct iommu_ops *ops; + int num_cells; +}; + +static struct iommu_device *parse_iommu(struct parse_info *info, + struct of_phandle_args *iommu_spec) +{ + if (!of_device_is_available(iommu_spec->np)) + return ERR_PTR(-ENODEV); + + if (info->num_cells != -1 && iommu_spec->args_count != info->num_cells) { + dev_err(info->pinf->dev, + FW_BUG + "Driver %ps expects number of cells %u but DT has %u\n", + info->ops, info->num_cells, iommu_spec->args_count); + return ERR_PTR(-EINVAL); + } + return iommu_device_from_fwnode_pinf(info->pinf, info->ops, + &iommu_spec->np->fwnode); +} + +static int parse_single_iommu(struct of_phandle_args *iommu_spec, void *_info) +{ + struct parse_info *info = _info; + struct iommu_device *iommu; + + iommu = parse_iommu(info, iommu_spec); + if (IS_ERR(iommu)) + return PTR_ERR(iommu); + info->pinf->num_ids++; + return 0; +} + +struct iommu_device *__iommu_of_get_single_iommu(struct iommu_probe_info *pinf, + const struct iommu_ops *ops, + int num_cells) +{ + struct parse_info info = { .pinf = pinf, + .ops = ops, + .num_cells = num_cells }; + int err; + + if (!pinf->is_dma_configure || !pinf->of_master_np) + return ERR_PTR(-ENODEV); + + iommu_fw_clear_cache(pinf); + err = of_iommu_for_each_id(pinf->dev, pinf->of_master_np, + pinf->of_map_id, parse_single_iommu, &info); + if (err) + return ERR_PTR(err); + return iommu_fw_finish_get_single(pinf); +} +EXPORT_SYMBOL_GPL(__iommu_of_get_single_iommu); diff --git a/include/linux/iommu-driver.h b/include/linux/iommu-driver.h index c572620d3069b4..597998a62b0dd6 100644 --- a/include/linux/iommu-driver.h +++ b/include/linux/iommu-driver.h @@ -13,25 +13,110 @@ #endif #include +#include +#include +struct of_phandle_args; struct fwnode_handle; +struct iommu_device; +struct iommu_ops; + +/* + * FIXME this is sort of like container_of_safe() that was removed, do we want + * to put it in the common header? + */ +#define container_of_err(ptr, type, member) \ + ({ \ + void *__mptr = (void *)(ptr); \ + \ + (offsetof(type, member) != 0 && IS_ERR(__mptr)) ? \ + (type *)ERR_CAST(__mptr) : \ + container_of(ptr, type, member); \ + }) struct iommu_probe_info { struct device *dev; struct list_head *deferred_group_list; + struct iommu_device *cached_iommu; + struct device_node *of_master_np; + const u32 *of_map_id; + unsigned int num_ids; bool defer_setup : 1; + bool is_dma_configure : 1; + bool cached_single_iommu : 1; }; +static inline void iommu_fw_clear_cache(struct iommu_probe_info *pinf) +{ + pinf->num_ids = 0; + pinf->cached_single_iommu = true; +} + int iommu_probe_device_pinf(struct iommu_probe_info *pinf); struct iommu_device *iommu_device_from_fwnode(struct fwnode_handle *fwnode); +struct iommu_device * +iommu_device_from_fwnode_pinf(struct iommu_probe_info *pinf, + const struct iommu_ops *ops, + struct fwnode_handle *fwnode); +struct iommu_device *iommu_fw_finish_get_single(struct iommu_probe_info *pinf); #if IS_ENABLED(CONFIG_OF_IOMMU) void of_iommu_get_resv_regions(struct device *dev, struct list_head *list); + +struct iommu_device *__iommu_of_get_single_iommu(struct iommu_probe_info *pinf, + const struct iommu_ops *ops, + int num_cells); #else static inline void of_iommu_get_resv_regions(struct device *dev, struct list_head *list) { } +static inline +struct iommu_device *__iommu_of_get_single_iommu(struct iommu_probe_info *pinf, + const struct iommu_ops *ops, + int num_cells) +{ + return ERR_PTR(-ENODEV); +} #endif +/** + * iommu_of_get_single_iommu - Return the driver's iommu instance + * @pinf: The iommu_probe_info + * @ops: The ops the iommu instance must have + * @num_cells: #iommu-cells value to enforce, -1 is no check + * @drv_struct: The driver struct containing the struct iommu_device + * @member: The name of the iommu_device member + * + * Parse the OF table describing the iommus and return a pointer to the driver's + * iommu_device struct that the OF table points to. Check that the OF table is + * well formed with a single iommu for all the entries and that the table refers + * to this iommu driver. Integrates a container_of() to simplify all users. + */ +#define iommu_of_get_single_iommu(pinf, ops, num_cells, drv_struct, member) \ + container_of_err(__iommu_of_get_single_iommu(pinf, ops, num_cells), \ + drv_struct, member) + +/** + * iommu_of_num_ids - Return the number of iommu associations the FW has + * @pinf: The iommu_probe_info + * + * For drivers using iommu_of_get_single_iommu() this will return the number + * of ids associated with the iommu instance. For other cases this will return + * the sum of all ids across all instances. Returns >= 1. + */ +static inline unsigned int iommu_of_num_ids(struct iommu_probe_info *pinf) +{ + return pinf->num_ids; +} + +/* + * Used temporarily to indicate drivers that have moved to the new probe method. + */ +static inline int iommu_dummy_of_xlate(struct device *dev, + struct of_phandle_args *args) +{ + return 0; +} + #endif From patchwork Thu Nov 30 01:10:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 13473767 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="bt72uduo" Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2053.outbound.protection.outlook.com [40.107.243.53]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CD75E10D7; Wed, 29 Nov 2023 17:10:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=EHviIIoeYGnFvTiRuP4hmMzCpBC1erusmHD//dURo3osiQ0nIWcAKYj9QktHk8QAD2528PE6Iaxr0rh9kusTlu3cBF8VFa59X3Wj42yihuiNCwpWbW6W130YmiWjCyJeiEqFYehK4RJ7VPUoYTybGq54JsezFl2Uy3GwyvtkZNSyDdbiSKVDmzka53QMJ/HpXaephtgKiHH984q/H4snhUys/o20JceuJuzLb6ulbknWu48dUiTjtbWWTtclouSu9sIPcmTtfVrVaRJAh9S3xE2L55WiruJhYGLJ+kXULIQAecnXF1hUTVNa/jnPxJrYmZh+SG10g8DQBH5V5Ly68g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=pH0gW84gOXxliY71EzUBCEAqil4815K+q+c+KD8Jig0=; b=grpc2QHgqMoqmavTtArDjqOThLx6m0b+fwvSpt11L5rBUQ8m1b8/GVNTbYKtmE6mPpFengzd+x5wQdW9h6kVe11lj602EQ4Ob8e8FqHJTRiv+XBttyFoCRC0hvs2D4eH944nijo6/aY6SAUHdPXGDsd7fRpoBZ82QKHsS4dDNdtvMMkAsOKe17dj+j1cCXYmpZh/njJxZqoWaPq6OycqUQMq4BVt99lCuwu0wgmCgEvwul8HxYE2GFiGYXJWrgJ8W9ct+C/U3XLWARtDPQdnj/OU9On9inFcXVWWT+QTKR+FK2sRHC1WdzX7+Jgm1F8L25R+XspdXz+hJQiP2ZzsZw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=pH0gW84gOXxliY71EzUBCEAqil4815K+q+c+KD8Jig0=; b=bt72uduozeMkhtIrVviUsicUctr6C6o5YJ0GvT3SQhYkQAZN+9Sz3IVs7fJ0MsiXt8wQ0+PGWpczdvbt92fHpO8F1JMaivnwyVFT5dGfxCHUNPPvL3tcQQjP4MIhuJvKKNLdPcxUtaHKUGbL4KJxSk1PKnBfD18lweBTSV2MSIzwmdLycn0lo9RagI5nHtZQB24eZzsnfYINr8I2YVMqhSnT8Ua36PUdIU7XZCtAnfcoikbWOSWPKEBNY2WC/dMR7nEqoXKOC1et/tsDB4zwGwSZ1kOdDIYf6LsGYruWtiwurhiyLOnKOBI+f4+XsgTlmErQrA/bnOnzpLkMYWLfaQ== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by PH0PR12MB5484.namprd12.prod.outlook.com (2603:10b6:510:eb::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.24; Thu, 30 Nov 2023 01:10:47 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.7046.015; Thu, 30 Nov 2023 01:10:47 +0000 From: Jason Gunthorpe To: acpica-devel@lists.linux.dev, Andy Gross , Alim Akhtar , Alyssa Rosenzweig , Bjorn Andersson , AngeloGioacchino Del Regno , asahi@lists.linux.dev, Baolin Wang , devicetree@vger.kernel.org, Frank Rowand , Hanjun Guo , "Gustavo A. R. Silva" , Heiko Stuebner , iommu@lists.linux.dev, Jean-Philippe Brucker , Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kees Cook , Konrad Dybcio , Krzysztof Kozlowski , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Lorenzo Pieralisi , Marek Szyprowski , Hector Martin , Matthias Brugger , Orson Zhai , "Rafael J. Wysocki" , Rob Clark , Robert Moore , Rob Herring , Robin Murphy , Samuel Holland , Sudeep Holla , Sven Peter , Thierry Reding , Krishna Reddy , virtualization@lists.linux.dev, Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: =?utf-8?q?Andr=C3=A9_Draszik?= , patches@lists.linux.dev Subject: [PATCH 09/30] iommu/rockchip: Move to iommu_of_get_single_iommu() Date: Wed, 29 Nov 2023 21:10:16 -0400 Message-ID: <9-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> In-Reply-To: <0-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> References: X-ClientProxiedBy: SN6PR16CA0043.namprd16.prod.outlook.com (2603:10b6:805:ca::20) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|PH0PR12MB5484:EE_ X-MS-Office365-Filtering-Correlation-Id: fc7ed155-37f1-4855-5c7a-08dbf1412b4e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: umO1ddYmJzHiPe/jglh3QVymxKzgOl3MVjcBhSWQDjWMRKWR8HZVwrI79C7ISCJr9SqH/28vyXDldPiqHoxK4wjKpDqIRfITgrO1HNCUqi+cqE3NfriRJMPlCMD737cdyI2IywQiD2HW2l3RV06Axv5ENsUPcDtd7WeW+PRLqh0p4Nyj9tMR5O+U/kK3lfsVhijwxxPkdyxR6FByxCIN6XssDr1ncHGfbXl+fvaiyBwVQGWCYvzBcJ4EH3og85kOP6+YebkGlapaQNdMEWDR5fUine7h0o57M8K+ZTYLHBJN3tSlX0S5qlvIfQXBmptAjdqq76AXo+if7d1cXg/Vi1F2AmIRlwvgNEO/Vbxi/byaz9tfWho0USuyrmtjec0a8Cu6tbCRAOm/cBZRAgUaIrzgkA/iCyy9NtHqunAVHrE0XsEXfhUj8OzKPrY6z85T6BYeJJFyAeXTuzAUR2fMPieYLQDs2kqEjay3aW0cV3rgNDDdapLoHCY6UnDIJV9EUyOHbKNPHChT2S/rUdFuR7b0aTjrXaghzPn4wGtyUS8i6fKHUiy6ZDX4BoT8zGcKvjierkteLZ9f8wpmxqG49KIf1byjgxkK8cQD7QtFttKijq/LkAW6mjLVdhWMGOCW/6Jh6gpuEmpOpDGc8pOav6AnI+iJvTCV6sNT467zjMs= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:LV2PR12MB5869.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(366004)(346002)(136003)(396003)(39860400002)(376002)(230922051799003)(451199024)(1800799012)(186009)(64100799003)(1191002)(8936002)(110136005)(8676002)(316002)(66556008)(4326008)(86362001)(66476007)(6486002)(478600001)(66946007)(41300700001)(36756003)(921008)(7416002)(7366002)(2906002)(7406005)(5660300002)(38100700002)(2616005)(6512007)(6506007)(6666004)(83380400001)(26005)(202311291699003)(4216001);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: RvweIR4IeBPVT59G+mnbsZU6UEVqLrPN3J6FlzJYjO7J+iz1H9Ah/TTZnpLVbzzXdnsYfu73hOvVyIhyFFy2Y9iAVTmQOGBNtfiNqHatKLecwWkvRnGucJYl6ayVdDsEhu6c09vb6JX0jl/6ylYdM5BnKZHVZMExj+31UkSpqyN2FuU5uT2Xr90Ueo0jXA2Z03kTEU8ch32Daa+DHzVEBQgRavFpjPYfxw5GRN2DMKctlHfmDFTmqw1mRmxXrKmQxuow1xsXgnt6IVv2HLHLfEV6J5u1iWc3eX0RFwewgApDZKmbxceJxhnuc0WMwnkzRKtis8NmuvwPf0/iTYocY1FXnBQMmQZVDu1YYw0bgiWqcbhhxouju/phOCCPrif2M0x8xucKxsDN1fjHrSKbJIrsyfaPlYahaJAdhgdvt0N+bbbSCcud2mG3QNAxEyZZiJ4aL184Yk4Zd88dgS6DA6T9o2uGWdhQLG/bOKomviLNB5exuz9DaGsBlXCQs7430xqlvDvrGsZ1/mQ1zoqyunFnNfny8Kou2tXkB3/vYaQ4/qTYAVWVuWsF+QGKpktcPneGCR5n7RGeeB4xV1Yh1m4b9hz5c23dJhHEA5a7RqEWhMMm2GNBSKL+tczXWR7OJYloObO47zOY3IBp+qWaoIXXLAmE7e7yqh1h+lVJUgGWuF35ywfY+uhqb/44D8xTB/TnYBIE4yoeiq1AjP9XQzew3lYb47TrHhWG7a57SHpabRxwdHJzlLFsCp6qWdS7TTjMYgp3Mb5TiYlRclucUXccEh/OhDKbShwAgWkBcCO6R4OCxIwWsSdVhYtaUiBkwAoGZY1sb0fD0Bq9TpDj7oyB4j6Nkm1uCcdbtCaz9GNCAOGCKHmogx610igV0IfQfp8uknMZkaDo6EcP4BHPC0/jdpMfRNgvvgMwSyqAwJQj/v7JQXXQ1l19Fp8hOKI/hYJMhq0+B3t4WbpGYuKWyrOEtTzE7hNq1vUJeLfVejwY710Xd4mb2UZrmrZyL+e35o8YcnGMnCwakua1HE94aRpW0sTilCvXyoTZGMkFmJXMUvTF7YJ2nYBRnzgeGrgcmaKpbL3tqtPt1HtwwNPnOyR7e1sFaip6WXk84n9Ci5NiYzdpKxo5ycWSzfSmeVlfe7p+yaYLSWVmH5/0GKCH+Td3zX2OXiEc4yK0DBYRQNfPww5KCYBUfMPTn+jTaGAjyXunmxpKxKVL8qkexOOVeEIOrp9RhbO0qRfnjH2yuZaEL2Ex85uF1huZMYmdsAym1TA5/HArddMm8fheg5PcwfD23SIPODEvBaumCKG2tTTFWcCdcCZ6B/BVKf0yXNzelhSF1EUIPbM3a1VaRWG1jK9wY12IIqkypXGcsARUQ8cBzBvRpn3OnspuU7z4+nV0P7vklV94icGGoExM5hxz/RShanrOe5mUGc8dt1fPi/77DPNR8ksydGyBX/CSpVWg+KLHtR/u++VBpfPB95h/3vBI9iMbswdR4273IB0fw9RKasdHtw+MqMsJjdI0idrWTtSQIdXIqD5yz+7fuL9KptqecViBCNaE4iZQwJTPGd8D5aTKbWX3FPdzKxCVvKbl X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: fc7ed155-37f1-4855-5c7a-08dbf1412b4e X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2023 01:10:40.7378 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: PVtzl/qCMXCu7rm7n3eTwSdj/9QrQ5oeVSrwEHZuO+Yjour4vrdh6fDtSjtcF5io X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5484 rockchip supports a single iommu instance and does not support multiple IDs. Move the per-device allocation from rk_iommu_of_xlate() and completely delete rk_iommu_of_xlate(). The iommu instance is obtained via iommu_of_get_single_iommu(). Don't use devm to manage the lifetime of the per-device data, this just results in memory leaking if there are probe error/retry paths. Use the normal lifecycle with alloc in probe_device and free in release_device. The comment about "virtual devices" seems out of date. With today's code the core will not call attach_device/detach_device unless dev->iommu is set and has an ops. This can only happen if probe_device was done. Remove the checks. Signed-off-by: Jason Gunthorpe --- drivers/iommu/rockchip-iommu.c | 74 +++++++++++----------------------- 1 file changed, 24 insertions(+), 50 deletions(-) diff --git a/drivers/iommu/rockchip-iommu.c b/drivers/iommu/rockchip-iommu.c index 2685861c0a1262..4cff06a2a24f74 100644 --- a/drivers/iommu/rockchip-iommu.c +++ b/drivers/iommu/rockchip-iommu.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -123,6 +124,7 @@ struct rk_iommudata { static struct device *dma_dev; static const struct rk_iommu_ops *rk_ops; static struct iommu_domain rk_identity_domain; +static const struct iommu_ops rk_iommu_ops; static inline void rk_table_flush(struct rk_iommu_domain *dom, dma_addr_t dma, unsigned int count) @@ -896,13 +898,6 @@ static size_t rk_iommu_unmap(struct iommu_domain *domain, unsigned long _iova, return unmap_size; } -static struct rk_iommu *rk_iommu_from_dev(struct device *dev) -{ - struct rk_iommudata *data = dev_iommu_priv_get(dev); - - return data ? data->iommu : NULL; -} - /* Must be called with iommu powered on and attached */ static void rk_iommu_disable(struct rk_iommu *iommu) { @@ -958,16 +953,12 @@ static int rk_iommu_enable(struct rk_iommu *iommu) static int rk_iommu_identity_attach(struct iommu_domain *identity_domain, struct device *dev) { - struct rk_iommu *iommu; + struct rk_iommudata *data = dev_iommu_priv_get(dev); + struct rk_iommu *iommu = data->iommu; struct rk_iommu_domain *rk_domain; unsigned long flags; int ret; - /* Allow 'virtual devices' (eg drm) to detach from domain */ - iommu = rk_iommu_from_dev(dev); - if (!iommu) - return -ENODEV; - rk_domain = to_rk_domain(iommu->domain); dev_dbg(dev, "Detaching from iommu domain\n"); @@ -1003,19 +994,12 @@ static struct iommu_domain rk_identity_domain = { static int rk_iommu_attach_device(struct iommu_domain *domain, struct device *dev) { - struct rk_iommu *iommu; + struct rk_iommudata *data = dev_iommu_priv_get(dev); + struct rk_iommu *iommu = data->iommu; struct rk_iommu_domain *rk_domain = to_rk_domain(domain); unsigned long flags; int ret; - /* - * Allow 'virtual devices' (e.g., drm) to attach to domain. - * Such a device does not belong to an iommu group. - */ - iommu = rk_iommu_from_dev(dev); - if (!iommu) - return 0; - dev_dbg(dev, "Attaching to iommu domain\n"); /* iommu already attached */ @@ -1115,20 +1099,30 @@ static void rk_iommu_domain_free(struct iommu_domain *domain) kfree(rk_domain); } -static struct iommu_device *rk_iommu_probe_device(struct device *dev) +static struct iommu_device *rk_iommu_probe_device(struct iommu_probe_info *pinf) { + struct device *dev = pinf->dev; struct rk_iommudata *data; struct rk_iommu *iommu; - data = dev_iommu_priv_get(dev); - if (!data) - return ERR_PTR(-ENODEV); + iommu = iommu_of_get_single_iommu(pinf, &rk_iommu_ops, -1, + struct rk_iommu, iommu); + if (IS_ERR(iommu)) + return ERR_CAST(iommu); + if (iommu_of_num_ids(pinf) != 1) + return ERR_PTR(-EINVAL); - iommu = rk_iommu_from_dev(dev); + data = kzalloc(sizeof(*data), GFP_KERNEL); + if (!data) + return ERR_PTR(-ENOMEM); + data->iommu = iommu; + data->iommu->domain = &rk_identity_domain; data->link = device_link_add(dev, iommu->dev, DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME); + dev_iommu_priv_set(dev, data); + return &iommu->iommu; } @@ -1137,37 +1131,17 @@ static void rk_iommu_release_device(struct device *dev) struct rk_iommudata *data = dev_iommu_priv_get(dev); device_link_del(data->link); -} - -static int rk_iommu_of_xlate(struct device *dev, - struct of_phandle_args *args) -{ - struct platform_device *iommu_dev; - struct rk_iommudata *data; - - data = devm_kzalloc(dma_dev, sizeof(*data), GFP_KERNEL); - if (!data) - return -ENOMEM; - - iommu_dev = of_find_device_by_node(args->np); - - data->iommu = platform_get_drvdata(iommu_dev); - data->iommu->domain = &rk_identity_domain; - dev_iommu_priv_set(dev, data); - - platform_device_put(iommu_dev); - - return 0; + kfree(data); } static const struct iommu_ops rk_iommu_ops = { .identity_domain = &rk_identity_domain, .domain_alloc_paging = rk_iommu_domain_alloc_paging, - .probe_device = rk_iommu_probe_device, + .probe_device_pinf = rk_iommu_probe_device, .release_device = rk_iommu_release_device, .device_group = generic_single_device_group, .pgsize_bitmap = RK_IOMMU_PGSIZE_BITMAP, - .of_xlate = rk_iommu_of_xlate, + .of_xlate = iommu_dummy_of_xlate, .default_domain_ops = &(const struct iommu_domain_ops) { .attach_dev = rk_iommu_attach_device, .map_pages = rk_iommu_map, From patchwork Thu Nov 30 01:10:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 13473763 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="GrHVtnkN" Received: from NAM04-BN8-obe.outbound.protection.outlook.com (mail-bn8nam04on2053.outbound.protection.outlook.com [40.107.100.53]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5F0EED7F; Wed, 29 Nov 2023 17:10:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Ph6Y0TDGKfYsXDdQSmbALLvMUMKS+Cn/AQ9CxmrCBemkMPo94kuZ4aD2TIDp6wieURJKWCLPGcl+pW2Np349cNP4NjhU0BvP/hhNPgP65H9aAiPJbKpws7X5u2GJUoq4j/Tvc7/UO28rw7OKc1+f9/0JZYlOCo4tyoImoWydZouh9tAnMxR5f8uzcFJutRh5L0GAOUkwSAcdSfumBQRxIi98THjpGffPOhNYFwqYkzcSrnOLnHkAzTVhTxIvswVT6wXVAjOAvbXmVTvCd4HOxymggJUyhAVEy7Ljy+ebP5bWiJzUoUVTT5xVeeoVxJNsGqu+RzZnv69cZopE0zlT/w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=jXjpmP7B5IXGBNr1m7J/QuIsLVIPvAV2ilVtcRlro38=; b=a7MaYNd2k1apltwaLBv2Dp9bbri47KvSoAvDT6r+ZDElO8PLoD6W1gwFUG4f2uGu8ASfh1yTPH3MFM7+mjpK+LEzQW7hTtGdveaGI3F8GL9X75VDH7JPQRrJUDTLygephqR8BuePPeFBUxHju+2feVigBZTXmAtrf3A4W4StEzNk17qta90Qx0v2ef6DSN2TBx+Vq52Bn7C2hhN6J97Vru5Ay94nG85octFN67Y62pUaHqgxZd4gTn2GFfQP1iuZ8kKx9qNNUpHzQvVxFNMViv7LY/WUhjh9RDAHhrOF5l5A4R9iQvHJXdQHcktry7JFpo4Q1zGDO0IwveaCiRP65A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=jXjpmP7B5IXGBNr1m7J/QuIsLVIPvAV2ilVtcRlro38=; b=GrHVtnkNkesZP7N37XdbYLMO92J0aXq1ByvSk9FZFfawvdsHozrADXtV9h6xhjFzhiWImFTpFGIwl2hFYmZu1m0qIZFfeTt8Dom3oce/uFb538QsNZtJa44asfBg8jNIA66Gc2Dt3dOhEPliO1v7G1SgXzfGsXw8SiIBNf40ZnSwar5r9Na1pvHnHcqf9JnaT2XJywr6QPuWJG8F/DAEAqmHuE0L3dbtbkYBTGkLyAvJbg+E1Wo03xtPwkcjZM89IEdlPCjy/KKJwu5ICzcQ5TFVOuy83b221Zo0Jwo4gffjOPzet51STQwuD5NutSrMnkHbsbrGCZSnsVwKyYIe7Q== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by DS0PR12MB7607.namprd12.prod.outlook.com (2603:10b6:8:13f::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.22; Thu, 30 Nov 2023 01:10:43 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.7046.015; Thu, 30 Nov 2023 01:10:43 +0000 From: Jason Gunthorpe To: acpica-devel@lists.linux.dev, Andy Gross , Alim Akhtar , Alyssa Rosenzweig , Bjorn Andersson , AngeloGioacchino Del Regno , asahi@lists.linux.dev, Baolin Wang , devicetree@vger.kernel.org, Frank Rowand , Hanjun Guo , "Gustavo A. R. Silva" , Heiko Stuebner , iommu@lists.linux.dev, Jean-Philippe Brucker , Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kees Cook , Konrad Dybcio , Krzysztof Kozlowski , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Lorenzo Pieralisi , Marek Szyprowski , Hector Martin , Matthias Brugger , Orson Zhai , "Rafael J. Wysocki" , Rob Clark , Robert Moore , Rob Herring , Robin Murphy , Samuel Holland , Sudeep Holla , Sven Peter , Thierry Reding , Krishna Reddy , virtualization@lists.linux.dev, Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: =?utf-8?q?Andr=C3=A9_Draszik?= , patches@lists.linux.dev Subject: [PATCH 10/30] iommu/sprd: Move to iommu_of_get_single_iommu() Date: Wed, 29 Nov 2023 21:10:17 -0400 Message-ID: <10-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> In-Reply-To: <0-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> References: X-ClientProxiedBy: SN1PR12CA0079.namprd12.prod.outlook.com (2603:10b6:802:21::14) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|DS0PR12MB7607:EE_ X-MS-Office365-Filtering-Correlation-Id: 14aed4a1-bf58-47eb-12ad-08dbf1412b13 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: W5Nxve/hqSj2fuhMm2GUE8Ugqq65w6lrhvAxJlDuYQAoascTZndUawxgYmMzPHUTROjaxA17hQEA1WAPy+gO1UeMF1jbAXKWgYt2iqL9YM6PyhRidYbqWuw0SXYp5rrrekwfvsduFWkgME8qJ8L2B6hZViLqSHqyBJzIkqRIHXGcGG8UqHIiXZeJdhq0S/ZiTbfdXC6UeZ4HcMXitUVnf2+RpEkQO9ZtW4Omer9YmPz26v4eZHDaVhkk1ZCq/YOt0JGDxQSpNNZKDnnm1QmPaPhjajk4x9R500US9vnR6Bk7e+z3DRo+sZyjfISmuxrLSUIxcGkpgPu0gY5OSRcDTV0/lU2MCJuQASBxx5ZxIGiAvXAJDgL9jmoAAFgwyBfVoTxS65dkMzhuelOVPoMe1nzSq8HWy1bVuDPYyhnTsEhKtvA+ICAI4GiwZ6yhBsAszJzHJyUoAInLT03gQRbzo8Uh8oz5bkxxEwc0lix2/WNL00WryIpk2SfjSCwPMmLMeQ2VsHcZ+4FyjJ0lZ7K8lEsqdhfU5pvYEMTRRen8dPhOFV2IxXRVI7tuHM/5AZxrhMlCV2np7AD/VRIzrd5NFMgaRrJHpmcR4iXOVU5hyb/zzRfbKPnOv1xAoLtjr02ZYpYx2ZrTLhd4jwPWuULtyQ== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:LV2PR12MB5869.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(396003)(39860400002)(346002)(136003)(366004)(376002)(230922051799003)(186009)(451199024)(64100799003)(1800799012)(38100700002)(202311291699003)(83380400001)(1191002)(5660300002)(110136005)(2906002)(86362001)(4326008)(8676002)(8936002)(66556008)(7366002)(7406005)(7416002)(66476007)(66946007)(6486002)(478600001)(6666004)(316002)(36756003)(6506007)(41300700001)(6512007)(921008)(26005)(2616005);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 5j5KbY0xHJ94YSN0oEFEhn+lLo7j7xo7/c6H3tHrg1HpeRqz4yUGA4TZ8Y233YrbRcuowllYoHvNBVkulCaqkMi58Gsoiz+HgOEOAuyaCAgtiXJvp64j4+fc6VrfezNBuKgPTnglm++deyPCIVlBg4w3ejnuUEZWJ8zY8orQLQ8L7yPenUVDk3BaRmdv5aaxBJiD4RgQ9nGxUZGR3ESi9+U09Q8A/ucxmwSESdpmK1yAwm9aPS0EOoSJJm3ijCJ1wwVzyxw5iDGLft6D7LWsxFnyNM51Brqdxn+ROdNuWB2+tl5bGn2uNxkfEOW/n87Q6sxbDlTHaa7/Qj8teTNK3Z3vURZ6ep7Plf3BK5/Wc3ZOQLAb/IepDYWRhHOZ5Iz+KIIxdq+OlX7jpv/twzd2zlxSVOMsE5fcMs8tRCQKo2dGCVs/GqhlXJT0ltmSmLvsy7k6g+Wr44gEjDQzLs1hHhXMJURG723ilhrEWNFn00SjpXxsYkLN4AJkMlPhgKV7uIKPNtWWPvaWt3OXZIRtMqpjc3arlZbAJhUFADkBO5yg8l9gPrvNQreQ0GxT5Qd5H80nur9MwYqHkcW9LCA5cUep5W2KuXytJ2aDkxR6544c+3B1MqzMvZuSDvJr1WvFH3ky3ljJ7BXczj9OTUw9A4e1X/3FGxQwqLmdwxXnOcnUFUUp1zFVKMNXCdzOAFwmPeaMRCg+eCUvaFH8krz7geNKxcCXV2k+iME5rTDdYPP1GebTGbsI30y7FFNhQ+NmcddyY5V4wdhA/ioHoMONjrhz8Ba9tGC/EkW0qGnqWUTQvdal0frVd7b1zOoN+g92c64KIYLW252azzq6SkwzNdI2z9+NxzZOM+/IX13KzFg4TIKJWMqcYlNOtBiicijYOmda4+SfdWF9ehMUb9LmkX3ZwB+5qye030ZLU84zwhy+nSkEU+9dEpJcOnX622KlG23KAY/EkZCDzMyL+0Dvb9u5ZfZxtdYq2zJnSbX0cJP6TjgL/7czlfa/8T5BuQu7NI9YrCroiEygbECFa0W6FKK2siugg/K9sHHqpts2XVDQJr2LBnOvVTQWsFWiH8/PL/whAGzvux+9zzOBIbBkkzCERlqQ4ocUEU7JVf6mUb466rarda8fc2vtEnLs/hh8ZJFR3HPpB5+QiK24qqN2A5HIvDHRbh+awlASW5abf+NZwIEeHjk7LwsPIxJCbd2lkP/rKvO1dlEXGUansYFblkgUWBARmlTcr/WqY+Kp15dBmFx/5i+82GuVsAdkOLygWMqjxXta0Xr4H1weIQQ0rVlrpFFf9DrCAZNKu1uzZaImIaS0gOWGXrVCPpx8iCDYfXq601fIPKfNV+/3RKLM/94io/A2Tca2msLl7Om2/XDoqRSUuFl7ncHEvDvFNu6OoPNCiKX3rWpwx7P/1OzYOnrVhy0TC2zZcmbSm5zbsZw6y22HqjEkkS+gWu3UBq3H6+el0LGPBOWDnD0FwW6C4r4WAgkHsGw/4MNSEmBoHq/R4NVfcotafuKDhLVjYHJmZgFad/SbnxPrqVJqtzlf99+mhkLt22RJ6t8irn8YBrPQCLETf6EIBZpYrDbBNj// X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 14aed4a1-bf58-47eb-12ad-08dbf1412b13 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2023 01:10:40.1895 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: RImw/klw6uR5u3kIEI5FDYwuyW8PkAy+C/GVi680wwYw6hU0nSKvh/ViUO5uWBs7 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7607 sprd suports a single iommu instance and only a single id. Parse it directly using iommu_of_get_single_iommu() and remove sprd_iommu_of_xlate(). It stores the iommu, not a per-driver struct in the dev_iommu_priv(), keep it that way for now. Signed-off-by: Jason Gunthorpe --- drivers/iommu/sprd-iommu.c | 32 ++++++++++++++------------------ 1 file changed, 14 insertions(+), 18 deletions(-) diff --git a/drivers/iommu/sprd-iommu.c b/drivers/iommu/sprd-iommu.c index 537359f109979b..f1b87f8661e199 100644 --- a/drivers/iommu/sprd-iommu.c +++ b/drivers/iommu/sprd-iommu.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -383,32 +384,27 @@ static phys_addr_t sprd_iommu_iova_to_phys(struct iommu_domain *domain, return pa; } -static struct iommu_device *sprd_iommu_probe_device(struct device *dev) +static struct iommu_device *sprd_iommu_probe_device(struct iommu_probe_info *pinf) { - struct sprd_iommu_device *sdev = dev_iommu_priv_get(dev); + struct sprd_iommu_device *sdev; + + sdev = iommu_of_get_single_iommu(pinf, &sprd_iommu_ops, -1, + struct sprd_iommu_device, iommu); + if (IS_ERR(sdev)) + return ERR_CAST(sdev); + if (iommu_of_num_ids(pinf) != 1) + return ERR_PTR(-EINVAL); + + dev_iommu_priv_set(pinf->dev, sdev); return &sdev->iommu; } -static int sprd_iommu_of_xlate(struct device *dev, struct of_phandle_args *args) -{ - struct platform_device *pdev; - - if (!dev_iommu_priv_get(dev)) { - pdev = of_find_device_by_node(args->np); - dev_iommu_priv_set(dev, platform_get_drvdata(pdev)); - platform_device_put(pdev); - } - - return 0; -} - - static const struct iommu_ops sprd_iommu_ops = { .domain_alloc_paging = sprd_iommu_domain_alloc_paging, - .probe_device = sprd_iommu_probe_device, + .probe_device_pinf = sprd_iommu_probe_device, .device_group = generic_single_device_group, - .of_xlate = sprd_iommu_of_xlate, + .of_xlate = iommu_dummy_of_xlate, .pgsize_bitmap = SPRD_IOMMU_PAGE_SIZE, .owner = THIS_MODULE, .default_domain_ops = &(const struct iommu_domain_ops) { From patchwork Thu Nov 30 01:10:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 13473779 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="Oa1cpIGp" Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2053.outbound.protection.outlook.com [40.107.243.53]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DE66E10F2; Wed, 29 Nov 2023 17:11:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Nktyx9JA0I562JHDUrqi82NUMQtWGrgvwLSQzncwN6YV5QgOtmkWjH32V5fbqYVzaqXUNxXlnjD/iOyVU5O1z27fMUqjbyo+uGrRpIwLHlvxcawZiD9SoAvUIhfJyyMzUy9EepVe5o4m/6NE91SjaKeDMWSLhpgzYE4k1nJKNqyjOVjIKja52WP2Uf4Bq4fU1kvXqXvHGVXwxtGGo4VzHQ0qOI0EWGTOLRBOSBHJhGEqEcgihIz/kI8D1MCl+pkTKCZkuJxDoO+JZ9VFO323V45ZLd7mNUaPGXf1HYKT1WzVU7FUMBa/KTf/t5nXauqQ4TgS2uWtKO8WSaTDwJmPlA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=GqEzauI1AR2owm9HEl6HCb3Z9hfFMw5b5rv0EaUHXus=; b=JCHEKOTANhMjHvs+0ng51OS4jbdBPM/IEbXBYMqDrukIeNSmK9r9qK4u0KHzi6hOJiBCD4xGjtytSWoj6r5ocpQzOINiSHrXH44HGnTDuFxewcBdXqSdgrgn9Ab/kLD/hQbVoBhiEhRyjZA2NZfKwCjYJ6vNnlf3eQqgS4rt8IaABw2YtuCoYua8pbN8/BwFXP4GkcO+EPeTWA5Ek4uP53VWF7F9gEOIrvXRNPvyIh4mOfRrJq8lHAkDAZXV5yCqmS/hlq/7v7v22x0QVK2i/4S4+3EfzatzfgKFGr/Q0uRM4mIy4+XhqbfxEzkC4db7DNYIT6Sb6PKH1/HTDrXceQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=GqEzauI1AR2owm9HEl6HCb3Z9hfFMw5b5rv0EaUHXus=; b=Oa1cpIGpuG5KCyGfODKBcoVPfpSKDiQNs/TEM8nYLpi4p1XDMZCa8Lt60WtmTtaCwHhIVy5916fYZhmG+tCi664qOSfDc0mSySoCo2RQDZL+Hr97ZrwOvrJnGi0Qt/KU5dLUosuMreIY9+9oI+pS6aACy6IbcFXrvzPqixZ3fP1q8TjDxgvmLPwaOm5rxwXKeUO2HLd8cGlr1jWxSy/b1TKQfucIHuqsm5qc+Ju5k9W/fyUO1dUkqosnVzjUNc3WM41YX1IbB1ZbUItoSyfNGE8KZeIA03j4IBKeustVWXlU281J/T121S8Vq0sVmJ+TCs+FVE+fRLveQj7RMFGSDA== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by PH0PR12MB5484.namprd12.prod.outlook.com (2603:10b6:510:eb::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.24; Thu, 30 Nov 2023 01:10:53 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.7046.015; Thu, 30 Nov 2023 01:10:53 +0000 From: Jason Gunthorpe To: acpica-devel@lists.linux.dev, Andy Gross , Alim Akhtar , Alyssa Rosenzweig , Bjorn Andersson , AngeloGioacchino Del Regno , asahi@lists.linux.dev, Baolin Wang , devicetree@vger.kernel.org, Frank Rowand , Hanjun Guo , "Gustavo A. R. Silva" , Heiko Stuebner , iommu@lists.linux.dev, Jean-Philippe Brucker , Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kees Cook , Konrad Dybcio , Krzysztof Kozlowski , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Lorenzo Pieralisi , Marek Szyprowski , Hector Martin , Matthias Brugger , Orson Zhai , "Rafael J. Wysocki" , Rob Clark , Robert Moore , Rob Herring , Robin Murphy , Samuel Holland , Sudeep Holla , Sven Peter , Thierry Reding , Krishna Reddy , virtualization@lists.linux.dev, Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: =?utf-8?q?Andr=C3=A9_Draszik?= , patches@lists.linux.dev Subject: [PATCH 11/30] iommu/sun50i: Move to iommu_of_get_single_iommu() Date: Wed, 29 Nov 2023 21:10:18 -0400 Message-ID: <11-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> In-Reply-To: <0-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> References: X-ClientProxiedBy: SN6PR08CA0012.namprd08.prod.outlook.com (2603:10b6:805:66::25) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|PH0PR12MB5484:EE_ X-MS-Office365-Filtering-Correlation-Id: 202f467c-ccd0-4067-7ecf-08dbf1412c4e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: wDaTT+ItBQkwfzcOkVg2Mm6eY2SM6MzCUmBpSQHf6eTxjKudDQ3FJrLtC7843i5IRrcwn8Wp3kyfu6/Yh11FUDQgsLe09RbqFC9c2+iHarhPjCgkaI2RwUCtNnHyx1f2GX4soqsXrPW3tZjeHuhABq1xMhcgDnPvrLZmLnuXL2YUzE6qEmHYTRhSCwDecEzEQqk3k0mZwtI9954N7vcDEfs3+s9793mSLR4FCD88WcYY3N9tSP7mTocrA7xWY9eF6jrtozd+HQst/hJospZz6+END6XGVPatK4VBOXB+imY7adaFenJ0MD1QGaumMJitErYRDwzrgCZmy418ZXqH30+cb/9zNzH/WcPrjxVK6W3kB0g6I70noY3NnRRyoT+NB7EWk3sYMVTq8fa6KlOPD9Pdxw/aOkJBCKwhLrM7al2n1j/5h3LbnyhJv+auY8lm0VOMlHMs97bHEXNDGBCVdGQcdHjui/H76ko5oarfbYDoF1fWy3AMooL7COYFS0X0YRtuzPAU+5RhjGp++wmJmXcNTrW38ZWCR1NwdSydhfmm8OyAUTknpAzEaWoLPV75JG8gvtcRUxLH8XQmiu9vkE7ux9a9ykBt+G4RepwDKzVS2XNyaYMOAz4Zl7eop97FzmS+T70+iRR9y9s9Oo4HCw== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:LV2PR12MB5869.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(366004)(346002)(136003)(396003)(39860400002)(376002)(230922051799003)(451199024)(1800799012)(186009)(64100799003)(1191002)(8936002)(110136005)(8676002)(316002)(66556008)(4326008)(86362001)(66476007)(6486002)(478600001)(66946007)(41300700001)(36756003)(921008)(7416002)(7366002)(2906002)(7406005)(5660300002)(38100700002)(2616005)(6512007)(6506007)(6666004)(83380400001)(26005)(202311291699003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: wWcuxQ+bqZ5gr7soEwznyBgBycyNZqXKcFDlwc7STj6auYzuzroGafPTSpivIwLxcXuyAoaQVLZ6IfPMCSvSqVvc+2/M0h6wJLXdgA9MQBYFSH+z/3Evzra7w2Aqf3rzO82n4GtdJo5pb0Eq1lCLtr/+m0yPelra2eVek7ZBOxGFOrDvAsLk89czFKtigbQw3ogWsAgRjTlhJsLudryGaq97tLfKg+GvnVP3aqsxJvMJGR1Ti7Ky2fr+8RoRNWeDguYNt7XHSrsnCzy4oGVUHJFPsaa4rmt51GZ6/BLrhv5o+0/B37CBhFKeLNT6Y72w8hkl7sMZ1Qf+lpZOW0dSNxXnS/Fd7nLg0wfFe6BgFjUfo8grRg2Vik/WiqLn6mQnvMvWvkFac0l9Vww722EeE/Nm1W4+q/OEurTFfwrw2qldfQL5up6pTVSGf1tH+6Ppx1DFeXBd93LkHUb6bCddqBslvFnev1DhIc+t6rSPBiiM0wo8cXd+4mVrV582BsXOfvXucezKbMBNAc6qMH+SmEioDZSPJbCRJTkiA1lb3hfhH6Lq/Zivt2j8DugFo7YyFOXu8/JZDd2sgUonx0LqVPmIhxq6sC43aMFfoDNB4sB0VYfHE6ZcuEWDEszyrahpHYVlcSAPvL5VNHi1In/X9EiFfaDGEGgVSo7++9gG0iuPro3R566N3C8ftrSJtrOmpbzTmRxeNfzAB5rnhxyfwxaYxvAkFL1ST4d1+4FjfYWJEDiDNGRQ/AkgiRb5e93aPtRQ6eWAtFsl9mTmtbcvc0WR2WJ95frA0979Zjmch18U7McnZ+4CthhaHY8uHBWuwq2/q2T/CtdfxFtbjx/7zD6eAMoUQ0E+1klw9aFI4pTv8bsev37W24cWlQAD5ntr9IxlfEGWWe3Es1c1zpCWeMjmAKi/3Yz2dEk9DGKyjfuzzYdO/bIY8RcmvzfylpnHKVsIqdSm863AKsFlR7UC93lbZsHYDepY3BZFmFVhYwdxDGp28dfW9luiELXOa+j0ZyaMK3J/9/14i3VaH6sULWA1dZoqy0YJBAMgOpcKD9GZ63TzlLG1Z9s36cUvswWBuYOrUEtfaN69cnXinClrdVVr1nK13HJSIgpP1OkiIpGPr7PZo+FaxwU0wDIVJtl9slL8E1pDe3fnelSGlGSfuA8fvLNbnl5trv+hgofCTicScRguIIQvEV0XS/gCsnKj944zUANMLSugalmGuGAuLHTE5kCWQPI4BHaiShXbAemH+QBVCNNWaFI+5YotCOVM3721IVlPIQWd25ANil9kSiX7IyXalWLP6O88+YoTgbG6+mrUS0oQFffU+R9YXI62lfgmd9Uk1HzljQm4tn6nCCc/FmROrOo/Ueqz6Im6pDAO7mPOQKT4ToaPakFOfgJEUVTe0n1CBZSHwzug5Qjmkc5dTRG+W5TrWQA/oa7bn6YYSV/Wr9iJSWVmGVVPAng+YHBcOpQJ4MYNTHNeBh6vumTi0y6mdUtAD9KPgo3I0eBCtQpAwBP8EdehOjkdPFIOMX39FvxKwZjRaIKs9+alpM5iW5h9pqHqgw2wb2g7IPGhxJ5hW1GLk/3ZOdArN+Vp X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 202f467c-ccd0-4067-7ecf-08dbf1412c4e X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2023 01:10:42.2642 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: iBIHLWUjNcLd7jknHW9Ss0txa1WTmqIItJzPMglQflJMXkc9yvM+62hk/Nml2vr3 X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5484 sun50i uses a simple binding where a the OF iommus's can describe a single iommu instrance with a single ID, reflecting the master, on it. The driver ignores the ID from the OF, it looks like the instance can only do a single translation as the entire thing is managed with generic_single_device_group(). Since there is a single translation the ID presumably doesn't matter. Allocate a sun50i_iommu_device struct during probe to be like all the other drivers. Signed-off-by: Jason Gunthorpe --- drivers/iommu/sun50i-iommu.c | 60 +++++++++++++++++++++--------------- 1 file changed, 36 insertions(+), 24 deletions(-) diff --git a/drivers/iommu/sun50i-iommu.c b/drivers/iommu/sun50i-iommu.c index 41484a5a399bb1..84038705cf657d 100644 --- a/drivers/iommu/sun50i-iommu.c +++ b/drivers/iommu/sun50i-iommu.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -95,6 +96,8 @@ #define SPAGE_SIZE 4096 +static const struct iommu_ops sun50i_iommu_ops; + struct sun50i_iommu { struct iommu_device iommu; @@ -110,6 +113,10 @@ struct sun50i_iommu { struct kmem_cache *pt_pool; }; +struct sun50i_iommu_device { + struct sun50i_iommu *iommu; +}; + struct sun50i_iommu_domain { struct iommu_domain domain; @@ -128,11 +135,6 @@ static struct sun50i_iommu_domain *to_sun50i_domain(struct iommu_domain *domain) return container_of(domain, struct sun50i_iommu_domain, domain); } -static struct sun50i_iommu *sun50i_iommu_from_dev(struct device *dev) -{ - return dev_iommu_priv_get(dev); -} - static u32 iommu_read(struct sun50i_iommu *iommu, u32 offset) { return readl(iommu->base + offset); @@ -760,7 +762,8 @@ static void sun50i_iommu_detach_domain(struct sun50i_iommu *iommu, static int sun50i_iommu_identity_attach(struct iommu_domain *identity_domain, struct device *dev) { - struct sun50i_iommu *iommu = dev_iommu_priv_get(dev); + struct sun50i_iommu_device *sdev = dev_iommu_priv_get(dev); + struct sun50i_iommu *iommu = sdev->iommu; struct sun50i_iommu_domain *sun50i_domain; dev_dbg(dev, "Detaching from IOMMU domain\n"); @@ -786,12 +789,9 @@ static struct iommu_domain sun50i_iommu_identity_domain = { static int sun50i_iommu_attach_device(struct iommu_domain *domain, struct device *dev) { + struct sun50i_iommu_device *sdev = dev_iommu_priv_get(dev); struct sun50i_iommu_domain *sun50i_domain = to_sun50i_domain(domain); - struct sun50i_iommu *iommu; - - iommu = sun50i_iommu_from_dev(dev); - if (!iommu) - return -ENODEV; + struct sun50i_iommu *iommu = sdev->iommu; dev_dbg(dev, "Attaching to IOMMU domain\n"); @@ -807,26 +807,37 @@ static int sun50i_iommu_attach_device(struct iommu_domain *domain, return 0; } -static struct iommu_device *sun50i_iommu_probe_device(struct device *dev) +static struct iommu_device * +sun50i_iommu_probe_device(struct iommu_probe_info *pinf) { + struct sun50i_iommu_device *sdev; struct sun50i_iommu *iommu; - iommu = sun50i_iommu_from_dev(dev); - if (!iommu) - return ERR_PTR(-ENODEV); + iommu = iommu_of_get_single_iommu(pinf, &sun50i_iommu_ops, 1, + struct sun50i_iommu, iommu); + if (IS_ERR(iommu)) + return ERR_CAST(iommu); + /* + * The ids are ignored because the all the devices are placed in a + * single group and the core code will enforce the same translation for + * all ids. + */ + + sdev = kzalloc(sizeof(*sdev), GFP_KERNEL); + if (!sdev) + return ERR_PTR(-ENOMEM); + sdev->iommu = iommu; + + dev_iommu_priv_set(pinf->dev, sdev); return &iommu->iommu; } -static int sun50i_iommu_of_xlate(struct device *dev, - struct of_phandle_args *args) +static void sun50i_iommu_release_device(struct device *dev) { - struct platform_device *iommu_pdev = of_find_device_by_node(args->np); - unsigned id = args->args[0]; + struct sun50i_iommu_device *sdev = dev_iommu_priv_get(dev); - dev_iommu_priv_set(dev, platform_get_drvdata(iommu_pdev)); - - return iommu_fwspec_add_ids(dev, &id, 1); + kfree(sdev); } static const struct iommu_ops sun50i_iommu_ops = { @@ -834,8 +845,9 @@ static const struct iommu_ops sun50i_iommu_ops = { .pgsize_bitmap = SZ_4K, .device_group = generic_single_device_group, .domain_alloc_paging = sun50i_iommu_domain_alloc_paging, - .of_xlate = sun50i_iommu_of_xlate, - .probe_device = sun50i_iommu_probe_device, + .of_xlate = iommu_dummy_of_xlate, + .probe_device_pinf = sun50i_iommu_probe_device, + .release_device = sun50i_iommu_release_device, .default_domain_ops = &(const struct iommu_domain_ops) { .attach_dev = sun50i_iommu_attach_device, .flush_iotlb_all = sun50i_iommu_flush_iotlb_all, From patchwork Thu Nov 30 01:10:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 13473771 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="WTeVm8yC" Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2053.outbound.protection.outlook.com [40.107.243.53]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 917D5122; Wed, 29 Nov 2023 17:10:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=VfDXirknL7L1BUCs8bc0tSs5Bu4CkkWpVp6Qq0z/Qc4hGiBnGVve7/OGkvEp49n/egXdGqIZa71tbmulM/d8nWqWUNjYeIa/wW5BmHNEsh5muKcWpIHoVDhLkxZ2d3DJ/atqkSPAi6F1Feouuj1o+uQkOl4vKiX8oMoiUvUFOxf1kM3fzQmq8U8hN/9ePVo8BBR/b6BoRuU5WARcb8wfSLSR8UHKdMgvwpbvGLhXdIUadzEwwB61w1a4faUk8FXcPCBYbGjhQjNa660t3n7gbO5BOn09FKNp5bON8ngxJ14YYnD+ahx1MD0lsmaCjryToDGbjTThoOyB1GdYX9hN/Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=at3ERfr6LNQE1weSlr6/SqXNAe3XLITf/XZmwv1CCw8=; b=kdDdHPTRHJzQFCJS+uU9G0X6tl97txATwKrM8u6EUWw+yDjEA85OcxGHOEz8MR4HK43kzzNYKol/sUGUpo0TK8/t44Alfk8zAqpgDua7TisGBYR8ouNNRgwEzP3cwhOaLJ8WhIZt9gKEVHYSwV9tPIYgpcXmdEIlYVBTWc33JLBBwc6wHYRJFXolZJwu1drCcOPaQmh2H1LH0qiSr0hNybD6isge74gj6E9xTsRuhVCk3Wsg2VEOSeoPfv3omWrj7cbY2uYaiwHOK77rXHHStD35HjkhSMrv5hj/hWYtcULHU+ZmiPpZpxr+aQxUn01c7H52/b187+F2huaxgwrflQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=at3ERfr6LNQE1weSlr6/SqXNAe3XLITf/XZmwv1CCw8=; b=WTeVm8yC8YoCWKayhEb92LyMM+ZHBIcQUVWj+Dx9ePMAEynIA88CXUkA8/ZT9N/KWM63fOvFtIyh8uydbNDYDsPZfZ2p9ni1U9sI8O9VvmqN4lYr9HtrwoqPD2HPTywBUo9m2wR54IqgqsUllx5Ko2DYJb5RnzD0rP4KHmY8eHXnyMITWM7ltIoGub7Dtwk63g+6rZD73jlSSHYDYkCma1AW6+aWMVa9NiZrtbfImc+V2sIByhNiyM0VVmeDxVilxTNIpJ0J+EyU7mbTHN68hW8HoXVqGaB5fnG3vaa/WSprmBAKqKEbYaViHm23lZm6lnSbB9el0+DD1M+UKX5pGw== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by PH0PR12MB5484.namprd12.prod.outlook.com (2603:10b6:510:eb::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.24; Thu, 30 Nov 2023 01:10:47 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.7046.015; Thu, 30 Nov 2023 01:10:47 +0000 From: Jason Gunthorpe To: acpica-devel@lists.linux.dev, Andy Gross , Alim Akhtar , Alyssa Rosenzweig , Bjorn Andersson , AngeloGioacchino Del Regno , asahi@lists.linux.dev, Baolin Wang , devicetree@vger.kernel.org, Frank Rowand , Hanjun Guo , "Gustavo A. R. Silva" , Heiko Stuebner , iommu@lists.linux.dev, Jean-Philippe Brucker , Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kees Cook , Konrad Dybcio , Krzysztof Kozlowski , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Lorenzo Pieralisi , Marek Szyprowski , Hector Martin , Matthias Brugger , Orson Zhai , "Rafael J. Wysocki" , Rob Clark , Robert Moore , Rob Herring , Robin Murphy , Samuel Holland , Sudeep Holla , Sven Peter , Thierry Reding , Krishna Reddy , virtualization@lists.linux.dev, Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: =?utf-8?q?Andr=C3=A9_Draszik?= , patches@lists.linux.dev Subject: [PATCH 12/30] iommu/of: Add iommu_of_xlate() Date: Wed, 29 Nov 2023 21:10:19 -0400 Message-ID: <12-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> In-Reply-To: <0-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> References: X-ClientProxiedBy: SN7P222CA0006.NAMP222.PROD.OUTLOOK.COM (2603:10b6:806:124::19) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|PH0PR12MB5484:EE_ X-MS-Office365-Filtering-Correlation-Id: 2f806ee4-4326-45e2-79e6-08dbf1412b63 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: TIZFqfzvtr2YcYNETFF/PTb94RNIUhTKxEEbcXysqAEzMAQoDXWV8aJFOi75zFaI0Il5TP4NPzByEX5F4XAhxGeE4tISihfjAz+eiHGxeNjT5XRrLukZy5iM2DLqlBNBSsBLqaXUUoO+tKjMsDsTVHkav75R34Yu1u5OQnfWYlp65PLg4mvIH4VJTfqV2FSsvPoEj1TASVrSAOkWsi1BMTHSMvlpSMReWwo5cDJoyzm6GcwrCmzB+zdkAxAP9htTkvIfi2vwU6Zw3jTV1A8/81ee52LNiTs6vtGNG0uuAJW7DGu+c+rmLV8pfxCiYjOL4p7wWpCN4wqDPYny4RUkKhxPRGhx1kGJnnQsViyHw6NxLspRbntoCnW7xEImAmedCqwHbZMngmgII4hR7G319RNBMiGxoCIv0BVsr19KkObtLnQOStGLEsSYVLRNU8qATn3Zn6wBiYaAnr1DIk47DQIdGs3l1h36pYGLA6RHiwM+6mm+G+ZB3SN7nOAy6P6KOHYrQlt3ptvtb5bN4dg+NZ2EOOf802I9EEbRwRjgYIeE8QTE/QcykFH/p+EkZez9d1lrBHCKQKAE9dtlxUPjBQ4trFIjKwjAT5H3dNvQJazHUc8/+NQhK2vYHdRsJXH20357ODwmeYDRCPFUicWPNw== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:LV2PR12MB5869.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(366004)(346002)(136003)(396003)(39860400002)(376002)(230922051799003)(451199024)(1800799012)(186009)(64100799003)(1191002)(8936002)(110136005)(8676002)(316002)(66556008)(4326008)(86362001)(66476007)(6486002)(478600001)(66946007)(41300700001)(36756003)(921008)(7416002)(7366002)(2906002)(7406005)(5660300002)(38100700002)(2616005)(6512007)(6506007)(6666004)(83380400001)(26005)(202311291699003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: HkGVBSCT9IGS1U/algNjEDu00nCBkERPgTh2ZudgjMK8/qB6HPEgafNREsBlG/4vTMnQ2uEbm33HKDHnsBzo2gHoqRyCyTKwrTiy7KuuEvxyJ9fnW5NrYqgGMVMTzIgR/TbZ5Es1Yp6KrUHGYmDTdfcfOzmMLiatRNaprFWGMXwruJWUhsDc97Fkdk/NgN+nl2HdEXVqrWJ7um1bn0sTa4MtAsTlcXTJI6XX3ZtJtW44YsPtA8paIVNJOp62CnVpeCufgbEx0Z9qfvLOMHWVnCcza5gMdxA0Yz9/adQkhU36+6wZR13bY+97HyPMaKhQLytgld10nHj3k+ToGH+n3c5CJ+VNlK3Qs+YcNJzFwGPa1wJrA9FFg/o3M2pTJSXpE+GiLVJNLSbd89RZBYFOsRESPH62svGVBTeLaupliGjznLkHf7hCR2FYm0W6RgoIi522IzjJuayYKq/leLq28CN8+L1lTyujvAiMDbuVg+7UxXH63FmuX2jFoN+U92G+W3Mgs2TrpMROhIllFkRqKeJjCH21+KAbZREINMDlNME3LO0W8ITTDcqT30lHRvb+bJFEts0y7y2knmVBJEZf5WAxoganc61AncBesmxvrOm/ByG2ZCzZYzE8tmZCS3A2qsvf4CcaYoEKGF3HWZghnjeJJwJT2VbfUAA+Z/gRu4wsekJZ8Pd2eUEQDiXHJhXnANp6hK4Tl4uJXui9fH/sNS7lUVNs55ukLC2lioLTNlRH0RFKT9wH8i4iMhqzpnMnaZ6KhSXh5LmPW+yOeTiSvUWZ8wH6ISJOvv5k3rforInSAFHs/k7YjTaCGn5Iu0dwvk1dfFw7cREWbdkx3iict5BWt0zfdnn7KQv4msGTSPKLouj4YtkS1TA5CoT4vUwOf1gWvPZlwVkIXjMDxYakxxsjrNf5RPkZkDRXeQOtZmqruseceH+xS02Pc3xFboBjciTW4G78EYMdHz2YgveI5cN5qlMuvNHg6u5H9CP8AWVr5YhHiaLYCG5qR6mV0Pns850dXm/wl5MDaV6qQgatKQTo7bD5lwyY7V4znNnAMEvCyuILT9BGlZcgOF42a4nKeftmaiElEK+wTWoLzNbSWj89X6yA35n6UoKqNNtUf4qCGvUFzgaJU2owZNycMrYws4k8aQ/zV38tu/+3ue9ZTI9GexHRYdJln3hxM0/J/PWFjji6BuTfDaM72ZTovBPeNJa7RgXZgru217vUnpUSQarBCG2TKMdesqeQlgOB2bPFVu9iHOnUeLtEIugulnONacvWYvPmtf5xlzUqf8yCeeEIGrax8xM28YXBgn3hMhVIl5P10WFM3bBIMMb0oKcG4KxdSuTLrlnGeD/T/IDYfvGxuNk8rxuXuiylpRcvv0t/NQ//gbJurtiIBVoSzEYKDaigCwVWNgy5zA8286mdTkYk5BqGaZ2USznxpIhd/eVfUF3CAxzkYWbzScdVtZvSr9XfPLPEE05aN03mDvoz+tH4A6CLxKRgiFLWzTsJi2eegK2zXIx0x2tKWQT33djZzavCGPecHCoN0ZznnjQ1Yj2uutamU7fneNgVD2rWJbpV5NxW+XyYVflFPKa529Hn X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2f806ee4-4326-45e2-79e6-08dbf1412b63 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2023 01:10:40.7736 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: wqSzRYknoJdjHiGX0z3ucmQf7nPG+CbmvO67yHZIMSADsmvKJUkHoPYZETTpR9Ko X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5484 This function can be called by drivers in their probe function if they want to parse their own ID table, almost always because the driver supports a multi-instance configuration and needs to extract the list of iommu_driver's and data from the ID into some internal format. The core code will find the iommu_driver for each ID table entry and validate that it matches the driver's ops. A driver provided function is called to handle the (iommu_driver, ID) tuple. Before calling this function the driver should allocate its per-driver private data and pass it through the opaque cookie priv argument. Driver's should follow a typical pattern in their probe_device: static int apple_dart_of_xlate(struct iommu_device *iommu, struct of_phandle_args *args, void *priv); [..] cfg = kzalloc(sizeof(*cfg), GFP_KERNEL); if (!cfg) return ERR_PTR(-ENOMEM); ret = iommu_of_xlate(pinf, &apple_dart_iommu_ops, 1, &apple_dart_of_xlate, cfg); if (ret) goto err_free; dev_iommu_priv_set(dev, cfg); return &??->iommu; // The first iommu_device parsed Signed-off-by: Jason Gunthorpe --- drivers/iommu/of_iommu.c | 58 ++++++++++++++++++++++++++++++++++++ include/linux/iommu-driver.h | 13 ++++++++ 2 files changed, 71 insertions(+) diff --git a/drivers/iommu/of_iommu.c b/drivers/iommu/of_iommu.c index 37af32a6bc84e5..9c1d398aa2cd9c 100644 --- a/drivers/iommu/of_iommu.c +++ b/drivers/iommu/of_iommu.c @@ -285,6 +285,8 @@ struct parse_info { struct iommu_probe_info *pinf; const struct iommu_ops *ops; int num_cells; + iommu_of_xlate_fn xlate_fn; + void *priv; }; static struct iommu_device *parse_iommu(struct parse_info *info, @@ -336,3 +338,59 @@ struct iommu_device *__iommu_of_get_single_iommu(struct iommu_probe_info *pinf, return iommu_fw_finish_get_single(pinf); } EXPORT_SYMBOL_GPL(__iommu_of_get_single_iommu); + +static int parse_of_xlate(struct of_phandle_args *iommu_spec, void *_info) +{ + struct parse_info *info = _info; + struct iommu_device *iommu; + + iommu = parse_iommu(info, iommu_spec); + if (IS_ERR(iommu)) + return PTR_ERR(iommu); + info->pinf->num_ids++; + return info->xlate_fn(iommu, iommu_spec, info->priv); +} + +/** + * iommu_of_xlate - Parse all OF ids for an IOMMU + * @pinf: The iommu_probe_info + * @ops: The ops the iommu instance must have + * @num_cells: #iommu-cells value to enforce, -1 is no check + * @fn: Call for each Instance and ID + * @priv: Opaque cookie for fn + * + * Drivers that support multiple iommu instances must call this function to + * parse each instance from the OF table. fn will be called with the driver's + * iommu_driver instance and the raw of_phandle_args that contains the ID. + * + * Drivers that need to parse a complex ID format should also use this function. + */ +int iommu_of_xlate(struct iommu_probe_info *pinf, const struct iommu_ops *ops, + int num_cells, iommu_of_xlate_fn fn, void *priv) +{ + struct parse_info info = { .pinf = pinf, + .ops = ops, + .num_cells = num_cells, + .xlate_fn = fn, + .priv = priv }; + + pinf->num_ids = 0; + return of_iommu_for_each_id(pinf->dev, pinf->of_master_np, + pinf->of_map_id, parse_of_xlate, &info); +} +EXPORT_SYMBOL_GPL(iommu_of_xlate); + +/* + * Temporary approach to allow drivers to opt into the bus probe. It configures + * the iommu_probe_info to probe the dev->of_node. This is a bit hacky because + * it mutates the iommu_probe_info and thus assumes there is only one op in the + * system. Remove when we call probe from the bus always anyhow. + */ +void iommu_of_allow_bus_probe(struct iommu_probe_info *pinf) +{ + if (pinf->is_dma_configure) + return; + pinf->of_master_np = pinf->dev->of_node; + pinf->is_dma_configure = true; +} +EXPORT_SYMBOL_GPL(iommu_of_allow_bus_probe); diff --git a/include/linux/iommu-driver.h b/include/linux/iommu-driver.h index 597998a62b0dd6..622d6ad9056ce0 100644 --- a/include/linux/iommu-driver.h +++ b/include/linux/iommu-driver.h @@ -60,9 +60,16 @@ iommu_device_from_fwnode_pinf(struct iommu_probe_info *pinf, struct fwnode_handle *fwnode); struct iommu_device *iommu_fw_finish_get_single(struct iommu_probe_info *pinf); +typedef int (*iommu_of_xlate_fn)(struct iommu_device *iommu, + struct of_phandle_args *args, void *priv); +void iommu_of_allow_bus_probe(struct iommu_probe_info *pinf); + #if IS_ENABLED(CONFIG_OF_IOMMU) void of_iommu_get_resv_regions(struct device *dev, struct list_head *list); +int iommu_of_xlate(struct iommu_probe_info *pinf, const struct iommu_ops *ops, + int num_cells, iommu_of_xlate_fn fn, void *priv); + struct iommu_device *__iommu_of_get_single_iommu(struct iommu_probe_info *pinf, const struct iommu_ops *ops, int num_cells); @@ -71,6 +78,12 @@ static inline void of_iommu_get_resv_regions(struct device *dev, struct list_head *list) { } +static inline int iommu_of_xlate(struct iommu_probe_info *pinf, + const struct iommu_ops *ops, int num_cells, + iommu_of_xlate_fn fn, void *priv) +{ + return -ENODEV; +} static inline struct iommu_device *__iommu_of_get_single_iommu(struct iommu_probe_info *pinf, const struct iommu_ops *ops, From patchwork Thu Nov 30 01:10:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 13473776 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="BjmT8lbX" Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2082.outbound.protection.outlook.com [40.107.243.82]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F3AC810EA; Wed, 29 Nov 2023 17:11:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=ka5+Tn0dtGD82doSLCdRzFAdZU+soCknlkmhpYprPjL/OEtXbLG43HRLzmLKkr86KdFd4lZ16IQm3mc908D2W7OUdSfCIWrg2xjtXemm56kaGKyct8QoRV6MNBE+Lkn//JGELyOgxoMcLTyZHXd8Jj6AV2Jm01O2opSey2ZeZ0+1McByqH8JPhpe3Auv1ufuu7X20oBZKsrz+sANhDt553M+BkaMB9wguQBxHF07TI1GxJfIZ2seqCWPfa+OXOQqD5gM9nOYuPodYuDiBNV2WZWMC+2ztS42sEKCWqCuEKGEcn7SLYuhabPGHG0Unl0c2Tx0hx8Q+SSIimQdjnsevg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=DWZ926ZLNg56KWjCc5bGDycCVGjrN5wZd1+rheKLVFg=; b=OC/gfjy7SmizxL5B+/qJlDZkBscnLWQJM8R1l85aeCrEQsEzkOSg3/CrHa4UbLSsvnDQlrAEKLaEWDkWZEToSD7VbLxsskvdvVWZ+IRZc8e6ZRg7e57mmXNShuGbo5ofD7JvEkkYU2sPru4Bgdh+c1298GWmJ+tk3KpSxyJy2e8jMGB7H6QQlnQaN5Zo5rGIFQVZETzEKBwy6avzhzPec9culajVcwnnvmUtLLfheF3Ebqu+PNm/IChmwu5E8bPWdsj6oECRe1YS1ChmYMHL6nHDlUfEz9Xe22sZdYXxN1JhZbSidmEAqtXx2vrqop6E99pOjUSClW3UGjnHrZraew== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=DWZ926ZLNg56KWjCc5bGDycCVGjrN5wZd1+rheKLVFg=; b=BjmT8lbXwnW6JZmFNYNAVEUqwi/eLtYmxKMIapa0cwURuUJa6Z70jxreC7lR9XxwdoljYcubePkyb3R0rhMfX/b9vGzcCNN7Vcav6tuQYd8x/UBEvuE2DohQCvsSI/iydQXQb9TLClZqlaLJJGsjRQuRv60Lm/in1VUWlv59XdyrePUxNn7ymqhnLjUzr2tiiAgZU7e745OS2irqIeyxTLfhPAhjjhyWmXs3oP+xQPOyGVWq37tglWPlKZp8Hwm5gLpCe3p6LR7oBx7lhkR5JTo5MOKATnsHwl1nRGlJxCb76EiQKJUCJnxiQUafxx8EvXtI9V0MjyKmgvzspPyV8Q== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by PH0PR12MB5484.namprd12.prod.outlook.com (2603:10b6:510:eb::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.24; Thu, 30 Nov 2023 01:10:52 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.7046.015; Thu, 30 Nov 2023 01:10:52 +0000 From: Jason Gunthorpe To: acpica-devel@lists.linux.dev, Andy Gross , Alim Akhtar , Alyssa Rosenzweig , Bjorn Andersson , AngeloGioacchino Del Regno , asahi@lists.linux.dev, Baolin Wang , devicetree@vger.kernel.org, Frank Rowand , Hanjun Guo , "Gustavo A. R. Silva" , Heiko Stuebner , iommu@lists.linux.dev, Jean-Philippe Brucker , Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kees Cook , Konrad Dybcio , Krzysztof Kozlowski , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Lorenzo Pieralisi , Marek Szyprowski , Hector Martin , Matthias Brugger , Orson Zhai , "Rafael J. Wysocki" , Rob Clark , Robert Moore , Rob Herring , Robin Murphy , Samuel Holland , Sudeep Holla , Sven Peter , Thierry Reding , Krishna Reddy , virtualization@lists.linux.dev, Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: =?utf-8?q?Andr=C3=A9_Draszik?= , patches@lists.linux.dev Subject: [PATCH 13/30] iommu/dart: Move to iommu_of_xlate() Date: Wed, 29 Nov 2023 21:10:20 -0400 Message-ID: <13-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> In-Reply-To: <0-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> References: X-ClientProxiedBy: SA1P222CA0145.NAMP222.PROD.OUTLOOK.COM (2603:10b6:806:3c2::29) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|PH0PR12MB5484:EE_ X-MS-Office365-Filtering-Correlation-Id: 675f93e3-a2ba-4189-b362-08dbf1412c35 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: PUAlnaI1V8lrqpJYdE+Z5UsVLxDGEt2eWMKw+SPfsu4wisFzlUhqybEK/ow+wJEhdQIneYbkL+7dH9e3M8SZEp5lb/G2Vw6HlIme/Yjow8R6tJRFi0IjHgy1vveoFIycYwkBVZwC3cLHS+lq47XNr/J/p8oZCNvQdK/CA8ZROqFj+KWhzkxeRVfpy93W6zfBtPckOvInRr5L8JnAaalosUGGyxf2V/ptxZkqQR9rDhS7xl5QPa8L/NTiNa4e5kY0+mVIRWhPqNENune8K6f2wUMmFRMtsVOnmrVmKOlsw4x+ILRZ2KGl+RbkEBlKi6M0i0RqCCCXVvsmGElptVU2J5UDFORw0uFD67dbQKsSbm3uATaqAxeo4lD1xzQTvifDD3veT10lHTUKclaojUG6nLOmrb/uo3Gt+BESHpsxzDadonEjgAGtETRQ8/yaU+sNxYgrZKIM3SkuFaCz6h6tqD3Vvu6fOrCMcV6KFQOCdKC5dUQ8DVL0UjH3kepHGLlRYeV7mwnrxNWhe7iz0+doMmm7kcvi39Xs7ZmnN9FxR41OIT1c/kNG46PhH8zktTgxZZpdxvnOs1GuRSz5tnnT8eT5Rz8tL8iupGSV7nPHxt7j1SCffFfg1DFEfeoBP6NjEOdRAJZc90qSgeHw5h7QOg== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:LV2PR12MB5869.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(366004)(346002)(136003)(396003)(39860400002)(376002)(230922051799003)(451199024)(1800799012)(186009)(64100799003)(1191002)(8936002)(110136005)(8676002)(316002)(66556008)(4326008)(86362001)(66476007)(6486002)(478600001)(66946007)(41300700001)(36756003)(921008)(7416002)(7366002)(2906002)(7406005)(5660300002)(38100700002)(2616005)(6512007)(6506007)(6666004)(83380400001)(26005)(202311291699003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: wYKUGMVw4jTZK9TpVBIlYxZXJsO5zzGTUYhbPmpelFOwHr8icXkROHVlpj5n8xxnJuZHz0o9Y4McQ3bEwIl2fGTleFmlreiZ/vf7pqUYhSj/8zt6k2pgvcApA6iF88hiWjbrWwd+ESPRo+SrtahSogrBWxyVSbHm42G1eCH8dWRjkdG9wrMzbFE5T2QpvWwBoTEgdnQaC6fASJaxHTNydtWVcZ+FowjAwY4tWvzan27Sd9/lfc7KmDImc+bKm3wRaetPHrleO0CJQhLrM73SHp024RI8AJxFZ92amlKTktHJTYwZ88LSALxaUJJC3eDWwdwx6cDzH6AqJtg8/OgulO3T3MBq/fHb1ajeHft1+2YihVnWM47fZ+WyQD+TtAkIOIf6fz334fYF9Im4vCGt6fjwp2v2QXLGBbggTO4PCb/cojUakfec9VQLOo4QG03fbZ4vg3/ugFbj5qgZDTJrz4HiApfaE5oGDQ8BZ9xY88D1DBRPAMOasCoRSXXYNz0k8l81jgBUTkefS0r4DIBqQQ0FRtDoO+jF8AUgcQBLpgiFweNmJr94qXFmKl5SySWi1XBF6WhSNa2ZIOG6aKuG7KUqAPM8fV8SUfLHihTj6xkCUGT/YGrz1f+M/27E4senglfWKBIizYdvm6tY4a1wOUTK+fYeix6+11tIXp2DvY5qjCXrKSfTvsA3+qKDr1GFXsHa92nnwabqoQpOY7TmuMqUD8z5+XmM325AR4QpGwriOiB2Q62kK3o/L/VG19o4amhDQQzd/jzclbJxJQdZkOvtujpkraGRfwCLgb1NFlLhyGl2LMs6foNv3ZFDvBXgGZ0aYS7uwXZvwLa4PDM8NMlkOO3jh8EPohP0wZdQVgPCDu7xQBgtSsPWrup86XOSEK2xHOgdxm8m+zJGFh/40sCvlow76JtLygZflyH1qb4G7KldqGD7D0g1u/JR9+cz6WHqVrQzEZxWmk5KMAOJ5WzfxOfSXqfjzQ17OLymF1Xg4SeW7w7YOXqfFY7Xv/Pi1MLB2NNZroriYSEHx+HgZyYr2oixB01n2eLeffMHuWF0afQz4ok5l2gxkqNVCHXSxHS7mu/7b7jLuMq41Rf2ie7nOYqr+P5j6mQELuSo2pWf0YhiyHnFvHliBDRKs2H91VexVw7h2UMAHxHRl/N0twxk07EqCT1j7objPVMAHglvwUpv78UV36QGHRcC/lE+1iVllZOD7xNKxQsCwQ+MI9Gxl5yaGRrhTyzUswzihWaADdM15/i98pB5B+BsDxYVC7UZFfDseebYDztILvt7aBCIcO3WhRkqsDS1TcBajNZaU1mZWnKHdcmtN0IX3FuF2AibZbWkVDJ4Ly9vFTF4tYmc8djT1TyoeaDxYplG9XVQHpTXMvsNop/iMxsbSRHanm/nSaEALTphAqitiqxNASbRpOOtcvgx3+/7fp7BIouXZhUr7N/ZO4E8KuhH0jMh2+E4jipLMu3o5iylv8XolkznNXcJ4Cid2fTynpl+VdUVecnAfJkYmh4an9rOUAPsgADwhSpy0JtuKEgsDh4PMtqZP1w/vWCYt1t4duwuE7LxA9WzdDo4waGLWcxs6wG6 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 675f93e3-a2ba-4189-b362-08dbf1412c35 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2023 01:10:42.0795 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: N4Y176JW/ot07qm4b/KpOoXLIROVYY8OkNl8DDPa1VZAbJe+cFFsKswX/8e6EebI X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5484 dart supports multiple instances with multiple IDs per instance. It loads the FW data into a pre-allocated 2d array inside it's per-device data. Switch over by allocating the per-device data at the top of probe then calling iommu_of_xlate() to fill in the 2d array. The iommu instance is located by the core code and container_of() gets to the dart version. Solve a few issues: - A bus probe was failing by accident because the of_xlate not being called left a NULL cfg in the priv, and other code tended to free the dev->iommu. iommu_of_xlate() will fail bus probe directly - Missing validation that the node in the iommus instance is actually pointing at this driver - Don't leak the cfg. It is allocated during probe, freed on probe failure, and freed in release_device() on probe success. Previously it would allocate it in of_xlate and leak it in some possible error flows. Signed-off-by: Jason Gunthorpe --- drivers/iommu/apple-dart.c | 58 +++++++++++++++++++++----------------- 1 file changed, 32 insertions(+), 26 deletions(-) diff --git a/drivers/iommu/apple-dart.c b/drivers/iommu/apple-dart.c index bb0e5a4577fc03..b796c68ae45ad8 100644 --- a/drivers/iommu/apple-dart.c +++ b/drivers/iommu/apple-dart.c @@ -268,10 +268,10 @@ struct apple_dart_domain { }; /* - * This structure is attached to devices with dev_iommu_priv_set() on of_xlate - * and contains a list of streams bound to this device. - * So far the worst case seen is a single device with two streams - * from different darts, such that this simple static array is enough. + * This structure is attached to devices with dev_iommu_priv_set() on + * probe_device and contains a list of streams bound to this device. So far the + * worst case seen is a single device with two streams from different darts, + * such that this simple static array is enough. * * @streams: streams for this device */ @@ -295,6 +295,9 @@ struct apple_dart_master_cfg { static struct platform_driver apple_dart_driver; static const struct iommu_ops apple_dart_iommu_ops; +static int apple_dart_of_xlate(struct iommu_device *iommu, + struct of_phandle_args *args, void *priv); + static struct apple_dart_domain *to_dart_domain(struct iommu_domain *dom) { return container_of(dom, struct apple_dart_domain, domain); @@ -721,21 +724,34 @@ static struct iommu_domain apple_dart_blocked_domain = { .ops = &apple_dart_blocked_ops, }; -static struct iommu_device *apple_dart_probe_device(struct device *dev) +static struct iommu_device * +apple_dart_probe_device(struct iommu_probe_info *pinf) { - struct apple_dart_master_cfg *cfg = dev_iommu_priv_get(dev); + struct device *dev = pinf->dev; + struct apple_dart_master_cfg *cfg; struct apple_dart_stream_map *stream_map; + int ret; int i; + cfg = kzalloc(sizeof(*cfg), GFP_KERNEL); if (!cfg) - return ERR_PTR(-ENODEV); + return ERR_PTR(-ENOMEM); + ret = iommu_of_xlate(pinf, &apple_dart_iommu_ops, 1, + &apple_dart_of_xlate, cfg); + if (ret) + goto err_free; for_each_stream_map(i, cfg, stream_map) device_link_add( dev, stream_map->dart->dev, DL_FLAG_PM_RUNTIME | DL_FLAG_AUTOREMOVE_SUPPLIER); + dev_iommu_priv_set(dev, cfg); return &cfg->stream_maps[0].dart->iommu; + +err_free: + kfree(cfg); + return ERR_PTR(ret); } static void apple_dart_release_device(struct device *dev) @@ -778,25 +794,15 @@ static void apple_dart_domain_free(struct iommu_domain *domain) kfree(dart_domain); } -static int apple_dart_of_xlate(struct device *dev, struct of_phandle_args *args) +static int apple_dart_of_xlate(struct iommu_device *iommu, + struct of_phandle_args *args, void *priv) { - struct apple_dart_master_cfg *cfg = dev_iommu_priv_get(dev); - struct platform_device *iommu_pdev = of_find_device_by_node(args->np); - struct apple_dart *dart = platform_get_drvdata(iommu_pdev); - struct apple_dart *cfg_dart; - int i, sid; + struct apple_dart *dart = container_of(iommu, struct apple_dart, iommu); + struct apple_dart_master_cfg *cfg = priv; + struct apple_dart *cfg_dart = cfg->stream_maps[0].dart; + int sid = args->args[0]; + int i; - if (args->args_count != 1) - return -EINVAL; - sid = args->args[0]; - - if (!cfg) - cfg = kzalloc(sizeof(*cfg), GFP_KERNEL); - if (!cfg) - return -ENOMEM; - dev_iommu_priv_set(dev, cfg); - - cfg_dart = cfg->stream_maps[0].dart; if (cfg_dart) { if (cfg_dart->supports_bypass != dart->supports_bypass) return -EINVAL; @@ -978,10 +984,10 @@ static const struct iommu_ops apple_dart_iommu_ops = { .identity_domain = &apple_dart_identity_domain, .blocked_domain = &apple_dart_blocked_domain, .domain_alloc_paging = apple_dart_domain_alloc_paging, - .probe_device = apple_dart_probe_device, + .probe_device_pinf = apple_dart_probe_device, .release_device = apple_dart_release_device, .device_group = apple_dart_device_group, - .of_xlate = apple_dart_of_xlate, + .of_xlate = iommu_dummy_of_xlate, .def_domain_type = apple_dart_def_domain_type, .get_resv_regions = apple_dart_get_resv_regions, .pgsize_bitmap = -1UL, /* Restricted during dart probe */ From patchwork Thu Nov 30 01:10:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 13473755 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="ChwDYoAE" Received: from NAM04-DM6-obe.outbound.protection.outlook.com (mail-dm6nam04on2060.outbound.protection.outlook.com [40.107.102.60]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8C0C8122; Wed, 29 Nov 2023 17:10:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Ny8U4BXRGrjsTjqBDBev9XGufVXNkkea80vTxOxuuAskL2MghKThfFf2Aylc3OJ0K0o0eKKyWJTe++DWtyA0oMauMb27O6fXZpAX1ToeEsv88hkVDDbT0xU/rjvcDiQ1Xsj84hSrUnlrSUAip8IiYRXSLcIAWe04l1FwSJG3Vz82cneGUL4DwlRJoa7JIjHdwvrqAdrMGbdUildZAcH9aBWuoEDg45UKTpd3VZH1cOzH1Kd0fau+SxxskPO2bPsangqmdfBVdID/aDYT8akKT/RwnNJwzuxw2z4i9VCitDsQr8NFPKp9nZbHnR8ym4xFeYcbmqyXHxx7VbxJuZUpkQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=aSoBvw6bu/xIaykTkLxhOIj0UNzTY38fiGKG2fa6Hhc=; b=g8NWH1EKqXATOdoLLEsykmZ/aR+i6jj5yPbcd731zAy2K5RaeGm580LMhImyW3Y+izpdgDXM2foFwi/obQ8/CRBX5brySchiOt/Uzf70di5XHmvknTfm1h/4V1bge8TF+VUZeMoEviyeqXV1ElcgmLPITjX7yWy4zBPdNipMRn+1NzvSKwTbfyQpQcdkL1YVlK/x7lpthPHs40t5QpMX5wQLTE6Kq+L101nZQap6+1AnvGq+m+A8Av6gM+0xt1jXxgkBSfEiGnk3rUWmDMhPXaUKbp+9T/b1egF6tTaQgPJ5EUnZN3aRm4yX9H9ZTh/VQ1wGCPgqz00QA8D/glvKlQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=aSoBvw6bu/xIaykTkLxhOIj0UNzTY38fiGKG2fa6Hhc=; b=ChwDYoAEExL5k8t7Bdhf33CtKVr5qwJwDio8HL3c0XNprZEp3Q1yQ+qcM+SMXYLQKR4kOFYjUglbOzDEAxJ1c9OkD6F3OdmD7Y49Fe0iXj803VoqMW+YOMCUinXXqZpadxtfnpg4gvW55ySDuE+bZGf4fMRdWQpf9UGoYeN3UX4km8gKm5A03QYql85TT3fJxaGgcjBpF6tl2vREqbFlNYemgi+ZulQ9nV6oJ23pDL7Lz9y31FLiax58ANYpLQuPkCgTkbgcxQ60i24zg+J2VngqUflaC5p5EBo7g82gK4hKSpJl+D65J9J/RRZjPeGnDaOjMIQNhzUhw3W5WxX6Jg== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by DS0PR12MB7607.namprd12.prod.outlook.com (2603:10b6:8:13f::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.22; Thu, 30 Nov 2023 01:10:38 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.7046.015; Thu, 30 Nov 2023 01:10:38 +0000 From: Jason Gunthorpe To: acpica-devel@lists.linux.dev, Andy Gross , Alim Akhtar , Alyssa Rosenzweig , Bjorn Andersson , AngeloGioacchino Del Regno , asahi@lists.linux.dev, Baolin Wang , devicetree@vger.kernel.org, Frank Rowand , Hanjun Guo , "Gustavo A. R. Silva" , Heiko Stuebner , iommu@lists.linux.dev, Jean-Philippe Brucker , Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kees Cook , Konrad Dybcio , Krzysztof Kozlowski , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Lorenzo Pieralisi , Marek Szyprowski , Hector Martin , Matthias Brugger , Orson Zhai , "Rafael J. Wysocki" , Rob Clark , Robert Moore , Rob Herring , Robin Murphy , Samuel Holland , Sudeep Holla , Sven Peter , Thierry Reding , Krishna Reddy , virtualization@lists.linux.dev, Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: =?utf-8?q?Andr=C3=A9_Draszik?= , patches@lists.linux.dev Subject: [PATCH 14/30] iommu/exynos: Move to iommu_of_xlate() Date: Wed, 29 Nov 2023 21:10:21 -0400 Message-ID: <14-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> In-Reply-To: <0-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> References: X-ClientProxiedBy: SN7P222CA0010.NAMP222.PROD.OUTLOOK.COM (2603:10b6:806:124::33) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|DS0PR12MB7607:EE_ X-MS-Office365-Filtering-Correlation-Id: 6f9142ec-ed01-441c-9964-08dbf1412a25 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 5/KQURr1SqdpVFCpIzQqkc3bWuhgfsoIg3eAY1j6KzGuEap6fFGi5AGHmNU7LaTrc8ikZlfTNDO4/6tkiP6kz0dA48rXEop51rHHDvEbvmaqVbDRzZBC+xX1vbVvlIFq9DGCFH2R3K9y9c2JeEFMxfKmeQUJ4RR0Dqb7haCjKshrSCpfYndyflzAjegs5lOZgpsT6rc0pz2+MrBo5B8H+YCQGI/W5cqmwhk9EsCavV1+RsNQj/wgb9DBKF4A8p2p89Wk1Yzh94hrGo8P5LfjVHuVlRwfNn/8Gyz6QecoSIXNpqvIzjnXQzw97mTLQfX86ahtoA8vmuy3T8aKX8Mp28Mo+j7Ibr9ZTbW1KPLiBvvivimiwcYUi5/uKnE78TJUfb+Dqwd0hckN+MHj2aeu0U8KKWXX1AF3zW92Zf53wGbTz0a7Nld6HE6SEorY5LP27EalIVRXZFc0ndOV/iMOWYILYDvqS6KVwGqMJr+v6gvoUqrbVxmFyZf/zbfz5bqT+G+5afwbD/vbt8A/enjn+tcA8t8bEGrF55nzKC77HIlB0WTbcqzMOW8za4Rpmf+5hPQNYcS7475CpPcRuZyqKCLKq9MkW1+h8AZ5LjLmtDmSWbyzncGOXyMisufSdO8FzJBcGFLaixh6AjLKCbwqCA== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:LV2PR12MB5869.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(396003)(39860400002)(346002)(136003)(366004)(376002)(230922051799003)(186009)(451199024)(64100799003)(1800799012)(38100700002)(202311291699003)(83380400001)(1191002)(5660300002)(110136005)(2906002)(86362001)(4326008)(8676002)(8936002)(66556008)(7366002)(7406005)(7416002)(66476007)(66946007)(6486002)(478600001)(6666004)(316002)(36756003)(6506007)(41300700001)(6512007)(921008)(26005)(2616005);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: +ZWXqKIWHWInPTY+5qeAm9OIgYb0NNVUk/pxR1RhzdMYjOc0c7+IJF9kBckDcs+mO2DyRJaW4eGlY5tZhutxPasw0s+uhytnC9rxCV+IkM1HYawCjObohj8xX6o+rgFCHVKv5n2oTvmcQ18En4+5r4Fg1QV9HAG2topLuHjPob9Bb3ZmAaEbHLNEBdAshrm+/PFw5NFD8GkONmu/AwcgSpfEFw4kTZ7W4Ib6Vmq17RzJKuP9Tsq+lyr9HN5AODI9cIiYK6R+xXDbEWKVLp6/Nim/Ckn7sR45c6Kvelqm77Y3prexvCak7S7CfTalkcmXPuBzt0VpKVb10MFQP6VG63Rw8VFa9uJLKfEvq+dmfsmQ1PVHCp7oQjuSH2j4yBGguPNqBCULOnQc+fRwU4PJpVWFwdc6B28DB6Irg1PfcLF4AEDguqs5Nhl8KIXzcBGwoBWjvPoB6C3cK7S6jIs6/UAv9mZ5U+AU1AVm8CXPRp6FT4n/Coj2wGczYsm3EYFB4EtJ/1ZO3AXdaPqApw4q0Bg/zj6RKXk5D2H0YjHPpGLwGl4Z2auJY4BUYc6ty191f0pwsNsyNb85ayIBLnmaNbRJbmAsX/YN8iwKvNthe7/xBcg/WRHfl+uEdBYgsw2gfeVme+Wo4VslXX4R1sAwvUjCkz1XYAgjhMF3xSPGnnAyyKFCYcMaxN1vsAL6LBky1odhviPk6czL306lVwh0PczHsji3RUbOY9sHY9HplpQnerkbSQfh4cDi6BC269XpTyRM/eGnxjJxjsQdTxYAfiYVn2BPHgBKCT/w52Dh+ZPqsMOAP15snJpE9/tglUGNPJ9rWQ1w3HDdiKC/nNrFFFy1mCXG7i36+otWFqDIxuqgaaH2wqkhY8PhFIEDdncebRRasM2M1Ytu7jRd6T+QoGT8Oz76/0erqbepdr1wb3Vd6FIWanaFh/plBjgo5ApD8tqQz069aKje7zNpB26Q3Loqietcd5jhv0tPrVFQKMHrYPEFXePWkam1UuGjPxQNUce6Qw3rdntQfHO9D6aJ6UoJ0oDGRUCazUk5ssSULgaQnMcxMNa9blEP7h5En91z+h9BqD6PAHgTaDzWbEI4EKFfpzQ7wpMs4+gXRQNP5mU/UejntI8aC69vcgGAe1bJW+1X4TPm+gTUv8e1wdQwtwpRFEVb/5o5xwkYDCXejI5KFz8wkxXdOS5XwhwBboBaQFKgJboIxCRDzzFba0I+xUSL5luxVpQKKXWu0Wk0f0cK8ezxJMBSVNUMXYqOr5/LmBuo7jGEYVjYpbl3291YSTa1Qbjmq5VltJBc7RnZ2vo/lS85YdXJ17tATnL4woIdI/4eXouROA2dRA1KC0qx0dKR3WQfcGJWU3q7A1TFi+7NJ/ruq2bcUO0TsyBo/VLPqY7pj7mvo5IpnZdg/MEznO/zAL5wjwBMvS0Ik0LB7C/ivAcsM2t0DDIJBhSxD75kdDCgtsSZcBFWZxUIQzRz4glq1loAFxRk/Q+I27GJZW0CBp8GUOPnKBdKvyI+17nOpM/D8RfEo+/XjqfyI8US7WblD+/iAwQ2KHPi9thiZZHWAZeMO/tYA5NTJt/QQV5p X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 6f9142ec-ed01-441c-9964-08dbf1412a25 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2023 01:10:38.7896 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Deblvtu+OhvbUyusQHTkQo0j4X2I8nR8y/aO6w+mQBX6yk8ZVJSGI5i6Bge1KT4A X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7607 exynos allocates a per-device struct in the of_xlate() that can point to multiple instances of the iommu. It looks like each iommu instance can point to only one device however. Move the allocation of the per-device struct to the top of probe and use iommu_of_xlate() to fill in the linked list. Rely on the core code to locate the iommu. Solve a few issues: - A bus probe was failing by accident because the of_xlate not being called left a NULL owner in the priv, and other code tended to free the dev->iommu. iommu_of_xlate() will fail bus probe directly - Missing validation that the node in the iommus instance is actually pointing at this driver - Don't leak the owner. It is allocated during probe, freed on probe failure, and freed in release_device() on probe success. Previously it would allocate it in of_xlate and leak it in some possible error flows. Signed-off-by: Jason Gunthorpe --- drivers/iommu/exynos-iommu.c | 79 +++++++++++++++++------------------- 1 file changed, 38 insertions(+), 41 deletions(-) diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c index 2c6e9094f1e979..c301aa87fe0ff0 100644 --- a/drivers/iommu/exynos-iommu.c +++ b/drivers/iommu/exynos-iommu.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -26,6 +27,9 @@ typedef u32 sysmmu_iova_t; typedef u32 sysmmu_pte_t; static struct iommu_domain exynos_identity_domain; +static int exynos_iommu_of_xlate(struct iommu_device *iommu, + struct of_phandle_args *args, void *priv); + /* We do not consider super section mapping (16MB) */ #define SECT_ORDER 20 #define LPAGE_ORDER 16 @@ -168,8 +172,6 @@ static u32 lv2ent_offset(sysmmu_iova_t iova) #define REG_V7_CAPA1 0x874 #define REG_V7_CTRL_VM 0x8000 -#define has_sysmmu(dev) (dev_iommu_priv_get(dev) != NULL) - static struct device *dma_dev; static struct kmem_cache *lv2table_kmem_cache; static sysmmu_pte_t *zero_lv2_table; @@ -779,8 +781,6 @@ static int exynos_sysmmu_probe(struct platform_device *pdev) if (ret) return ret; - platform_set_drvdata(pdev, data); - if (PG_ENT_SHIFT < 0) { if (MMU_MAJ_VER(data->version) < 5) { PG_ENT_SHIFT = SYSMMU_PG_ENT_SHIFT; @@ -1393,15 +1393,29 @@ static phys_addr_t exynos_iommu_iova_to_phys(struct iommu_domain *iommu_domain, return phys; } -static struct iommu_device *exynos_iommu_probe_device(struct device *dev) +static struct iommu_device * +exynos_iommu_probe_device(struct iommu_probe_info *pinf) { - struct exynos_iommu_owner *owner = dev_iommu_priv_get(dev); + struct exynos_iommu_owner *owner; + struct device *dev = pinf->dev; struct sysmmu_drvdata *data; + int ret; - if (!has_sysmmu(dev)) - return ERR_PTR(-ENODEV); + owner = kzalloc(sizeof(*owner), GFP_KERNEL); + if (!owner) + return ERR_PTR(-ENOMEM); + + INIT_LIST_HEAD(&owner->controllers); + mutex_init(&owner->rpm_lock); + owner->domain = &exynos_identity_domain; + + ret = iommu_of_xlate(pinf, &exynos_iommu_ops, -1, + &exynos_iommu_of_xlate, owner); + if (ret) + goto err_free; list_for_each_entry(data, &owner->controllers, owner_node) { + data->master = dev; /* * SYSMMU will be runtime activated via device link * (dependency) to its master device, so there are no @@ -1412,11 +1426,17 @@ static struct iommu_device *exynos_iommu_probe_device(struct device *dev) DL_FLAG_PM_RUNTIME); } - /* There is always at least one entry, see exynos_iommu_of_xlate() */ + /* iommu_of_xlate() fails if there are no entries */ data = list_first_entry(&owner->controllers, struct sysmmu_drvdata, owner_node); + dev_iommu_priv_set(dev, owner); + return &data->iommu; + +err_free: + kfree(owner); + return ERR_PTR(ret); } static void exynos_iommu_release_device(struct device *dev) @@ -1430,42 +1450,19 @@ static void exynos_iommu_release_device(struct device *dev) device_link_del(data->link); } -static int exynos_iommu_of_xlate(struct device *dev, - struct of_phandle_args *spec) +static int exynos_iommu_of_xlate(struct iommu_device *iommu, + struct of_phandle_args *args, void *priv) { - struct platform_device *sysmmu = of_find_device_by_node(spec->np); - struct exynos_iommu_owner *owner = dev_iommu_priv_get(dev); - struct sysmmu_drvdata *data, *entry; - - if (!sysmmu) - return -ENODEV; - - data = platform_get_drvdata(sysmmu); - if (!data) { - put_device(&sysmmu->dev); - return -ENODEV; - } - - if (!owner) { - owner = kzalloc(sizeof(*owner), GFP_KERNEL); - if (!owner) { - put_device(&sysmmu->dev); - return -ENOMEM; - } - - INIT_LIST_HEAD(&owner->controllers); - mutex_init(&owner->rpm_lock); - owner->domain = &exynos_identity_domain; - dev_iommu_priv_set(dev, owner); - } + struct sysmmu_drvdata *data = + container_of(iommu, struct sysmmu_drvdata, iommu); + struct exynos_iommu_owner *owner = priv; + struct sysmmu_drvdata *entry; + /* FIXME this relies on iommu_probe_device_lock */ list_for_each_entry(entry, &owner->controllers, owner_node) if (entry == data) return 0; - list_add_tail(&data->owner_node, &owner->controllers); - data->master = dev; - return 0; } @@ -1473,10 +1470,10 @@ static const struct iommu_ops exynos_iommu_ops = { .identity_domain = &exynos_identity_domain, .domain_alloc_paging = exynos_iommu_domain_alloc_paging, .device_group = generic_device_group, - .probe_device = exynos_iommu_probe_device, + .probe_device_pinf = exynos_iommu_probe_device, .release_device = exynos_iommu_release_device, .pgsize_bitmap = SECT_SIZE | LPAGE_SIZE | SPAGE_SIZE, - .of_xlate = exynos_iommu_of_xlate, + .of_xlate = iommu_dummy_of_xlate, .default_domain_ops = &(const struct iommu_domain_ops) { .attach_dev = exynos_iommu_attach_device, .map_pages = exynos_iommu_map, From patchwork Thu Nov 30 01:10:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 13473757 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="FCgE9t3o" Received: from NAM04-DM6-obe.outbound.protection.outlook.com (mail-dm6nam04on2060.outbound.protection.outlook.com [40.107.102.60]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C1553D7D; Wed, 29 Nov 2023 17:10:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=HgdG6WMU5tRyo+pu8hMHlBvB63s+Qf82sgIF5JKsUmypHk2HTVBtV12ItkQbz8+kN4n2ItL81qChoZ9tvxNS6mMvzpevjf48abgUAzCsFTu5BbSrIUW5+NkKPD+GXuDj6te/PCpVVoRbdOj1gQDJJPo+HhOq1m1g5NJxj37KrxfiGyMl4e6A8Tzfgpk6s9wLSyG8ay5xqtb8crQSeWHS8UqDWzEcCb9vBBK0nQEOXCHaLbLs3/q+vR5VpVDaRnGGhgj2hqVmZL3QNUxSeJZsAYafDYHtHukWpJ+6M06sCJkXAFqmMuhbAWKbI52vXc/dzpS3/I6znk8l9etMdNF0ow== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Em3umxu+TrgBsDrHGwW96pPsBzA9rtgyJQRI8gBte78=; b=lULuIsxwC5byjV71CeEwJzenNNsw8IF/Woi1hMHCO0kyFMd5pwAXCZJYX4eAUitTSAEDXc3fCeLSqhFgEF4pWScioUWpGbNB1JkeS+sjYM2Ms9c2K0RUz7aLaD8lm5PvD6OQA7rHVTq5etYYnSfboIaH3yrd7sL1ns5wCbNBummU0v8qK5VZ8NSO8cplW2NYszN6zP6O4XiNjdTk2Z6N30b7l+6LxTPXttzhCXCdT6vHuyWOhiDkBifMzb0EDc/ugpMK/JLXlTLdTKvW62o9UbI7ofzV5WtEep9XPWoSCl3UWG1HEqWKoLDMOI+TIqHLeGZcpceer5JzE776P3A/mQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Em3umxu+TrgBsDrHGwW96pPsBzA9rtgyJQRI8gBte78=; b=FCgE9t3oSP+BSi+R9rMlOousaMLCXfKCzdml/A0zH0wwGGzu1RBLGHwiG/Zlce904THeVhNTL5bJd+kc8XIp1baJ18FW0WhrWMTcdr6ghET9HbMxvrNlZkFcr5/5dXgc9oKmNQ+BQVjyHETX9JZ6lME+gFiP4DALyNDSIIgW9vEEl9YkfUYSEke+ZIKW8+o/DGbnI0U8lzKSI94W1pqVcPV5TrVbNvjkoHJytldV52yfi34l7kYecc1JuMFuzi+/OGaUTplgc7tkYP1qrzeuAxs3FWVOIIrWIp2iez5yfZmgP38BVfHAQF2+KEWNtJNSx1hbiwlc/5DtM3kUlNjVdA== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by DS0PR12MB7607.namprd12.prod.outlook.com (2603:10b6:8:13f::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.22; Thu, 30 Nov 2023 01:10:39 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.7046.015; Thu, 30 Nov 2023 01:10:39 +0000 From: Jason Gunthorpe To: acpica-devel@lists.linux.dev, Andy Gross , Alim Akhtar , Alyssa Rosenzweig , Bjorn Andersson , AngeloGioacchino Del Regno , asahi@lists.linux.dev, Baolin Wang , devicetree@vger.kernel.org, Frank Rowand , Hanjun Guo , "Gustavo A. R. Silva" , Heiko Stuebner , iommu@lists.linux.dev, Jean-Philippe Brucker , Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kees Cook , Konrad Dybcio , Krzysztof Kozlowski , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Lorenzo Pieralisi , Marek Szyprowski , Hector Martin , Matthias Brugger , Orson Zhai , "Rafael J. Wysocki" , Rob Clark , Robert Moore , Rob Herring , Robin Murphy , Samuel Holland , Sudeep Holla , Sven Peter , Thierry Reding , Krishna Reddy , virtualization@lists.linux.dev, Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: =?utf-8?q?Andr=C3=A9_Draszik?= , patches@lists.linux.dev Subject: [PATCH 15/30] iommu/msm: Move to iommu_of_xlate() Date: Wed, 29 Nov 2023 21:10:22 -0400 Message-ID: <15-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> In-Reply-To: <0-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> References: X-ClientProxiedBy: SN7P222CA0011.NAMP222.PROD.OUTLOOK.COM (2603:10b6:806:124::32) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|DS0PR12MB7607:EE_ X-MS-Office365-Filtering-Correlation-Id: 1221a765-a291-4493-44d5-08dbf1412a2f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: vQUJtwMzpKbiN/x6qAz49eIAv7c4i7aj6n6Pu5q5HuPH6JQwvAkMQ4YOyUtO+evP23+MtCFsnqTCJmevSMU2vye73fyePNX4hcirTy+MclDVS2gPVSKoZq/Y6qq9tJV1eLw2yS5tqbYbaCSFLGMeUUF72Yj/rAocm28MfWejlYBm5pD295oTWbRfyCpe68qWcSRCt3DZa2/N9KjXN7yttsxwjH7pVbM63fQ19I9FzPlfOtQQB/dR8UJZNpZUbECfxw+yJf1jI9DayzACXacfbTEN6gdr1GSDNlvD5bry/RgjQIhnIaGKBIdbNjx3iZmYX24n1twbs2W49h1YgYNya+Z1nTPkLNnUbbLbcAC7OCjpJhWuU9S1P+BoypMV7mr8+jmVvwxzbR6DQ0eaaFfkBeY8lHQSyVOZsuPyxuK4AjAdpL4z1saB7YATBqaGP+etW1guvs0yVGXbgsniv4NEiWq9wiN21r3ySGCLn7weriOlgsYjtC6J619iNbIMbMURHBkPhO60dsmvmyL3kk8mXc9mQi4OJI+nXyCyRsFMGnn4T564hiI+PNY7UaidL4lQj7Ko/To/r9Pf4QGNKzseCnErRiLfUke4/rJx3lGR0Pg/TsfxepBhxmZMz9JY5//DnrZJSPdeTKXlcK9rOfhV5w== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:LV2PR12MB5869.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(396003)(39860400002)(346002)(136003)(366004)(376002)(230922051799003)(186009)(451199024)(64100799003)(1800799012)(38100700002)(202311291699003)(83380400001)(66899024)(1191002)(5660300002)(110136005)(2906002)(86362001)(4326008)(8676002)(8936002)(66556008)(7366002)(7406005)(7416002)(66476007)(66946007)(6486002)(478600001)(6666004)(316002)(36756003)(6506007)(41300700001)(6512007)(921008)(26005)(2616005);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 1z9nljq3YwhKkQLW7r3lOZa1VrRpPUzgK/sQ/NLsmZ6cz1YyPenNRkYNj9zNlv0gXvhlYdLXbYMga9l/G/YHnsl6JTWWIm9t901St/UCxH7nMldMQ4Q1eMEhrJ4JJwva6khYeZvuK04jo2WMMIiVoPuVwL8d6Gdpg9u4SKNQKNyFp86DCp3qhNMNi4/4UrHAAoUJ/0EcN6mALgTdxpg5TO6OfUEd/1UzPmpHc1zYeHq5bdpV1nqoJNZ61R6afR001Mk/X7s/RGX7C14VQpWNLxmXE60Yd8VxMw6VP6afSNRLZJ5byuEtzb7/Tv3/W0r+xqVXIuEGG3QHprZlLQ9SIvZ0Zz9Qxez28Ht/6vJ09BgB/ZNq/nP3toe3hAS36YhUqUorIzC7yVqX57Iv4Garf1jExDRdrVopFo+tR+wJQYOjR7dnX11kBzLjGmry2V6dne8gD1Ep5KZ4HP/N8eWQUcr8y7sc/CUUhXg6kD3xy2BaNz4F7eBo8iMvhx7KJvLEnnCi4jQxmCKBGuHAGptklUCYNiKmgwxfIqD17vWEladGstNOx2R3SYH/N7dPEOz/an3Y6AqSKXApdvn5UyLvfCb2L+kW+b1NHARcyEzvIn++nI7OMtiPZd1Kv6uM3PEaBI69iw4AgyUMDOOkCRgW/ftxPeMmiD9b7uXY6WTXYinzlllwJ26vADhMyok+9WNjr3MjCa2jJNx6V09+I8AU7MW5n3HrmrZACDKsY98MPIMmqzXOWgnSikXUdbklFtmp2xytgU0dl0RL2butV5+wiBXJAaqnb1VlmkuddjJxmfGl+Ekvuif14QM7ckoI9xdDJ3InZv743jsVRIx5EAdT6dKtJKyWX/lYlXj34o9Cy8L5dBEM3zH627aPrquR0h4qoLTu1Anmt9GorLpQrMQHyENKP3CSgJA3Pwvo72bONp8qv31V2t40yKSp+J56anqjHUGlCT1NmvNZrJbGXrvbWTYZ46FwTRukrjnkMvyaAGUEdl1LCLuCnVcspUhAGeeFciIo9f0ZGduiWxDpIFj9Zde3PR5rLPw3WyNEnBYxw+iGk+6VvDeVuKH+0qEr/nd1rkpYYY2tQxmIC/ez7gEZWE/cSlLXYQsDyQNWWor47uLQgf7GW650itfZt1FQuAPYDpVnXN0L2Lb23JzROuPUlEkskiIYm00sj+zPwa5Yf8ram3LAoRVsqd9SlYPBpaYd73Q6WT/ygGNwgxl9WiMKq54BCseYDsTFybnk+TrI4ghb8TC790M1qvr6fuocc2Hv7Qb8lfrsVFHGccUX45u+rRULoJMY0B+9cH//zQSO9lC0vPn9eX0S2WMvsBTFhfcWHn6DOID1pZwFeXhG8nWA6jwS/T13pRwZcyuuZxRZGstIvLDKZu3GoGWKo4CKgtsonET9ob0wUW46vthBU4bqr6XF6R+50Qjm3pVCRaGHGhqzvD9xTJnwQEXlBrqtITyWX4ow+E9RXpQ4pf7FVEiw7LbaQd5JWvg/85pi6mSrTN5W7T5FxlfQ0Jl3e9oW3vAJW33VKD3AeWI80tNgZZWgdo9pAp4uAXroDOaXm3xunMz3XzcXBVDe8MeXhsf74tAt X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1221a765-a291-4493-44d5-08dbf1412a2f X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2023 01:10:38.8409 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: qqKM7lR3SnpMu9gDv/MPVPNew9e4qSPTtWyAIv1UdK05CNjfSVrsO84rY1P+1Sa2 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7607 It is confusing what this driver is doing. The insert_iommu_master(), especially the list_empty(), doesn't make a lot of sense. Based on the dtsi this supports an iommu instance that has exactly one device attached it. However each device may be connected to multiple instances with multiple stream ids. The iommus list must be sorted by instance or it will not parse correctly. Ideally this driver would work more like dart where each master allocates memory for dev_iommu_priv and records a list of the all the iommus and stream ids in that struct. That is too big of a change for this patch. Keep things basically the same, but rely on the core code to discover the iommu_device and stop confusingly using dev_iommu_priv to join SIDs into the same master when processing the assumed-to-be-sorted iommus list. Signed-off-by: Jason Gunthorpe --- drivers/iommu/msm_iommu.c | 93 ++++++++++++++++----------------------- 1 file changed, 37 insertions(+), 56 deletions(-) diff --git a/drivers/iommu/msm_iommu.c b/drivers/iommu/msm_iommu.c index f86af9815d6f98..6f21eec857c7d7 100644 --- a/drivers/iommu/msm_iommu.c +++ b/drivers/iommu/msm_iommu.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include @@ -37,6 +38,15 @@ static DEFINE_SPINLOCK(msm_iommu_lock); static LIST_HEAD(qcom_iommu_devices); static struct iommu_ops msm_iommu_ops; +struct msm_xlate_args { + struct device *dev; + struct msm_iommu_ctx_dev *master; + struct msm_iommu_dev *iommu; +}; + +static int msm_iommu_of_xlate(struct iommu_device *core_iommu, + struct of_phandle_args *args, void *priv); + struct msm_priv { struct list_head list_attached; struct iommu_domain domain; @@ -357,38 +367,17 @@ static int msm_iommu_domain_config(struct msm_priv *priv) return 0; } -/* Must be called under msm_iommu_lock */ -static struct msm_iommu_dev *find_iommu_for_dev(struct device *dev) +static struct iommu_device * +msm_iommu_probe_device(struct iommu_probe_info *pinf) { - struct msm_iommu_dev *iommu, *ret = NULL; - struct msm_iommu_ctx_dev *master; + struct msm_xlate_args args = { .dev = pinf->dev }; + int ret; - list_for_each_entry(iommu, &qcom_iommu_devices, dev_node) { - master = list_first_entry(&iommu->ctx_list, - struct msm_iommu_ctx_dev, - list); - if (master->of_node == dev->of_node) { - ret = iommu; - break; - } - } - - return ret; -} - -static struct iommu_device *msm_iommu_probe_device(struct device *dev) -{ - struct msm_iommu_dev *iommu; - unsigned long flags; - - spin_lock_irqsave(&msm_iommu_lock, flags); - iommu = find_iommu_for_dev(dev); - spin_unlock_irqrestore(&msm_iommu_lock, flags); - - if (!iommu) - return ERR_PTR(-ENODEV); - - return &iommu->iommu; + ret = iommu_of_xlate(pinf, &msm_iommu_ops, -1, &msm_iommu_of_xlate, + &args); + if (ret) + return ERR_PTR(ret); + return &args.iommu->iommu; } static int msm_iommu_attach_dev(struct iommu_domain *domain, struct device *dev) @@ -596,22 +585,26 @@ static void print_ctx_regs(void __iomem *base, int ctx) GET_SCTLR(base, ctx), GET_ACTLR(base, ctx)); } -static int insert_iommu_master(struct device *dev, - struct msm_iommu_dev **iommu, - struct of_phandle_args *spec) +static int insert_iommu_master(struct msm_xlate_args *args, + struct msm_iommu_dev *iommu, + struct of_phandle_args *spec) { - struct msm_iommu_ctx_dev *master = dev_iommu_priv_get(dev); + struct msm_iommu_ctx_dev *master = args->master; + struct device *dev = args->dev; int sid; - if (list_empty(&(*iommu)->ctx_list)) { + if (!args->iommu) + args->iommu = iommu; + + if (list_empty(&iommu->ctx_list)) { master = kzalloc(sizeof(*master), GFP_ATOMIC); if (!master) { dev_err(dev, "Failed to allocate iommu_master\n"); return -ENOMEM; } master->of_node = dev->of_node; - list_add(&master->list, &(*iommu)->ctx_list); - dev_iommu_priv_set(dev, master); + list_add(&master->list, &iommu->ctx_list); + args->master = master; } for (sid = 0; sid < master->num_mids; sid++) @@ -625,28 +618,16 @@ static int insert_iommu_master(struct device *dev, return 0; } -static int qcom_iommu_of_xlate(struct device *dev, - struct of_phandle_args *spec) +static int msm_iommu_of_xlate(struct iommu_device *core_iommu, + struct of_phandle_args *args, void *priv) { - struct msm_iommu_dev *iommu = NULL, *iter; + struct msm_iommu_dev *iommu = + container_of(core_iommu, struct msm_iommu_dev, iommu); unsigned long flags; int ret = 0; spin_lock_irqsave(&msm_iommu_lock, flags); - list_for_each_entry(iter, &qcom_iommu_devices, dev_node) { - if (iter->dev->of_node == spec->np) { - iommu = iter; - break; - } - } - - if (!iommu) { - ret = -ENODEV; - goto fail; - } - - ret = insert_iommu_master(dev, &iommu, spec); -fail: + ret = insert_iommu_master(priv, iommu, args); spin_unlock_irqrestore(&msm_iommu_lock, flags); return ret; @@ -690,10 +671,10 @@ irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id) static struct iommu_ops msm_iommu_ops = { .identity_domain = &msm_iommu_identity_domain, .domain_alloc_paging = msm_iommu_domain_alloc_paging, - .probe_device = msm_iommu_probe_device, + .probe_device_pinf = msm_iommu_probe_device, .device_group = generic_device_group, .pgsize_bitmap = MSM_IOMMU_PGSIZES, - .of_xlate = qcom_iommu_of_xlate, + .of_xlate = iommu_dummy_of_xlate, .default_domain_ops = &(const struct iommu_domain_ops) { .attach_dev = msm_iommu_attach_dev, .map_pages = msm_iommu_map, From patchwork Thu Nov 30 01:10:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 13473781 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="iHAsBDjE" Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2082.outbound.protection.outlook.com [40.107.243.82]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6A12810FD; Wed, 29 Nov 2023 17:11:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=GESKahWtw+xHbGN+sQu71KsveenbTNe52XJz5ajDxjTPdqDXbUFZqbFbYhCyxt7hzV8eYrscSilb/QXycGI/L8AUlq7xIlD+m7G/sZzP7JuRvyMgJZ2eoxnT5fZoemQtUNfejol96DQ58rT9wRyPUHlR19JqGBFYaLQqYpfDzqMdtbwA+CCE79Eu+ZEY+4foyFX0/pDhDQWnoQnAFeEYhUX/lyCTrljlGX9Xgldggh3534i7deo1F6KaBM8K5VuUeSiUe/6oJ6a1qq+udJDUGtQpD4V/ebdCFAhVU6BbRCxWkvTz488xr/L4oUIq7W9IRRDIcKeR1MkBpDQFumBZ6A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=O/4MHf/uztcI2ZbwWSG0abT7rilc4zmCRB6JzHjLkew=; b=lxJ4rjt4VUAHC4cgfPbMgW6vv4qx/zjY2cbbk6OSkAdKk74c56sfo3cA3ouXsYjEd0n4PDezqbNW8bygO202TVcbLor5xTrP4ziOvtT2ngrR6hf3lEoEiZ3v5h4k7WoTApd7ud6/X8SkiY51TC62fMaRKWfwrzeFbMpzBWxGwI5xcLym7jXUCRR86eRV7Q7ezrz/F7QETdm3VPWTD2VXCgwERN5D3jYvVMv7VDm2OBjDhp4xorqUTmooho0ANLiTJkSEpMwPJr/vHK2ikfD/XTCc05NlKDY8J9TA650ikJLLOi5ZflVHzPl1PpmWU/LsNAbe8CPHFsjA1339CUzPtg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=O/4MHf/uztcI2ZbwWSG0abT7rilc4zmCRB6JzHjLkew=; b=iHAsBDjEocOSjiCmAFZLIsmZLQJbWnOFDlG5bJOsDT/M2us1Qxt3M3b64SrYwtR7jTH2RWeng+D8+WMdRE6YZz5X9BOJck02NtaXEC7GL8q8kmdg5H9tPmuORhSOu2inaOhwTM5OYOit5WwV7UFnXqKqjIpWiHiU11CG4LWyd5qpPifb/yi3A8dlgU3QYgoZgIUVXuOo0S7FsQdzEEs9CmEKHjh5mBIJQh2L8xQLiFg+P6b+p9K/KMY797nHT3AwLe9b0X9KEdy3FOGExDv9/O9V+i5wsticiOuJu8lOSqFAGekdULvSvpN/MRqgzVjQ9qGavpS6XT6YL56K0Cbo5g== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by PH0PR12MB5484.namprd12.prod.outlook.com (2603:10b6:510:eb::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.24; Thu, 30 Nov 2023 01:10:55 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.7046.015; Thu, 30 Nov 2023 01:10:55 +0000 From: Jason Gunthorpe To: acpica-devel@lists.linux.dev, Andy Gross , Alim Akhtar , Alyssa Rosenzweig , Bjorn Andersson , AngeloGioacchino Del Regno , asahi@lists.linux.dev, Baolin Wang , devicetree@vger.kernel.org, Frank Rowand , Hanjun Guo , "Gustavo A. R. Silva" , Heiko Stuebner , iommu@lists.linux.dev, Jean-Philippe Brucker , Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kees Cook , Konrad Dybcio , Krzysztof Kozlowski , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Lorenzo Pieralisi , Marek Szyprowski , Hector Martin , Matthias Brugger , Orson Zhai , "Rafael J. Wysocki" , Rob Clark , Robert Moore , Rob Herring , Robin Murphy , Samuel Holland , Sudeep Holla , Sven Peter , Thierry Reding , Krishna Reddy , virtualization@lists.linux.dev, Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: =?utf-8?q?Andr=C3=A9_Draszik?= , patches@lists.linux.dev Subject: [PATCH 16/30] iommu/tegra: Route tegra_dev_iommu_get_stream_id() through an op Date: Wed, 29 Nov 2023 21:10:23 -0400 Message-ID: <16-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> In-Reply-To: <0-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> References: X-ClientProxiedBy: SA0PR13CA0025.namprd13.prod.outlook.com (2603:10b6:806:130::30) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|PH0PR12MB5484:EE_ X-MS-Office365-Filtering-Correlation-Id: 4fa0a03f-6310-43d0-24b9-08dbf1412c67 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Axh8U+OgK236KJem6Iaft/R29G17WDEEqRxR7Rr4raKiNOFcmS/xiPA8dVUZAVj76ELIGL6kcnCOseDPR4UiT1kKUgsoSOC4Ci/+yaArbMdg9TmUQuobOj2Ih8pr3/h9Ax/NeWCedkAbVRUFtTEU1XKUVmFz0+NGQ8FL/rsr+JAqfvCLkh7sSo7JmDycadl/WBOaqY0I8FTRGoKHlE/IHhOP/GZKRJIpunsrAK61qDtsd6u8I6C6S0a1Np+XZmNjHU4Kw/dRIyIrtVdhwDpy4RS7o9EiM5ApOPJug3osS55yoiRySSDzqu26u0Ps067gA69lOfReRFnqehMydb7B8IPyLJyd5/Xtgessu7FuH1D9qQNTsS3gWaMlh8zl+MhlWoV+/4ILD2ei7gHNYf9z1KuS1DyhccY1stcfsAhiH02+VJuUsJ5rRibvZ6GGafW4UnaDw2XICrn6+P5RymLd7jfaBBZxe6DrD1KzATkwLzsV1SpLXGBBFlR1O3yNMiy50ALFeVBz24aceugfoaA6NylrMcLMtgz6L2WBDTuepoIllsa6hlI58zClhm98ma7TuoYnpU+GHp5Whp4uuAKvaxsEDQPju3YFXuJnZfHolA3htnIKbY/gYLnE+iUBPs6AAmraj4Lsueqzpkn9NSQXCg== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:LV2PR12MB5869.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(366004)(346002)(136003)(396003)(39860400002)(376002)(230922051799003)(451199024)(1800799012)(186009)(64100799003)(1191002)(8936002)(110136005)(8676002)(316002)(66556008)(4326008)(86362001)(66476007)(6486002)(478600001)(66946007)(41300700001)(36756003)(921008)(7416002)(7366002)(2906002)(7406005)(5660300002)(38100700002)(2616005)(6512007)(6506007)(6666004)(83380400001)(26005)(202311291699003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: z9MsOw3PN68N9nhL4dgg2jPuSd3/ZVUH/tXz8cV6NR04UuOdUsaOzVUKW+Xt1G76h8/g2QWFVoxtqjjKr9+r6yiPYHQojPyMZXVmxOSr8t9dPWxGLIeDwKDEN1fOe+kmtrsFXSAX7LGBUlUfjuONfjzSENrSOEWxSlSU3aclJ48kCZpi4rpHzzIDXgzDhE9KQ1ONfMlAyq48+8+LUfCIH+3muiZvDtLjOLI/6QXxkgZsq1dB9g8R5iuDVAPuYM6u2Mas1oJBQ2X7cFiplz7RWbn7tT2HC0iaVUICBy32qdwexeZVYikSeNdsoAObiSHZ/+zdfZKrW88pigBkUyPgmg6+sBbsBMSc4MiWETyLqkVgUymaqNiGH73RQsm3kAPCnweJFhRkKaCt1BT2htNw6Gz4CslKV6d+ainYTwi55XIaI7//7g4s6mAj519KVmYNdfjGxvkeyLpnr5zAOK00hm7I9nnd6VRmxkAS/2lqaGLtoTTwCbxz1odrsr/V9b9H6oO1qtCR8UOc3lnTDM0tdoTO6Opdeu/Zj1HOBdDT5pvXJAS8bvP+v04Bt95CqV74q0q5N2yytqpq0RZBCRsu0BANyrKAWLyX2EQBx68Za8TqsJa9/mDAZR8O3EVP2uoZX6LZi5E98LFzQGqbEq42n6xUq2XIfmtFDWD15PPLv8oZDeEpyTmKt95VBe1LygNebFIs8x6DdhaF4/BDqOl9IAhVQaPMpU97c86daZ7M0SwLSb/euvnqeQ1HkzHFaJrPVYOV67wI3NeI9Z8yetxeer0WHOGY45xV7dzcs94iKD/6YjM99vMf3B5hH9vq0XbbTYQIaCnrjyjieoK9rUNU7bD2cK59l8Nn+rKMqXqwobVzqXyRDAsAeS+usC1xdrOdyKMs35an+g9hHsK9ZP4s44/uDK1OHqxRKSdESCdLHJIi0iwpgTDBzOigJHcsZ+jNVWxoZTtc0jrsZG5H01llvPUbI/jw+kGSmkgSiDanFSaZ8vDYGJqk8GcFFAxYRWt8PIGecyyPibjzvbf+vHcstfUNRUNCIgW0P9RS2wclbN8lJYPU+A6GEKDdJblErW8up5uwItiCHq1OEqKLywMOdimZZ3GVgFrMNiDy6DjR11T4yr0bKW8WD94UdXfhkGI96qc8bTRVOGciDY3ga7QC6jW3LV+DiSdKOxUU642u1IyQ9U3AeKsknh0308zoYqoFXdTZ4E4qEauK9xo9s7aHNbTbrYK2plmO+xLgPHparKPCzN0vv1LVj+JKADIy2iPBaBwT7bvcVuxn25oNi+uJFizdAV23+VlcpARqAnCZwExQtS++k6OdNgozLHrfoFQJmTVUZ81d1nSWehjmYa5veCfLn1HyriIuUbfG1NZZscgdDilYIK1cWdOVaUR2Iici6Z+vEbKrSHwfuDypFLOeLVZ1GU+VKJSuO73w6svB3sdz3R1wtpF65+rg0QffMLaOQvCF+B5Xf2IVGWWjPFlfnJ9YAz8nYT4sLEA09lafvmmKz7PwZ91uviX/r7D8kq33kwP/F19pIVw2bySsRV+/MlCiQtNAdk2OHopfdalcmvucTYAF+UqilW6FuKlT/f2J X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4fa0a03f-6310-43d0-24b9-08dbf1412c67 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2023 01:10:42.4987 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: off+h7Q9ytz3pN0OV/1oNmNUkPZa/PPDwqMZoDF0RmPqU8XgV4E0cA/poIxlgnLW X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5484 This special function exists because fwspec->ids is intended to be private to the driver but tegra needs to program the FW ID into registers on the initiating units. The function allows such units, only for tegra, to get the IDs they are supposed to program. The tegra HW that needs this function only supports tegra-smmu and arm-smmu, so implement the function there. This makes way to moving the id list into the private memory of the driver. Signed-off-by: Jason Gunthorpe --- drivers/iommu/arm/arm-smmu/arm-smmu.c | 11 +++++++++++ drivers/iommu/of_iommu.c | 18 ++++++++++++++++++ drivers/iommu/tegra-smmu.c | 11 +++++++++++ include/linux/iommu.h | 21 +++++++-------------- 4 files changed, 47 insertions(+), 14 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c index adc7937fd8a3a3..02b8dc4f366aa9 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c @@ -1551,6 +1551,16 @@ static int arm_smmu_def_domain_type(struct device *dev) return 0; } +static bool arm_smmu_get_stream_id(struct device *dev, u32 *stream_id) +{ + struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); + + if (fwspec->num_ids != 1) + return false; + *stream_id = fwspec->ids[0] & 0xffff; + return true; +} + static struct iommu_ops arm_smmu_ops = { .capable = arm_smmu_capable, .domain_alloc = arm_smmu_domain_alloc, @@ -1561,6 +1571,7 @@ static struct iommu_ops arm_smmu_ops = { .of_xlate = arm_smmu_of_xlate, .get_resv_regions = arm_smmu_get_resv_regions, .def_domain_type = arm_smmu_def_domain_type, + .tegra_dev_iommu_get_stream_id = arm_smmu_get_stream_id, .pgsize_bitmap = -1UL, /* Restricted during device attach */ .owner = THIS_MODULE, .default_domain_ops = &(const struct iommu_domain_ops) { diff --git a/drivers/iommu/of_iommu.c b/drivers/iommu/of_iommu.c index 9c1d398aa2cd9c..8d5495f03dbbcb 100644 --- a/drivers/iommu/of_iommu.c +++ b/drivers/iommu/of_iommu.c @@ -8,6 +8,7 @@ #include #include #include +#include "iommu-priv.h" #include #include #include @@ -281,6 +282,23 @@ void of_iommu_get_resv_regions(struct device *dev, struct list_head *list) } EXPORT_SYMBOL(of_iommu_get_resv_regions); +#if IS_ENABLED(CONFIG_TEGRA_IOMMU_SMMU) || IS_ENABLED(CONFIG_ARM_SMMU) +/* + * Newer generations of Tegra SoCs require devices' stream IDs to be directly + * programmed into some registers. These are always paired with a Tegra SMMU or + * ARM SMMU which provides an implementation of this op. + */ +bool tegra_dev_iommu_get_stream_id(struct device *dev, u32 *stream_id) +{ + const struct iommu_ops *ops = dev_iommu_ops(dev); + + if (!ops || !ops->tegra_dev_iommu_get_stream_id) + return false; + return ops->tegra_dev_iommu_get_stream_id(dev, stream_id); +} +EXPORT_SYMBOL_GPL(tegra_dev_iommu_get_stream_id); +#endif + struct parse_info { struct iommu_probe_info *pinf; const struct iommu_ops *ops; diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c index 310871728ab4b6..cf563db3e3b48d 100644 --- a/drivers/iommu/tegra-smmu.c +++ b/drivers/iommu/tegra-smmu.c @@ -989,6 +989,16 @@ static int tegra_smmu_def_domain_type(struct device *dev) return IOMMU_DOMAIN_IDENTITY; } +static bool tegra_smmu_get_stream_id(struct device *dev, u32 *stream_id) +{ + struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); + + if (fwspec->num_ids != 1) + return false; + *stream_id = fwspec->ids[0] & 0xffff; + return true; +} + static const struct iommu_ops tegra_smmu_ops = { .identity_domain = &tegra_smmu_identity_domain, .def_domain_type = &tegra_smmu_def_domain_type, @@ -996,6 +1006,7 @@ static const struct iommu_ops tegra_smmu_ops = { .probe_device = tegra_smmu_probe_device, .device_group = tegra_smmu_device_group, .of_xlate = tegra_smmu_of_xlate, + .tegra_dev_iommu_get_stream_id = tegra_smmu_get_stream_id, .pgsize_bitmap = SZ_4K, .default_domain_ops = &(const struct iommu_domain_ops) { .attach_dev = tegra_smmu_attach_dev, diff --git a/include/linux/iommu.h b/include/linux/iommu.h index f0aaf55db3c09b..0ba12e0e450705 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -412,6 +412,9 @@ struct iommu_ops { int (*def_domain_type)(struct device *dev); void (*remove_dev_pasid)(struct device *dev, ioasid_t pasid); + bool (*tegra_dev_iommu_get_stream_id)(struct device *dev, + u32 *stream_id); + const struct iommu_domain_ops *default_domain_ops; unsigned long pgsize_bitmap; struct module *owner; @@ -1309,26 +1312,16 @@ static inline void iommu_dma_compose_msi_msg(struct msi_desc *desc, struct msi_m #endif /* CONFIG_IOMMU_DMA */ -/* - * Newer generations of Tegra SoCs require devices' stream IDs to be directly programmed into - * some registers. These are always paired with a Tegra SMMU or ARM SMMU, for which the contents - * of the struct iommu_fwspec are known. Use this helper to formalize access to these internals. - */ #define TEGRA_STREAM_ID_BYPASS 0x7f +#if IS_ENABLED(CONFIG_TEGRA_IOMMU_SMMU) || IS_ENABLED(CONFIG_ARM_SMMU) +bool tegra_dev_iommu_get_stream_id(struct device *dev, u32 *stream_id); +#else static inline bool tegra_dev_iommu_get_stream_id(struct device *dev, u32 *stream_id) { -#ifdef CONFIG_IOMMU_API - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); - - if (fwspec && fwspec->num_ids == 1) { - *stream_id = fwspec->ids[0] & 0xffff; - return true; - } -#endif - return false; } +#endif #ifdef CONFIG_IOMMU_SVA static inline void mm_pasid_init(struct mm_struct *mm) From patchwork Thu Nov 30 01:10:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 13473770 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="t9NhqxCR" Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2082.outbound.protection.outlook.com [40.107.243.82]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 40D5F10E6; Wed, 29 Nov 2023 17:10:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=oH+7EL3W6Oc2sBQZfrO5SXnZsJh09wEJbKsTB1yKAIiPI/3bt3wGb+Qz4SVbXrZfi3FtUrmdh5QlIbK4UPSQG/W9cI02V4ptbutCUjh6zBQH53njaSysoNAD1c1RPehMEj8FB6Zl/gweDCzuQUhV0CHDDwXZ4gTjK/51xTHOiWtHqFGwORx3CNO6tLu2Wdo0FDPtSBfwYVrQXYkNaWmFLiTBIU9dUnCDaALsL1VGO3qfTVMzNvbnkhzbX+B9Z7z7PbBOe+z4g1/btxGPhz3DAm7O7CMNlMN82E04hyu0+xU0SFIdbwmQbr8/4ZnWrjuM3fWQ1rFaYk2yJZznWpU4yg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=VONoI5R3dY9brGBShgi69AqKHU3yQbManu8ZQ6jk5IU=; b=UZQM4r3z3vP0zD2KE6B/i1fqSzTCLkHMiLjja4kQyEDT9Ad9hKxbzQVii3kADuNTHRhtXhtuhSA4rcgd/YqZJ1O4qQv22Pul+ZvG3PjOl8LDDsRoQZlxoc+Kd9DtyI4UnNWPIVIZpl/UOmqQFQC41l7Poh90571KDB3AUmXvi9Zvh6AJYUjes+ezRqU0HzvjtVHQEE68eEhZfTYwb9sFUEkn59FprWZ7u0kFzlAmKVKb5IpMkt3RkoGVT+kcvX1Kpdlu7eQa8cw+JqUuwbd5XL955vy77wEvZmkdUg9ufN8hmeVpnAh8kR7oGwjPT5ho63YyFodjC+z7W6kSnqnBBA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=VONoI5R3dY9brGBShgi69AqKHU3yQbManu8ZQ6jk5IU=; b=t9NhqxCR/HnnlufMSXxVICsXoXOrHordY+coscGIHglAavA8+T3ahEkQDwzGE/JHDesJVCujmF1yzWIZ5bdoOjT/9HdOWlIlGZ/s45LFCEDxMFhWXaKm4Y1c8mnML16W13y6iGqWHGMM3R+aWo/1GHUU+7ZD0j9nCdZpHPo+Y/Zf0ePKdTBxVI2TpSmz6M3TBPg29hXdwRykdUKt7vvU10WzkwBqZgSmLjg/iR+tYK37jXY2XHAOSWeOr3IrwTLldKT8OHrGNnLKuPTSvWcOJEMw0lzdjyqv1Dl1cbbj8OSADnDLlql4Y5XJsfNL3jh9IgN6TaFzvTIPmlmzJoSGHQ== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by PH0PR12MB5484.namprd12.prod.outlook.com (2603:10b6:510:eb::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.24; Thu, 30 Nov 2023 01:10:49 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.7046.015; Thu, 30 Nov 2023 01:10:49 +0000 From: Jason Gunthorpe To: acpica-devel@lists.linux.dev, Andy Gross , Alim Akhtar , Alyssa Rosenzweig , Bjorn Andersson , AngeloGioacchino Del Regno , asahi@lists.linux.dev, Baolin Wang , devicetree@vger.kernel.org, Frank Rowand , Hanjun Guo , "Gustavo A. R. Silva" , Heiko Stuebner , iommu@lists.linux.dev, Jean-Philippe Brucker , Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kees Cook , Konrad Dybcio , Krzysztof Kozlowski , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Lorenzo Pieralisi , Marek Szyprowski , Hector Martin , Matthias Brugger , Orson Zhai , "Rafael J. Wysocki" , Rob Clark , Robert Moore , Rob Herring , Robin Murphy , Samuel Holland , Sudeep Holla , Sven Peter , Thierry Reding , Krishna Reddy , virtualization@lists.linux.dev, Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: =?utf-8?q?Andr=C3=A9_Draszik?= , patches@lists.linux.dev Subject: [PATCH 17/30] iommu: Add iommu_fw_alloc_per_device_ids() Date: Wed, 29 Nov 2023 21:10:24 -0400 Message-ID: <17-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> In-Reply-To: <0-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> References: X-ClientProxiedBy: SA0PR11CA0133.namprd11.prod.outlook.com (2603:10b6:806:131::18) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|PH0PR12MB5484:EE_ X-MS-Office365-Filtering-Correlation-Id: d05d55fc-83fa-40da-adad-08dbf1412b80 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Tr+LUjzPbR/EMxIsP4k8AZp6N5+iW3J5X8G1RATSwPjWGh9xxXNVltEtIrqWdTIercGf9TVpdos8gGSMwdZjarqc9Y4l3IdZcTjSPbJtUzYqWOs7/wmeFcCtRHabz5UfMEs7RcKXgwp0Z/DBuklARetQycO3QTIlAiGQhoG7UnagAHKq9KN5oACY0YEMusMEI3fpjjMQiH0eZAQAYCi/YixLmDN5omOQD6PM6Cz0N0aF7JiyPai3r84p8rYNd6k/1TJh4iAU/bw+xFQvHDZPzvoG6GXB05C0QassWWaJweOuXjmQZi2ZZYkbZ/0D1VvthKk7sDANh9vBczurwSjgTVOwyeZz3kzOqvPy7pGf3ZgjQBRiUoWcaCmmjPQnn4wrPTcWS+MKf/31PF5glLbBnMspp5tt6DdpgZWlY24mrGf+VbBOeOBMHglkW4VxLbwWJJ3IVDEyZYiR5Ht5P8LQINCeFNe+VX3BiBVbNovwlg880vifKQ2S9YPdWFuEDYeedPfn0vrE0N8BJ+7Wy+bFesuJ5DTnXUPKesVyms6Ui+pTfswTxhh1Vofo3hVP34X7K4fnpKF/Vsxue+IHOVXkxYTi3f2uEZzs/UAw4/fuJeLNXDTNlkD8fFGYRpgVnso+NgNhvAYDUAgNZ8Wc3x666A== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:LV2PR12MB5869.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(366004)(346002)(136003)(396003)(39860400002)(376002)(230922051799003)(451199024)(1800799012)(186009)(64100799003)(1191002)(8936002)(110136005)(8676002)(316002)(66556008)(4326008)(86362001)(66476007)(6486002)(478600001)(66946007)(41300700001)(36756003)(921008)(7416002)(7366002)(2906002)(7406005)(5660300002)(38100700002)(2616005)(6512007)(6506007)(6666004)(83380400001)(26005)(202311291699003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 0Yzl4YfQS2zKnePlOPeSel1Vs1Tv5UcL1D64L8yrayHAfw3LNALIMcFZEk3LWfQ8uFNs57Wa3ytF14ETFJrW99CYML/xYOk6MvZWUqdc+coXpyGluKJAPsTL4IIISIdwxyeldzkWwjkpJzMMOB+Ngp5pDdTEXAcMv7eBWGhCEvtSWLXFI6s+eQuEeDag6HxxvAYZUPxHbZ1WzNM0I0q0dselbiWMx3sKJS8djiM7v5b5/QMDQMPM0BzSw6vYrYq1skYnCXZazM6WYHUDtM/hHTbj62b+07sXAjj+XOSmyejIheaEf6qs0gfAaS3qEniqsXr/VaKaD0IwIVTrQSAyJmNNOyLjj0bDZrQqM8Al5MjPtsz5oC8EA/ueLC9ZAxye1y1m10TAqf+ZBlnzyjv3mm4TesG80F7IG/ieaCFPIfWzYZAU16j6ZWqHYhnWB6huvQIKexm+F/savsqxbJADwtvvzgktfUewH7oM/3RzRXcXonvWTRnr3dcPF3fPKPuS288PlGA5Skf+Z29GK6VRrhcFfzV0K+Y8QpAHPZgcqJkC5eddrIFZLRea0qkqrmNcgc9traNnBfYNP7M5xjK1cXyT7P6X85uZjPupg62+XVdltTo3Drscbp2Us6mnA7rCDTGTDjZKHFv+p5cNW+7sGsLBp3S0ZVFb5VDF0OXfT7w92V3pwZsCJOgWhIzDGUkHiVm1Pr3KSWJ75j5EkFKMrs93shN4nOjypcD41LvNWeWZPRo7Aeo/yz/XJQN5rJeNp+JYQzZ8irHhsn8yR/MnwPX7PyUu06PTy3/IcGYnFmkofi1wiaZQiSs5Y2hDx21c5tJPJtruf8KrtM4NCBMHzJFf8Yy/ZHCnE2XgMlmV/ZiFWSpGh5ceq99sxvmSiglB0mQjgJinhny47f9rAw3fV2fqAQGznD5sEJTrdWEMBpW08p7+Di+fR4Ztlarmwk6BuAUNkRryd84NYwlHDBNyz9+gnAVjYgZfoYXXXwl3rihlRtKWOSxfamV7376qGIcyDJe8nYnT06HxGh51+ST8HkiVmOVevavVzV/mMX/+0imKOIHvhR7Bd41xTFn9rXRbJt+7IjE30CGNvtbPIJzADHM+TN9nFxnu5NdNQWh7C8VJMhG/WiNcVVdaWvPE/UPcxCfp2SsE5v63sTTh/YxyFNESI3rXiTGwB3OWmhKAbx6rLlcRDiKA1VBZYxpNBY2TZd/zvm7i9TgxQRiG8Y1KuGYMoSnlsWBqJV/OpPJoPP+/psFV4VpTsqDkKBuWppy+Sm2EntJAHIe5OUX82oK0HBF2HCQaI6Aw2N+WKFbRARV5DTdzX48/SFpjAVDWtjcbpvXaXn7engxXekv5084b2LIoGZTLC7xBOqSE10PuXXlDr7BYvoVm81EERVgwUZXrLnv+/dUqNNrqZyFMofrAlNZwqM2v4Gxa3QipqVcx0qoczm75KeA0HbV+HxYB8tJ+8hnKp7beobt+n0ZmDhX+n3og1UfubQzCas/6ZWXdQ61w4rxKFIadOqvW6ZqSZRE8Kz4QdBy4MeeGAriJIxGMETAFr9axiMK8nw1sHU7Nif/43zueLzG44Z/o6k5YhoqE X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: d05d55fc-83fa-40da-adad-08dbf1412b80 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2023 01:10:40.9994 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: aJMyQNqWZ/e4wRCik6bJ1jQSIxUV6HrStxdFZB1eOQs1MQv1EnzIX48OQ8PEU0V1 X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5484 This helper can be called after iommu_of_get_single_iommu() to automatically extract the raw list of IDs. It can be used by drivers that expect to have a list of simple u32 IDs for a single IOMMU instance. The driver must provide a per-driver structure with a trailing flex array to hold the IDs. This helper will allocate the structure, size the ids flex array, and fill it in with data. Driver's should follow a typical pattern in their probe_device: struct tegra_smmu_device { struct tegra_smmu *smmu; unsigned int num_ids; u32 ids[] __counted_by(num_ids); }; smmu = iommu_of_get_single_iommu(pinf, &tegra_smmu_ops, 1, struct tegra_smmu, iommu); if (IS_ERR(smmu)) return ERR_CAST(smmu); smmu_device = iommu_fw_alloc_per_device_ids(pinf, smmu_device); if (IS_ERR(smmu_device)) return ERR_CAST(smmu_device); [..] dev_iommu_priv_set(dev, data); return &iommu->iommu; Signed-off-by: Jason Gunthorpe --- drivers/iommu/iommu.c | 21 ++++++++++++++ drivers/iommu/of_iommu.c | 21 +++++++++++++- include/linux/iommu-driver.h | 56 ++++++++++++++++++++++++++++++++++++ 3 files changed, 97 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index ca411ad14c1182..caf14a53ed1952 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -3067,6 +3067,27 @@ struct iommu_device *iommu_fw_finish_get_single(struct iommu_probe_info *pinf) return pinf->cached_iommu; } +/* + * This function shouldn't be called directly without a pretty good reason, + * prefer to structure the driver to use iommu_fw_alloc_per_device_ids() + * instead. + */ +int iommu_fw_get_u32_ids(struct iommu_probe_info *pinf, u32 *ids) +{ + if (WARN_ON(!pinf->get_u32_ids)) + return -EINVAL; + + /* + * We pre-parse a small number if IDs and keep it on the stack. If that + * isn't enough then just reparse again. + */ + if (pinf->num_ids > ARRAY_SIZE(pinf->cached_ids)) + return pinf->get_u32_ids(pinf, ids); + memcpy(ids, pinf->cached_ids, pinf->num_ids * sizeof(*ids)); + return 0; +} +EXPORT_SYMBOL_GPL(iommu_fw_get_u32_ids); + int iommu_fwspec_init(struct device *dev, struct fwnode_handle *iommu_fwnode, const struct iommu_ops *ops) { diff --git a/drivers/iommu/of_iommu.c b/drivers/iommu/of_iommu.c index 8d5495f03dbbcb..6f6e442f899ded 100644 --- a/drivers/iommu/of_iommu.c +++ b/drivers/iommu/of_iommu.c @@ -332,10 +332,28 @@ static int parse_single_iommu(struct of_phandle_args *iommu_spec, void *_info) iommu = parse_iommu(info, iommu_spec); if (IS_ERR(iommu)) return PTR_ERR(iommu); - info->pinf->num_ids++; + iommu_fw_cache_id(info->pinf, iommu_spec->args[0]); return 0; } +static int parse_read_ids(struct of_phandle_args *iommu_spec, void *_info) +{ + struct parse_info *info = _info; + u32 *ids = info->priv; + + *ids = iommu_spec->args[0]; + info->priv = ids + 1; + return 0; +} + +static int iommu_of_get_u32_ids(struct iommu_probe_info *pinf, u32 *ids) +{ + struct parse_info info = { .pinf = pinf, .priv = ids }; + + return of_iommu_for_each_id(pinf->dev, pinf->of_master_np, + pinf->of_map_id, parse_read_ids, &info); +} + struct iommu_device *__iommu_of_get_single_iommu(struct iommu_probe_info *pinf, const struct iommu_ops *ops, int num_cells) @@ -353,6 +371,7 @@ struct iommu_device *__iommu_of_get_single_iommu(struct iommu_probe_info *pinf, pinf->of_map_id, parse_single_iommu, &info); if (err) return ERR_PTR(err); + pinf->get_u32_ids = iommu_of_get_u32_ids; return iommu_fw_finish_get_single(pinf); } EXPORT_SYMBOL_GPL(__iommu_of_get_single_iommu); diff --git a/include/linux/iommu-driver.h b/include/linux/iommu-driver.h index 622d6ad9056ce0..632c7b4a389abe 100644 --- a/include/linux/iommu-driver.h +++ b/include/linux/iommu-driver.h @@ -40,7 +40,9 @@ struct iommu_probe_info { struct iommu_device *cached_iommu; struct device_node *of_master_np; const u32 *of_map_id; + int (*get_u32_ids)(struct iommu_probe_info *pinf, u32 *ids); unsigned int num_ids; + u32 cached_ids[8]; bool defer_setup : 1; bool is_dma_configure : 1; bool cached_single_iommu : 1; @@ -123,6 +125,60 @@ static inline unsigned int iommu_of_num_ids(struct iommu_probe_info *pinf) return pinf->num_ids; } +unsigned int iommu_of_num_ids(struct iommu_probe_info *pinf); +int iommu_fw_get_u32_ids(struct iommu_probe_info *pinf, u32 *ids); + +static inline void iommu_fw_cache_id(struct iommu_probe_info *pinf, u32 id) +{ + if (pinf->num_ids < ARRAY_SIZE(pinf->cached_ids)) + pinf->cached_ids[pinf->num_ids] = id; + pinf->num_ids++; +} + +static inline void * +__iommu_fw_alloc_per_device_ids(struct iommu_probe_info *pinf, void *mem, + unsigned int num_ids, unsigned int *num_ids_p, + u32 *ids_p) +{ + int ret; + + if (!mem) + return ERR_PTR(-ENOMEM); + + ret = iommu_fw_get_u32_ids(pinf, ids_p); + if (ret) { + kfree(mem); + return ERR_PTR(ret); + } + + *num_ids_p = num_ids; + return mem; +} + +/** + * iommu_fw_alloc_per_device_ids - Allocate a per-device struct with ids + * @pinf: The iommu_probe_info + * @drv_struct: Name of a variable to a pointer of the driver structure + * + * Called by a driver during probe this helper allocates and initializes the + * driver struct that embeds the ids array with the trailing members: + * + * unsigned int num_ids; + * u32 ids[] __counted_by(num_ids); + * + * The helper allocates the driver struct with the right size flex array, + * and initializes both members. Returns the driver struct or ERR_PTR. + */ +#define iommu_fw_alloc_per_device_ids(pinf, drv_struct) \ + ({ \ + unsigned int num_ids = iommu_of_num_ids(pinf); \ + typeof(drv_struct) drv; \ + \ + drv = kzalloc(struct_size(drv, ids, num_ids), GFP_KERNEL); \ + drv = __iommu_fw_alloc_per_device_ids( \ + pinf, drv, num_ids, &drv->num_ids, drv->ids); \ + }) + /* * Used temporarily to indicate drivers that have moved to the new probe method. */ From patchwork Thu Nov 30 01:10:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 13473760 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="HQUzZjYH" Received: from NAM04-BN8-obe.outbound.protection.outlook.com (mail-bn8nam04on2053.outbound.protection.outlook.com [40.107.100.53]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 37540D6C; Wed, 29 Nov 2023 17:10:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=kIB7myq+wy1HkVTiYfCrsjCYGm81Ntqt911tXQnYbVUBhPrsOZ9B6JMD8d00KgW4OmR8HwF5E4Ui0TvBCnVqhUbUkhrmQGex7RwMvUKAcFK7DadepjEeGMaKSYkuDzzsksdC/7yzZ4MCwJa6ofdfUDRZEySwlrHIFyZf4O7oMu4ct4g1id92TwhQp1VQMngp+HITAmXPr0ETSPMR1sYR6k/EVSSnUeakurvSsCf1GMcjMIWmIdTTi6yByWX2rVRgEd//rRbQLl7WmqC4rIiszPuRUBLWqAP2Ueb6OVLb5YD6mYWQJ63rc3cRg7dHKhWrEAPm3Zl/txnd/AeL4nW2EA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=c3gvB8+jcuszFrOcv/8o0zSHcCWgbZ8CoZJyYlaYjMU=; b=Q6LimCsOr0kUXJUFznTYQz/iBsAD2IjR/7EdyRDcsfFzgfi7bOtde7Gm+BUHmlkav+DxrxRkFcrLjSc1a/HA5svPoGghGzU2UjVENdSSQ5M8NZUUNQU2lBC8qZ1TVyYXm1AQGBxHMHXt73/xfIWTPro19m+/eAXprS7ZKhVXYoC7FCwooVElvzfoRc7Bp0H33BcbC+VE07dafCG0h0jRuf8cYYFF3AcvxPgdJlugcqh3nvezKTSUD2vdb8u1dhyMs5Cak13+jSGd0jkCwnbJfDo+MRlQsZgrnF3avm4Uni2l29GY2wjft+yNqeumPVEFsEwrQGWDbKBwTdXxZdYozg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=c3gvB8+jcuszFrOcv/8o0zSHcCWgbZ8CoZJyYlaYjMU=; b=HQUzZjYHJ5o3dv42aVGSYQkTZUqN01+cI3GhktoqxXXgW1vG3oqy4VVJ9KAA8iUZBWmlHhDiDReFQ5dvycFO+xsGG1b7fIjJArhWfddxhP/fdrr9B+pAz+sZyc5UblEHpxejZUjA3kYv0IpMq1pWCBTjMOPonih4HAPShGqHc+DKzGnIaAzanGDUFu3Y2s0r+6fTdlpu1wOt3btUG/LkhkUEEdBUd5W3iTuQqllkAOB5YMaJHUpQXxn3bxcviC0BUuNiQuRmXuZ3FK9zY7waquVuDHWJnXEH3PibhNO0xm/m16sSMMmi6q+f8A73Jr8dNkRQr7xyOWyAPfQUFHcAwQ== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by DS0PR12MB7607.namprd12.prod.outlook.com (2603:10b6:8:13f::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.22; Thu, 30 Nov 2023 01:10:41 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.7046.015; Thu, 30 Nov 2023 01:10:41 +0000 From: Jason Gunthorpe To: acpica-devel@lists.linux.dev, Andy Gross , Alim Akhtar , Alyssa Rosenzweig , Bjorn Andersson , AngeloGioacchino Del Regno , asahi@lists.linux.dev, Baolin Wang , devicetree@vger.kernel.org, Frank Rowand , Hanjun Guo , "Gustavo A. R. Silva" , Heiko Stuebner , iommu@lists.linux.dev, Jean-Philippe Brucker , Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kees Cook , Konrad Dybcio , Krzysztof Kozlowski , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Lorenzo Pieralisi , Marek Szyprowski , Hector Martin , Matthias Brugger , Orson Zhai , "Rafael J. Wysocki" , Rob Clark , Robert Moore , Rob Herring , Robin Murphy , Samuel Holland , Sudeep Holla , Sven Peter , Thierry Reding , Krishna Reddy , virtualization@lists.linux.dev, Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: =?utf-8?q?Andr=C3=A9_Draszik?= , patches@lists.linux.dev Subject: [PATCH 18/30] iommu/tegra: Move to iommu_fw_alloc_per_device_ids() Date: Wed, 29 Nov 2023 21:10:25 -0400 Message-ID: <18-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> In-Reply-To: <0-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> References: X-ClientProxiedBy: SN6PR16CA0039.namprd16.prod.outlook.com (2603:10b6:805:ca::16) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|DS0PR12MB7607:EE_ X-MS-Office365-Filtering-Correlation-Id: 1432f4cc-9e44-409d-cd33-08dbf1412a55 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 70m8ZkXBhK9E+PSknZOffPHQt4gitZ0toaCp5TG9m8aLfwY3XAfraLbChk3AOuqyHrSxpHQRUkQXAzaZx4VqcXSuSB8zVZxBPEX1CrYUhSny9FAivS/fR36DnK9P5uRsgMyWWogRgZgQyUAMx9iiyulVCwZi/myWcvxR6a1odl07qlN+rux34xqtvKPuVnUZV93RYebbipByvgO3uADD43zjIH/wbqooPYMrf9fXVS/B/MWxOFc0invNfLJtM3t/2kcTti5+tf1HOtpvq/572wgQ8yFVmqH/SkTeST+B33+ZU5SovLu2R0QZD6LlEQDtklUXDzwm5Dq0tYGMCyCHUrnmvqrYlu3+wZGFJ2pIDFDfotuzjisYQyziLjV2frhBJGwSibJ359Tk8Cn1hldO4twVDor5kc1flASEStmQ4Um7g3ioJYFb8WUqqSfl2phEoV4/36JplSPFxReKGWvPZIc72iX0EQBm2xjrUtGvCY+iHHANQP38VQ8NVl2XQ3pDpVCNnMqUW8QWLfJOAzFn0XiqqEszrtEqFbwSbqhvFjM4GIoz2LjzFqppV5ObDdoeYaZ5KZmiikZXEvM6venf6BJPKNJ0Tqpcly+hp9jabbrs47km2FtvJcoEtTRh2AFkEnzkORuitnBNERYZcmMwTQ== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:LV2PR12MB5869.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(396003)(39860400002)(346002)(136003)(366004)(376002)(230922051799003)(186009)(451199024)(64100799003)(1800799012)(38100700002)(202311291699003)(83380400001)(1191002)(5660300002)(110136005)(2906002)(86362001)(4326008)(8676002)(8936002)(66556008)(7366002)(7406005)(7416002)(66476007)(66946007)(6486002)(478600001)(6666004)(316002)(36756003)(6506007)(41300700001)(6512007)(921008)(26005)(2616005);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: sdW7pmWu21ZWoAqVQ0tg3WLJd0/rYyWPpS7VgoiC4MCb2qEVqPtaC0jDH+zDBpwiNwQhNEkOPv8sXrOwSlXIcIWfMdjAvPipOVOePQzmr4t/XQXb4I/9dZC9YaOyOnhxtoSjP3aHUJuNQ1GsE07GAIznHG/A/zgxkrSxngIqPRljW9M2e9+WBdPJPe73z+LFMyW83Ki8IG+7PGHZkUQmC9Kb/fgpRZq372Npg1WHo/wdDoKHzk3eMVXu3eDjm4PDaefNl+V0woNaQh7I3VWVsLobnYl8P97LQm/TMq4/K4VOo6sLVrxSOT33sg/gNmIN406Al4GWzl8oGch+O7jTD24oW4BCKak63yKPOvmDo0DETl9NfhK7F7E7FpBrmOoUj5ZQen3h1/tTBHzYnXENrAROBgAz0Nv31VOba5kRcYeVVcDBe6CljTgtvVxdfG55lm8BpcG/T18KebQHhUT2krw0ahriDCi+kTj4RRl89i5Si8F0aJNHSDtE7C9gHfg+0jdIYHfY9x8DON2K8mZkB+PukKwRG2jSRp0rd2B6m6Tic5rU63GPfON+yDOrc6Qc365q4RBiJ22yFLHYy8Jvt/bu/KACZ7vmW8QWTo8EuhhrpGYk4YgUgk5HVJZQKVCg0PqrGQLsv9D9E9svsMzzBw+N7cwl8y4/2utrjabqIvQvEy85Nl9Zq1ZBerruZnuMNKh7BRT4m3T3n1y5paic7NNFdFx/PKRlhuLr1idQn/Sg0/wjGxdNsQf0EY3gX53kYYT6Q98Ncob34gbSB1YMBZKa58tfHTqZqtrQ3qK/bGAe6ZgVW9j/Hl9hojtQpAA3DzMIXMm3zvXg4oRpnygC5QLvIzq6TcOc0s5WTbSUNIBVLENbuqZ0HjcEkvigGaYn6+CF4NL6JNqEusOugle0yD48fa0kbmC7U0YosysBHr0ibkmLJRfDR3nHdta082Nf1bPtO2smC19iY/2FHMISaWslkW7pDri5v/KKdm9CZA0l/UZW13Ll/ifolMkOvbxo1dJvHSdGO8lz421+lf15KDna9AxkbODCpBoQDGkKx8Q6EbgtjoiNZFuBeL1dzgZv/n0hNzr61TIxA6XZDOFFCjt4l0cMqfoY9JsOzS2cklXE3Un2l4cCxNIE55pGfggChiUs7OL/mDoKyL9eKjXPoCYpmmrhLMK8HAFGCw164j7nIUIOFRciPu+zIIdoD/AlVZllMpni7ywu+GuXWYjhErejtwQ7w05HGjl3KY+yMGZHTSUpBRdIZinTIeXyaDzOpEnhJ95jyeP+cTtKeaiLEgoH5H7SGZwby2E/NmYq1ObjntJbLMBt3N1S2zF/95ISZg+KhgbDULtNzM1coZcB9z70d9dfcNaCc/gVZPWo7fZTilVHQ+AUTMrxbpQJPAt6ndIDnKbNS1e3zmdrOrgfsUcjDIMKK5Bc7mmwlf3GbH4AjMyGkN/tEIVnnU0E4pfA5HBs0IMhTmXHsAr/TmrumUv+LftftjSlaUBu6h9KC1lJTDDdCE0fkPU70Z1XmT+79YmiYHagjnTUXtBsKHzk7uhDf20cxGHl6B2Y3w8CwvmCu10qms5w6mcK3TVSIk5d X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1432f4cc-9e44-409d-cd33-08dbf1412a55 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2023 01:10:39.0647 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Ubwf2F8qyqpmX8C6Oow8z2AdHECCrVGP8JL7N9r1AURPcZNzYxCnY4lRVugm0y1W X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7607 Tegra supports a single iommu instance with multiple ids. Introduce a per-device data to store the iommu and ids list. Allocate and initialize it with iommu_fw_alloc_per_device_ids(). Remove tegra_smmu_of_xlate(). This now checks that all the iommu instances are the same. Tegra can self-probe without having to go through the fwspec path because it self-initializes the fwspec. Use iommu_of_allow_bus_probe() to achieve the same thing. Convert the rest of the funcs from calling dev_iommu_fwspec_get() to using the per-device data and remove all use of fwspec. Convert the places using dev_iommu_priv_get() to use the per-device data not the iommu. Signed-off-by: Jason Gunthorpe --- drivers/iommu/tegra-smmu.c | 154 +++++++++++-------------------------- 1 file changed, 47 insertions(+), 107 deletions(-) diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c index cf563db3e3b48d..1daa92f524452b 100644 --- a/drivers/iommu/tegra-smmu.c +++ b/drivers/iommu/tegra-smmu.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -19,6 +20,8 @@ #include #include +static const struct iommu_ops tegra_smmu_ops; + struct tegra_smmu_group { struct list_head list; struct tegra_smmu *smmu; @@ -49,6 +52,12 @@ struct tegra_smmu { struct iommu_device iommu; /* IOMMU Core code handle */ }; +struct tegra_smmu_device { + struct tegra_smmu *smmu; + unsigned int num_ids; + u32 ids[] __counted_by(num_ids); +}; + struct tegra_smmu_as { struct iommu_domain domain; struct tegra_smmu *smmu; @@ -477,21 +486,18 @@ static void tegra_smmu_as_unprepare(struct tegra_smmu *smmu, static int tegra_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) { - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); - struct tegra_smmu *smmu = dev_iommu_priv_get(dev); + struct tegra_smmu_device *smmu_device = dev_iommu_priv_get(dev); + struct tegra_smmu *smmu = smmu_device->smmu; struct tegra_smmu_as *as = to_smmu_as(domain); unsigned int index; int err; - if (!fwspec) - return -ENOENT; - - for (index = 0; index < fwspec->num_ids; index++) { + for (index = 0; index < smmu_device->num_ids; index++) { err = tegra_smmu_as_prepare(smmu, as); if (err) goto disable; - tegra_smmu_enable(smmu, fwspec->ids[index], as->id); + tegra_smmu_enable(smmu, smmu_device->ids[index], as->id); } if (index == 0) @@ -501,7 +507,7 @@ static int tegra_smmu_attach_dev(struct iommu_domain *domain, disable: while (index--) { - tegra_smmu_disable(smmu, fwspec->ids[index], as->id); + tegra_smmu_disable(smmu, smmu_device->ids[index], as->id); tegra_smmu_as_unprepare(smmu, as); } @@ -511,22 +517,19 @@ static int tegra_smmu_attach_dev(struct iommu_domain *domain, static int tegra_smmu_identity_attach(struct iommu_domain *identity_domain, struct device *dev) { + struct tegra_smmu_device *smmu_device = dev_iommu_priv_get(dev); struct iommu_domain *domain = iommu_get_domain_for_dev(dev); - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); struct tegra_smmu_as *as; struct tegra_smmu *smmu; unsigned int index; - if (!fwspec) - return -ENODEV; - if (domain == identity_domain || !domain) return 0; as = to_smmu_as(domain); smmu = as->smmu; - for (index = 0; index < fwspec->num_ids; index++) { - tegra_smmu_disable(smmu, fwspec->ids[index], as->id); + for (index = 0; index < smmu_device->num_ids; index++) { + tegra_smmu_disable(smmu, smmu_device->ids[index], as->id); tegra_smmu_as_unprepare(smmu, as); } return 0; @@ -811,77 +814,34 @@ static phys_addr_t tegra_smmu_iova_to_phys(struct iommu_domain *domain, return SMMU_PFN_PHYS(pfn) + SMMU_OFFSET_IN_PAGE(iova); } -static struct tegra_smmu *tegra_smmu_find(struct device_node *np) +static struct iommu_device * +tegra_smmu_probe_device(struct iommu_probe_info *pinf) { - struct platform_device *pdev; - struct tegra_mc *mc; + struct tegra_smmu_device *smmu_device; + struct tegra_smmu *smmu; - pdev = of_find_device_by_node(np); - if (!pdev) - return NULL; + iommu_of_allow_bus_probe(pinf); + smmu = iommu_of_get_single_iommu(pinf, &tegra_smmu_ops, 1, + struct tegra_smmu, iommu); + if (IS_ERR(smmu)) + return ERR_CAST(smmu); - mc = platform_get_drvdata(pdev); - if (!mc) { - put_device(&pdev->dev); - return NULL; - } - - return mc->smmu; -} - -static int tegra_smmu_configure(struct tegra_smmu *smmu, struct device *dev, - struct of_phandle_args *args) -{ - const struct iommu_ops *ops = smmu->iommu.ops; - int err; - - err = iommu_fwspec_init(dev, &dev->of_node->fwnode, ops); - if (err < 0) { - dev_err(dev, "failed to initialize fwspec: %d\n", err); - return err; - } - - err = ops->of_xlate(dev, args); - if (err < 0) { - dev_err(dev, "failed to parse SW group ID: %d\n", err); - iommu_fwspec_free(dev); - return err; - } - - return 0; -} - -static struct iommu_device *tegra_smmu_probe_device(struct device *dev) -{ - struct device_node *np = dev->of_node; - struct tegra_smmu *smmu = NULL; - struct of_phandle_args args; - unsigned int index = 0; - int err; - - while (of_parse_phandle_with_args(np, "iommus", "#iommu-cells", index, - &args) == 0) { - smmu = tegra_smmu_find(args.np); - if (smmu) { - err = tegra_smmu_configure(smmu, dev, &args); - - if (err < 0) { - of_node_put(args.np); - return ERR_PTR(err); - } - } - - of_node_put(args.np); - index++; - } - - smmu = dev_iommu_priv_get(dev); - if (!smmu) - return ERR_PTR(-ENODEV); + smmu_device = iommu_fw_alloc_per_device_ids(pinf, smmu_device); + if (IS_ERR(smmu_device)) + return ERR_CAST(smmu_device); + smmu_device->smmu = smmu; + dev_iommu_priv_set(pinf->dev, smmu_device); return &smmu->iommu; } +static void tegra_smmu_release_device(struct device *dev) +{ + struct tegra_smmu_device *smmu_device = dev_iommu_priv_get(dev); + + kfree(smmu_device); +} + static const struct tegra_smmu_group_soc * tegra_smmu_find_group(struct tegra_smmu *smmu, unsigned int swgroup) { @@ -907,10 +867,10 @@ static void tegra_smmu_group_release(void *iommu_data) static struct iommu_group *tegra_smmu_device_group(struct device *dev) { - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); - struct tegra_smmu *smmu = dev_iommu_priv_get(dev); + struct tegra_smmu_device *smmu_device = dev_iommu_priv_get(dev); + struct tegra_smmu *smmu = smmu_device->smmu; const struct tegra_smmu_group_soc *soc; - unsigned int swgroup = fwspec->ids[0]; + unsigned int swgroup = smmu_device->ids[0]; struct tegra_smmu_group *group; struct iommu_group *grp; @@ -958,27 +918,6 @@ static struct iommu_group *tegra_smmu_device_group(struct device *dev) return group->group; } -static int tegra_smmu_of_xlate(struct device *dev, - struct of_phandle_args *args) -{ - struct platform_device *iommu_pdev = of_find_device_by_node(args->np); - struct tegra_mc *mc = platform_get_drvdata(iommu_pdev); - u32 id = args->args[0]; - - /* - * Note: we are here releasing the reference of &iommu_pdev->dev, which - * is mc->dev. Although some functions in tegra_smmu_ops may keep using - * its private data beyond this point, it's still safe to do so because - * the SMMU parent device is the same as the MC, so the reference count - * isn't strictly necessary. - */ - put_device(&iommu_pdev->dev); - - dev_iommu_priv_set(dev, mc->smmu); - - return iommu_fwspec_add_ids(dev, &id, 1); -} - static int tegra_smmu_def_domain_type(struct device *dev) { /* @@ -991,11 +930,11 @@ static int tegra_smmu_def_domain_type(struct device *dev) static bool tegra_smmu_get_stream_id(struct device *dev, u32 *stream_id) { - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); + struct tegra_smmu_device *smmu_device = dev_iommu_priv_get(dev); - if (fwspec->num_ids != 1) + if (smmu_device->num_ids != 1) return false; - *stream_id = fwspec->ids[0] & 0xffff; + *stream_id = smmu_device->ids[0] & 0xffff; return true; } @@ -1003,9 +942,10 @@ static const struct iommu_ops tegra_smmu_ops = { .identity_domain = &tegra_smmu_identity_domain, .def_domain_type = &tegra_smmu_def_domain_type, .domain_alloc_paging = tegra_smmu_domain_alloc_paging, - .probe_device = tegra_smmu_probe_device, + .probe_device_pinf = tegra_smmu_probe_device, + .release_device = tegra_smmu_release_device, .device_group = tegra_smmu_device_group, - .of_xlate = tegra_smmu_of_xlate, + .of_xlate = iommu_dummy_of_xlate, .tegra_dev_iommu_get_stream_id = tegra_smmu_get_stream_id, .pgsize_bitmap = SZ_4K, .default_domain_ops = &(const struct iommu_domain_ops) { From patchwork Thu Nov 30 01:10:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 13473775 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="INXWqdqc" Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2053.outbound.protection.outlook.com [40.107.243.53]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4FA3DD54; Wed, 29 Nov 2023 17:10:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=MdI03JHoSpNb6wfkhxmvINBZ5QE3A1X7JT0qNXTCqxTSnw9/G5qjD1TxxRyE8cnk0mU4W05J9+24jseiY0nLbPcz226Z/UXgtcHZUUll7xgF9HMqiBw4Ns8weogdaYbAMFZj3bRt4nIjxx7+c5A14sRbSytt9kP/7LoL/2HZRDMv/j5aOtxz19rPmXjRlZ1MdJqvqna8vUS+FMRpBkwzjrJjPKe5XdvIx6YmHaIuYoUSL8WlhhGY4bHqn9zxuygVF/l+JOXg8QMem/w3QkdSFj0GGnDAKa0bKDDPkhyYL/cSj8XgGzVKrQ9TqXX5dFEeA/Xd1Z8cHQyJuz3Cjrlx1A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=mNc0i8b19f67qGg7jaCMO7gIkmzVDan6cC8FlSSYH2o=; b=PVFYPcyxvDMzXhe1i/g0aqirYRrbXjl7/xMmKcK3yWNwrjaHQMe/Q9MvRBUnMrR9lKrMwHW/z4pgj2ikNbQGZUGtQKz2SdJM8aX3ZZz8yXJgWf0RHx7LnDbviOQwHIslqon/FK5+CC9qhj5DtjNVrZVpsJQ2kBSmvfkY2Z8KTXsdbUcrQZQlrwevWAC/GT2PMMUmFUr5VsIsAFyrhQVJM4wnyQqrd1Le5RD/wXslCDWrrPVwoiP0BPFMRIzqtfnQYVwoKI1WoKG1TxvQtB3/JI53UGmYDhKi9ETC/DqnrPx8kmE0xFB57LvGprjMnImIJRjiRt6+IFX6OaJtEKleaQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=mNc0i8b19f67qGg7jaCMO7gIkmzVDan6cC8FlSSYH2o=; b=INXWqdqclBICUJjjXFuMPgFLO24Al4fug/47pDUXnE+dt1EFdrhWsovH259yZyK99z8XSxR4I1TkDubuSn4KmxnLbYUuSqkFYH0U6lNYIGg1A4wJErBXg8VA0c3CFT4XSnTEepmicUaBzj37Xa1J+JY1UfIH4R3tFnSskHMB/uHbAIQIkfSKEZ4W1Fka1eEqpHqjfb+3D1FPWxUb5jnMrjrEHYByhvZDEAhvLmGD+wIXq0Ofr0EXtTb80ygvF75xkmQ8oAZa/O01ND5rfMm/3Pb2LnZ2tn57AAJUt33N6cPKlEq936U3CUKjiPmBatbxI9D1yj7RWPYqM1tC2rR8jA== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by PH0PR12MB5484.namprd12.prod.outlook.com (2603:10b6:510:eb::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.24; Thu, 30 Nov 2023 01:10:48 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.7046.015; Thu, 30 Nov 2023 01:10:48 +0000 From: Jason Gunthorpe To: acpica-devel@lists.linux.dev, Andy Gross , Alim Akhtar , Alyssa Rosenzweig , Bjorn Andersson , AngeloGioacchino Del Regno , asahi@lists.linux.dev, Baolin Wang , devicetree@vger.kernel.org, Frank Rowand , Hanjun Guo , "Gustavo A. R. Silva" , Heiko Stuebner , iommu@lists.linux.dev, Jean-Philippe Brucker , Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kees Cook , Konrad Dybcio , Krzysztof Kozlowski , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Lorenzo Pieralisi , Marek Szyprowski , Hector Martin , Matthias Brugger , Orson Zhai , "Rafael J. Wysocki" , Rob Clark , Robert Moore , Rob Herring , Robin Murphy , Samuel Holland , Sudeep Holla , Sven Peter , Thierry Reding , Krishna Reddy , virtualization@lists.linux.dev, Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: =?utf-8?q?Andr=C3=A9_Draszik?= , patches@lists.linux.dev Subject: [PATCH 19/30] iommu/mtk: Move to iommu_fw_alloc_per_device_ids() Date: Wed, 29 Nov 2023 21:10:26 -0400 Message-ID: <19-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> In-Reply-To: <0-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> References: X-ClientProxiedBy: SN7P222CA0004.NAMP222.PROD.OUTLOOK.COM (2603:10b6:806:124::18) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|PH0PR12MB5484:EE_ X-MS-Office365-Filtering-Correlation-Id: 9d3c6e54-176d-498f-da95-08dbf1412b79 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: EXY2ttH4pyhsm2YJc/WuQ+XxNnXTnWaCedP+qxpCDaXJuBY7Tnu6X3q/091tlNCC51kpIbTaV+RhcD0QTjd9Wn31YcPOcpLPqPFZ2idU9CL24yyyLpMxYkxNIjqawWiQJfWFzsKlC+0cStc9n7I7OFBViRdl7j3L1TFzbKltsBS0yN3nwdpzkDFkOR05+zo2V+9kWqmk/tCTPetycKAUMb+k6uoVs9HIMiMJnWGBkSDm3Q3+0fmyD4y8Q5osfIPiOzvEcY54fo5SEd2EYrKtrH6/UQTsTvtQjKzYbxcRf25toMrpwSgvung13rUy657rXuy0YLCCYOqwM5naOAf2Jgj1ldhmcWLjtLHIlh0yTZHOn6XofOzXdv+yN3yrzfuh3i0mpY6r4tLI4zw4r3Ca3RGIPRgR/k7/r4H7OZg65TMBsx1j08VyZ/t1ELExLLCG4FjJylPecIfH1Fw/QgRxmNm/GfUEHUNx6kdmAprvP2NNKtH4UFpchmT01d40+nEaxXlXfgjRvHiAIYliKu5HY4ilGKQjFyaRMlTbAowRCHO6L/TGuwqvf9MVkygm9SGIpxqzS6RoXFCRcSdAkIxOBYZNfwf6swBYZnf/H4Znb/SQhHLfreFkaiYHM7vKzKx0Kt6GxYsj2RdD1xCZpQoMrg== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:LV2PR12MB5869.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(366004)(346002)(136003)(396003)(39860400002)(376002)(230922051799003)(451199024)(1800799012)(186009)(64100799003)(1191002)(8936002)(110136005)(8676002)(316002)(66556008)(4326008)(86362001)(66476007)(6486002)(478600001)(66946007)(41300700001)(36756003)(921008)(30864003)(7416002)(7366002)(2906002)(7406005)(5660300002)(38100700002)(2616005)(6512007)(6506007)(6666004)(83380400001)(26005)(202311291699003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: m/tpZQKcluujheAqzGnsfhypUuiVioZwVqtFoS6Q8reZVg9Zvx1h+ck+rqme/IFQXOPfDArHdTxbN5Qka4omTa/liI0RQTbxtrQiH9h7KjMpn7Q46tLjqL35V3QoIp2OVmHeX0zUV0lexS7xuwH3jodV6j2wBf7Y48ARZEwHR1ndObPARt5DvoqLcEV7proUdCQtWgXqoOuAN96KOifHDPX0jbMx3I+ee5idllzMTlQaHzECbJbWzQBzcEQoDKGeSiTYBhbwXHkQNm0jJu36TucLgk88rpLncdj9/IzvnAaFT+NMTTAdg/2RJfNLJjO0giloleI05kNDngZ6sCxTVY5csnFPwX0l5c0Jr3KDPUy7YUx85Jzq9G9FjhZ8L2b0u09ZXt8BXwGEl556I8ca5BVcfdfE7gGWxe3JlgVorbhV2kG0hxDsYVzs7eUIhQPaXfMmq+dQzi3yI6Pz+1cDEoAVONG9/MkbJEkGIyUJCjBKcwDl3WC6/CmONsaCpzcLgyam+GYbKDJ/Xwz4Wdxl039/i+X+BgP5u6YndVo58649BClQx9i8jDfTlpqTLEF5pwJA1mA5g7XUgziOga06oymnUbybEPCiOxyMIQG256kegwt/x2YyfEQSFBqDxsSZZ+O9mBrH5VBrZRfPks57jb4n57JK39llHLHGjpAbrI9L/HthwY7Gwi+S7P5Qfzgg5kZnNxYZ3PD/fPUpCvv/shtva1wsV0e3W1W56v/9hMbwyL8x42Zru8/y2qlavaP9Aqgs9eETqasDhcRVFFShTGN9rRcTlYD6UnzLaTOcOeASXFQ01RsjJn3h+CbKXlH+RqXA2JtrdIBPGVi5AqpyT12aC5q+9ce1P0WnNkreDaawWIs8cuKjv5oXMpq0D9j8eYlodJwq0SetltIwuMbX3cPJo+1zZRm972yo7JHsj0B0CjvSl/uE1F8yNXC/vMSnmC6Ko9d3eZ4nwuYX/1sH0r4pYs2mghmt3QPuCS5RT6SK16tBaifBr4MC7sQqtF9KvcUb0EAzw5n8JsSg4Dfs6zX4I2VUD5fDfgXVK4tXAAobuS/ZH8JjDzwrss/KYsy24HniPbN/sqR0VOK/jmN0P1mDhCWO3zIW5LVilY1ZelPqQ1KIU54peTMiDpzZ5JkyBKwRTU0KM3eh9KRdWrLXhDi6qNDxn40E60HtuMDaNP4dQbwt27NbK87+MrR8cCM+WG8xgjhNjZ2ZhJnZBaOz4QcIVSKcIhxaoKMtQQNiL4eELSvLc/8YnE6y7dSlR4Uzdpz2PTIX64jy/X/8VxI7M+O92spUPjKEmuZQ2Il14f/jeP6239QQ8iehu+v/KIqtdWsVezVpdY6FpREB4866WE2I7QkWAuVWR9S3JTUOeU9FLEAcTyPdfkctEpfcnelFPTpwr6wgOHgrMqzj22KRo3JYJbzuAZBcNufjsPruG6rg4K8rp5GM0Vhvv44yOhYagbJlhlVJ1CwSFipPCtf5KOupaqaw558DhHJIdqLQNEN9DGppCNN30Oi6DwHjpSPoEJl17j6/twzaVcaH9jPaGYfP7goRcjFeKuBAqkSUooyq1SO+J5Rv7WWdj2YW4DOQ X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 9d3c6e54-176d-498f-da95-08dbf1412b79 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2023 01:10:40.9319 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 5iQCpGHG8rrK0heO2B4CQgapUNp1ZK85FyWiYHYC54oG2yQrFPC3AxQeYD/nYFkY X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5484 mtk was doing a lot of stuff under of_xlate, and it looked kind of like it might support multi-instances. But the dt files don't do that, and the driver has no way to keep track of which instance the ids are for. Enforce single instance with iommu_of_get_single_iommu(). Introduce a per-device data to store the iommu and ids list. Allocate and initialize it with iommu_fw_alloc_per_device_ids(). Remove mtk_iommu_of_xlate(). Convert the rest of the funcs from calling dev_iommu_fwspec_get() to using the per-device data and remove all use of fwspec. Covnert the places using dev_iommu_priv_get() to use the per-device data not the iommu. Signed-off-by: Jason Gunthorpe --- drivers/iommu/mtk_iommu.c | 116 ++++++++++++++++++++------------------ 1 file changed, 62 insertions(+), 54 deletions(-) diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 7abe9e85a57063..477171e83eaa6e 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -277,6 +278,12 @@ struct mtk_iommu_data { struct mtk_smi_larb_iommu larb_imu[MTK_LARB_NR_MAX]; }; +struct mtk_iommu_device { + struct mtk_iommu_data *iommu; + unsigned int num_ids; + u32 ids[] __counted_by(num_ids); +}; + struct mtk_iommu_domain { struct io_pgtable_cfg cfg; struct io_pgtable_ops *iop; @@ -526,14 +533,14 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id) static unsigned int mtk_iommu_get_bank_id(struct device *dev, const struct mtk_iommu_plat_data *plat_data) { - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); + struct mtk_iommu_device *mtkdev = dev_iommu_priv_get(dev); unsigned int i, portmsk = 0, bankid = 0; if (plat_data->banks_num == 1) return bankid; - for (i = 0; i < fwspec->num_ids; i++) - portmsk |= BIT(MTK_M4U_TO_PORT(fwspec->ids[i])); + for (i = 0; i < mtkdev->num_ids; i++) + portmsk |= BIT(MTK_M4U_TO_PORT(mtkdev->ids[i])); for (i = 0; i < plat_data->banks_num && i < MTK_IOMMU_BANK_MAX; i++) { if (!plat_data->banks_enable[i]) @@ -550,7 +557,7 @@ static unsigned int mtk_iommu_get_bank_id(struct device *dev, static int mtk_iommu_get_iova_region_id(struct device *dev, const struct mtk_iommu_plat_data *plat_data) { - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); + struct mtk_iommu_device *mtkdev = dev_iommu_priv_get(dev); unsigned int portidmsk = 0, larbid; const u32 *rgn_larb_msk; int i; @@ -558,9 +565,9 @@ static int mtk_iommu_get_iova_region_id(struct device *dev, if (plat_data->iova_region_nr == 1) return 0; - larbid = MTK_M4U_TO_LARB(fwspec->ids[0]); - for (i = 0; i < fwspec->num_ids; i++) - portidmsk |= BIT(MTK_M4U_TO_PORT(fwspec->ids[i])); + larbid = MTK_M4U_TO_LARB(mtkdev->ids[0]); + for (i = 0; i < mtkdev->num_ids; i++) + portidmsk |= BIT(MTK_M4U_TO_PORT(mtkdev->ids[i])); for (i = 0; i < plat_data->iova_region_nr; i++) { rgn_larb_msk = plat_data->iova_region_larb_msk[i]; @@ -579,22 +586,22 @@ static int mtk_iommu_get_iova_region_id(struct device *dev, static int mtk_iommu_config(struct mtk_iommu_data *data, struct device *dev, bool enable, unsigned int regionid) { + struct mtk_iommu_device *mtkdev = dev_iommu_priv_get(dev); struct mtk_smi_larb_iommu *larb_mmu; unsigned int larbid, portid; - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); const struct mtk_iommu_iova_region *region; unsigned long portid_msk = 0; struct arm_smccc_res res; int i, ret = 0; - for (i = 0; i < fwspec->num_ids; ++i) { - portid = MTK_M4U_TO_PORT(fwspec->ids[i]); + for (i = 0; i < mtkdev->num_ids; ++i) { + portid = MTK_M4U_TO_PORT(mtkdev->ids[i]); portid_msk |= BIT(portid); } if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) { /* All ports should be in the same larb. just use 0 here */ - larbid = MTK_M4U_TO_LARB(fwspec->ids[0]); + larbid = MTK_M4U_TO_LARB(mtkdev->ids[0]); larb_mmu = &data->larb_imu[larbid]; region = data->plat_data->iova_region + regionid; @@ -618,7 +625,7 @@ static int mtk_iommu_config(struct mtk_iommu_data *data, struct device *dev, } else { /* PCI dev has only one output id, enable the next writing bit for PCIe */ if (dev_is_pci(dev)) { - if (fwspec->num_ids != 1) { + if (mtkdev->num_ids != 1) { dev_err(dev, "PCI dev can only have one port.\n"); return -ENODEV; } @@ -708,7 +715,9 @@ static void mtk_iommu_domain_free(struct iommu_domain *domain) static int mtk_iommu_attach_device(struct iommu_domain *domain, struct device *dev) { - struct mtk_iommu_data *data = dev_iommu_priv_get(dev), *frstdata; + struct mtk_iommu_device *mtkdev = dev_iommu_priv_get(dev); + struct mtk_iommu_data *data = mtkdev->iommu; + struct mtk_iommu_data *frstdata; struct mtk_iommu_domain *dom = to_mtk_domain(domain); struct list_head *hw_list = data->hw_list; struct device *m4udev = data->dev; @@ -777,12 +786,12 @@ static int mtk_iommu_identity_attach(struct iommu_domain *identity_domain, struct device *dev) { struct iommu_domain *domain = iommu_get_domain_for_dev(dev); - struct mtk_iommu_data *data = dev_iommu_priv_get(dev); + struct mtk_iommu_device *mtkdev = dev_iommu_priv_get(dev); if (domain == identity_domain || !domain) return 0; - mtk_iommu_config(data, dev, false, 0); + mtk_iommu_config(mtkdev->iommu, dev, false, 0); return 0; } @@ -860,14 +869,28 @@ static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain, return pa; } -static struct iommu_device *mtk_iommu_probe_device(struct device *dev) +static struct iommu_device * +mtk_iommu_probe_device(struct iommu_probe_info *pinf) { - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); - struct mtk_iommu_data *data = dev_iommu_priv_get(dev); + struct mtk_iommu_device *mtkdev; + struct device *dev = pinf->dev; + struct mtk_iommu_data *data; struct device_link *link; struct device *larbdev; unsigned int larbid, larbidx, i; + data = iommu_of_get_single_iommu(pinf, &mtk_iommu_ops, 1, + struct mtk_iommu_data, iommu); + if (IS_ERR(data)) + return ERR_CAST(data); + + mtkdev = iommu_fw_alloc_per_device_ids(pinf, mtkdev); + if (IS_ERR(mtkdev)) + return ERR_CAST(mtkdev); + mtkdev->iommu = data; + + dev_iommu_priv_set(dev, mtkdev); + if (!MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) return &data->iommu; @@ -876,42 +899,46 @@ static struct iommu_device *mtk_iommu_probe_device(struct device *dev) * The device that connects with each a larb is a independent HW. * All the ports in each a device should be in the same larbs. */ - larbid = MTK_M4U_TO_LARB(fwspec->ids[0]); + larbid = MTK_M4U_TO_LARB(mtkdev->ids[0]); if (larbid >= MTK_LARB_NR_MAX) - return ERR_PTR(-EINVAL); + goto err_out; - for (i = 1; i < fwspec->num_ids; i++) { - larbidx = MTK_M4U_TO_LARB(fwspec->ids[i]); + for (i = 1; i < mtkdev->num_ids; i++) { + larbidx = MTK_M4U_TO_LARB(mtkdev->ids[i]); if (larbid != larbidx) { dev_err(dev, "Can only use one larb. Fail@larb%d-%d.\n", larbid, larbidx); - return ERR_PTR(-EINVAL); + goto err_out; } } larbdev = data->larb_imu[larbid].dev; if (!larbdev) - return ERR_PTR(-EINVAL); + goto err_out; link = device_link_add(dev, larbdev, DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS); if (!link) dev_err(dev, "Unable to link %s\n", dev_name(larbdev)); return &data->iommu; + +err_out: + kfree(mtkdev); + return ERR_PTR(-EINVAL); } static void mtk_iommu_release_device(struct device *dev) { - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); - struct mtk_iommu_data *data; + struct mtk_iommu_device *mtkdev = dev_iommu_priv_get(dev); + struct mtk_iommu_data *data = mtkdev->iommu; struct device *larbdev; unsigned int larbid; - data = dev_iommu_priv_get(dev); if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) { - larbid = MTK_M4U_TO_LARB(fwspec->ids[0]); + larbid = MTK_M4U_TO_LARB(mtkdev->ids[0]); larbdev = data->larb_imu[larbid].dev; device_link_remove(dev, larbdev); } + kfree(mtkdev); } static int mtk_iommu_get_group_id(struct device *dev, const struct mtk_iommu_plat_data *plat_data) @@ -931,7 +958,9 @@ static int mtk_iommu_get_group_id(struct device *dev, const struct mtk_iommu_pla static struct iommu_group *mtk_iommu_device_group(struct device *dev) { - struct mtk_iommu_data *c_data = dev_iommu_priv_get(dev), *data; + struct mtk_iommu_device *mtkdev = dev_iommu_priv_get(dev); + struct mtk_iommu_data *c_data = mtkdev->iommu; + struct mtk_iommu_data *data; struct list_head *hw_list = c_data->hw_list; struct iommu_group *group; int groupid; @@ -957,32 +986,11 @@ static struct iommu_group *mtk_iommu_device_group(struct device *dev) return group; } -static int mtk_iommu_of_xlate(struct device *dev, struct of_phandle_args *args) -{ - struct platform_device *m4updev; - - if (args->args_count != 1) { - dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n", - args->args_count); - return -EINVAL; - } - - if (!dev_iommu_priv_get(dev)) { - /* Get the m4u device */ - m4updev = of_find_device_by_node(args->np); - if (WARN_ON(!m4updev)) - return -EINVAL; - - dev_iommu_priv_set(dev, platform_get_drvdata(m4updev)); - } - - return iommu_fwspec_add_ids(dev, args->args, 1); -} - static void mtk_iommu_get_resv_regions(struct device *dev, struct list_head *head) { - struct mtk_iommu_data *data = dev_iommu_priv_get(dev); + struct mtk_iommu_device *mtkdev = dev_iommu_priv_get(dev); + struct mtk_iommu_data *data = mtkdev->iommu; unsigned int regionid = mtk_iommu_get_iova_region_id(dev, data->plat_data), i; const struct mtk_iommu_iova_region *resv, *curdom; struct iommu_resv_region *region; @@ -1012,10 +1020,10 @@ static void mtk_iommu_get_resv_regions(struct device *dev, static const struct iommu_ops mtk_iommu_ops = { .identity_domain = &mtk_iommu_identity_domain, .domain_alloc_paging = mtk_iommu_domain_alloc_paging, - .probe_device = mtk_iommu_probe_device, + .probe_device_pinf = mtk_iommu_probe_device, .release_device = mtk_iommu_release_device, .device_group = mtk_iommu_device_group, - .of_xlate = mtk_iommu_of_xlate, + .of_xlate = iommu_dummy_of_xlate, .get_resv_regions = mtk_iommu_get_resv_regions, .pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M, .owner = THIS_MODULE, From patchwork Thu Nov 30 01:10:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 13473759 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="CFU4n2BF" Received: from NAM04-DM6-obe.outbound.protection.outlook.com (mail-dm6nam04on2060.outbound.protection.outlook.com [40.107.102.60]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2C192122; Wed, 29 Nov 2023 17:10:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=LEOSp8LojpsztFQ8MpYwW1O2ZIAzxkf4yNWGaAHXOP3wtasQGMdqQIgQOwIn75VVsPxrC50hZIav58EgbboU7u3p2yy17WNg66fUqW4ya6IAfIK/SzFCQQ+alGIpySdIviym/D5LjAuB6/IRml9+I9bW+ELetDpfrzVnOPU0NBMvET7dzsyrN/GaPsvGw/2uMPzefJ3ArzCf5K5miJZIZN1eHibC5i5rqc6jKDoq/bkFf2G5uWnP8xHhyiUyBflkEquteOzK91GB+x4bRWFbkYXIEKMXW69qi3b5DOBRtGzWdjgxJaf4UEmCv8V3wEN1KNjs4MJzEMk33dho0dq6rw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=gjJdDHI+AITYfSvxiqF0GgwRht7dfBc7a3uv3e45GaI=; b=GKLgIPTMxJQ7NkYjBKcLmz51v0Cys/F/zSlUN2ttpMgFJQ8RZuQLVpirZUB7J7uevu3d7SZ+OmW43RYnrBiLChSCx/TnvwHJJ+rEr7oY1xxKfoUajs2LK2ZymxQucQl+cixGXFQLt01DmM4BwpCqsx88sKfj4XAlUUZSEbndwmK1EWYV/BBPgLm6QRg3FKzYTpv3f7sq+BTUBUT21ule5K8L60DMSgJkMdVmv6B1BGxZacRCP3cjXsT4nfkpM1EuhjMsgHgLtwYag401qwMO2Up16wq7y3sjjzRh3aAjY5EnCvK49turPnnksVoq3/DfyJRkPYLRqGoEUZC93lzaPg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=gjJdDHI+AITYfSvxiqF0GgwRht7dfBc7a3uv3e45GaI=; b=CFU4n2BFkMtpGDmXngCQHuDXXqTcKhUIr1Fq4tJ7qnavTr79R6AefH0F8r/rN76tlm6OhOtfiM8t/i+B2Os6faeQ7vDe8LmIbp0b2x75f2/ypOhEef+21WrroxQPpV0XP6jSc8G1J9+18bV6/aexU9rl36nwOqsSHD4b+ykq7dGCBRkx3c5oK3tLyYmJNyLIZs0BLq9xNp37fX5ZUG+RaY+Nt3Pfdfc/Asi9hidM+IWKMGrH/3RyyDA7IIgvkfX01DIOl71EDOTjonuz+zdcltMG6tJvY0CVsh1tqRavKct4/b+Oh2E+n5dEPb8j4SdouM8t7DMyCjXOO4xP03euQg== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by DS0PR12MB7607.namprd12.prod.outlook.com (2603:10b6:8:13f::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.22; Thu, 30 Nov 2023 01:10:42 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.7046.015; Thu, 30 Nov 2023 01:10:42 +0000 From: Jason Gunthorpe To: acpica-devel@lists.linux.dev, Andy Gross , Alim Akhtar , Alyssa Rosenzweig , Bjorn Andersson , AngeloGioacchino Del Regno , asahi@lists.linux.dev, Baolin Wang , devicetree@vger.kernel.org, Frank Rowand , Hanjun Guo , "Gustavo A. R. Silva" , Heiko Stuebner , iommu@lists.linux.dev, Jean-Philippe Brucker , Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kees Cook , Konrad Dybcio , Krzysztof Kozlowski , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Lorenzo Pieralisi , Marek Szyprowski , Hector Martin , Matthias Brugger , Orson Zhai , "Rafael J. Wysocki" , Rob Clark , Robert Moore , Rob Herring , Robin Murphy , Samuel Holland , Sudeep Holla , Sven Peter , Thierry Reding , Krishna Reddy , virtualization@lists.linux.dev, Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: =?utf-8?q?Andr=C3=A9_Draszik?= , patches@lists.linux.dev Subject: [PATCH 20/30] iommu/ipmmu-vmsa: Move to iommu_fw_alloc_per_device_ids() Date: Wed, 29 Nov 2023 21:10:27 -0400 Message-ID: <20-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> In-Reply-To: <0-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> References: X-ClientProxiedBy: SN6PR16CA0047.namprd16.prod.outlook.com (2603:10b6:805:ca::24) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|DS0PR12MB7607:EE_ X-MS-Office365-Filtering-Correlation-Id: 8e29a214-41ce-4329-91e6-08dbf1412a6b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: /RJ2KekhIZ/9FvZTbwgp3tGsaW2gq7WODqPGvmzeDxCk+0v0u/c+Y89nkoST/WWkvPvCw7SkEPScltSJiufLl47hdBiukrGJY2Z1yDudK8eAL0LJyiPad3WxmLLzrcOubvSAK1c1MuVqPcVWGIqSRJ0kiIabj32gv+7TlGvPFElgqC7JOaHXTvlWqUxcARkiQS0z6serUy2ChPT5HNJZWeyRhAw2mXwnw0uzGy5Cw4DYZJMbIhOeZHUE8oDMo9nKwRnPcuhYSogcdGq9xMoWNuX1qCOorYwlRZB0atcD3xytrcHGBNi+GVvBKWkaPYnHTzM33B1Vm/GMqeERd4N6inrSJzeIJkR/aEgsUHrQny0z/1SFYdZwfUnqWdIqyuNaTcDvx6cjyToqnKF9zIfNMaDawLV3rWzPCc4YMsQn3qGBW21RakgZlXjlyKcswcJYJsozWZh3n1gvN8r03yg8Px4+svQ39E9dnlYUhozPpLZh3ZC4ONIQyn6/GJQtlMIKv7rWgDg466eD/7pSmO45S5ra9tdb4dh2aroXjSfOXrLZ1PEUYnelXd+7MEHNK5u2jMgmuy7b8QxptGJEchwu2fSus+ZNFSj5kK/83+eClCfKH3nRjafLNSmj+Aya97MntnoQMSkwKhdvVDAyTFCOXQ== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:LV2PR12MB5869.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(396003)(39860400002)(346002)(136003)(366004)(376002)(230922051799003)(186009)(451199024)(64100799003)(1800799012)(38100700002)(202311291699003)(83380400001)(1191002)(5660300002)(110136005)(2906002)(86362001)(4326008)(8676002)(8936002)(66556008)(7366002)(7406005)(7416002)(66476007)(66946007)(6486002)(478600001)(6666004)(316002)(36756003)(6506007)(41300700001)(6512007)(921008)(26005)(2616005);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: mbImv2xeatnCFPsd9Do35WSABEP6L5JyzhkK9KNTExS80+lNlERWh60T46o08+1tBoKrM/maC37DnacXdjqL//8bPhH19ucd82MKskkSGgjoSDxjg3AfuDtuFCM0Q0/7+h9UGVjexvBp1MVrxS1N+xVVQRnMwximw6LuswtoTDxCcP4McOhn2OeufuizSoO7lnmvZ2E9GOUNcGTQEkXDdWO3zv4DPMQ1ZDFMidS9qVL31DKdV/EgKgC22fYRW5Nhw74BhuCuE4W0ODM/LgupUzmsgBm2+cmnDvvkd7FKV7vDBYJ6RonLsrR20nm2NW4tH6W9OiOgy3wC25/7Xba7jaHnT7DhhVu/TThZbiyy5DYIQIpyIme2EQKVf2CMH4bF6ypVshgUSh9bEc8Ku32zZ4IRGXLR8sCu+P3q7tJbBc2Q6aEE0+Y2pHRiHMzvtZt+tM48s7KKVUyMzdio2lBHWeKdLY1TOm9PJDhVOXhJ3eGHN2M2XGtqr+HneC3mo1nJDOfLk97OrtVL+bbffZ7w3BX22P25+DM9ePBSb02PeuNLEe94why6eP13hpjXz7AoFd7rCDGKAGcVxmwHL5JneTe3dO7Dkd5Qw0YP3Ddb/7tNRWAfgR9GgGAIvIDOG6kjFnZMhzntzwy5+wukj2tyX2ELazEGa+Kd8aMqL9RLOAV4a1c0c70jJawRWOxlBrbRf7eQyns2yxn1VCHa3XpS6EUUYsvM0nrChxiXVL52xCGleUamUon6dsyUO9xAxzLVj4Uz94fq9Ezj7OMzdQvupPhrfWz+TOP56A+YWgEJbKSg2SxNri032dje8VBrhsLYi3eXZO+oevJld/uNwT7/Q6QZl0A7AFjpeBxHn7uuwN70s8xIfYds9Oytbh8myqwT4nk1rXhciM4rXn1m28pFYwXNsv4wN/UjEMhb5+YAT3fPukQfBs05ZAsZ5n16Qs2++Bzif8RFG/QlxF71rYLGh5FZq/D1+uD2q7rdvEQECx1242W0BR4SD9skg7V56t4A76rEgf5diPUro21F6+GaTNmrUhSoSPaYFddcTxUi0y4dmdkHSSNIpY+N1JCpEXFwPuLKnn/UbRp1K4Knxl//dTXGDgCA9Gq76Nw232FCy+fcXA2YUmVpPLoMXUNxt+Hka/slaumbCk64R+G6St7OpLptWdByI8ux2iXAi0CKJK5meEJ0pJGHB3uQR1rPYpQy66HVyN1iCoSLD9skLca3PPWlJTW/HcnWOfpMCfbYuXP9fqP+CIY+IwKJ07V99f6YyTLNDJBEvoed8KWBZxQBhr8r5+q3Hy64R4XyuPDAp9atbM+aGceMBhPsWNZNSOrhJr2gPvkMoWLcmDskiCSZ6DdIy5hb35lnwvm5kjx3pFVCInuBxdfcsQM7REmRVeS6pmE8VsBEx/h7cjw5qw9yuZIf0PQN5hYVzI75RP7k7xiZNmZTdW9ElxXSRBXVW/6OV6wbl70fk2bquV3dSOXGoI/IMjEpBcRzYYfaHL4y8nfvzBwMIkcBWaXcwj2m3b2DjR1c+5Y3WBNnuySl9NkumIRRBr1UN5+J2vcDahmj34GFZeiQQPjeYzG0IOSRgBR9 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 8e29a214-41ce-4329-91e6-08dbf1412a6b X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2023 01:10:39.1998 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: xPEmXM+q46raBIV/5oEHOHBYtvZgcViHkkaCMolPMmkVRH+fJO7gv4pqjqkrRr/x X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7607 ipmmmu-vmsa supports a single instance with multiple ids. It has a special check if the device is permitted, move that to the top of probe. Use iommu_of_get_single_iommu() to check and obtain the iommu device. Introduce a per-device data to store the iommu and ids list. Allocate and initialize it with iommu_fw_alloc_per_device_ids(). Remove ipmmu_of_xlate(), ipmmu_init_platform_device(), and to_ipmmu(). Convert the rest of the funcs from calling dev_iommu_fwspec_get() to using the per-device data and remove all use of fwspec. Convert the places using dev_iommu_priv_get() to use the per-device data not the iommu. Signed-off-by: Jason Gunthorpe --- drivers/iommu/ipmmu-vmsa.c | 96 +++++++++++++++++--------------------- 1 file changed, 42 insertions(+), 54 deletions(-) diff --git a/drivers/iommu/ipmmu-vmsa.c b/drivers/iommu/ipmmu-vmsa.c index ace1fc4bd34b0f..ba984017065f98 100644 --- a/drivers/iommu/ipmmu-vmsa.c +++ b/drivers/iommu/ipmmu-vmsa.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -38,6 +39,8 @@ #define IPMMU_UTLB_MAX 64U +static const struct iommu_ops ipmmu_ops; + struct ipmmu_features { bool use_ns_alias_offset; bool has_cache_leaf_nodes; @@ -67,6 +70,12 @@ struct ipmmu_vmsa_device { struct dma_iommu_mapping *mapping; }; +struct ipmmu_vmsa_master { + struct ipmmu_vmsa_device *iommu; + unsigned int num_ids; + u32 ids[] __counted_by(num_ids); +}; + struct ipmmu_vmsa_domain { struct ipmmu_vmsa_device *mmu; struct iommu_domain io_domain; @@ -83,11 +92,6 @@ static struct ipmmu_vmsa_domain *to_vmsa_domain(struct iommu_domain *dom) return container_of(dom, struct ipmmu_vmsa_domain, io_domain); } -static struct ipmmu_vmsa_device *to_ipmmu(struct device *dev) -{ - return dev_iommu_priv_get(dev); -} - #define TLB_LOOP_TIMEOUT 100 /* 100us */ /* ----------------------------------------------------------------------------- @@ -591,9 +595,9 @@ static void ipmmu_domain_free(struct iommu_domain *io_domain) static int ipmmu_attach_device(struct iommu_domain *io_domain, struct device *dev) { - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); - struct ipmmu_vmsa_device *mmu = to_ipmmu(dev); + struct ipmmu_vmsa_master *master = dev_iommu_priv_get(dev); struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain); + struct ipmmu_vmsa_device *mmu = master->iommu; unsigned int i; int ret = 0; @@ -629,8 +633,8 @@ static int ipmmu_attach_device(struct iommu_domain *io_domain, if (ret < 0) return ret; - for (i = 0; i < fwspec->num_ids; ++i) - ipmmu_utlb_enable(domain, fwspec->ids[i]); + for (i = 0; i < master->num_ids; ++i) + ipmmu_utlb_enable(domain, master->ids[i]); return 0; } @@ -639,7 +643,7 @@ static int ipmmu_iommu_identity_attach(struct iommu_domain *identity_domain, struct device *dev) { struct iommu_domain *io_domain = iommu_get_domain_for_dev(dev); - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); + struct ipmmu_vmsa_master *master = dev_iommu_priv_get(dev); struct ipmmu_vmsa_domain *domain; unsigned int i; @@ -647,8 +651,8 @@ static int ipmmu_iommu_identity_attach(struct iommu_domain *identity_domain, return 0; domain = to_vmsa_domain(io_domain); - for (i = 0; i < fwspec->num_ids; ++i) - ipmmu_utlb_disable(domain, fwspec->ids[i]); + for (i = 0; i < master->num_ids; ++i) + ipmmu_utlb_disable(domain, master->ids[i]); /* * TODO: Optimize by disabling the context when no device is attached. @@ -708,20 +712,6 @@ static phys_addr_t ipmmu_iova_to_phys(struct iommu_domain *io_domain, return domain->iop->iova_to_phys(domain->iop, iova); } -static int ipmmu_init_platform_device(struct device *dev, - struct of_phandle_args *args) -{ - struct platform_device *ipmmu_pdev; - - ipmmu_pdev = of_find_device_by_node(args->np); - if (!ipmmu_pdev) - return -ENODEV; - - dev_iommu_priv_set(dev, platform_get_drvdata(ipmmu_pdev)); - - return 0; -} - static const struct soc_device_attribute soc_needs_opt_in[] = { { .family = "R-Car Gen3", }, { .family = "R-Car Gen4", }, @@ -772,24 +762,10 @@ static bool ipmmu_device_is_allowed(struct device *dev) return false; } -static int ipmmu_of_xlate(struct device *dev, - struct of_phandle_args *spec) -{ - if (!ipmmu_device_is_allowed(dev)) - return -ENODEV; - - iommu_fwspec_add_ids(dev, spec->args, 1); - - /* Initialize once - xlate() will call multiple times */ - if (to_ipmmu(dev)) - return 0; - - return ipmmu_init_platform_device(dev, spec); -} - static int ipmmu_init_arm_mapping(struct device *dev) { - struct ipmmu_vmsa_device *mmu = to_ipmmu(dev); + struct ipmmu_vmsa_master *master = dev_iommu_priv_get(dev); + struct ipmmu_vmsa_device *mmu = master->iommu; int ret; /* @@ -831,16 +807,27 @@ static int ipmmu_init_arm_mapping(struct device *dev) return ret; } -static struct iommu_device *ipmmu_probe_device(struct device *dev) +static struct iommu_device *ipmmu_probe_device(struct iommu_probe_info *pinf) { - struct ipmmu_vmsa_device *mmu = to_ipmmu(dev); + struct device *dev = pinf->dev; + struct ipmmu_vmsa_master *master; + struct ipmmu_vmsa_device *mmu; - /* - * Only let through devices that have been verified in xlate() - */ - if (!mmu) + if (!ipmmu_device_is_allowed(dev)) return ERR_PTR(-ENODEV); + mmu = iommu_of_get_single_iommu(pinf, &ipmmu_ops, -1, + struct ipmmu_vmsa_device, iommu); + if (IS_ERR(mmu)) + return ERR_CAST(mmu); + + master = iommu_fw_alloc_per_device_ids(pinf, master); + if (IS_ERR(master)) + return ERR_CAST(master); + master->iommu = mmu; + + dev_iommu_priv_set(dev, master); + return &mmu->iommu; } @@ -857,24 +844,25 @@ static void ipmmu_probe_finalize(struct device *dev) static void ipmmu_release_device(struct device *dev) { - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); - struct ipmmu_vmsa_device *mmu = to_ipmmu(dev); + struct ipmmu_vmsa_master *master = dev_iommu_priv_get(dev); + struct ipmmu_vmsa_device *mmu = master->iommu; unsigned int i; - for (i = 0; i < fwspec->num_ids; ++i) { - unsigned int utlb = fwspec->ids[i]; + for (i = 0; i < master->num_ids; ++i) { + unsigned int utlb = master->ids[i]; ipmmu_imuctr_write(mmu, utlb, 0); mmu->utlb_ctx[utlb] = IPMMU_CTX_INVALID; } arm_iommu_release_mapping(mmu->mapping); + kfree(master); } static const struct iommu_ops ipmmu_ops = { .identity_domain = &ipmmu_iommu_identity_domain, .domain_alloc_paging = ipmmu_domain_alloc_paging, - .probe_device = ipmmu_probe_device, + .probe_device_pinf = ipmmu_probe_device, .release_device = ipmmu_release_device, .probe_finalize = ipmmu_probe_finalize, /* @@ -884,7 +872,7 @@ static const struct iommu_ops ipmmu_ops = { .device_group = IS_ENABLED(CONFIG_ARM) && !IS_ENABLED(CONFIG_IOMMU_DMA) ? generic_device_group : generic_single_device_group, .pgsize_bitmap = SZ_1G | SZ_2M | SZ_4K, - .of_xlate = ipmmu_of_xlate, + .of_xlate = iommu_dummy_of_xlate, .default_domain_ops = &(const struct iommu_domain_ops) { .attach_dev = ipmmu_attach_device, .map_pages = ipmmu_map, From patchwork Thu Nov 30 01:10:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 13473784 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="ZMogeSyr" Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2084.outbound.protection.outlook.com [40.107.243.84]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 91E99D6C; Wed, 29 Nov 2023 17:11:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=DFiLaMzjGL4xIELbk/3RnaadF7Tfu+iR9VKXWTKEAZ2F4ja/LfZ4GKjSJXZOo4IpXkFjmMkFAkd3cy2bChiCBonNSGFhXtDuJRyPRqzdGlZ+aAqxwRCy53iNBmi6rGWuBIMVnFO0SkdOD68iJHRYhA7wrZbpbwsXFU8r7C9CEHJWk6LWyG+3Q5pUgjaCTBTpSsSwoonItEClzOTo5kAWy8390o9KOHgxh3mWO27guITry31ANIFLHGZQKUUX6uEt84z+RAMIPDVc4NunFbYAASpygbrWG9woLFBq6BecMicXCjCuX+6MOw279GRS76AVF5ag/j9n2oyLiSd6TMqbHg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=cmT9sPIBC3zysKQfnRxRs9D8QedigHbyG5FAziwg6D8=; b=eVAvxlujyys66sXmYOzrRr2jGzvDJ6zo/9AnBODykRvLM9MfsxjMXSHNtehLYidXTq417ZbS2fGXyQuCeqZkKp0Dfxi8Kdzcax3CNm3rmR2Q0GoN2et5ZfsSxkxq35BfAnFreZsSjDGjFNfo7kMJ6ka6nM/yRMjRjS4t98hHIbCc+1V7P2losR4bDaad5Hp88/f3oVCuA3K6BFdMXwh4nDUqLC7/rhoO2vsnc0B2eMWYUu0p6vA8YqynS5NyrcbHG7bg5T+4gUTE9kCjHfFf1Y8oUYTpJPtAWk95MjBTNr4RdJ4oJTOzrm7HHZaEKlFUl7gXhC/mnPmCv+aNu9ErUw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=cmT9sPIBC3zysKQfnRxRs9D8QedigHbyG5FAziwg6D8=; b=ZMogeSyrHSb0hQo0F0XwNRHvcxtaitvVGc6td5a+tfeWbdR2ZeIvH2CbNy6j0xUfCqjMBvlPI8YPtw11U56YuMYIYe60a2eU0OYmPfNA+8yg844RJjKPzcq40ecM89e2ZE6v6Fe9EWfqxIFuMzMxPS7KH0LGQhGf/H2plldfHJTv3dwr1+IxoJGNqW4RthYy7FDZKWDN+Ketg/tEDE4jiMLI1j2Kc4YjRMdixA78x6W+ed7nsFWdxoqHzC28JPxK2HgT4i0xUoZqOfW0/a3HZVsIrtpbFAN2hboLMU/9id0K7jjaD7L8kem+W8Mi6Zh/Vi5wusRGuk7dwGHl2Ik9eg== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by PH0PR12MB5484.namprd12.prod.outlook.com (2603:10b6:510:eb::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.24; Thu, 30 Nov 2023 01:10:52 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.7046.015; Thu, 30 Nov 2023 01:10:52 +0000 From: Jason Gunthorpe To: acpica-devel@lists.linux.dev, Andy Gross , Alim Akhtar , Alyssa Rosenzweig , Bjorn Andersson , AngeloGioacchino Del Regno , asahi@lists.linux.dev, Baolin Wang , devicetree@vger.kernel.org, Frank Rowand , Hanjun Guo , "Gustavo A. R. Silva" , Heiko Stuebner , iommu@lists.linux.dev, Jean-Philippe Brucker , Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kees Cook , Konrad Dybcio , Krzysztof Kozlowski , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Lorenzo Pieralisi , Marek Szyprowski , Hector Martin , Matthias Brugger , Orson Zhai , "Rafael J. Wysocki" , Rob Clark , Robert Moore , Rob Herring , Robin Murphy , Samuel Holland , Sudeep Holla , Sven Peter , Thierry Reding , Krishna Reddy , virtualization@lists.linux.dev, Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: =?utf-8?q?Andr=C3=A9_Draszik?= , patches@lists.linux.dev Subject: [PATCH 21/30] iommu/mtk_v1: Move to iommu_fw_alloc_per_device_ids() Date: Wed, 29 Nov 2023 21:10:28 -0400 Message-ID: <21-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> In-Reply-To: <0-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> References: X-ClientProxiedBy: SN7P222CA0016.NAMP222.PROD.OUTLOOK.COM (2603:10b6:806:124::16) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|PH0PR12MB5484:EE_ X-MS-Office365-Filtering-Correlation-Id: 4c71b8dc-de76-4503-8d14-08dbf1412c30 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: a6a2zUzjdjhRFCvzaWHAMi0z+IrR0x1ELp0Z/kqamgLbcrGLNLm5x+99P9dFvMlK5kyCHp4CSZOvcBHxJdGwqlmBgR57ITxcianUOMXJKfIuA0lQbdzxme/r8bblr/xIPN9DujxMJ5dOF0xsGqxI1nqmLToNPmI7h8iyrAxcbtRVKtogWNzMK3H6KeXbaUQaOPWKg+Q9ud1hGMibZNWu3MBXNqWXW3nn/Z7BX6qb2YTwdO9k+2k0KvyOcboo/+QydAuhFeCocGAd1IzlDsIGrUa/oOUwPb7WV4PDE/MP9h2+DyOWc50COWmQ2W6Gq5YxJmSJ3EuNANDMSepEtuZ8+M6Cx6FrR4Y0QS5jL9rsQMtpJM+/ZpRfsfNIeZpq2Tl9yzhXEhrL5JuCuppthJd62lc8SI3BEWMaVf2f6+cahOa4hAYZeIHOen527AEZCDtP91W133xAsGEU5aAWGJowK6YsqRG5Btbstn4foLy7QVHmwUJsE+qSe825JAjZM5Kxu7/8P3EeGeg2W+cw51TgrWmD4lU2km61jCaCzrUYx9hhcwJESZS54FQthWWT5dB5nawp7c+Z/pg5YFOnwrE8AtbrqRxmFOR6214NVjNqwF/Gvp5fk1yG5jxOl6YDt+tIzSpx9/tRdQM5tnWqsUX+WQ== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:LV2PR12MB5869.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(366004)(346002)(136003)(396003)(39860400002)(376002)(230922051799003)(451199024)(1800799012)(186009)(64100799003)(1191002)(8936002)(110136005)(8676002)(316002)(66556008)(4326008)(86362001)(66476007)(6486002)(478600001)(66946007)(41300700001)(36756003)(921008)(7416002)(7366002)(2906002)(7406005)(5660300002)(38100700002)(2616005)(6512007)(6506007)(6666004)(83380400001)(26005)(202311291699003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: jhN5h5ieux9M+dWgHi4UApksQ0EusFtgK1UZAIVELUXyDe1tP3dmpPES4iuNEvcD7oGuslGk3KrvnSaJCkv6kEfwhJYthX/LLhVXPbbiuDIK1AM9RlvncOplNHHYq0x9JVWmtbt7hmkdt2JP95C7cXwW9YT661iQzw01fn67su7f/7Xun81Kf06jlu9QoM/ye3xEKzq/aYk1S/S5QbAtGMViHyHERD18mwJPbJHcWuy/7YjUtKvLtpsbl+F3PMxKx8IxdIqCq+RhIODlP3ijl44ZdiSnQqpUSYBu2iT3/LJsd0MQWCmqylOk+CLU595VM5rrFLr63dFpKNW8lFMy6J8frFO0JXN2xds6XhzQJLet8pv/58BGRVbflDGTjT1iek2RW8rCxIInt4prGmWDmO/X1aglW85M4532vIV2rLLvBkf3G3NtlRVq+UGMWAaawrGDT4vIj4Q7yMaMC+/ys+NpSzXxAVcM9Y3qtJqwfWHhywVFbxVkXl5WgkEjmTYD3tWAcNzrknntLJ9l69zicZtxW0h3KAYwXsNGunfQ4FquPbl116mnX5mfBcv75v3Gp/PJbQ5PpZiezZ60sHby2c8KlGIsGHLMAFIFQcOCybgJ+JOYh0JfMikj+JfRSCWJ6MRkSioFecUL4rlEPTXIOnbg+kitAJzH46wl8/Kd9/kafU0711KDF9s88vwf2/WH7Kk5mUNIwLatGsDrUM4aXisW0+Tr1KJbGsSw8Yodl63iXm9DLFHD/QmND+fmY0sSCsRzKoF1fMBX8tIOY1tUp/rUYS0U2iz+4vffh5ZWW/qby01V0crlZ0gIeKyfBwy+sJVT1GyW+SwgoGH0zc2xTwwyI7pBJZqTuYOIYzfbb3dVovXdBhZYoCIy0inujeL7ONBdcGE28mX4Rb4Z4hBgHIg1/1w2ZXam0kHeBlOM9i9k+Pl4lXI2UW9DCJinybbej5Akjq6jwypN6dr4d9qZLGNPiEYyCyN+fjKac1DrF/o493sKT660HuuwOgpQtTRNcFwG90rZJokbWk5N5yEiNtYeWW/xiZ1W8fnWjWSgK4fI/CYj3QfnU6jI2hkQkehnXVUcgbpAwmu/JV9tAm/SAoJoW7gEU5pc2QI0qQvGof0mC9fW3RyHZv/L9Yvh080++5wnPDy7lpYL8kGfgWuYFTpGuPaF8vfzIJKxn+y9u/4P+oZ2l8ZBCamzvAp6j/QHJZAr4vnvAsfS/glOSBqfEAwWKnsT588lx96k21xrDidWfHkOUOYB+lBSp/OwEshB/0cKpEut51cABZOkrc0Xe1/4BF7K4+kxphRQf8GgUmnG7O78hVUrY9lzIYTbBYnuoYou45bhFSWCt1HQFc3mXVN4bIBlO48ZeYSpx/tN8zhkbmPuuGz9hWECWou098OEUm8kvfm+VLUsKlNraHLBM+1gHbfTGhXe4v6nvBCeGzat9Cs4C9EEMGSk8h8YLzjVJVSTLNWNQUPG9PRXzPYyq8DZSkCI+Py/qWvZJBOpk5BTE//wxfHS/sdGqxbDo1mYDFD1F8d4KAB/wOoGeVlXKFGTUUWdBOY9wnu7+fmf2KgHTGbzhphf2dAl7FVq07Z9 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4c71b8dc-de76-4503-8d14-08dbf1412c30 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2023 01:10:42.1282 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 1lrE0VFQK0CIwfE+Q2VPQVeLKyz3T+ah96t1DC1KIqTlf0zqIzfcMYfwD3xMmls2 X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5484 mtk_v1 supports a single iommu instance with multiple ids. It open codes the fwspec parse inside the driver, remove all of this and just call iommu_of_get_single_iommu() to do the same parsing. Using iommu_of_allow_bus_probe() so this continues to work at bus probe time. Introduce a per-device data to store the iommu and ids list. Allocate and initialize it with iommu_fw_alloc_per_device_ids(). Fold mtk_iommu_v1_create_mapping() into mtk_iommu_v1_probe_device() as it is done only once per device. Fix the error handling so we don't leak mappings on error paths. Convert the rest of the funcs from calling dev_iommu_fwspec_get() to using the per-device data and remove all use of fwspec. Convert the places using dev_iommu_priv_get() to use the per-device data not the iommu. Signed-off-by: Jason Gunthorpe --- drivers/iommu/mtk_iommu_v1.c | 162 +++++++++++++++-------------------- 1 file changed, 67 insertions(+), 95 deletions(-) diff --git a/drivers/iommu/mtk_iommu_v1.c b/drivers/iommu/mtk_iommu_v1.c index 25b41222abaec1..82f500a1ad74e9 100644 --- a/drivers/iommu/mtk_iommu_v1.c +++ b/drivers/iommu/mtk_iommu_v1.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -108,6 +109,12 @@ struct mtk_iommu_v1_data { struct mtk_iommu_v1_suspend_reg reg; }; +struct mtk_iommu_v1_device { + struct mtk_iommu_v1_data *iommu; + unsigned int num_ids; + u32 ids[] __counted_by(num_ids); +}; + struct mtk_iommu_v1_domain { spinlock_t pgtlock; /* lock for page table */ struct iommu_domain domain; @@ -232,14 +239,14 @@ static irqreturn_t mtk_iommu_v1_isr(int irq, void *dev_id) static void mtk_iommu_v1_config(struct mtk_iommu_v1_data *data, struct device *dev, bool enable) { + struct mtk_iommu_v1_device *mdev = dev_iommu_priv_get(dev); struct mtk_smi_larb_iommu *larb_mmu; unsigned int larbid, portid; - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); int i; - for (i = 0; i < fwspec->num_ids; ++i) { - larbid = mt2701_m4u_to_larb(fwspec->ids[i]); - portid = mt2701_m4u_to_port(fwspec->ids[i]); + for (i = 0; i < mdev->num_ids; ++i) { + larbid = mt2701_m4u_to_larb(mdev->ids[i]); + portid = mt2701_m4u_to_port(mdev->ids[i]); larb_mmu = &data->larb_imu[larbid]; dev_dbg(dev, "%s iommu port: %d\n", @@ -293,7 +300,8 @@ static void mtk_iommu_v1_domain_free(struct iommu_domain *domain) static int mtk_iommu_v1_attach_device(struct iommu_domain *domain, struct device *dev) { - struct mtk_iommu_v1_data *data = dev_iommu_priv_get(dev); + struct mtk_iommu_v1_device *mdev = dev_iommu_priv_get(dev); + struct mtk_iommu_v1_data *data = mdev->iommu; struct mtk_iommu_v1_domain *dom = to_mtk_domain(domain); struct dma_iommu_mapping *mtk_mapping; int ret; @@ -319,7 +327,8 @@ static int mtk_iommu_v1_attach_device(struct iommu_domain *domain, struct device static int mtk_iommu_v1_identity_attach(struct iommu_domain *identity_domain, struct device *dev) { - struct mtk_iommu_v1_data *data = dev_iommu_priv_get(dev); + struct mtk_iommu_v1_device *mdev = dev_iommu_priv_get(dev); + struct mtk_iommu_v1_data *data = mdev->iommu; mtk_iommu_v1_config(data, dev, false); return 0; @@ -394,128 +403,91 @@ static phys_addr_t mtk_iommu_v1_iova_to_phys(struct iommu_domain *domain, dma_ad static const struct iommu_ops mtk_iommu_v1_ops; -/* - * MTK generation one iommu HW only support one iommu domain, and all the client - * sharing the same iova address space. - */ -static int mtk_iommu_v1_create_mapping(struct device *dev, struct of_phandle_args *args) +static struct iommu_device * +mtk_iommu_v1_probe_device(struct iommu_probe_info *pinf) { - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); - struct mtk_iommu_v1_data *data; - struct platform_device *m4updev; struct dma_iommu_mapping *mtk_mapping; + struct mtk_iommu_v1_device *mdev; + struct device *dev = pinf->dev; + struct mtk_iommu_v1_data *data; + int idx, larbid, larbidx; + struct device_link *link; + struct device *larbdev; int ret; - if (args->args_count != 1) { - dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n", - args->args_count); - return -EINVAL; - } + iommu_of_allow_bus_probe(pinf); + data = iommu_of_get_single_iommu(pinf, &mtk_iommu_v1_ops, 1, + struct mtk_iommu_v1_data, iommu); + if (IS_ERR(data)) + return ERR_CAST(data); - if (!fwspec) { - ret = iommu_fwspec_init(dev, &args->np->fwnode, &mtk_iommu_v1_ops); - if (ret) - return ret; - fwspec = dev_iommu_fwspec_get(dev); - } else if (dev_iommu_fwspec_get(dev)->ops != &mtk_iommu_v1_ops) { - return -EINVAL; - } + mdev = iommu_fw_alloc_per_device_ids(pinf, mdev); + if (IS_ERR(mdev)) + return ERR_CAST(mdev); + mdev->iommu = data; - if (!dev_iommu_priv_get(dev)) { - /* Get the m4u device */ - m4updev = of_find_device_by_node(args->np); - if (WARN_ON(!m4updev)) - return -EINVAL; - - dev_iommu_priv_set(dev, platform_get_drvdata(m4updev)); - } - - ret = iommu_fwspec_add_ids(dev, args->args, 1); - if (ret) - return ret; - - data = dev_iommu_priv_get(dev); + /* + * MTK generation one iommu HW only support one iommu domain, and all + * the client sharing the same iova address space. + */ mtk_mapping = data->mapping; if (!mtk_mapping) { /* MTK iommu support 4GB iova address space. */ mtk_mapping = arm_iommu_create_mapping(&platform_bus_type, 0, 1ULL << 32); - if (IS_ERR(mtk_mapping)) - return PTR_ERR(mtk_mapping); + if (IS_ERR(mtk_mapping)) { + ret = PTR_ERR(mtk_mapping); + goto err_free; + } data->mapping = mtk_mapping; } - return 0; -} - -static struct iommu_device *mtk_iommu_v1_probe_device(struct device *dev) -{ - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); - struct of_phandle_args iommu_spec; - struct mtk_iommu_v1_data *data; - int err, idx = 0, larbid, larbidx; - struct device_link *link; - struct device *larbdev; - - /* - * In the deferred case, free the existed fwspec. - * Always initialize the fwspec internally. - */ - if (fwspec) { - iommu_fwspec_free(dev); - fwspec = dev_iommu_fwspec_get(dev); - } - - while (!of_parse_phandle_with_args(dev->of_node, "iommus", - "#iommu-cells", - idx, &iommu_spec)) { - - err = mtk_iommu_v1_create_mapping(dev, &iommu_spec); - of_node_put(iommu_spec.np); - if (err) - return ERR_PTR(err); - - /* dev->iommu_fwspec might have changed */ - fwspec = dev_iommu_fwspec_get(dev); - idx++; - } - - data = dev_iommu_priv_get(dev); - /* Link the consumer device with the smi-larb device(supplier) */ - larbid = mt2701_m4u_to_larb(fwspec->ids[0]); - if (larbid >= MT2701_LARB_NR_MAX) - return ERR_PTR(-EINVAL); + larbid = mt2701_m4u_to_larb(mdev->ids[0]); + if (larbid >= MT2701_LARB_NR_MAX) { + ret = -EINVAL; + goto err_mapping; + } - for (idx = 1; idx < fwspec->num_ids; idx++) { - larbidx = mt2701_m4u_to_larb(fwspec->ids[idx]); + for (idx = 1; idx < mdev->num_ids; idx++) { + larbidx = mt2701_m4u_to_larb(mdev->ids[idx]); if (larbid != larbidx) { dev_err(dev, "Can only use one larb. Fail@larb%d-%d.\n", larbid, larbidx); - return ERR_PTR(-EINVAL); + ret = -EINVAL; + goto err_mapping; } } larbdev = data->larb_imu[larbid].dev; - if (!larbdev) - return ERR_PTR(-EINVAL); + if (!larbdev) { + ret = -EINVAL; + goto err_mapping; + } link = device_link_add(dev, larbdev, DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS); if (!link) dev_err(dev, "Unable to link %s\n", dev_name(larbdev)); + dev_iommu_priv_set(pinf->dev, mdev); return &data->iommu; + +err_mapping: + arm_iommu_release_mapping(mtk_mapping); +err_free: + kfree(mdev); + return ERR_PTR(ret); } static void mtk_iommu_v1_probe_finalize(struct device *dev) { + struct mtk_iommu_v1_device *mdev = dev_iommu_priv_get(dev); + struct mtk_iommu_v1_data *data = mdev->iommu; struct dma_iommu_mapping *mtk_mapping; - struct mtk_iommu_v1_data *data; int err; - data = dev_iommu_priv_get(dev); mtk_mapping = data->mapping; err = arm_iommu_attach_device(dev, mtk_mapping); @@ -525,15 +497,15 @@ static void mtk_iommu_v1_probe_finalize(struct device *dev) static void mtk_iommu_v1_release_device(struct device *dev) { - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); - struct mtk_iommu_v1_data *data; + struct mtk_iommu_v1_device *mdev = dev_iommu_priv_get(dev); + struct mtk_iommu_v1_data *data = mdev->iommu; struct device *larbdev; unsigned int larbid; - data = dev_iommu_priv_get(dev); - larbid = mt2701_m4u_to_larb(fwspec->ids[0]); + larbid = mt2701_m4u_to_larb(mdev->ids[0]); larbdev = data->larb_imu[larbid].dev; device_link_remove(dev, larbdev); + kfree(mdev); } static int mtk_iommu_v1_hw_init(const struct mtk_iommu_v1_data *data) @@ -580,7 +552,7 @@ static int mtk_iommu_v1_hw_init(const struct mtk_iommu_v1_data *data) static const struct iommu_ops mtk_iommu_v1_ops = { .identity_domain = &mtk_iommu_v1_identity_domain, .domain_alloc_paging = mtk_iommu_v1_domain_alloc_paging, - .probe_device = mtk_iommu_v1_probe_device, + .probe_device_pinf = mtk_iommu_v1_probe_device, .probe_finalize = mtk_iommu_v1_probe_finalize, .release_device = mtk_iommu_v1_release_device, .device_group = generic_device_group, From patchwork Thu Nov 30 01:10:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 13473777 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="qUzNgBO+" Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2084.outbound.protection.outlook.com [40.107.243.84]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A04B310A; Wed, 29 Nov 2023 17:11:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=USTuXHmK9Yve50+rPdo4WGbIIiOmphE+Th3lmWyNB9fKIhzYZWaqYFffCAKvhey4k0suO1/Idem4tgdD7VLTDmwdvj/K/Zc/4tLUigtwcd/y43+e9yjqdo4+gq6kkdvTUzeeeezN1gGv8RjeKrBuEajHJ58NmDHQ5SL4aE+nBNvbCzPQ17fSjXCFnA9jzpsDcTPoo13NOS2IfBwp0YuRIP3kCbLBonQzJHStxg+EvYwANjuCpQ19Fj1Lve/qr2B5rha4EpMGMsQW0UTNdqt+21oD/uYL0UeZTV1ELRu/SqA04J+s//h8oAWCF6zlsJ32yWB5YdDyvvuuFULnpv+jVA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=fVSr9+bQP69hK+Giq+u9FoxDlVZiQRDX7oYqcWOEYLw=; b=RfuNUbceIX+fMVB/97Y19iu5ygkF5v5OMMyjLkYVPv5zAbbswGJRtbcXLJy0plggwoR1ofaMwXZZBbMi92MIFIwnqDSwVZeEuAdmcpxYkEM09pf2RrpySoQuJhU4gEcpvzLb/P8X6Lcqy9Oz3/rKO3Y6JyvxApgwD8sMxvBBDDTeZhEgEkpBtmu81IKCeh37YcvfEeJiZAnPchRuMpcMqFIZjVvQNotpwQ4ZCIfo1Fe9Wmr+tT+Qpg95EQR+cqu95s5lZnYmqSUAfvOXS357aNJ6byWmJx9pDWVE9LjaEUdauRPkyJxRO1APrSqErSYWGkG3PeDCWQt2dmqwfTuF6Q== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=fVSr9+bQP69hK+Giq+u9FoxDlVZiQRDX7oYqcWOEYLw=; b=qUzNgBO+o7gXJ1qy8tdR1rnxs4iyg4ZBn7GmWgXmnhP2WMGfJYK2NhgvSm0AqDPuPGbX0Sz5PaeGEPeRutml62wF92HXfVT5nHA5PR+PyULp44S6ER4d+8rPBwch4KPdxum5ITHjapFNaGS1B37+PTulaGnE55N0Gqe5d3GaMn7x6kk9YlrWzo8K4djwWMdoAnLrwOhaP+JXIvAA7kOPv7BBpcZaugR0CbkUbnPdRrocg8Ve5qmkw+ZiVrtd6aFprMs4hkf5zryIBTpp9+FLmSMxxa6cA016W9FY5KlhE+N38icGnuda3TAsLuG29RtNRjmGcAYHiizAiHlJ3JjU5A== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by PH0PR12MB5484.namprd12.prod.outlook.com (2603:10b6:510:eb::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.24; Thu, 30 Nov 2023 01:10:50 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.7046.015; Thu, 30 Nov 2023 01:10:50 +0000 From: Jason Gunthorpe To: acpica-devel@lists.linux.dev, Andy Gross , Alim Akhtar , Alyssa Rosenzweig , Bjorn Andersson , AngeloGioacchino Del Regno , asahi@lists.linux.dev, Baolin Wang , devicetree@vger.kernel.org, Frank Rowand , Hanjun Guo , "Gustavo A. R. Silva" , Heiko Stuebner , iommu@lists.linux.dev, Jean-Philippe Brucker , Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kees Cook , Konrad Dybcio , Krzysztof Kozlowski , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Lorenzo Pieralisi , Marek Szyprowski , Hector Martin , Matthias Brugger , Orson Zhai , "Rafael J. Wysocki" , Rob Clark , Robert Moore , Rob Herring , Robin Murphy , Samuel Holland , Sudeep Holla , Sven Peter , Thierry Reding , Krishna Reddy , virtualization@lists.linux.dev, Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: =?utf-8?q?Andr=C3=A9_Draszik?= , patches@lists.linux.dev Subject: [PATCH 22/30] iommu/qcom: Move to iommu_fw_alloc_per_device_ids() Date: Wed, 29 Nov 2023 21:10:29 -0400 Message-ID: <22-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> In-Reply-To: <0-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> References: X-ClientProxiedBy: SN1PR12CA0110.namprd12.prod.outlook.com (2603:10b6:802:21::45) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|PH0PR12MB5484:EE_ X-MS-Office365-Filtering-Correlation-Id: 724c4ab5-7a07-4e75-5bae-08dbf1412b96 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: O+TTURoAd06a5nhc1hEqPMI3UF8xNQp/QEVs/OUUBk0iMdto60WmWpf0sfwLRxPgM1BswcDjOFzMZx/5EE0DCvqWUNUGIP7cP+8bGBieThqSlPuA7qKb3DdTBxPgZzWsZ2ad4o0usd2s0iGKLXdw6Duqld/uNibwRtS10IRhkVxe8pgTKJ6pThePbAAEHB0fEYNbAWAlFKa9O1+jrjKeYWMvt4cxZeW0Z8fuoV3BmuRIYGYy+YNxYJs3vp2iJsmrKj5gm5hVv8/yMhSH/6OteNodtVk5QWub0hg2h5ZAZv+h+jh0GrLCYG5ZKTs6g2rB/1Lxc/+enNHqRU7Q8EOiF9+Gz7Q9LJ4MzLcH+7lI6NuuK8pK0V0pytzM1220Y0lkDfjhkEfVl9KVlKDTJVozKo2kF6vsiKI1Ge9F2dNdGYQULwTsrwWExe4do2X2vmy96DkOrRTU88xIqPrYguEMepRXMes+ZNJFZxi6uvTl14mdPgjlnA20EWX4kSQ4Ju8Z+JCotFAx7NmaYU48A3HT4bImxGGSX3ucqu1HrY7cLGw2POV7xR26GUCGvUy+AbU0+LGp+FdyU432yfHwR+G2oWxy5QQqEPD1HvuDmcdEKqEdH8TSnDlyUCBdWo1xi40I6gAo8qPCbXlrfA7NClCCsw== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:LV2PR12MB5869.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(366004)(346002)(136003)(396003)(39860400002)(376002)(230922051799003)(451199024)(1800799012)(186009)(64100799003)(1191002)(8936002)(110136005)(8676002)(316002)(66556008)(4326008)(86362001)(66476007)(6486002)(478600001)(66946007)(41300700001)(36756003)(921008)(30864003)(7416002)(7366002)(2906002)(7406005)(5660300002)(38100700002)(2616005)(6512007)(6506007)(6666004)(83380400001)(26005)(202311291699003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: vEIPybqBLOiEuo3wsynDBlSBXaFbdYbgJaHD2oWwfj+LAKucVu0ZJpP3YhRqX0PGwcQOcTzO5ihXrB46zlTwSqguYit90dUKLwjVdoOuNPzhYAipOMOb+4LmbE0pnGXxEQ7sSmcBHtNYr/wSFjYvmXSSpY/CPvf+pIaJqcWB0MRWc8Ma+og2CipW+bze01eNmWb2JZOqUCMNh9CPFRwj1xsIHzSzGcZ84ssKj4GRrUaKkTAW/mdOvwdX8PmdvTffsjNZqJJe5bJA5vjCSupEE6aHODwB5JLf9A1v4t7Xo17oM2GFVMZQw3Bpvrcj+0CNIeukF+KDsWsCTTNb+iFBg2UbKoOl1gDNqjkt+VJujaOWwaD5xtiA2Ud56vA1e7aXFU/+NDM/DvCmhRweJ2FV3B6UQVoPPqBG5Fhp2sUygZqUVZ1HWIW3/UE/JhYvhRB943UGO3GrfWleyY/qmCBLKc5tI08eukC3hPpxiWKs3umDUHQeIM4VZvSOzOXVDEm/gNGFBtCGRoGOcF29Ozfx3dqFL80zw/Qic4xYFBR0qUdA+uS/RL62GwEO0wU5WwJRfyj9d5kY5+o3wIPp0c0+xTJgpbJ9L7HMdoruiBRaQos9Bmi0pE9TQbANrJ8i0sEZ0smGeiKKKLNOrzPT5mQktpEXGyacpSS+uqiCr0sAITBBn9oWYVZgdejrnDodhliZ6qWn0cyBKp0huiJswQclonOJV9Gr7Swx8QvXH1TC9WCO8KWOC6R+Qe52ZBq+LI47S92ccuchTKTqORKcf+l8GkZRDKUv9sSs1NsTtvOU4k/M48X2txz3i5Ertm2YS/GOi99/Rzzu6FFjMNHV2R5amjd+AaRYTM7VEdwpqrU6aD5xRbsJMHKJZj/CKHf6yYKeCMRLSfSb/X5cLern8NsVvR8eLxy/WZx5vbo3SfjUFqah8S2sjf7D0qRBcUwnKf0iIh+dwPV+pUhtcqjIflfYC9NhKKBqBl1g2Y2AGIqXnWdYzQVvkor7o5kj/h9hczJC1QlS7xSm2F9GUIaCy4AxLlqtc9Pz3nE9EiULD/Ppe+bXceBRf6GHnvuTd+bxm23VJ8UYRwouOsQyzhEN3CRgHc1ipRERxmhyUn77WAI+HtusSeofn3kiRcKiEnKqMSWiwdLl7f5xbhi7n1CudL5CiuvGhn5DQMGlgZ+8kBqw/bzF2GgtV3uCe9V7V2U1HjZvgNblTMReqd/QlWVc+AfPaONwwXLSKdKR8Y8Iwxk/Ag8GkYOODVGlRFrITOj4h7G56UM8K6oqkpuxIso+bQO6CuIowpCLZnnSgUb6H5O/uXaBlpPQb/9QKo8qw/C3FB/Q6oQ4BDa6DQTOQ8oFWfvLVTDHoCxeIFWqDVIQBNBGymISE3KF2l4w3lfMWhfyzIiH8A6oB3Ml4V5SE4OeEJyWFvETCMvJQZmgGSfp90tVOPQvuMLPIk5XA6scj++xIh2Y3wj9TY7cqgEmSfWlM6B9MaOkItm/PIbls66OU8DWYA1+WVwMevvxeDZ/fwpURfbyjeqfadUKrdMV+E+9i5l8M7SLrznQxtKTDoqjeyh2iEKdjK5Q2Csv0oqrHtMYzXp5 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 724c4ab5-7a07-4e75-5bae-08dbf1412b96 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2023 01:10:41.1568 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: iHNY0/XFKudzaiQDGPMOffWaW/5YTl7Yg2HEy+dh2h1S10ihP0NQa7LaOTuM9PsT X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5484 qcom supports a single iommu instance with multiple ids. Introduce a per-device data to store the iommu and ids list. Allocate and initialize it with iommu_fw_alloc_per_device_ids(). Remove qcom_iommu_of_xlate(). This already was checking that all instances are the same, it is now done in common code. Convert the rest of the funcs from calling dev_iommu_fwspec_get() to using the per-device data and remove all use of fwspec. Store the per-dev data in the qcom_iommu_domain instead of the iommu and fwspec pointers. Convert the places using dev_iommu_priv_get() to use the per-device data not the iommu. Remove to_iommu(). Signed-off-by: Jason Gunthorpe --- drivers/iommu/arm/arm-smmu/qcom_iommu.c | 161 ++++++++++++------------ 1 file changed, 81 insertions(+), 80 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu/qcom_iommu.c b/drivers/iommu/arm/arm-smmu/qcom_iommu.c index 33f3c870086cea..4baca45df99971 100644 --- a/drivers/iommu/arm/arm-smmu/qcom_iommu.c +++ b/drivers/iommu/arm/arm-smmu/qcom_iommu.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -54,6 +55,12 @@ struct qcom_iommu_dev { struct qcom_iommu_ctx *ctxs[]; /* indexed by asid */ }; +struct qcom_iommu_master { + struct qcom_iommu_dev *iommu; + unsigned int num_ids; + u32 ids[] __counted_by(num_ids); +}; + struct qcom_iommu_ctx { struct device *dev; void __iomem *base; @@ -68,8 +75,7 @@ struct qcom_iommu_domain { spinlock_t pgtbl_lock; struct mutex init_mutex; /* Protects iommu pointer */ struct iommu_domain domain; - struct qcom_iommu_dev *iommu; - struct iommu_fwspec *fwspec; + struct qcom_iommu_master *master; }; static struct qcom_iommu_domain *to_qcom_iommu_domain(struct iommu_domain *dom) @@ -81,7 +87,7 @@ static const struct iommu_ops qcom_iommu_ops; static struct qcom_iommu_ctx * to_ctx(struct qcom_iommu_domain *d, unsigned asid) { - struct qcom_iommu_dev *qcom_iommu = d->iommu; + struct qcom_iommu_dev *qcom_iommu = d->master->iommu; if (!qcom_iommu) return NULL; return qcom_iommu->ctxs[asid]; @@ -114,11 +120,11 @@ iommu_readq(struct qcom_iommu_ctx *ctx, unsigned reg) static void qcom_iommu_tlb_sync(void *cookie) { struct qcom_iommu_domain *qcom_domain = cookie; - struct iommu_fwspec *fwspec = qcom_domain->fwspec; + struct qcom_iommu_master *master = qcom_domain->master; unsigned i; - for (i = 0; i < fwspec->num_ids; i++) { - struct qcom_iommu_ctx *ctx = to_ctx(qcom_domain, fwspec->ids[i]); + for (i = 0; i < master->num_ids; i++) { + struct qcom_iommu_ctx *ctx = to_ctx(qcom_domain, master->ids[i]); unsigned int val, ret; iommu_writel(ctx, ARM_SMMU_CB_TLBSYNC, 0); @@ -133,11 +139,11 @@ static void qcom_iommu_tlb_sync(void *cookie) static void qcom_iommu_tlb_inv_context(void *cookie) { struct qcom_iommu_domain *qcom_domain = cookie; - struct iommu_fwspec *fwspec = qcom_domain->fwspec; + struct qcom_iommu_master *master = qcom_domain->master; unsigned i; - for (i = 0; i < fwspec->num_ids; i++) { - struct qcom_iommu_ctx *ctx = to_ctx(qcom_domain, fwspec->ids[i]); + for (i = 0; i < master->num_ids; i++) { + struct qcom_iommu_ctx *ctx = to_ctx(qcom_domain, master->ids[i]); iommu_writel(ctx, ARM_SMMU_CB_S1_TLBIASID, ctx->asid); } @@ -148,13 +154,13 @@ static void qcom_iommu_tlb_inv_range_nosync(unsigned long iova, size_t size, size_t granule, bool leaf, void *cookie) { struct qcom_iommu_domain *qcom_domain = cookie; - struct iommu_fwspec *fwspec = qcom_domain->fwspec; + struct qcom_iommu_master *master = qcom_domain->master; unsigned i, reg; reg = leaf ? ARM_SMMU_CB_S1_TLBIVAL : ARM_SMMU_CB_S1_TLBIVA; - for (i = 0; i < fwspec->num_ids; i++) { - struct qcom_iommu_ctx *ctx = to_ctx(qcom_domain, fwspec->ids[i]); + for (i = 0; i < master->num_ids; i++) { + struct qcom_iommu_ctx *ctx = to_ctx(qcom_domain, master->ids[i]); size_t s = size; iova = (iova >> 12) << 12; @@ -218,14 +224,14 @@ static int qcom_iommu_init_domain(struct iommu_domain *domain, struct device *dev) { struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain); - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); + struct qcom_iommu_master *master = dev_iommu_priv_get(dev); struct io_pgtable_ops *pgtbl_ops; struct io_pgtable_cfg pgtbl_cfg; int i, ret = 0; u32 reg; mutex_lock(&qcom_domain->init_mutex); - if (qcom_domain->iommu) + if (qcom_domain->master) goto out_unlock; pgtbl_cfg = (struct io_pgtable_cfg) { @@ -236,8 +242,7 @@ static int qcom_iommu_init_domain(struct iommu_domain *domain, .iommu_dev = qcom_iommu->dev, }; - qcom_domain->iommu = qcom_iommu; - qcom_domain->fwspec = fwspec; + qcom_domain->master = master; pgtbl_ops = alloc_io_pgtable_ops(ARM_32_LPAE_S1, &pgtbl_cfg, qcom_domain); if (!pgtbl_ops) { @@ -251,8 +256,8 @@ static int qcom_iommu_init_domain(struct iommu_domain *domain, domain->geometry.aperture_end = (1ULL << pgtbl_cfg.ias) - 1; domain->geometry.force_aperture = true; - for (i = 0; i < fwspec->num_ids; i++) { - struct qcom_iommu_ctx *ctx = to_ctx(qcom_domain, fwspec->ids[i]); + for (i = 0; i < master->num_ids; i++) { + struct qcom_iommu_ctx *ctx = to_ctx(qcom_domain, master->ids[i]); if (!ctx->secure_init) { ret = qcom_scm_restore_sec_cfg(qcom_iommu->sec_id, ctx->asid); @@ -316,7 +321,7 @@ static int qcom_iommu_init_domain(struct iommu_domain *domain, return 0; out_clear_iommu: - qcom_domain->iommu = NULL; + qcom_domain->master = NULL; out_unlock: mutex_unlock(&qcom_domain->init_mutex); return ret; @@ -345,16 +350,16 @@ static void qcom_iommu_domain_free(struct iommu_domain *domain) { struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain); - if (qcom_domain->iommu) { + if (qcom_domain->master) { /* * NOTE: unmap can be called after client device is powered * off, for example, with GPUs or anything involving dma-buf. * So we cannot rely on the device_link. Make sure the IOMMU * is on to avoid unclocked accesses in the TLB inv path: */ - pm_runtime_get_sync(qcom_domain->iommu->dev); + pm_runtime_get_sync(qcom_domain->master->iommu->dev); free_io_pgtable_ops(qcom_domain->pgtbl_ops); - pm_runtime_put_sync(qcom_domain->iommu->dev); + pm_runtime_put_sync(qcom_domain->master->iommu->dev); } kfree(qcom_domain); @@ -362,7 +367,8 @@ static void qcom_iommu_domain_free(struct iommu_domain *domain) static int qcom_iommu_attach_dev(struct iommu_domain *domain, struct device *dev) { - struct qcom_iommu_dev *qcom_iommu = dev_iommu_priv_get(dev); + struct qcom_iommu_master *master = dev_iommu_priv_get(dev); + struct qcom_iommu_dev *qcom_iommu = master->iommu; struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain); int ret; @@ -382,7 +388,7 @@ static int qcom_iommu_attach_dev(struct iommu_domain *domain, struct device *dev * Sanity check the domain. We don't support domains across * different IOMMUs. */ - if (qcom_domain->iommu != qcom_iommu) + if (qcom_domain->master->iommu != qcom_iommu) return -EINVAL; return 0; @@ -393,20 +399,20 @@ static int qcom_iommu_identity_attach(struct iommu_domain *identity_domain, { struct iommu_domain *domain = iommu_get_domain_for_dev(dev); struct qcom_iommu_domain *qcom_domain; - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); - struct qcom_iommu_dev *qcom_iommu = dev_iommu_priv_get(dev); + struct qcom_iommu_master *master = dev_iommu_priv_get(dev); + struct qcom_iommu_dev *qcom_iommu = master->iommu; unsigned int i; if (domain == identity_domain || !domain) return 0; qcom_domain = to_qcom_iommu_domain(domain); - if (WARN_ON(!qcom_domain->iommu)) + if (WARN_ON(!qcom_domain->master)) return -EINVAL; pm_runtime_get_sync(qcom_iommu->dev); - for (i = 0; i < fwspec->num_ids; i++) { - struct qcom_iommu_ctx *ctx = to_ctx(qcom_domain, fwspec->ids[i]); + for (i = 0; i < master->num_ids; i++) { + struct qcom_iommu_ctx *ctx = to_ctx(qcom_domain, master->ids[i]); /* Disable the context bank: */ iommu_writel(ctx, ARM_SMMU_CB_SCTLR, 0); @@ -461,11 +467,11 @@ static size_t qcom_iommu_unmap(struct iommu_domain *domain, unsigned long iova, * cannot rely on the device_link. Make sure the IOMMU is on to * avoid unclocked accesses in the TLB inv path: */ - pm_runtime_get_sync(qcom_domain->iommu->dev); + pm_runtime_get_sync(qcom_domain->master->iommu->dev); spin_lock_irqsave(&qcom_domain->pgtbl_lock, flags); ret = ops->unmap_pages(ops, iova, pgsize, pgcount, gather); spin_unlock_irqrestore(&qcom_domain->pgtbl_lock, flags); - pm_runtime_put_sync(qcom_domain->iommu->dev); + pm_runtime_put_sync(qcom_domain->master->iommu->dev); return ret; } @@ -478,9 +484,9 @@ static void qcom_iommu_flush_iotlb_all(struct iommu_domain *domain) if (!qcom_domain->pgtbl_ops) return; - pm_runtime_get_sync(qcom_domain->iommu->dev); + pm_runtime_get_sync(qcom_domain->master->iommu->dev); qcom_iommu_tlb_sync(pgtable->cookie); - pm_runtime_put_sync(qcom_domain->iommu->dev); + pm_runtime_put_sync(qcom_domain->master->iommu->dev); } static void qcom_iommu_iotlb_sync(struct iommu_domain *domain, @@ -523,13 +529,38 @@ static bool qcom_iommu_capable(struct device *dev, enum iommu_cap cap) } } -static struct iommu_device *qcom_iommu_probe_device(struct device *dev) +static struct iommu_device * +qcom_iommu_probe_device(struct iommu_probe_info *pinf) { - struct qcom_iommu_dev *qcom_iommu = dev_iommu_priv_get(dev); + struct qcom_iommu_dev *qcom_iommu; + struct qcom_iommu_master *master; + struct device *dev = pinf->dev; struct device_link *link; + int ret; + int i; - if (!qcom_iommu) - return ERR_PTR(-ENODEV); + qcom_iommu = iommu_of_get_single_iommu(pinf, &qcom_iommu_ops, 1, + struct qcom_iommu_dev, iommu); + if (IS_ERR(qcom_iommu)) + return ERR_CAST(qcom_iommu); + + master = iommu_fw_alloc_per_device_ids(pinf, master); + if (IS_ERR(master)) + return ERR_CAST(master); + + for (i = 0; i != master->num_ids; i++) { + u32 asid = master->ids[i]; + + /* + * Make sure the asid specified in dt is valid, so we don't have + * to sanity check this elsewhere: + */ + if (WARN_ON(asid > qcom_iommu->max_asid) || + WARN_ON(qcom_iommu->ctxs[asid] == NULL)) { + ret = -EINVAL; + goto err_free; + } + } /* * Establish the link between iommu and master, so that the @@ -540,63 +571,33 @@ static struct iommu_device *qcom_iommu_probe_device(struct device *dev) if (!link) { dev_err(qcom_iommu->dev, "Unable to create device link between %s and %s\n", dev_name(qcom_iommu->dev), dev_name(dev)); - return ERR_PTR(-ENODEV); + ret = -ENODEV; + goto err_free; } + dev_iommu_priv_set(dev, master); return &qcom_iommu->iommu; + +err_free: + kfree(master); + return ERR_PTR(ret); } -static int qcom_iommu_of_xlate(struct device *dev, struct of_phandle_args *args) +static void qcom_iommu_release_device(struct device *dev) { - struct qcom_iommu_dev *qcom_iommu; - struct platform_device *iommu_pdev; - unsigned asid = args->args[0]; + struct qcom_iommu_master *master = dev_iommu_priv_get(dev); - if (args->args_count != 1) { - dev_err(dev, "incorrect number of iommu params found for %s " - "(found %d, expected 1)\n", - args->np->full_name, args->args_count); - return -EINVAL; - } - - iommu_pdev = of_find_device_by_node(args->np); - if (WARN_ON(!iommu_pdev)) - return -EINVAL; - - qcom_iommu = platform_get_drvdata(iommu_pdev); - - /* make sure the asid specified in dt is valid, so we don't have - * to sanity check this elsewhere: - */ - if (WARN_ON(asid > qcom_iommu->max_asid) || - WARN_ON(qcom_iommu->ctxs[asid] == NULL)) { - put_device(&iommu_pdev->dev); - return -EINVAL; - } - - if (!dev_iommu_priv_get(dev)) { - dev_iommu_priv_set(dev, qcom_iommu); - } else { - /* make sure devices iommus dt node isn't referring to - * multiple different iommu devices. Multiple context - * banks are ok, but multiple devices are not: - */ - if (WARN_ON(qcom_iommu != dev_iommu_priv_get(dev))) { - put_device(&iommu_pdev->dev); - return -EINVAL; - } - } - - return iommu_fwspec_add_ids(dev, &asid, 1); + kfree(master); } static const struct iommu_ops qcom_iommu_ops = { .identity_domain = &qcom_iommu_identity_domain, .capable = qcom_iommu_capable, .domain_alloc_paging = qcom_iommu_domain_alloc_paging, - .probe_device = qcom_iommu_probe_device, + .probe_device_pinf = qcom_iommu_probe_device, + .release_device = qcom_iommu_release_device, .device_group = generic_device_group, - .of_xlate = qcom_iommu_of_xlate, + .of_xlate = iommu_dummy_of_xlate, .pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M, .default_domain_ops = &(const struct iommu_domain_ops) { .attach_dev = qcom_iommu_attach_dev, From patchwork Thu Nov 30 01:10:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 13473766 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="W3Fyl+x8" Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2082.outbound.protection.outlook.com [40.107.243.82]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E8C1E10D3; Wed, 29 Nov 2023 17:10:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=ZiEU4CYxCxCMvETPUn7OkArhjhsix3Xvy/p49AHMHPmM4C8P1Xhl+vrPGo7r1gs5BucfOdRAPS3cIVoAaW2gXBrcO2ypGxbJtMN9nW/ZcB5cbiiG5BN5zCzhrYnzefe/mvYFkbmNxzXP4KXYVfone7Vx+jysPmBBhw+J9tJIFvc5MaFKsr3Mqsod8Br3/wIX92toyAGoLiFNgUyZG6+NqooSWltb++gF/HUK4KI2MVOP12q38cwQqtIhR4M4u0tBZ8szNcE0krTKYjo0+vEmdlGLkAraHhs9RTsvkmm+/wRfOQ0rxBXOf2F66MKQbGRzKE6KeTjfv7AQ8Y6d2iC4eQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=O1KisvyhyyfD/zj56awPrs2Vc26WKPVJEkpLqxbG9xM=; b=jvB9n6FVaRvLpJXI0m0aZpeZZxe3vqDKY4y75eZdDA2jbdBv7C/Pk6y7dAKkzhquQToZQSzbcIgCqQMjWJihY7bynA9xNA/EDAQV5iIwtCuOgEol/AkKkMu2CNzr8FzdyTZQBEdNlO+G99DNp5hH1gsLs+hoSqqVq6epeLuFbK4uPhz3CxXhXqtT1uvkEUOE2ITA4Megdqj4JehI5EuxFYxnkCGkVZ3MPnyT9iZProPj51jXD5/6ZCD5pz63Bsf0oN2DM2oqq+uoHGuIlWX7D+MI4W47pH7qastkkEx7caynJ5vFHnQRW01obvGNXnmKN87y45YyA0Vu3U+NaNu3tw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=O1KisvyhyyfD/zj56awPrs2Vc26WKPVJEkpLqxbG9xM=; b=W3Fyl+x8fai9FMBMKPC8eR+Ucldqg5DjbtgRnhci8MOQ/CDggJ/mTeKSsR4568XpSuHyp2jhFuoOobjK6nAKj9WDEbE6PcoY763WS/v2Q7n56hJN63nSeXFZZ70P6E+e1mh3hBUKEIpip8xTyuSdqfb2aDVTL+YAr45f/k89BSyZaHWea3oxbvBwdZSo7vzVJIrgL+RP3Uu0gTLi4HE/czrPOA86gnIpIrLDMnheBnJsEK7K9lX3EUXh9pVzjAgWv6NN3AbZp6ddXs2R/9x6zOJR0F8fIWQNHJhoSkeoYv6XbeOgottdgQ9fp0ONrkd0snk6ogyX3OisSqFBJgslfA== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by PH0PR12MB5484.namprd12.prod.outlook.com (2603:10b6:510:eb::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.24; Thu, 30 Nov 2023 01:10:46 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.7046.015; Thu, 30 Nov 2023 01:10:46 +0000 From: Jason Gunthorpe To: acpica-devel@lists.linux.dev, Andy Gross , Alim Akhtar , Alyssa Rosenzweig , Bjorn Andersson , AngeloGioacchino Del Regno , asahi@lists.linux.dev, Baolin Wang , devicetree@vger.kernel.org, Frank Rowand , Hanjun Guo , "Gustavo A. R. Silva" , Heiko Stuebner , iommu@lists.linux.dev, Jean-Philippe Brucker , Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kees Cook , Konrad Dybcio , Krzysztof Kozlowski , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Lorenzo Pieralisi , Marek Szyprowski , Hector Martin , Matthias Brugger , Orson Zhai , "Rafael J. Wysocki" , Rob Clark , Robert Moore , Rob Herring , Robin Murphy , Samuel Holland , Sudeep Holla , Sven Peter , Thierry Reding , Krishna Reddy , virtualization@lists.linux.dev, Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: =?utf-8?q?Andr=C3=A9_Draszik?= , patches@lists.linux.dev Subject: [PATCH 23/30] iommu/viot: Add iommu_viot_get_single_iommu() Date: Wed, 29 Nov 2023 21:10:30 -0400 Message-ID: <23-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> In-Reply-To: <0-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> References: X-ClientProxiedBy: SN6PR08CA0022.namprd08.prod.outlook.com (2603:10b6:805:66::35) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|PH0PR12MB5484:EE_ X-MS-Office365-Filtering-Correlation-Id: 22d41282-ade7-4f6e-da64-08dbf1412b3c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: FcqJkDaYCRW1+7dfxPXuWx2kWu3henT4khNouNcMiZc7W2186WW7W3Ve22iiLrIZOVelThuER0SrdP9LSLVLbGxImJyfpOArdiQhOIVeAOU/MklT2rTP6/jMIa6dqGjhLtVyz91ogokFhXWUatoGtgaU5YNNoy2WT3z8iVwmhlOHP0oFrtD5jrpSxuqPQadDBqkM2RtYaAjkJR7P7pBZggnYqtPgQ2Vi/ckrMb15v2BezzyJkbwp9bvIiOvh0wKw+1xjZCXyOdjHzmQDF6pTkzLlHhFGXidDLWI4j0EHa3vVI0XBFRaXKE/u2imXHXmK2SHo6nbdzFOkxQxJyfAWnaf9QkhsB9dqpfveUm7NBHed9nx10BAoLe34E8U6J+9t13xw22+aimw8qOor1CQsrrILgMjCcpukkh9m75rGRhCEHGEb8zqIBd7YHoVNY0Vo+XcEJgsuiLp4NVBYNnF+n8Ji6JhODtuAOA9ObYcndIseS/JGH01Iq58bFqbmoSUWvc1TDkMy02O5ta01xtdvD+9gQ+C32aW7Nf/CtwcLhbLZJVK/TGyn+V3RmaK8pc8W2JaTWVAw1EivjOmEFIH2ERThjXCb709CVG+0u32ewfHpNxlMw85tyDqpJ0U0HVN9TPhy0mCHQN6Mp3wI52bAog== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:LV2PR12MB5869.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(366004)(346002)(136003)(396003)(39860400002)(376002)(230922051799003)(451199024)(1800799012)(186009)(64100799003)(1191002)(8936002)(110136005)(8676002)(316002)(66556008)(4326008)(86362001)(66476007)(6486002)(478600001)(66946007)(41300700001)(36756003)(921008)(7416002)(7366002)(2906002)(7406005)(5660300002)(38100700002)(2616005)(6512007)(6506007)(6666004)(83380400001)(26005)(202311291699003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: db4P0KPYS+8E+xzoxKDLUd3iPFwRqT+I9RIQsox54u7ajxrminkGT4Po5eV8OHE3Bcxm1wg48v24Oa7Srr5QECWtQ/QuaALN9hIR52TI0pB0dIMQ3opN+N4gGiOYasYXArQ3/75FQNCD6+Dvxo1Nfv4h9eCU7lLrBoArSCgi90nbGor9bSRwC6EwbrCmb45ILpHeORA/GCO89yY5xpuiCnvywlY/rVuj8TbM0yD29aLJCWlLt/O/DxQmq0hO9TIPfkyN7WSEXYShu3Xs7TjdIgXf6Lh31/pW7xh+zkGfoFQNFWLNKZg8ohrbFoz8nwExW/VTanvfim7j94wMj8Tg2qfUplKuHjLN1CNWUchDsxAISnaL9womVz9q+1WtShngbHI2vstOHVJWi3YwGslAQOS3qGgjuty9sjrBef5F4kivpflsS/X235CpA2coJBCmcmPLbL9bueEy8z+PBYycnpLH+FBthsX4Gug0XOcuAA21/WnTwTFYzSDgQ34Tf1J92h75PLwfvfruLPtWHfo7jSeM6ri+yjXDP7nTV3IMjpRinsbyBjfILNXcKwbYtCRSRkaRi6CFK1d+bioQiE55rl+MadUf3SGSXL437QUZCJmJmbHIjITOLJbzET7rk4yGFdpTzDiNTU7lHy1GQ/Gd0cTPRvtJc7srlM3yII0HUPTpIVyKQc8pRGR9aOxnETUWdDGdGGNNb4/ppwFUvPyTNZSLgtP5mapQRC9U+r2/DkfWIK+3R9eIjJL24iFT3uSbKXDaU+jpi9nlbbz72Sq/uKS3rLnlajMWf04QuPdis+FCwoPcq9i+X/eSdhNezOX7mXJ+Gc3bsFFTwEiNXU4FVenfjZO+dffO/Eq9wYG9e2eYIDWjJPOsMOQuPPo6eyk71Ovu/uDmIMxwmc5ONDcbVOwQVhu0eht+bdkFZhCgAQrEsXn3HL2r0efV//GMiy6GMrs7iOc/hQc4DTc4sfVk/4GIu66Clm28VEyOMYpLYkqmitSF3su9YZEN0TztJiTApufKKhzeYvE3SYpHj8XpWb8uDo99ar32swu147JmzgREuwm7GUNOKALXaFemdjN4YZk1Sc/rdDYJAqzFTkWtlzNMlFb9fyx0qN912l9BSonp+9/DjDQ9ufifHD+YivOCoQGJ/J1Epf7KtZQRCxHf+VXZGTitLptxrSdwiaYrYFdbjmhN7Q0F1fQZdxz306Mb6xND3PUdILOkOcNIHFWWi5LLvza1ZctzWH13QPajVDygWQtBlY9CdgUyaKlPL+Zm/68zMWoqjXMefXdL2qxZbtEOfw6ekWr/m+tT2sxzT/nGFlWQWDqALwJfL3sFLrsyOjQml2gd0X5eC2nMKr3j/XjyA3bTei3znMPsVjFCRiemZeMaizbPiHLBzExmyV1co+Av+QoPDw8g5KupGhsXQfsalOjBEqhv8t6NAn2OLGhXaHogYakFKiXbrfVwXkz4gUHLxEqzobCKD0LdPVXvM/+CnARXpTpjT0DCteKZjUyf+6lxg//SzorSt9VV0MKNza4M4yEwYh5gUvusktaU/wx6Fs6kFZxzizF6cFoRtyLj+ZRTC+oT0vk3XkCUOHZE X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 22d41282-ade7-4f6e-da64-08dbf1412b3c X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2023 01:10:40.5225 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 33NPhtelYllkoQCYFic3Jpwc/yPXINMej/xnKpzw+033M/3F2PXpsGOi+A0YlHle X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5484 This is the ACPI VIOT version like iommu_of_get_single_iommu(). It parses the ACPI table, confirms all entries points to a single iommu_driver and then returns a pointer to it. Also cache the u32 id list in the iommu_probe_info and provide a getter function which re-parses in case we overflow the cache. Signed-off-by: Jason Gunthorpe --- drivers/acpi/scan.c | 1 + drivers/iommu/Makefile | 1 + drivers/iommu/viot_iommu.c | 70 ++++++++++++++++++++++++++++++++++++ include/linux/iommu-driver.h | 25 +++++++++++++ 4 files changed, 97 insertions(+) create mode 100644 drivers/iommu/viot_iommu.c diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c index de36299c3b75bf..9ec01196573b6e 100644 --- a/drivers/acpi/scan.c +++ b/drivers/acpi/scan.c @@ -1571,6 +1571,7 @@ static int acpi_iommu_configure_id(struct device *dev, const u32 *id_in) struct iommu_probe_info pinf = { .dev = dev, .is_dma_configure = true, + .is_acpi = true, }; /* Serialise to make dev->iommu stable under our potential fwspec */ diff --git a/drivers/iommu/Makefile b/drivers/iommu/Makefile index 95ad9dbfbda022..9c35b106cecb2e 100644 --- a/drivers/iommu/Makefile +++ b/drivers/iommu/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_IOMMU_IO_PGTABLE_LPAE) += io-pgtable-arm.o obj-$(CONFIG_IOMMU_IO_PGTABLE_DART) += io-pgtable-dart.o obj-$(CONFIG_IOMMU_IOVA) += iova.o obj-$(CONFIG_OF_IOMMU) += of_iommu.o +obj-$(CONFIG_ACPI_VIOT) += viot_iommu.o obj-$(CONFIG_MSM_IOMMU) += msm_iommu.o obj-$(CONFIG_IPMMU_VMSA) += ipmmu-vmsa.o obj-$(CONFIG_IRQ_REMAP) += irq_remapping.o diff --git a/drivers/iommu/viot_iommu.c b/drivers/iommu/viot_iommu.c new file mode 100644 index 00000000000000..e35bd4099e6c6a --- /dev/null +++ b/drivers/iommu/viot_iommu.c @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES + */ +#include +#include +#include + +struct parse_info { + struct iommu_probe_info *pinf; + const struct iommu_ops *ops; + u32 *ids; +}; + +static int parse_single_iommu(struct viot_iommu *viommu, u32 epid, void *_info) +{ + struct fwnode_handle *fwnode = viommu->fwnode; + struct parse_info *info = _info; + struct iommu_probe_info *pinf = info->pinf; + struct iommu_device *iommu; + + /* We're not translating ourself */ + if (device_match_fwnode(pinf->dev, fwnode)) + return -ENODEV; + + iommu = iommu_device_from_fwnode_pinf(pinf, info->ops, fwnode); + if (IS_ERR(iommu)) { + if (!IS_ENABLED(CONFIG_VIRTIO_IOMMU) && + iommu == ERR_PTR(-EPROBE_DEFER)) + return -ENODEV; + return PTR_ERR(iommu); + } + iommu_fw_cache_id(pinf, epid); + return 0; +} + +static int parse_read_ids(struct viot_iommu *viommu, u32 epid, void *_info) +{ + struct parse_info *info = _info; + + *info->ids = epid; + (*info->ids)++; + return 0; +} + +static int viot_get_u32_ids(struct iommu_probe_info *pinf, u32 *ids) +{ + struct parse_info info = { .pinf = pinf, .ids = ids }; + + return viot_iommu_for_each_id(pinf->dev, parse_read_ids, &info); +} + +struct iommu_device * +__iommu_viot_get_single_iommu(struct iommu_probe_info *pinf, + const struct iommu_ops *ops) +{ + struct parse_info info = { .pinf = pinf, .ops = ops }; + int err; + + if (!pinf->is_dma_configure || !pinf->is_acpi) + return ERR_PTR(-ENODEV); + + iommu_fw_clear_cache(pinf); + err = viot_iommu_for_each_id(pinf->dev, parse_single_iommu, &info); + if (err) + return ERR_PTR(err); + pinf->get_u32_ids = viot_get_u32_ids; + return iommu_fw_finish_get_single(pinf); +} +EXPORT_SYMBOL(__iommu_viot_get_single_iommu); diff --git a/include/linux/iommu-driver.h b/include/linux/iommu-driver.h index 632c7b4a389abe..ce0ba1f35bb5dc 100644 --- a/include/linux/iommu-driver.h +++ b/include/linux/iommu-driver.h @@ -45,6 +45,7 @@ struct iommu_probe_info { u32 cached_ids[8]; bool defer_setup : 1; bool is_dma_configure : 1; + bool is_acpi : 1; bool cached_single_iommu : 1; }; @@ -188,4 +189,28 @@ static inline int iommu_dummy_of_xlate(struct device *dev, return 0; } +#define __iommu_first(a, b) \ + ({ \ + struct iommu_device *a_dev = a; \ + a_dev != ERR_PTR(-ENODEV) ? a_dev : (b); \ + }) + +#if IS_ENABLED(CONFIG_ACPI_VIOT) +struct iommu_device * +__iommu_viot_get_single_iommu(struct iommu_probe_info *pinf, + const struct iommu_ops *ops); +#else +static inline struct iommu_device * +__iommu_viot_get_single_iommu(struct iommu_probe_info *pinf, + const struct iommu_ops *ops) +{ + return ERR_PTR(-ENODEV); +} +#endif +#define iommu_viot_get_single_iommu(pinf, ops, drv_struct, member) \ + container_of_err( \ + __iommu_first(__iommu_viot_get_single_iommu(pinf, ops), \ + __iommu_of_get_single_iommu(pinf, ops, -1)), \ + drv_struct, member) + #endif From patchwork Thu Nov 30 01:10:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 13473761 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="oTWOZQwI" Received: from NAM04-BN8-obe.outbound.protection.outlook.com (mail-bn8nam04on2053.outbound.protection.outlook.com [40.107.100.53]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DD8B3D7D; Wed, 29 Nov 2023 17:10:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=hmKwT6bexloyKBzeBinohdFYv0WwZUO9rnEZLicr75WLrlczS3hQeMqCbSiFw3ShpEhZ7PXv0nb2qDJVqo4/u1iawKSV8LAVK1nYEb0J0ebSiWoqp9dfZR9z6NVl3bzFLRYD3THvaiTixgZKqLc0YUyq/gYJskVfYwj3pRuN/F9vmlIB4gLmmxW1Eoyyq9/rW6N83l6sm0rTXA3ouKYadJsudqxTVdTymvSBuwCfNHkmgkhgzXXYRmV7Sa+kp7P+JRQOWfayOk4F4B1bvAwn1g3SFIW9e8mH27L2mkr81GZU7gq40YEGFahgJxG7hbVRoAVnFuX5Yx7joST9Q3RfQA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=n7aJKu7BohUpFcYIdwpDeid+Mzh23OW02rRcztcHd+0=; b=fcXLs3QALOfSwmxljqVm2JObO59htJiL0MrAcI2p8xb0lFsY8T6Fh4al49GD++RA3rRO4WkzN+75h4cWt9dMCymB+kaHtO5Moz0hnpYgLFMDMs1Yq55cEh5cJhfIJBxJnZxw1QsX9e+s28l0xGrKt8KTCjJ2mwsXe70QCps8fDYRcwg9rptArc4KRbxqzrdA53YNpCI0VfGpqWsDOf4KSWKhi64SsvF9Re0+taEpSYE6iiSUVvddhKjZBIT2s7zwo59M2+jCxtDmP/aCHaNSQk7lKcSpUk9SfbDz7G3UJgfXP77U95WU64j1sja7Gtw41e+3MvtYZfjguJ69XDqXQw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=n7aJKu7BohUpFcYIdwpDeid+Mzh23OW02rRcztcHd+0=; b=oTWOZQwIRW+sRoJKgscUvtc8f2NmgRZbSzUE4lwGfogXcueSQPihSV+yNIkgGtgLGhTYWFPgCGqjLaQi8kTcTMr4Ay9ADyfKMLLzvZ320Ix4FTYMHwE/kehbAq60SwunwoTODfWNgbYgT5HIl+picAnGxU6I+7+AQHrIC5iwdL3wVszT8M5Ygw8j/iGI6QHn3hs50Jau5bEuCCbvdSxCGQxMpCM9u0d8oWp45gtCO67eUrXmiaOG5fqjRHVJpPAa7F+fk+IGE4Xoj0IBVsTR1idugCRFKtyipchb9giYcpDRZ5U9jP8NoRrRdmAtKJ+a4Vlv2vrgaQJI2/ZmlBuWdw== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by DS0PR12MB7607.namprd12.prod.outlook.com (2603:10b6:8:13f::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.22; Thu, 30 Nov 2023 01:10:43 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.7046.015; Thu, 30 Nov 2023 01:10:43 +0000 From: Jason Gunthorpe To: acpica-devel@lists.linux.dev, Andy Gross , Alim Akhtar , Alyssa Rosenzweig , Bjorn Andersson , AngeloGioacchino Del Regno , asahi@lists.linux.dev, Baolin Wang , devicetree@vger.kernel.org, Frank Rowand , Hanjun Guo , "Gustavo A. R. Silva" , Heiko Stuebner , iommu@lists.linux.dev, Jean-Philippe Brucker , Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kees Cook , Konrad Dybcio , Krzysztof Kozlowski , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Lorenzo Pieralisi , Marek Szyprowski , Hector Martin , Matthias Brugger , Orson Zhai , "Rafael J. Wysocki" , Rob Clark , Robert Moore , Rob Herring , Robin Murphy , Samuel Holland , Sudeep Holla , Sven Peter , Thierry Reding , Krishna Reddy , virtualization@lists.linux.dev, Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: =?utf-8?q?Andr=C3=A9_Draszik?= , patches@lists.linux.dev Subject: [PATCH 24/30] iommu/virtio: Move to iommu_fw_alloc_per_device_ids() Date: Wed, 29 Nov 2023 21:10:31 -0400 Message-ID: <24-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> In-Reply-To: <0-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> References: X-ClientProxiedBy: SN7P222CA0017.NAMP222.PROD.OUTLOOK.COM (2603:10b6:806:124::15) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|DS0PR12MB7607:EE_ X-MS-Office365-Filtering-Correlation-Id: f184cbfa-52b3-4d89-5ed6-08dbf1412a6b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: LGVZ66x0Z/c4A6yfd8vLDEdf+b6sgChnN84rSZ7LBwHl2BtRXlBVm+2WpXBl5Lkgt3fvU9Y1jumfYyLXJwVsnSFmOeTPAuBHcQDCgsdIdbAPylZktkseaBYMxfcarg8nttCn/+57uar/E2l1KQB/VJWY9cA+j8Y3mvgbsDbFIa9pp9m991KxuSayertSROc3nPNAz51GFOUAe2rHa9DOrbyDMKntkOq92h+axz5GMHkTRVWdoZdNDpMMl9i6/YGtbvRS6eCqkt022p8DRfU3hoXgunNUV7EgTapOcWYY53teGi+TQoCViuNRCLerPKEKh1ETHIHmW21/uEqIsHCdQQUJnTpHffTwP3Gk8tXacvS3FqFSFc/FMNiAC2it8rjjbfsF1krkCJUfkUJaeBmSV8vOifI0dT6gZfKt0dbN3VQnwDogqEL3voeyWIIaQ/mn8TyHU2gNhhicbFjBJmRK9Ry0te6+5aw9mFHFSJwINCHBl7E6rQbUdzR1hUWbHP4in+htuzLmpRngudq7rkQ4bvcgHBH4gTeu/HwCZUpN60oPIz+0OPu7flsHG5DMHRHgRIQXuwjMFc4H+iKvhhBn7TWz8nARPFxV3Vj5Ug/lbRDB1hF/TzlsGlMMVErzoNN54o4jAv/2JE1X2R/zz8kc1A== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:LV2PR12MB5869.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(396003)(39860400002)(346002)(136003)(366004)(376002)(230922051799003)(186009)(451199024)(64100799003)(1800799012)(38100700002)(202311291699003)(83380400001)(1191002)(5660300002)(110136005)(2906002)(86362001)(4326008)(8676002)(8936002)(66556008)(7366002)(7406005)(7416002)(66476007)(66946007)(6486002)(478600001)(6666004)(316002)(36756003)(6506007)(41300700001)(6512007)(921008)(26005)(2616005);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Nwh4P5igKZINuWBNkgxmbvQVTx47VsyJlltLwDktBJ5Sfp+zWmHQRpNfPorx4iyl/Hgvhh1/FEeVyBF5Zq6fZ+2eyUE5WCbGEENQVCQPOwqldo36I2pczKDdV+eJ8nL0hCElkytr7kOfsogkKAV5pW5CD91YfwGzNL9eaX9C7/qO/l3e1zZUC4n4PaBymBeYddMrCztcXPyYl7P0iWtG5BA6K56QnJaLNcag9o+CbNGC+xFzJOREmljn/ZBaTzekHRAtiL/dYVB8ahqkg5ATjqWO+GoeObHVJ226nME2nEPIkZlS3Bd84gVE4AO/WNv11kXn5i45BoeLjdAi5U/cokM+QZYgLNepxmBaR1f7pMT3mwyfzNKF4jobw40tRv0LrcuUS3zIwhCnEMBKuo3G8fLapkZdyAZEVjfl6DVgov90plihm222NmdccwdRZFkrL7TI9dZwc6moWNNFPYwY+WLwDZQxitzRWQ/QjNcLiHRQPkncotfYaAbRHoNxu/GDxwvi0bRtKMMHMm8coHdM0MwGDWth9m12fNr2jfD+T9dLbuBzDQxgtxSHY0sSrJHPwYH76Jf5+Rcctt/o7vcc0Nbn8dYGs0FU1E/Q7EFdJDiLC3/hVAMfFW7xSkBWxGUpzSce4wKc/VpKg5NdJ9wyyPBItYvh+PG6dHk31G7BUwZ07mmPSX1kB5zisliy+8Qoj9vZh1PKlyjxVgQwW3ygv+MQ2KWlMn2MtxPDCvcxrKw1ngCSVMsgMV9GJUVWRSdUfxiCfF3r9MXqs1UA9ttjsz8173lGm0pI6Z+saOjrid9zq+fFjk1rkxn0Hh+bSnZbIBZ761+3jo5tvjXV3FvnfNx6MZIMnxl7/vGrNyxPDUck+d6l5FkyMs+XOoNLuwE54XUvoOvRlKlx84Tgxis7ttjSB+gqjrGGRqcdAEE9PqyyCgGkuzmB771Xyc/pcnsxYw3QCS9nQxEp1vztCE/+fcTz/nyaPpvfVdJMyVyDf7KbwZ2c92TAOXEhZykKl6qdXeppjvdL46Ctb2Qpcq5AmP6/x+gQqWM8CXH2sG4LZhcSBjJtrJHpYBs2MJbb8FUuF10DjM1hW3cVwm21wdp+VV1ZEjkKBOqRebIRzp6TpxZNr5zhgl5+Z89NRMG+U5LIDJx3nrveJCfPi/x7GoRMQHsCBx8ZEqBXpBlk8hLdGc8xDQizKMlQhoKN3t9Vdr+yRgyLqBnxZJhGWl+yhIfdn9qR+l0hnuMt+kfAXcxaS9HrOfL8TlYf93+7AFXXOt3sZTozi+zH+wkCGvp+hV2mgcV07gtlkVL8wtnDqgvcfTF5PB8xLsxnO2O/8O7WP6fB+3sjijOwEPiRTknInkW8KApty5bMTfglfpsLXa7eINg9E17IYIJxSn9kQOVk8nRnKTHIKKaaldEG+gFcKPJAJH40I5NEsbdu02UOtY86j9Vv6ttgh/yDZM0X6jl+UnvjA/X921+yeXFPEKlQzJLICs509GYnwWQG/7V4oY/8gV/svW0abeQxthJGvNGt+YWN0/PHHnXxDimEbTQfaLcso3Ons4SGokaZcshVdezW+tK1s33bzXmp51Mo0XVv7s+N X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: f184cbfa-52b3-4d89-5ed6-08dbf1412a6b X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2023 01:10:39.2211 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 6f71zxWNLJgkgz6I6UQT2udJEyUgiiFHt2tncVABgwqBz9pvFR9sJ/GUov3TVaZL X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7607 virtio supports a single iommu instance with multiple ids. It has a combined ACPI (via the VIOT table) and OF probe path, add iommu_viot_get_single_iommu() to respresent this. It already has a per-instance structure, extend it with the ids[] array and use iommu_fw_alloc_per_device_ids() to populate it. Convert the rest of the funcs from calling dev_iommu_fwspec_get() to using he per-device data and remove all use of fwspec. Signed-off-by: Jason Gunthorpe --- drivers/iommu/virtio-iommu.c | 67 +++++++++++++----------------------- 1 file changed, 23 insertions(+), 44 deletions(-) diff --git a/drivers/iommu/virtio-iommu.c b/drivers/iommu/virtio-iommu.c index b1a7b14a6c7a2f..767919bf848999 100644 --- a/drivers/iommu/virtio-iommu.c +++ b/drivers/iommu/virtio-iommu.c @@ -77,6 +77,8 @@ struct viommu_endpoint { struct viommu_dev *viommu; struct viommu_domain *vdomain; struct list_head resv_regions; + unsigned int num_ids; + u32 ids[] __counted_by(num_ids); }; struct viommu_request { @@ -510,19 +512,16 @@ static int viommu_add_resv_mem(struct viommu_endpoint *vdev, return 0; } -static int viommu_probe_endpoint(struct viommu_dev *viommu, struct device *dev) +static int viommu_probe_endpoint(struct viommu_endpoint *vdev) { int ret; u16 type, len; size_t cur = 0; size_t probe_len; + struct device *dev = vdev->dev; struct virtio_iommu_req_probe *probe; struct virtio_iommu_probe_property *prop; - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); - struct viommu_endpoint *vdev = dev_iommu_priv_get(dev); - - if (!fwspec->num_ids) - return -EINVAL; + struct viommu_dev *viommu = vdev->viommu; probe_len = sizeof(*probe) + viommu->probe_size + sizeof(struct virtio_iommu_req_tail); @@ -535,7 +534,7 @@ static int viommu_probe_endpoint(struct viommu_dev *viommu, struct device *dev) * For now, assume that properties of an endpoint that outputs multiple * IDs are consistent. Only probe the first one. */ - probe->endpoint = cpu_to_le32(fwspec->ids[0]); + probe->endpoint = cpu_to_le32(vdev->ids[0]); ret = viommu_send_req_sync(viommu, probe, probe_len); if (ret) @@ -721,7 +720,6 @@ static int viommu_attach_dev(struct iommu_domain *domain, struct device *dev) int i; int ret = 0; struct virtio_iommu_req_attach req; - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); struct viommu_endpoint *vdev = dev_iommu_priv_get(dev); struct viommu_domain *vdomain = to_viommu_domain(domain); @@ -763,8 +761,8 @@ static int viommu_attach_dev(struct iommu_domain *domain, struct device *dev) if (vdomain->bypass) req.flags |= cpu_to_le32(VIRTIO_IOMMU_ATTACH_F_BYPASS); - for (i = 0; i < fwspec->num_ids; i++) { - req.endpoint = cpu_to_le32(fwspec->ids[i]); + for (i = 0; i < vdev->num_ids; i++) { + req.endpoint = cpu_to_le32(vdev->ids[i]); ret = viommu_send_req_sync(vdomain->viommu, &req, sizeof(req)); if (ret) @@ -792,7 +790,6 @@ static void viommu_detach_dev(struct viommu_endpoint *vdev) int i; struct virtio_iommu_req_detach req; struct viommu_domain *vdomain = vdev->vdomain; - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(vdev->dev); if (!vdomain) return; @@ -802,8 +799,8 @@ static void viommu_detach_dev(struct viommu_endpoint *vdev) .domain = cpu_to_le32(vdomain->id), }; - for (i = 0; i < fwspec->num_ids; i++) { - req.endpoint = cpu_to_le32(fwspec->ids[i]); + for (i = 0; i < vdev->num_ids; i++) { + req.endpoint = cpu_to_le32(vdev->ids[i]); WARN_ON(viommu_send_req_sync(vdev->viommu, &req, sizeof(req))); } vdomain->nr_endpoints--; @@ -974,34 +971,21 @@ static void viommu_get_resv_regions(struct device *dev, struct list_head *head) static struct iommu_ops viommu_ops; static struct virtio_driver virtio_iommu_drv; -static int viommu_match_node(struct device *dev, const void *data) -{ - return device_match_fwnode(dev->parent, data); -} - -static struct viommu_dev *viommu_get_by_fwnode(struct fwnode_handle *fwnode) -{ - struct device *dev = driver_find_device(&virtio_iommu_drv.driver, NULL, - fwnode, viommu_match_node); - put_device(dev); - - return dev ? dev_to_virtio(dev)->priv : NULL; -} - -static struct iommu_device *viommu_probe_device(struct device *dev) +static struct iommu_device *viommu_probe_device(struct iommu_probe_info *pinf) { int ret; + struct viommu_dev *viommu; struct viommu_endpoint *vdev; - struct viommu_dev *viommu = NULL; - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); + struct device *dev = pinf->dev; - viommu = viommu_get_by_fwnode(fwspec->iommu_fwnode); - if (!viommu) - return ERR_PTR(-ENODEV); + viommu = iommu_viot_get_single_iommu(pinf, &viommu_ops, + struct viommu_dev, iommu); + if (IS_ERR(viommu)) + return ERR_CAST(viommu); - vdev = kzalloc(sizeof(*vdev), GFP_KERNEL); - if (!vdev) - return ERR_PTR(-ENOMEM); + vdev = iommu_fw_alloc_per_device_ids(pinf, vdev); + if (IS_ERR(vdev)) + return ERR_CAST(vdev); vdev->dev = dev; vdev->viommu = viommu; @@ -1010,7 +994,7 @@ static struct iommu_device *viommu_probe_device(struct device *dev) if (viommu->probe_size) { /* Get additional information for this endpoint */ - ret = viommu_probe_endpoint(viommu, dev); + ret = viommu_probe_endpoint(vdev); if (ret) goto err_free_dev; } @@ -1050,11 +1034,6 @@ static struct iommu_group *viommu_device_group(struct device *dev) return generic_device_group(dev); } -static int viommu_of_xlate(struct device *dev, struct of_phandle_args *args) -{ - return iommu_fwspec_add_ids(dev, args->args, 1); -} - static bool viommu_capable(struct device *dev, enum iommu_cap cap) { switch (cap) { @@ -1070,12 +1049,12 @@ static bool viommu_capable(struct device *dev, enum iommu_cap cap) static struct iommu_ops viommu_ops = { .capable = viommu_capable, .domain_alloc = viommu_domain_alloc, - .probe_device = viommu_probe_device, + .probe_device_pinf = viommu_probe_device, .probe_finalize = viommu_probe_finalize, .release_device = viommu_release_device, .device_group = viommu_device_group, .get_resv_regions = viommu_get_resv_regions, - .of_xlate = viommu_of_xlate, + .of_xlate = iommu_dummy_of_xlate, .owner = THIS_MODULE, .default_domain_ops = &(const struct iommu_domain_ops) { .attach_dev = viommu_attach_dev, From patchwork Thu Nov 30 01:10:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 13473769 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="Q5s5GwYE" Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2082.outbound.protection.outlook.com [40.107.243.82]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 07BAA10DB; Wed, 29 Nov 2023 17:10:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=YMaX4Tx9vDBKa7I9rBQIVRYCNB1Q2n+ZttlnycpSfsZwsSZ/NQTzTbHiH0JXXRXOsgV9iDZM86YCDaOLAQTVTti1Vv6ts5diGgEEqFFHGbm0doUr0b3uEozqLAsr+OLB7tgYsakz8rz5Sbr/zC3bsMURKOb6jKMQHsft+ApJY/kwhfg+De263Gh4ABrHQcCmBnEf1W21axmZ6QcVTQh1tX/wi8T18gUmNPPReIWKnkHkwXWM/ATToz2/lJ2n5xkW6ekdxJGQf9xEeroz8rVNQjzFVl9rsGw3sJ45FOp0BcVTphaoE9ovOZb3aw8NypptNEgh9fUhGv80OpL9pq/rEw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=VpeNqsmcMauXdixm8QlzYdUa9vz4mLMc6TLXvjWdet4=; b=cYt8xDvqmHoKgcIg71OQjPW6VY2vBCmTcEkGYHO9uXBKw03j243eMQTNVu5yNqqkSUaupq+9oihZBHJ3CLLHhx6fqENFPyFs9T32vX41RUMokiXfTXxzhMsCJ7M1QutVqB5fvsTAYFK/LT/1C29BWyeFfC6XVVFsn9cV88lO/9mBpzreSvYpxIoyYFnSUOn+Jgx6ZvLkPAc/dJxyKBRSGTqG7NQ+3ipdApjl/8nsxmoN8WQMriG+GXhvf6HeDiTNUFAMRbwDRks+liGWLyECkpfqYO+42dlOYjzA2L+9E3do3FeHKLZ/VAHSzMZs+g3PRLFJuwpBhg57iSCKqvQ4Dw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=VpeNqsmcMauXdixm8QlzYdUa9vz4mLMc6TLXvjWdet4=; b=Q5s5GwYE0m3R5dLpeUooCHUWM2nSHqqih9byV7HB+PlQEbJTTKFo6EGTnzjcLh9K0NAAqq1rBg68bDHsGWdLD7jEYLTfAT2GDx7n6W+Hjk0fbJzQOPtJthJW8J2lDCGNfqjaPdWvB4a3SJPQPYkONK0pGBwpfuctBaEwReDFzh+VaPg2Uz6vbM2GHvhxDJ2rUbgowJeTpN8TnuJTvYAZ1dZPxDiBxqbsgTyOA+m00xBsdeQspzTWNqx2CU2M/SbDXZPoiPoW4qjLSwc5E9YV7Aj5bMmLEnYGEHSPOIPRv53CBv77ReFbEQRHyXzL791aN14eNBuMXfoyVY/tfDhIZA== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by PH0PR12MB5484.namprd12.prod.outlook.com (2603:10b6:510:eb::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.24; Thu, 30 Nov 2023 01:10:46 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.7046.015; Thu, 30 Nov 2023 01:10:46 +0000 From: Jason Gunthorpe To: acpica-devel@lists.linux.dev, Andy Gross , Alim Akhtar , Alyssa Rosenzweig , Bjorn Andersson , AngeloGioacchino Del Regno , asahi@lists.linux.dev, Baolin Wang , devicetree@vger.kernel.org, Frank Rowand , Hanjun Guo , "Gustavo A. R. Silva" , Heiko Stuebner , iommu@lists.linux.dev, Jean-Philippe Brucker , Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kees Cook , Konrad Dybcio , Krzysztof Kozlowski , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Lorenzo Pieralisi , Marek Szyprowski , Hector Martin , Matthias Brugger , Orson Zhai , "Rafael J. Wysocki" , Rob Clark , Robert Moore , Rob Herring , Robin Murphy , Samuel Holland , Sudeep Holla , Sven Peter , Thierry Reding , Krishna Reddy , virtualization@lists.linux.dev, Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: =?utf-8?q?Andr=C3=A9_Draszik?= , patches@lists.linux.dev Subject: [PATCH 25/30] iommu/iort: Add iommu_iort_get_single_iommu() Date: Wed, 29 Nov 2023 21:10:32 -0400 Message-ID: <25-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> In-Reply-To: <0-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> References: X-ClientProxiedBy: SN7P222CA0024.NAMP222.PROD.OUTLOOK.COM (2603:10b6:806:124::20) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|PH0PR12MB5484:EE_ X-MS-Office365-Filtering-Correlation-Id: 0ba4ed4b-c8b8-4b73-6c85-08dbf1412b2e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 2JeKNRlI6vQmBvNqI3r/MC2iGwy98kh+yqTFTheuJ/cA4n/03zJRILbuuiDEw9A5ByJYqzcmEIH/0B/41ldDouMvELZwBYlQ85VJTT4IlfMEaGEwxqFxzxqrCAuoMd/BgPdmJrSvNbpFbFkZU5+Xp6jjBUleRg8Iqph2DZ7yC2rC/W7O7BTZU+b6IKHnlUKK9M6MMYrh1CC1w7LUKfSxgEZHTPvVaoKB2YZFpkau2GYCjuVjvxNXRFSXZyQ7X/oJF4Y1rWl18BN+wqXJp6rzW3va+8ECDJ/FS9A9wuQNEExja55s/avbZa8/dUATA0fvijYIGaSdVgrZdHt1oLHMYuhc3QD5QDTt63Oij/0bucxrj0KOU+OfwXESN4I/hCYJqlJ3ilti63alsGhgvqg1wmxnfvgd6+22UnJ9oCYA4RPakyqVUexAJZ0alFG747F4dhZ0XHHmzWSqKCmjrkscoXMfaEwiqxfT7AtXpTfA1pPJFLYmJiPJKWOrED775HnupYgOc+bWB9oX4Wh9J/17amBZ64CwNqnYlrY5k/uvtHUlu9fvGZQKiLmgS0XveIlPMgKeGsvCmfToC9PVGTrfYzIIVdfqUivMN62DODe/sStO3etVABOJ4pV61JFMMx7YjS+o7XmBvXStWJvgE9j7Dg== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:LV2PR12MB5869.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(366004)(346002)(136003)(396003)(39860400002)(376002)(230922051799003)(451199024)(1800799012)(186009)(64100799003)(1191002)(8936002)(110136005)(8676002)(316002)(66556008)(4326008)(86362001)(66476007)(6486002)(478600001)(66946007)(41300700001)(36756003)(921008)(7416002)(7366002)(2906002)(7406005)(5660300002)(38100700002)(2616005)(6512007)(6506007)(6666004)(83380400001)(26005)(202311291699003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: +DDY0B7tA7PB0dRRBXyE54dSkQ0AmSQcYgFiz2FZb1NHkGPaUzdec4FSkiYNwpxwSjfTnKSf6tREttknkmX6iTtSon1wC75j+GyMDCxBE92Pjzj9xGjyJbekwTsaQhB2vN44Wnp5Hml+5yvlMbmhndXKCFAsPeMS4gCG++ECIZdZ1KyIKBV8CvR7aNdrIk8pQsHKJwWzmbNVZDKuMQvm6oT5hftMZub4VppMA+73lFTR/ev0imkt+O8BWmYVykaoQIiDVQD5o19OM7txglBbhMgDMdjrINkglUabxpPMFomgRHTIW2JT+yGrYezzVnNAMJ5brZMlu1Ad8edmP+R2rfcRtqZyKU35oHvR794VFr5PYBBeUU15oXxeqeigZkCvGqDwU7V93VPUV9OJUhgN3aa/6TQzA0WJazb24VeIWkolrWOBAu0RgwKgC7vRLyBDx8dEou0ZEB8ISmI2q66KgyIusfa2hykuCoxKtoEtjP7CqRKvJO3G/wPIVxuFMF2NTA0d5e6KOMMOmVYhUAWRZ3DcGzZco8t3oUo65dFXQMRgbuubCR6rrKRAdoNLYvi0XRtujrVWX1q/UlM9/oNMUoOdryarR6WlwdSHEZOIax/8vRsOmGDByLct0Fddpi3pfwwerKL35H//n3l9ly1H8iKPtsMFyXe1aOkLw73si85AdRROubo9K+bo971gBumTqdwfJmNJFi8nB5KWI7iQNp7MjwIH3N41AkRQ9dAQ46KX2EMqsvwR+7hw7NRYTeUF8QNaPEEKDakIQLY0whT1SoWXa7XxI7vT8cKfZEhJMo/khN9PSAFbUy6lEoHGTHbQYE+5ciA7TaZDI7QDJJOh+ww4useldU/mDftwfuYNbOeUmVCBLOwYzFTAVwOlhN7wAK8jNRannpcCUmOsbSnclGaXDpupinuTxk4whBLW+Zp3lwdnBpfLUenJbpTMc940d5tkXiMT6XCGNQyjFfwxAmZVouFDOSoQ9k+FODvLoE3FFuGvxaI1iNUrjkQPjogvb7UqaTJvdVn0PmYpRT7Rri08TrRFUFq2VVDK1wgYXVs++p2RrPdgGzK1g3CLyvQGcLxI2FRRGkL+I6i45QArP4zWa0i+DB6hUCSk0Dkk/LCZ+0BUQviPOUa0kmVnlTFC1g/wJSZ8yUFyALKA+c3NnPPoF8yrKckIx3HsOUf+tlD+jlW4GXQxvUl7hPqS3CI0DILqkb/94D8YlWkVeycE3WDjZ9l/PBKDKGbq9AjKNhNAmZT7QtJ4YmDTwHuv9uker7jj5ZfBIeSA/Gj247SI1sm2rs2omunZju3kZrkoYht8XKV6QNDq3nGd+b8tJrSH7Lx9rVlB8/YSLGb0ms49bdPuy9zmUx2jlnUF8iI4MUTs4iukSKky87SbPfvV/lEb7ZJkPHVbgRjQA3zsKBZImjD8ifwvKX8YpqFKHVbA+y9myucbWetzo97TyPyKSN7qanqNUcnfPYEQ+UsXAixgCLB26DqLO4y49mEuckrAC3WLtteWoACWpg32sBcmdx043pSjtqI1mFkeeXZYgV0o3Ew1GbGOds+cgqLh8gd6RNsT+mGl6cLxn5E6zxM3GnBz X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0ba4ed4b-c8b8-4b73-6c85-08dbf1412b2e X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2023 01:10:40.5310 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: T1ptQ4YEgwN12VSPI5d2e8VoSf0UaubtgfJzy2NZU2EGMrMwSithTO2wuZ6PAL3w X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5484 This API is basically the same as iommu_of_get_single_iommu(), except that it will try to parse the ACPI IORT table if it is available. The ACPI IORT table can return a flags value to indicate IOMMU_FWSPEC_PCI_RC_ATS, return this through an output flags pointer. Signed-off-by: Jason Gunthorpe --- drivers/acpi/arm64/iort.c | 3 +- drivers/acpi/scan.c | 1 + drivers/iommu/Makefile | 1 + drivers/iommu/iommu.c | 3 ++ drivers/iommu/iort_iommu.c | 98 ++++++++++++++++++++++++++++++++++++ include/linux/acpi_iort.h | 1 + include/linux/iommu-driver.h | 41 +++++++++++++++ 7 files changed, 146 insertions(+), 2 deletions(-) create mode 100644 drivers/iommu/iort_iommu.c diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c index 798c0b344f4be8..6b2d50cc9ac180 100644 --- a/drivers/acpi/arm64/iort.c +++ b/drivers/acpi/arm64/iort.c @@ -79,8 +79,7 @@ static inline int iort_set_fwnode(struct acpi_iort_node *iort_node, * * Returns: fwnode_handle pointer on success, NULL on failure */ -static inline struct fwnode_handle *iort_get_fwnode( - struct acpi_iort_node *node) +struct fwnode_handle *iort_get_fwnode(struct acpi_iort_node *node) { struct iort_fwnode *curr; struct fwnode_handle *fwnode = NULL; diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c index 9ec01196573b6e..eb7406cdc9a464 100644 --- a/drivers/acpi/scan.c +++ b/drivers/acpi/scan.c @@ -1571,6 +1571,7 @@ static int acpi_iommu_configure_id(struct device *dev, const u32 *id_in) struct iommu_probe_info pinf = { .dev = dev, .is_dma_configure = true, + .acpi_map_id = id_in, .is_acpi = true, }; diff --git a/drivers/iommu/Makefile b/drivers/iommu/Makefile index 9c35b106cecb2e..ebf6c151a97746 100644 --- a/drivers/iommu/Makefile +++ b/drivers/iommu/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_IOMMU_IO_PGTABLE_LPAE) += io-pgtable-arm.o obj-$(CONFIG_IOMMU_IO_PGTABLE_DART) += io-pgtable-dart.o obj-$(CONFIG_IOMMU_IOVA) += iova.o obj-$(CONFIG_OF_IOMMU) += of_iommu.o +obj-$(CONFIG_ACPI_IORT) += iort_iommu.o obj-$(CONFIG_ACPI_VIOT) += viot_iommu.o obj-$(CONFIG_MSM_IOMMU) += msm_iommu.o obj-$(CONFIG_IPMMU_VMSA) += ipmmu-vmsa.o diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index caf14a53ed1952..7468a64778931b 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -3030,6 +3030,9 @@ iommu_device_from_fwnode_pinf(struct iommu_probe_info *pinf, if (!pinf->num_ids) pinf->cached_single_iommu = true; + if (pinf->is_acpi) + pinf->acpi_fwnode = fwnode; + if (!iommu || iommu->fwnode != fwnode) { iommu = iommu_device_from_fwnode(fwnode); if (!iommu) diff --git a/drivers/iommu/iort_iommu.c b/drivers/iommu/iort_iommu.c new file mode 100644 index 00000000000000..9a997b0fd5d5f1 --- /dev/null +++ b/drivers/iommu/iort_iommu.c @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES + */ +#include +#include + +#include +#include + +struct parse_info { + struct iommu_probe_info *pinf; + const struct iommu_ops *ops; + u32 *ids; +}; + +static bool iort_iommu_driver_enabled(struct iommu_probe_info *pinf, u8 type) +{ + switch (type) { + case ACPI_IORT_NODE_SMMU_V3: + return IS_ENABLED(CONFIG_ARM_SMMU_V3); + case ACPI_IORT_NODE_SMMU: + return IS_ENABLED(CONFIG_ARM_SMMU); + default: + dev_warn(pinf->dev, + FW_WARN + "IORT node type %u does not describe an SMMU\n", + type); + return false; + } +} + +static int parse_single_iommu(struct acpi_iort_node *iort_iommu, u32 streamid, + void *_info) +{ + struct parse_info *info = _info; + struct iommu_probe_info *pinf = info->pinf; + struct fwnode_handle *fwnode; + struct iommu_device *iommu; + + fwnode = iort_get_fwnode(iort_iommu); + if (!fwnode) + return -ENODEV; + + iommu = iommu_device_from_fwnode_pinf(pinf, info->ops, fwnode); + if (IS_ERR(iommu)) { + if (iommu == ERR_PTR(-EPROBE_DEFER) && + !iort_iommu_driver_enabled(pinf, iort_iommu->type)) + return -ENODEV; + return PTR_ERR(iommu); + } + iommu_fw_cache_id(pinf, streamid); + return 0; +} + +static int parse_read_ids(struct acpi_iort_node *iommu, u32 streamid, + void *_info) +{ + struct parse_info *info = _info; + + *info->ids = streamid; + (*info->ids)++; + return 0; +} + +static int iort_get_u32_ids(struct iommu_probe_info *pinf, u32 *ids) +{ + struct parse_info info = { .pinf = pinf, .ids = ids }; + struct iort_params params; + + return iort_iommu_for_each_id(pinf->dev, pinf->acpi_map_id, ¶ms, + parse_read_ids, &info); +} + +struct iommu_device * +__iommu_iort_get_single_iommu(struct iommu_probe_info *pinf, + const struct iommu_ops *ops, + struct iort_params *params) +{ + struct parse_info info = { .pinf = pinf, .ops = ops }; + struct iort_params unused_params; + int err; + + if (!pinf->is_dma_configure || !pinf->is_acpi) + return ERR_PTR(-ENODEV); + + if (!params) + params = &unused_params; + + iommu_fw_clear_cache(pinf); + err = iort_iommu_for_each_id(pinf->dev, pinf->acpi_map_id, params, + parse_single_iommu, &info); + if (err) + return ERR_PTR(err); + pinf->get_u32_ids = iort_get_u32_ids; + return iommu_fw_finish_get_single(pinf); +} +EXPORT_SYMBOL(__iommu_iort_get_single_iommu); diff --git a/include/linux/acpi_iort.h b/include/linux/acpi_iort.h index 13f0cefb930693..bacba2a76c3acb 100644 --- a/include/linux/acpi_iort.h +++ b/include/linux/acpi_iort.h @@ -40,6 +40,7 @@ typedef int (*iort_for_each_fn)(struct acpi_iort_node *iommu, u32 streamid, int iort_iommu_for_each_id(struct device *dev, const u32 *id_in, struct iort_params *params, iort_for_each_fn fn, void *info); +struct fwnode_handle *iort_get_fwnode(struct acpi_iort_node *node); #ifdef CONFIG_ACPI_IORT u32 iort_msi_map_id(struct device *dev, u32 id); diff --git a/include/linux/iommu-driver.h b/include/linux/iommu-driver.h index ce0ba1f35bb5dc..c4e133cdef2c78 100644 --- a/include/linux/iommu-driver.h +++ b/include/linux/iommu-driver.h @@ -19,6 +19,7 @@ struct of_phandle_args; struct fwnode_handle; struct iommu_device; +struct iort_params; struct iommu_ops; /* @@ -39,7 +40,9 @@ struct iommu_probe_info { struct list_head *deferred_group_list; struct iommu_device *cached_iommu; struct device_node *of_master_np; + struct fwnode_handle *acpi_fwnode; const u32 *of_map_id; + const u32 *acpi_map_id; int (*get_u32_ids)(struct iommu_probe_info *pinf, u32 *ids); unsigned int num_ids; u32 cached_ids[8]; @@ -63,6 +66,21 @@ iommu_device_from_fwnode_pinf(struct iommu_probe_info *pinf, struct fwnode_handle *fwnode); struct iommu_device *iommu_fw_finish_get_single(struct iommu_probe_info *pinf); +/** + * iommu_fw_acpi_fwnode - Get an ACPI fwnode_handle + * @pinf: The iommu_probe_info + * + * Return the ACPI version of the fwnode describing the iommu data that is + * associated with the device being probed. + */ +static inline struct fwnode_handle * +iommu_fw_acpi_fwnode(struct iommu_probe_info *pinf) +{ + if (!pinf->is_acpi) + return NULL; + return pinf->acpi_fwnode; +} + typedef int (*iommu_of_xlate_fn)(struct iommu_device *iommu, struct of_phandle_args *args, void *priv); void iommu_of_allow_bus_probe(struct iommu_probe_info *pinf); @@ -213,4 +231,27 @@ __iommu_viot_get_single_iommu(struct iommu_probe_info *pinf, __iommu_of_get_single_iommu(pinf, ops, -1)), \ drv_struct, member) +#if IS_ENABLED(CONFIG_ACPI_IORT) +struct iommu_device * +__iommu_iort_get_single_iommu(struct iommu_probe_info *pinf, + const struct iommu_ops *ops, + struct iort_params *params); +#else +static inline struct iommu_device * +__iommu_iort_get_single_iommu(struct iommu_probe_info *pinf, + const struct iommu_ops *ops, + struct iort_params *params) +{ + return ERR_PTR(-ENODEV); +} +#endif +#define iommu_iort_get_single_iommu(pinf, ops, params, drv_struct, member) \ + ({ \ + memset(params, 0, sizeof(*(params))); \ + container_of_err(__iommu_first(__iommu_iort_get_single_iommu( \ + pinf, ops, params), \ + __iommu_of_get_single_iommu( \ + pinf, ops, -1)), \ + drv_struct, member) \ + }) #endif From patchwork Thu Nov 30 01:10:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 13473765 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="CN8+7BV7" Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2053.outbound.protection.outlook.com [40.107.243.53]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D415B10CB; Wed, 29 Nov 2023 17:10:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=hjV3rTR3+SA39psoQrZ3kS7cP03e/9qjRlFxkSBeC8e+kiwCpenOl2eoKx8wijlChlBVULb64KGZZTMkHPuWbOIbWnNWMC+kN4RT4YaHvNE0w0y6JWma2awAkc4QlvpluOdhlWhG2h1MgDZeDhErXg/Ya7lyuOPldf5O7qWE/I5TSg90Q5/b/7i+BQvR2z2o1teWEFGI3/t3TC4zymdW7kc29MIjv9BQ08MPxgLD39G5OXGXs94384xux+8uqHJ9m84ya8AScgT06ccVtUqk+u1WQCruAMzvPqFZmMN/Wrteoq6YIv4GIfN8oAxJu8FydsHzJPmZZSkEJ+ujT9O8ng== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=XwJ+G8korP3D4LufwIZ/Z16nvSXw1vjgiBys05/mYhQ=; b=E4qtsL42FrziqsVoxPf8KU7atR7/UWeVz2+dNMk3qpyMX29dUXDQrWyhaja1xrMM6PDp1BDtTDtXyqgFH+ihqyf+OQCNSzbVdKiZ8LP9VjxiecvPRpohK4rStBWwT7wvRgnf/w9ZAI77GJz2vKyVZKHeMtRMTAxO40Bom2yoxsFEfLZXHrw+Bw46z3HMrvgg+Mv+mb5xeIloH65c6VPFNcn/FW9qyeCxoTrOm9YU8+exf5fJIWsRFHGR/I7O7bgdYIioqSim79J1E/XbELqAObYop+uzGrGdi4kQ9vRPCBPhtg+A27iiQNOJhgvZ25RbXtoABOV7c//jyLUxn0+Wow== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=XwJ+G8korP3D4LufwIZ/Z16nvSXw1vjgiBys05/mYhQ=; b=CN8+7BV7GMQRyS4Yh6g7FIO4aRqKaUjMeSM5434CqB5HkuaSUQc+8BaPGMRN0nSzLWfiXuyBHFRY6sN7cEF0oH3hm+M+UcWXUjeUvMqNuSZKiZhgnHYJmrQHnkPgEgXjNKeAnq1Q8N4qYw2FV3fflybi5JUna9j28unf5xurqYRcspaDDZ80oAQb7d32Tz+mPQZ6FsC+aZmYAWP26jX4Qx/vcv+XMBCF9otESqDeMWPsw7Lrn4Sf8uL8lE6cuE8s0okNMAEf5YngS5qaZYvgj9+eairoothKKrZnJjDpYIHEyy4JpOmiBEuiYnsN++Ez4tekK4msNn6cSnZi+nsEHA== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by PH0PR12MB5484.namprd12.prod.outlook.com (2603:10b6:510:eb::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.24; Thu, 30 Nov 2023 01:10:46 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.7046.015; Thu, 30 Nov 2023 01:10:46 +0000 From: Jason Gunthorpe To: acpica-devel@lists.linux.dev, Andy Gross , Alim Akhtar , Alyssa Rosenzweig , Bjorn Andersson , AngeloGioacchino Del Regno , asahi@lists.linux.dev, Baolin Wang , devicetree@vger.kernel.org, Frank Rowand , Hanjun Guo , "Gustavo A. R. Silva" , Heiko Stuebner , iommu@lists.linux.dev, Jean-Philippe Brucker , Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kees Cook , Konrad Dybcio , Krzysztof Kozlowski , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Lorenzo Pieralisi , Marek Szyprowski , Hector Martin , Matthias Brugger , Orson Zhai , "Rafael J. Wysocki" , Rob Clark , Robert Moore , Rob Herring , Robin Murphy , Samuel Holland , Sudeep Holla , Sven Peter , Thierry Reding , Krishna Reddy , virtualization@lists.linux.dev, Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: =?utf-8?q?Andr=C3=A9_Draszik?= , patches@lists.linux.dev Subject: [PATCH 26/30] iommu/arm-smmu-v3: Move to iommu_fw_alloc_per_device_ids() Date: Wed, 29 Nov 2023 21:10:33 -0400 Message-ID: <26-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> In-Reply-To: <0-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> References: X-ClientProxiedBy: SN6PR08CA0001.namprd08.prod.outlook.com (2603:10b6:805:66::14) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|PH0PR12MB5484:EE_ X-MS-Office365-Filtering-Correlation-Id: 72d5ace2-3b95-4d23-87a1-08dbf1412b2c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 92Xkiy7Ge3EyyeZMq1jHCmrHDof2nfgXnt5krfuyp9sXi5zeS2ZGZyMrV6BODuhKVOxL/AUCDG8k3aP3Q9diTte8jlkNdoNTiQaEQAg1uA5/BzT0l4TrCaV2MkMLSU5bCsDB3Oz8BtjmiY6ToeQJtpjT+YOTO8FW5SnVCUg615BnKNDZBoHvhUF70D5L93CnxfzK1mnAChT1KjyqQHJU6NcloZjQNdI7Zz4W0B6BOIVpK1VVt1sbObC38NKWcahueEozbssTYBNci7B9u0RjxjitSPIxiCypxWTKgNHQJSZ8g70qh2AJn0dWjHpbYzOQJWqk/SRx3BnT3IIixzAHsTKifAShMiXY3nxFT6OicBPkwv38/2jIw+bGZk8Gh8VoPAqa6THx13y9KP3GxVM1Y9Dzqze7kBxN80YpqcT8BOyx+Zq8qhtokRrwuA3Aicz37U2/uMHmqCG06Bj6MqP6JneUuURaUCXBcgVIQgT382RsNifCMTixt+yuCDzwva11J4DFikqxx+pKbo+NeC63iCeUxnJqJuIIP1NwvYUrE62z7QC6kmrU9w5uW1T9PtpUlB+ziRAnilzZrRb9nGhDzmmT3Ck7P9yNIGYCZ4mzrKsLw+3/BnpZzV8gNfejkPvWw1c2yn5WpHJRazxA+uqL6g== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:LV2PR12MB5869.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(366004)(346002)(136003)(396003)(39860400002)(376002)(230922051799003)(451199024)(1800799012)(186009)(64100799003)(1191002)(8936002)(110136005)(8676002)(316002)(66556008)(4326008)(86362001)(66476007)(6486002)(478600001)(66946007)(41300700001)(36756003)(921008)(7416002)(7366002)(2906002)(7406005)(5660300002)(38100700002)(2616005)(6512007)(6506007)(6666004)(83380400001)(26005)(202311291699003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: sJvPkKnT8OSWWSISjBxvPyOFfkzFZcWpoixVo4xEwL74hOkh8fL0JxMduSr+AvWSIcipMikb42ZUgKnGDZvvDZBR+Ugsinx8GGDY1LACAoRCpOBYFipKMSXv8r+ZfjVFEk9IvOIZkInwyBBzRQdPs2onnnLRZQT/6aKmLbdXmqgcGXfjlLsTeC2DDVCebf0nRYY0/5fOZME9YxM7I9YZ0xF7+GQ1rPAD4qJuNCfB5wOm3UY74IUQM0Ss1ftMB/8gtpp0dShVgtv3X7p1zQ82a7/2EC8Rz+QQKQfZXAPvUdHz9FAUKJcmIqwyl4b8jNMVLrWFlGxVw+ZDe1pc22HAQ34Uk+mgYPwMeOUEDXEeJqBitoe4N6XDnw1vLSSwbCD+x1XHy4ufGmay8me0gD9x0tdtTicRP6AbVpW7Bd/dFCp2eAS2bjcRiw0OM3I7iY6AK0BbPZ9EuepRBZ9thCy7nHwLm3fCgmQpv1xdAgSU9BbsYQJcUr/sp6QD9j6i1y3LRPZl/PomMsl0NI1XjW7b2qg3voR5Ki22pcY1owZHkJrNfc9u+np6svDjw3Q91BDyh1Sc2RLIcVlL0tKDv+n/TKgy9NN6sGHU5G6SphvazGn0udlfpgyK5ZIMjVe6O3J0mXsBGX3SZeIMDQYoVkDYNN9c2NW67dq0nbq9eKguBuLaB0F7rK2OZ36WCqTNBxbvCqTRSZpDlQ56XBPAB4zsAthR20n9c2ReguPEYgRNJduX94s5PQMF1aECpAPafZhDZYDjh0rnU6l8h6J7Lqa1H6hCVYSZDVYCDxWEz8LRBFq1nBHPDbtZhWcgpBthIAd/6isoxsBxOknvJjkgDZ3MTbf2ZJn8v/Ipos9ft6k3Z6V29yM8BL0tshhVfkuR0lKC4bOAcNXIKMa1j3rJCyogOZFSNrf3QSZ+/3iZoP6e6VMQpH9BYU7cGnfmP6qW6loNphSG78algA7ncihi95VlKwU7WAAgYQoqkwIS/3d2S3V72fDYtYlX6nMaSHvKZYEZewHnHv4Qw4PKom31Hoz8qQ7zkUoKCd2vZ4F4aZMsfu3p7iFgvRKzRJHF+J7NT1bIqH/222/Nb8UPJ5WnVsrvPszLPtjlSE3e4MHjgSy9uMRsNCIYnhitK70li3C5oqKkgDqlkT6J/MfTRbGfP5hEcCCQR8l13bY+BeQAEEjZ/dM46feMtnYIB3gCheDHlG8/yfYFgGpGxMFqdyCGs+hM2xNjqg9xRkllCTfj80tiSxMCpwIWYsBGQ/6PpXWUS2IK+BALXA6UQNjwSW/WA/lygxzosVeSssxImkZkxWhVdwrd12tS7R6pZHPVu03PT8q9EiVs/eknw/dhTVGTTjT9A04bgz2y24RL2wUXn1KLhmR1IuKdpwA12E7Ap0hcGp+PXF8i1YMEn7HKD3Oj2nvEWWyIT+E1Khqv3DcmFox6rEwkPNbD0vEJZOD0ErHHKRK+eaXaRmOBEEZ6tYddrs4MRiH/LKQseXA6ogAstefjZux1ay4QWGam54uLgwmZvY/HB33OtAYFNtsZQ2cyJYtIs52nAGmxvsK3I4R+3jWYCkZW8Hi5JEYo2ROcy0q89VgK X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 72d5ace2-3b95-4d23-87a1-08dbf1412b2c X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2023 01:10:40.4864 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 4t7oHSiKphoopW92I1Rm+6YwRFEu5JL6Inb7Ybt6vg/SK6SPNORu2XecHKqXHdbE X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5484 SMMUv3 supports a single iommu instance with multiple ids. It has a combined ACPI (via the IORT table) and OF probe path, add iommu_iort_get_single_iommu() to respresent this. It already has a per-instance structure, extend it with the ids[] array and use iommu_fwb_alloc_per_device_ids() to populate it. Convert the rest of the funcs from calling dev_iommu_fwspec_get() to using the per-device data and remove all use of fwspec. Directly call iort_iommu_get_resv_regions() and pass in the internal id array instead of getting it from the fwspec. Signed-off-by: Jason Gunthorpe --- drivers/acpi/arm64/iort.c | 2 - drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 74 +++++++++------------ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 4 ++ include/linux/iommu-driver.h | 2 +- 4 files changed, 35 insertions(+), 47 deletions(-) diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c index 6b2d50cc9ac180..acd2e48590f37a 100644 --- a/drivers/acpi/arm64/iort.c +++ b/drivers/acpi/arm64/iort.c @@ -1297,8 +1297,6 @@ static void iort_named_component_init(struct device *dev, props[0] = PROPERTY_ENTRY_U32("pasid-num-bits", FIELD_GET(ACPI_IORT_NC_PASID_BITS, nc->node_flags)); - if (nc->node_flags & ACPI_IORT_NC_STALL_SUPPORTED) - props[1] = PROPERTY_ENTRY_BOOL("dma-can-stall"); if (device_create_managed_software_node(dev, props, NULL)) dev_warn(dev, "Could not add device properties\n"); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 1855d3892b15f8..1a43c677e2feaf 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -26,9 +26,9 @@ #include #include #include +#include #include "arm-smmu-v3.h" -#include "../../dma-iommu.h" #include "../../iommu-sva.h" static bool disable_bypass = true; @@ -2255,12 +2255,11 @@ static bool arm_smmu_ats_supported(struct arm_smmu_master *master) { struct device *dev = master->dev; struct arm_smmu_device *smmu = master->smmu; - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); if (!(smmu->features & ARM_SMMU_FEAT_ATS)) return false; - if (!(fwspec->flags & IOMMU_FWSPEC_PCI_RC_ATS)) + if (!master->pci_rc_ats) return false; return dev_is_pci(dev) && pci_ats_supported(to_pci_dev(dev)); @@ -2382,14 +2381,10 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) { int ret = 0; unsigned long flags; - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); struct arm_smmu_device *smmu; struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); struct arm_smmu_master *master; - if (!fwspec) - return -ENOENT; - master = dev_iommu_priv_get(dev); smmu = master->smmu; @@ -2529,15 +2524,6 @@ arm_smmu_iova_to_phys(struct iommu_domain *domain, dma_addr_t iova) static struct platform_driver arm_smmu_driver; -static -struct arm_smmu_device *arm_smmu_get_by_fwnode(struct fwnode_handle *fwnode) -{ - struct device *dev = driver_find_device_by_fwnode(&arm_smmu_driver.driver, - fwnode); - put_device(dev); - return dev ? dev_get_drvdata(dev) : NULL; -} - static bool arm_smmu_sid_in_range(struct arm_smmu_device *smmu, u32 sid) { unsigned long limit = smmu->strtab_cfg.num_l1_ents; @@ -2568,17 +2554,16 @@ static int arm_smmu_insert_master(struct arm_smmu_device *smmu, int ret = 0; struct arm_smmu_stream *new_stream, *cur_stream; struct rb_node **new_node, *parent_node = NULL; - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(master->dev); - master->streams = kcalloc(fwspec->num_ids, sizeof(*master->streams), + master->streams = kcalloc(master->num_ids, sizeof(*master->streams), GFP_KERNEL); if (!master->streams) return -ENOMEM; - master->num_streams = fwspec->num_ids; + master->num_streams = master->num_ids; mutex_lock(&smmu->streams_mutex); - for (i = 0; i < fwspec->num_ids; i++) { - u32 sid = fwspec->ids[i]; + for (i = 0; i < master->num_ids; i++) { + u32 sid = master->ids[i]; new_stream = &master->streams[i]; new_stream->id = sid; @@ -2627,13 +2612,12 @@ static void arm_smmu_remove_master(struct arm_smmu_master *master) { int i; struct arm_smmu_device *smmu = master->smmu; - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(master->dev); if (!smmu || !master->streams) return; mutex_lock(&smmu->streams_mutex); - for (i = 0; i < fwspec->num_ids; i++) + for (i = 0; i < master->num_ids; i++) rb_erase(&master->streams[i].node, &smmu->streams); mutex_unlock(&smmu->streams_mutex); @@ -2642,26 +2626,27 @@ static void arm_smmu_remove_master(struct arm_smmu_master *master) static struct iommu_ops arm_smmu_ops; -static struct iommu_device *arm_smmu_probe_device(struct device *dev) +static struct iommu_device *arm_smmu_probe_device(struct iommu_probe_info *pinf) { int ret; + struct device *dev = pinf->dev; struct arm_smmu_device *smmu; struct arm_smmu_master *master; - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); + struct iort_params params; - if (WARN_ON_ONCE(dev_iommu_priv_get(dev))) - return ERR_PTR(-EBUSY); + smmu = iommu_iort_get_single_iommu(pinf, &arm_smmu_ops, ¶ms, + struct arm_smmu_device, iommu); + if (IS_ERR(smmu)) + return ERR_CAST(smmu); - smmu = arm_smmu_get_by_fwnode(fwspec->iommu_fwnode); - if (!smmu) - return ERR_PTR(-ENODEV); - - master = kzalloc(sizeof(*master), GFP_KERNEL); - if (!master) - return ERR_PTR(-ENOMEM); + master = iommu_fw_alloc_per_device_ids(pinf, master); + if (IS_ERR(master)) + return ERR_CAST(master); master->dev = dev; master->smmu = smmu; + master->pci_rc_ats = params.pci_rc_ats; + master->acpi_fwnode = iommu_fw_acpi_fwnode(pinf); INIT_LIST_HEAD(&master->bonds); dev_iommu_priv_set(dev, master); @@ -2670,7 +2655,8 @@ static struct iommu_device *arm_smmu_probe_device(struct device *dev) goto err_free_master; device_property_read_u32(dev, "pasid-num-bits", &master->ssid_bits); - master->ssid_bits = min(smmu->ssid_bits, master->ssid_bits); + master->ssid_bits = min(smmu->ssid_bits, + max(params.pasid_num_bits, master->ssid_bits)); /* * Note that PASID must be enabled before, and disabled after ATS: @@ -2687,7 +2673,8 @@ static struct iommu_device *arm_smmu_probe_device(struct device *dev) CTXDESC_LINEAR_CDMAX); if ((smmu->features & ARM_SMMU_FEAT_STALLS && - device_property_read_bool(dev, "dma-can-stall")) || + (device_property_read_bool(dev, "dma-can-stall") || + params.dma_can_stall)) || smmu->features & ARM_SMMU_FEAT_STALL_FORCE) master->stall_enabled = true; @@ -2744,14 +2731,10 @@ static int arm_smmu_enable_nesting(struct iommu_domain *domain) return ret; } -static int arm_smmu_of_xlate(struct device *dev, struct of_phandle_args *args) -{ - return iommu_fwspec_add_ids(dev, args->args, 1); -} - static void arm_smmu_get_resv_regions(struct device *dev, struct list_head *head) { + struct arm_smmu_master *master = dev_iommu_priv_get(dev); struct iommu_resv_region *region; int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO; @@ -2762,7 +2745,10 @@ static void arm_smmu_get_resv_regions(struct device *dev, list_add_tail(®ion->list, head); - iommu_dma_get_resv_regions(dev, head); + if (master->acpi_fwnode) + iort_iommu_get_resv_regions(dev, head, master->acpi_fwnode, + master->ids, master->num_ids); + of_iommu_get_resv_regions(dev, head); } static int arm_smmu_dev_enable_feature(struct device *dev, @@ -2851,10 +2837,10 @@ static void arm_smmu_remove_dev_pasid(struct device *dev, ioasid_t pasid) static struct iommu_ops arm_smmu_ops = { .capable = arm_smmu_capable, .domain_alloc = arm_smmu_domain_alloc, - .probe_device = arm_smmu_probe_device, + .probe_device_pinf = arm_smmu_probe_device, .release_device = arm_smmu_release_device, .device_group = arm_smmu_device_group, - .of_xlate = arm_smmu_of_xlate, + .of_xlate = iommu_dummy_of_xlate, .get_resv_regions = arm_smmu_get_resv_regions, .remove_dev_pasid = arm_smmu_remove_dev_pasid, .dev_enable_feat = arm_smmu_dev_enable_feature, diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 961205ba86d25d..ac293265b21a13 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -692,6 +692,7 @@ struct arm_smmu_stream { struct arm_smmu_master { struct arm_smmu_device *smmu; struct device *dev; + struct fwnode_handle *acpi_fwnode; struct arm_smmu_domain *domain; struct list_head domain_head; struct arm_smmu_stream *streams; @@ -702,8 +703,11 @@ struct arm_smmu_master { bool stall_enabled; bool sva_enabled; bool iopf_enabled; + bool pci_rc_ats; struct list_head bonds; unsigned int ssid_bits; + unsigned int num_ids; + u32 ids[] __counted_by(num_ids); }; /* SMMU private data for an IOMMU domain */ diff --git a/include/linux/iommu-driver.h b/include/linux/iommu-driver.h index c4e133cdef2c78..8f7089d3bb7135 100644 --- a/include/linux/iommu-driver.h +++ b/include/linux/iommu-driver.h @@ -252,6 +252,6 @@ __iommu_iort_get_single_iommu(struct iommu_probe_info *pinf, pinf, ops, params), \ __iommu_of_get_single_iommu( \ pinf, ops, -1)), \ - drv_struct, member) \ + drv_struct, member); \ }) #endif From patchwork Thu Nov 30 01:10:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 13473778 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="Wx9x3nJa" Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2082.outbound.protection.outlook.com [40.107.243.82]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E7F82D7D; Wed, 29 Nov 2023 17:10:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=c7rGNXqgfgJjOqkjeCl5vt8LOlzcnalB8wxI9aoARl8eDPSibutQvyYDlog0AQE6mFGfB7kX++7/xB3VUzvvqLKMrQ81dbYuTKX4C+WvM6muGLg9n4GrxvmO+dHsGO8sWHdBK1E61HsktgrXvXqWiXW0k2Y2tpM8Hhfnl7pBm2/61LjsYXpUacPFpPVryv8vJD6s6ZyT3RoJB5ulq/sqmwCxwoVWQXb1M+ecduObSVgDInhYdZaw1gy+prqfoksNntCI+hzp0VTwpVfZO8Pz0crjV9x0cNtPgDJMVcdjX0DtOIzQmWEJS7ISc67os3cSMsUsh5C1+QR4yY5fcALikQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=tVfjFiF2fSnhxlRRXNND7TRJRH/U77+j8K1B2oK4udg=; b=N8afihFThkQHF/yPelNoYXCtPKglsc0j9IOqlPwEwv6Wdy12wD7uOafgFseIpWxSgdx5UIh3eK+sXRlTjLo89IDw9bOIQNlivAPMa7hHnyOWWp+T3BMRzo6kGEK29RmPvrUPXPWLpN+EJ0tYnzAH6ovEA8gVRQY3v6URtw6ADnneW2EGcb8Ji5IEotkOKWOZtV1qmm5dGCrsCH3ky+adQizejpimiC6jFsnzTAwfRVmjxGkg3azOGrj3eHQVwuZMFHR5GmpryKEiT1Ib87N49o1lUmeWyElLgglO8gDxVO1v8xRQ2zWo+FrdsJlQudbVyLYqdrN3DZ+0z76BmmA0ow== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=tVfjFiF2fSnhxlRRXNND7TRJRH/U77+j8K1B2oK4udg=; b=Wx9x3nJaMbXLoBI9ECOgZcWNcQf3038G8tZS+Bv14TMC6WUj91zZwf3Np4/wo5QbwYz/O+KAMH5Rs8VxlSfvF68u21D+UK9CDHxr+UFi5plsj0Qdrc20n0KvO2G58O0fIPWjrrhEuJYpzIx6gqnHUfzQZBDTa3quI9jDScrNGaleZed3IDMbZAfI0stv++qjLPlWjM+R3a3fxadrlPLExaQ/QkG39mUoPzn6BT7xHNk4Tbat/6h+cXv2JXEnuyDkVHKrXkFkQOeGiDuJ46F4ZwhsAnVB61jF0llpsL6MxWIj+4hDsNYVpIVUTlJUN6fUt1HteQHbZJ4n/4b+29mw2w== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by PH0PR12MB5484.namprd12.prod.outlook.com (2603:10b6:510:eb::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.24; Thu, 30 Nov 2023 01:10:49 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.7046.015; Thu, 30 Nov 2023 01:10:49 +0000 From: Jason Gunthorpe To: acpica-devel@lists.linux.dev, Andy Gross , Alim Akhtar , Alyssa Rosenzweig , Bjorn Andersson , AngeloGioacchino Del Regno , asahi@lists.linux.dev, Baolin Wang , devicetree@vger.kernel.org, Frank Rowand , Hanjun Guo , "Gustavo A. R. Silva" , Heiko Stuebner , iommu@lists.linux.dev, Jean-Philippe Brucker , Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kees Cook , Konrad Dybcio , Krzysztof Kozlowski , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Lorenzo Pieralisi , Marek Szyprowski , Hector Martin , Matthias Brugger , Orson Zhai , "Rafael J. Wysocki" , Rob Clark , Robert Moore , Rob Herring , Robin Murphy , Samuel Holland , Sudeep Holla , Sven Peter , Thierry Reding , Krishna Reddy , virtualization@lists.linux.dev, Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: =?utf-8?q?Andr=C3=A9_Draszik?= , patches@lists.linux.dev Subject: [PATCH 27/30] iommu/arm-smmu: Move to iommu_of_xlate() Date: Wed, 29 Nov 2023 21:10:34 -0400 Message-ID: <27-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> In-Reply-To: <0-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> References: X-ClientProxiedBy: SA0PR11CA0134.namprd11.prod.outlook.com (2603:10b6:806:131::19) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|PH0PR12MB5484:EE_ X-MS-Office365-Filtering-Correlation-Id: 1945286a-540d-467a-13b8-08dbf1412b80 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: EumLFNss2oLG+ZZ7Q+mKLqv4ZGj0yVj9O/upQk/owSSUhlz3VSWsuwREjDOKrBnJSIznAUAohZ1rW24i/r7BrhiwT5IQEJU4leyHBAY76r/gSf4agwa1F6Xzl75N1+fe1tji408/9ARGF1X58a0+9Wz0skI8yZ61+rQ4RG3QsKRIZW/64Jf7ULYONCH35k4LbXqJNadw5eErtN7MS3TDTR3uR8KwYifp7Pvfkm9cfxDMy8LVBlBntpWKGNLGRSSysg+RJhy2ivjUzUwpzgofP34+X55tN8kGBqLHyx+qgRsUh7CAhi7RGjjR3FLirL5uQjafX7PGn4iYljPQuHHgH0PHvZQLUyhj3gGTkwKn3WDlbENSAubjUGf5oi0Dpzi9X1OPnmvXl5pmPXuyhyLLUU2qe0bhRMFc5WurQARipcUkEqepNZZDR8jbdAQuXrAB5GlerYfHHOgPGHY/d6NDPdy73RU2/5YolxcfqBeEpSLtBdtSSW1K9BV2uGk576iU+TgqTBO4IUuIKJgm5AvRctYQfv8O2Az+hwxykdZ607Svk4KKPPLwbs2EU8OX4haJp1ZHngT8QuanCKHDso0vUrRCZWugdtQLc1WlevTIDusAUJEjfSwW9pUrS8lalefeQIOYqqlyWUxMcoqR32gOjQ== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:LV2PR12MB5869.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(366004)(346002)(136003)(396003)(39860400002)(376002)(230922051799003)(451199024)(1800799012)(186009)(64100799003)(1191002)(8936002)(110136005)(8676002)(316002)(66556008)(4326008)(86362001)(66476007)(6486002)(478600001)(66946007)(41300700001)(36756003)(921008)(30864003)(7416002)(7366002)(2906002)(7406005)(5660300002)(38100700002)(2616005)(6512007)(6506007)(6666004)(83380400001)(26005)(202311291699003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: DCXf/pNZ30FYKhzYGjHjkttr2gWAu7MD+zXo8kgVAXwbMxu0AkG7T+IuUc5XwvhsztfwB/5ViLSeblTHvCx4pQ5FK8ihS41h0k2u174nQO3b/hGwAxGRbHMHnLlJAWRoRCAo5gPaycxweFMRZfcBJgu0/SLBYO3TxRXSF5G86XZRwAPKpbK5JemKZDrO6rjA59/OQnfSc9WBWmv4Vz965WOhXwXmGVmXpCrOHDa3tzD0ZMjFpn/SU4xaY2yq01Gh03P6V4uK+9BmPbxTQhurM/FU/5rlqQ3nBwpyJOOJFm6pa90aFbciEsWZQZSdom+9vRnJUGv/y5/njWSr9wA4oZd3vLJXhJ+pDEVDetthSmFhZtP0iLZDZEIh5KsL6Bswd83yXYpnQ8oIbyYAad6Vjo9ohBp43CYIXWFkS3057j2KcV0nBqbi0Sj1q/QwpPSsik05Mxp94zAoWMD5IJy54OAv4+B4kH5VoU6I0baKToh+MhLe07uVuyykLafe4TSbBmXhsi/vCNVRXmdXATe25orAd4LxK/KT0K+3XJ9+r02sXYT4FGfzGnScQgfC/+QiA8ns7LTVDDmjkMIwPLWnRO6X+n5+WlAkar2LKoVj7wUNYspkpEqevxGLNUgAaHJ75Zde7Kjz2PNPozgpx5NX3KAjkpXb+eq1VQQwvQ5iGRslUjwbc9AFD+pfyj7ut4unHObz3Qf1RaTV6huk3qj9eaRWr2f2lw66x2O1C4w/CwzF1+iiEy8lPSws1Clk3t98xq9eS0d8Cgt/WGQMxHIRWiVeO/VO4CR6jFrt/HlesXxjvf86FfsE+lCPKR+gCbwx8rSJ92w6FfGncLvW9Y5yj8d/Wd7hCnFLFYUIPnIWRcIbYhwls6XvBmhJ2ZFVceHS/0p5azngLEsuy0iI7ho+UWYtWj/MO30sH4NE/u5q4HvVuPDl5BIiwLb/fRpalHX/pKgbWQPEQfRoBs0sLq6roVCNIJSSXg06UI93CaQ8+ciYVs89p/y42E8yQ/LU9eyBZN2uH60kuE31ZKF66fisjexMfOAAeHoviFNp66eLF5ZKIYEzR6DpQdgyDxbTP8Ca5khrTwnveY/S2fMF0hs8y25bH8v9jTXMn8aIyaZFD60HOZtDH2x91g0b9kFAa/rZQK8vCwSdL9YjKOybEXUV284iVclkEMfK+SYpXCRYz+AviWE36KQGJC744OUjZmR6EHniFlZ+1mDOKVDdzJFYQmgc2GJEBBaH6uWyHoLyDIHoAQbS6Xceugqf7RpwdDSTfE3fV7jqWhkLUZ+fI+39CqY/Ze3xcXq2hUemvezEwdaqI2LwWgEAQwpxF0d09JcMVMkxRUj6tOaLEcUkbRbK+80nPtiuTaMhbYOA3Q5+cpZ4+PAcon79jNK7gGcobCLqFGqaNxAoLjN3kEAepxCB3WV48BkcWQfTAnmuWCONOC8Q7DAwTTshP6WcbeABaAILmuRc33A4UfmMOTJX7ciG8TL2zf96k3DgcIOM0kQvB0KSLoumWNaAdEMv2KtBcQqYeacUwBoK/r2EpkbJPAlBg4Fl2Jv9RUJgYmqhM0Y3uvSfrlwnZA/A0NGPTQ5XYadc X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1945286a-540d-467a-13b8-08dbf1412b80 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2023 01:10:41.0547 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: hqfUjf6+JZKBQgp7fJUPNnUzaw3I+ZlleFlAmAzIN1Rhie2ZJ4umh5si9CV3mlsx X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5484 Compared to every other driver SMMU supports a lot of different formats for it's firmware description: - The legacy OF mmu-masters with a 1 cell id - The OF iommus with a 1 cell id - The OF iommus with a 2 cell id - The OF iommus with a 1 cell id and stream-match-mask - ACPI with a 1 cell id They all get reduced down to a single array of u32 ids in the driver. Store the id array as a flex array in the arm_smmu_master_cfg, and change the smendx to an allocated array. This allows using the iommu_fw_alloc_per_device_ids() path for ACPI. Have the legacy flow just allocate the cfg of the proper size and copy the cells into the ids. The OF and ACPI flows all call iommu_iort_get_single_iommu(). ACPI will use iommu_fw_alloc_per_device_ids(). The remaining OF flows will make another pass using iommu_of_xlate() to parse the complex details and format the IDs list. Remove fwspec from the other places in the driver. Directly call iort_iommu_get_resv_regions() and pass in the internal id array instead of getting it from the fwspec. Signed-off-by: Jason Gunthorpe --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 6 +- drivers/iommu/arm/arm-smmu/arm-smmu.c | 205 +++++++++++---------- drivers/iommu/arm/arm-smmu/arm-smmu.h | 13 +- 3 files changed, 118 insertions(+), 106 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index 549ae4dba3a681..95199de33ca865 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -101,15 +101,15 @@ static void qcom_adreno_smmu_resume_translation(const void *cookie, bool termina static bool qcom_adreno_smmu_is_gpu_device(struct device *dev) { - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); + struct arm_smmu_master_cfg *cfg = dev_iommu_priv_get(dev); int i; /* * The GPU will always use SID 0 so that is a handy way to uniquely * identify it and configure it for per-instance pagetables */ - for (i = 0; i < fwspec->num_ids; i++) { - u16 sid = FIELD_GET(ARM_SMMU_SMR_ID, fwspec->ids[i]); + for (i = 0; i < cfg->num_ids; i++) { + u16 sid = FIELD_GET(ARM_SMMU_SMR_ID, cfg->ids[i]); if (sid == QCOM_ADRENO_SMMU_GPU_SID) return true; diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c index 02b8dc4f366aa9..f18d40532af433 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c @@ -34,11 +34,11 @@ #include #include #include +#include #include #include "arm-smmu.h" -#include "../../dma-iommu.h" /* * Apparently, some Qualcomm arm64 platforms which appear to expose their SMMU @@ -89,6 +89,8 @@ static struct arm_smmu_domain *to_smmu_domain(struct iommu_domain *dom) static struct platform_driver arm_smmu_driver; static struct iommu_ops arm_smmu_ops; +static int arm_smmu_of_xlate(struct iommu_device *iommu, + struct of_phandle_args *args, void *priv); #ifdef CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS static struct device_node *dev_get_dev_node(struct device *dev) @@ -126,21 +128,21 @@ static int __find_legacy_master_phandle(struct device *dev, void *data) return err == -ENOENT ? 0 : err; } -static int arm_smmu_register_legacy_master(struct device *dev, - struct arm_smmu_device **smmu) +static struct arm_smmu_master_cfg * +arm_smmu_register_legacy_master(struct device *dev) { + struct arm_smmu_master_cfg *cfg; struct device *smmu_dev; struct device_node *np; struct of_phandle_iterator it; void *data = ⁢ - u32 *sids; __be32 pci_sid; int err; np = dev_get_dev_node(dev); if (!np || !of_property_present(np, "#stream-id-cells")) { of_node_put(np); - return -ENODEV; + return ERR_PTR(-ENODEV); } it.node = np; @@ -149,9 +151,9 @@ static int arm_smmu_register_legacy_master(struct device *dev, smmu_dev = data; of_node_put(np); if (err == 0) - return -ENODEV; + return ERR_PTR(-ENODEV); if (err < 0) - return err; + return ERR_PTR(err); if (dev_is_pci(dev)) { /* "mmu-masters" assumes Stream ID == Requester ID */ @@ -161,26 +163,20 @@ static int arm_smmu_register_legacy_master(struct device *dev, it.cur_count = 1; } - err = iommu_fwspec_init(dev, &smmu_dev->of_node->fwnode, - &arm_smmu_ops); - if (err) - return err; + cfg = kzalloc(struct_size(cfg, ids, it.cur_count), GFP_KERNEL); + if (!cfg) + return ERR_PTR(-ENOMEM); - sids = kcalloc(it.cur_count, sizeof(*sids), GFP_KERNEL); - if (!sids) - return -ENOMEM; - - *smmu = dev_get_drvdata(smmu_dev); - of_phandle_iterator_args(&it, sids, it.cur_count); - err = iommu_fwspec_add_ids(dev, sids, it.cur_count); - kfree(sids); - return err; + cfg->num_ids = it.cur_count; + cfg->smmu = dev_get_drvdata(smmu_dev); + of_phandle_iterator_args(&it, cfg->ids, it.cur_count); + return 0; } #else -static int arm_smmu_register_legacy_master(struct device *dev, - struct arm_smmu_device **smmu) +static struct arm_smmu_master_cfg * +arm_smmu_register_legacy_master(struct device *dev) { - return -ENODEV; + return ERR_PTR(-ENODEV); } #endif /* CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS */ @@ -1019,7 +1015,6 @@ static bool arm_smmu_free_sme(struct arm_smmu_device *smmu, int idx) static int arm_smmu_master_alloc_smes(struct device *dev) { - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); struct arm_smmu_master_cfg *cfg = dev_iommu_priv_get(dev); struct arm_smmu_device *smmu = cfg->smmu; struct arm_smmu_smr *smrs = smmu->smrs; @@ -1027,9 +1022,9 @@ static int arm_smmu_master_alloc_smes(struct device *dev) mutex_lock(&smmu->stream_map_mutex); /* Figure out a viable stream map entry allocation */ - for_each_cfg_sme(cfg, fwspec, i, idx) { - u16 sid = FIELD_GET(ARM_SMMU_SMR_ID, fwspec->ids[i]); - u16 mask = FIELD_GET(ARM_SMMU_SMR_MASK, fwspec->ids[i]); + for_each_cfg_sme(cfg, i, idx) { + u16 sid = FIELD_GET(ARM_SMMU_SMR_ID, cfg->ids[i]); + u16 mask = FIELD_GET(ARM_SMMU_SMR_MASK, cfg->ids[i]); if (idx != INVALID_SMENDX) { ret = -EEXIST; @@ -1051,7 +1046,7 @@ static int arm_smmu_master_alloc_smes(struct device *dev) } /* It worked! Now, poke the actual hardware */ - for_each_cfg_sme(cfg, fwspec, i, idx) + for_each_cfg_sme(cfg, i, idx) arm_smmu_write_sme(smmu, idx); mutex_unlock(&smmu->stream_map_mutex); @@ -1066,14 +1061,13 @@ static int arm_smmu_master_alloc_smes(struct device *dev) return ret; } -static void arm_smmu_master_free_smes(struct arm_smmu_master_cfg *cfg, - struct iommu_fwspec *fwspec) +static void arm_smmu_master_free_smes(struct arm_smmu_master_cfg *cfg) { struct arm_smmu_device *smmu = cfg->smmu; int i, idx; mutex_lock(&smmu->stream_map_mutex); - for_each_cfg_sme(cfg, fwspec, i, idx) { + for_each_cfg_sme(cfg, i, idx) { if (arm_smmu_free_sme(smmu, idx)) arm_smmu_write_sme(smmu, idx); cfg->smendx[i] = INVALID_SMENDX; @@ -1082,8 +1076,7 @@ static void arm_smmu_master_free_smes(struct arm_smmu_master_cfg *cfg, } static int arm_smmu_domain_add_master(struct arm_smmu_domain *smmu_domain, - struct arm_smmu_master_cfg *cfg, - struct iommu_fwspec *fwspec) + struct arm_smmu_master_cfg *cfg) { struct arm_smmu_device *smmu = smmu_domain->smmu; struct arm_smmu_s2cr *s2cr = smmu->s2crs; @@ -1096,7 +1089,7 @@ static int arm_smmu_domain_add_master(struct arm_smmu_domain *smmu_domain, else type = S2CR_TYPE_TRANS; - for_each_cfg_sme(cfg, fwspec, i, idx) { + for_each_cfg_sme(cfg, i, idx) { if (type == s2cr[idx].type && cbndx == s2cr[idx].cbndx) continue; @@ -1111,24 +1104,10 @@ static int arm_smmu_domain_add_master(struct arm_smmu_domain *smmu_domain, static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) { struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); - struct arm_smmu_master_cfg *cfg; - struct arm_smmu_device *smmu; + struct arm_smmu_master_cfg *cfg = dev_iommu_priv_get(dev); + struct arm_smmu_device *smmu = cfg->smmu; int ret; - /* - * FIXME: The arch/arm DMA API code tries to attach devices to its own - * domains between of_xlate() and probe_device() - we have no way to cope - * with that, so until ARM gets converted to rely on groups and default - * domains, just say no (but more politely than by dereferencing NULL). - * This should be at least a WARN_ON once that's sorted. - */ - cfg = dev_iommu_priv_get(dev); - if (!cfg) - return -ENODEV; - - smmu = cfg->smmu; - ret = arm_smmu_rpm_get(smmu); if (ret < 0) return ret; @@ -1148,7 +1127,7 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) } /* Looks ok, so add the device to the domain */ - ret = arm_smmu_domain_add_master(smmu_domain, cfg, fwspec); + ret = arm_smmu_domain_add_master(smmu_domain, cfg); /* * Setup an autosuspend delay to avoid bouncing runpm state. @@ -1325,59 +1304,85 @@ static bool arm_smmu_capable(struct device *dev, enum iommu_cap cap) } } -static -struct arm_smmu_device *arm_smmu_get_by_fwnode(struct fwnode_handle *fwnode) +static struct arm_smmu_master_cfg * +arm_smmu_probe_new_master(struct iommu_probe_info *pinf) { - struct device *dev = driver_find_device_by_fwnode(&arm_smmu_driver.driver, - fwnode); - put_device(dev); - return dev ? dev_get_drvdata(dev) : NULL; -} - -static struct iommu_device *arm_smmu_probe_device(struct device *dev) -{ - struct arm_smmu_device *smmu = NULL; struct arm_smmu_master_cfg *cfg; - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); - int i, ret; + struct arm_smmu_device *smmu; - if (using_legacy_binding) { - ret = arm_smmu_register_legacy_master(dev, &smmu); + smmu = iommu_iort_get_single_iommu(pinf, &arm_smmu_ops, NULL, + struct arm_smmu_device, iommu); + if (IS_ERR(smmu)) + return ERR_CAST(smmu); + + if (!pinf->of_master_np) { + /* In ACPI mode the smmu uses the usual u32 format */ + cfg = iommu_fw_alloc_per_device_ids(pinf, cfg); + if (IS_ERR(cfg)) + return cfg; + cfg->acpi_fwnode = iommu_fw_acpi_fwnode(pinf); + } else { + unsigned int num_ids; + int ret; /* - * If dev->iommu_fwspec is initally NULL, arm_smmu_register_legacy_master() - * will allocate/initialise a new one. Thus we need to update fwspec for - * later use. + * In OF mode it supports several different formats for the arg, + * pass through arm_smmu_of_xlate to extract it. */ - fwspec = dev_iommu_fwspec_get(dev); - if (ret) - goto out_free; - } else { - smmu = arm_smmu_get_by_fwnode(fwspec->iommu_fwnode); + num_ids = iommu_of_num_ids(pinf); + cfg = kzalloc(struct_size(cfg, ids, num_ids), GFP_KERNEL); + if (!cfg) + return ERR_PTR(-ENOMEM); + + ret = iommu_of_xlate(pinf, &arm_smmu_ops, -1, + &arm_smmu_of_xlate, cfg); + if (ret) { + kfree(cfg); + return ERR_PTR(ret); + } } + cfg->smmu = smmu; + return cfg; +} + +static struct iommu_device *arm_smmu_probe_device(struct iommu_probe_info *pinf) +{ + struct arm_smmu_master_cfg *cfg; + struct device *dev = pinf->dev; + struct arm_smmu_device *smmu; + int i, ret; + + if (using_legacy_binding) + cfg = arm_smmu_register_legacy_master(dev); + else + cfg = arm_smmu_probe_new_master(pinf); + if (IS_ERR(cfg)) + return ERR_CAST(cfg); + smmu = cfg->smmu; + ret = -EINVAL; - for (i = 0; i < fwspec->num_ids; i++) { - u16 sid = FIELD_GET(ARM_SMMU_SMR_ID, fwspec->ids[i]); - u16 mask = FIELD_GET(ARM_SMMU_SMR_MASK, fwspec->ids[i]); + for (i = 0; i < cfg->num_ids; i++) { + u16 sid = FIELD_GET(ARM_SMMU_SMR_ID, cfg->ids[i]); + u16 mask = FIELD_GET(ARM_SMMU_SMR_MASK, cfg->ids[i]); if (sid & ~smmu->streamid_mask) { dev_err(dev, "stream ID 0x%x out of range for SMMU (0x%x)\n", sid, smmu->streamid_mask); - goto out_free; + goto out_cfg_free; } if (mask & ~smmu->smr_mask_mask) { dev_err(dev, "SMR mask 0x%x out of range for SMMU (0x%x)\n", mask, smmu->smr_mask_mask); - goto out_free; + goto out_cfg_free; } } ret = -ENOMEM; - cfg = kzalloc(offsetof(struct arm_smmu_master_cfg, smendx[i]), - GFP_KERNEL); + cfg->smendx = kzalloc(array_size(sizeof(*cfg->smendx), cfg->num_ids), + GFP_KERNEL); if (!cfg) - goto out_free; + goto out_cfg_free; cfg->smmu = smmu; dev_iommu_priv_set(dev, cfg); @@ -1400,15 +1405,13 @@ static struct iommu_device *arm_smmu_probe_device(struct device *dev) return &smmu->iommu; out_cfg_free: + kfree(cfg->smendx); kfree(cfg); -out_free: - iommu_fwspec_free(dev); return ERR_PTR(ret); } static void arm_smmu_release_device(struct device *dev) { - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); struct arm_smmu_master_cfg *cfg = dev_iommu_priv_get(dev); int ret; @@ -1416,10 +1419,11 @@ static void arm_smmu_release_device(struct device *dev) if (ret < 0) return; - arm_smmu_master_free_smes(cfg, fwspec); + arm_smmu_master_free_smes(cfg); arm_smmu_rpm_put(cfg->smmu); + kfree(cfg->smendx); kfree(cfg); } @@ -1438,13 +1442,12 @@ static void arm_smmu_probe_finalize(struct device *dev) static struct iommu_group *arm_smmu_device_group(struct device *dev) { struct arm_smmu_master_cfg *cfg = dev_iommu_priv_get(dev); - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); struct arm_smmu_device *smmu = cfg->smmu; struct iommu_group *group = NULL; int i, idx; mutex_lock(&smmu->stream_map_mutex); - for_each_cfg_sme(cfg, fwspec, i, idx) { + for_each_cfg_sme(cfg, i, idx) { if (group && smmu->s2crs[idx].group && group != smmu->s2crs[idx].group) { mutex_unlock(&smmu->stream_map_mutex); @@ -1468,7 +1471,7 @@ static struct iommu_group *arm_smmu_device_group(struct device *dev) /* Remember group for faster lookups */ if (!IS_ERR(group)) - for_each_cfg_sme(cfg, fwspec, i, idx) + for_each_cfg_sme(cfg, i, idx) smmu->s2crs[idx].group = group; mutex_unlock(&smmu->stream_map_mutex); @@ -1506,8 +1509,10 @@ static int arm_smmu_set_pgtable_quirks(struct iommu_domain *domain, return ret; } -static int arm_smmu_of_xlate(struct device *dev, struct of_phandle_args *args) +static int arm_smmu_of_xlate(struct iommu_device *iommu, + struct of_phandle_args *args, void *priv) { + struct arm_smmu_master_cfg *cfg = priv; u32 mask, fwid = 0; if (args->args_count > 0) @@ -1517,13 +1522,14 @@ static int arm_smmu_of_xlate(struct device *dev, struct of_phandle_args *args) fwid |= FIELD_PREP(ARM_SMMU_SMR_MASK, args->args[1]); else if (!of_property_read_u32(args->np, "stream-match-mask", &mask)) fwid |= FIELD_PREP(ARM_SMMU_SMR_MASK, mask); - - return iommu_fwspec_add_ids(dev, &fwid, 1); + cfg->ids[cfg->num_ids++] = fwid; + return 0; } static void arm_smmu_get_resv_regions(struct device *dev, struct list_head *head) { + struct arm_smmu_master_cfg *cfg = dev_iommu_priv_get(dev); struct iommu_resv_region *region; int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO; @@ -1534,7 +1540,10 @@ static void arm_smmu_get_resv_regions(struct device *dev, list_add_tail(®ion->list, head); - iommu_dma_get_resv_regions(dev, head); + if (cfg->acpi_fwnode) + iort_iommu_get_resv_regions(dev, head, cfg->acpi_fwnode, + cfg->ids, cfg->num_ids); + of_iommu_get_resv_regions(dev, head); } static int arm_smmu_def_domain_type(struct device *dev) @@ -1553,22 +1562,22 @@ static int arm_smmu_def_domain_type(struct device *dev) static bool arm_smmu_get_stream_id(struct device *dev, u32 *stream_id) { - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); + struct arm_smmu_master_cfg *cfg = dev_iommu_priv_get(dev); - if (fwspec->num_ids != 1) + if (cfg->num_ids != 1) return false; - *stream_id = fwspec->ids[0] & 0xffff; + *stream_id = cfg->ids[0] & 0xffff; return true; } static struct iommu_ops arm_smmu_ops = { .capable = arm_smmu_capable, .domain_alloc = arm_smmu_domain_alloc, - .probe_device = arm_smmu_probe_device, + .probe_device_pinf = arm_smmu_probe_device, .release_device = arm_smmu_release_device, .probe_finalize = arm_smmu_probe_finalize, .device_group = arm_smmu_device_group, - .of_xlate = arm_smmu_of_xlate, + .of_xlate = iommu_dummy_of_xlate, .get_resv_regions = arm_smmu_get_resv_regions, .def_domain_type = arm_smmu_def_domain_type, .tegra_dev_iommu_get_stream_id = arm_smmu_get_stream_id, diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h index 703fd5817ec11f..ba8224751fdcdc 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h @@ -378,7 +378,10 @@ struct arm_smmu_domain { struct arm_smmu_master_cfg { struct arm_smmu_device *smmu; - s16 smendx[]; + struct fwnode_handle *acpi_fwnode; + s16 *smendx; + unsigned int num_ids; + u32 ids[] __counted_by(num_ids); }; static inline u32 arm_smmu_lpae_tcr(const struct io_pgtable_cfg *cfg) @@ -446,10 +449,10 @@ struct arm_smmu_impl { }; #define INVALID_SMENDX -1 -#define cfg_smendx(cfg, fw, i) \ - (i >= fw->num_ids ? INVALID_SMENDX : cfg->smendx[i]) -#define for_each_cfg_sme(cfg, fw, i, idx) \ - for (i = 0; idx = cfg_smendx(cfg, fw, i), i < fw->num_ids; ++i) +#define cfg_smendx(cfg, i) \ + (i >= cfg->num_ids ? INVALID_SMENDX : cfg->smendx[i]) +#define for_each_cfg_sme(cfg, i, idx) \ + for (i = 0; idx = cfg_smendx(cfg, i), i < cfg->num_ids; ++i) static inline int __arm_smmu_alloc_bitmap(unsigned long *map, int start, int end) { From patchwork Thu Nov 30 01:10:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 13473785 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="s3wngbFb" Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2040.outbound.protection.outlook.com [40.107.236.40]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3151ED71; Wed, 29 Nov 2023 17:11:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=fzoFXtmWBXzsPfBCwYx586ekbkp1+qHKZh6BimWR46HgE3gyyfriSfRSmbG0D7Y81af21i14Fb8iL7C844qkYPBInD1a0QbktcINRNQyzahGpaBP7t9ePgh5Vz4Dl2hdl0nWnWWRo42I/cmzD/v9srOCDfYtbW5rFzeCP8jJZ7sELg3zO/rVs5oY+sF9lZvm6A9gFxjcUMqxZL4cpfO8teEG/8GOtoHkHAuJ/506qsGY50R2g/IZFM8dp+9zvewetUIDZTK/RDRDXNODbQzIzBzyJx52xqVdeUZDfPOKGkTAeNJVFGgrDuzdAiK1Jj1g8kWswR8q7YlNohc5GoPfyA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=fXP8tNimHbY+P2znJMc85H2A6muYmbWuFS7YeFp+CTM=; b=gB3u+y5bfwmO+JiD8taKxphua9V4E4F1xCTnY1IfV/EdVNzQ002T3/7jzz32vSZaflO+Rl3fp6OJLw/M70fLqrMj6L98QBOb/tVT6eG5QdfmHPz+pRXaOfBGUO1lGFEh8LjMToDAGgauwSR22fRCBq92PbrOlzatG9X5a6SlMPe4xe0e6Rnq+xllgRMF3a41u2sRhB31r9cSAKqSo3iUzIAjCN2qYTcmQm/C2FvLRqFuGhbjcQ8CXRMHEShicrKFI1rC4/+YrnCCEU04Rym/KeHXrvZHuOpn1M7lyN0JdUjCCfJ56hlMkkIPPbAvq0jdtYJaekgXE+5LYY0S1P7+lg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=fXP8tNimHbY+P2znJMc85H2A6muYmbWuFS7YeFp+CTM=; b=s3wngbFbOoI2792SiKY/cUYh0g3S/j/PfpsXAVbdXLwe7wtU2iYmslRfI0pPSyDaYwjw+XNbPImOs0OJtaDhhr1Y+fX0bdqksGx6Tm72ntPFEMxVcMeXGh8Skb83zpt+tzNAULuPvtyeGRhGOYFthRIx1v3q+SJzi2ysXLrRLopngcbtLxlhqtabzYWoxKORAqW/xxK4lA2S0X0Zp3z9ymmJcne/TOuKM6leMWkT5AmS74ktBgH97DvW6mIzZs4Fq8uHIklV2+RBmkjXeCyD4OEaMlAI/8LuVkbBBELasb2mwNpdqFQh/u8+VE/KD3fsy194xsE6HPj5dW+amIbUtQ== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by DM6PR12MB4484.namprd12.prod.outlook.com (2603:10b6:5:28f::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.23; Thu, 30 Nov 2023 01:11:26 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.7046.015; Thu, 30 Nov 2023 01:11:26 +0000 From: Jason Gunthorpe To: acpica-devel@lists.linux.dev, Andy Gross , Alim Akhtar , Alyssa Rosenzweig , Bjorn Andersson , AngeloGioacchino Del Regno , asahi@lists.linux.dev, Baolin Wang , devicetree@vger.kernel.org, Frank Rowand , Hanjun Guo , "Gustavo A. R. Silva" , Heiko Stuebner , iommu@lists.linux.dev, Jean-Philippe Brucker , Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kees Cook , Konrad Dybcio , Krzysztof Kozlowski , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Lorenzo Pieralisi , Marek Szyprowski , Hector Martin , Matthias Brugger , Orson Zhai , "Rafael J. Wysocki" , Rob Clark , Robert Moore , Rob Herring , Robin Murphy , Samuel Holland , Sudeep Holla , Sven Peter , Thierry Reding , Krishna Reddy , virtualization@lists.linux.dev, Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: =?utf-8?q?Andr=C3=A9_Draszik?= , patches@lists.linux.dev Subject: [PATCH 28/30] iommu: Call all drivers if there is no fwspec Date: Wed, 29 Nov 2023 21:10:35 -0400 Message-ID: <28-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> In-Reply-To: <0-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> References: X-ClientProxiedBy: SA0PR13CA0030.namprd13.prod.outlook.com (2603:10b6:806:130::35) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|DM6PR12MB4484:EE_ X-MS-Office365-Filtering-Correlation-Id: f67500fe-40c5-4676-d4a3-08dbf1412d51 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: kU3T7H5J57NLM9QajWOnU7z7Xu9y794iVNtOqReqjjMT9Tu3yv2lFF8WAgFzrOqUWvpglv1Igb3RhXi2xM94Vmx3ebqu31En5zdMgZdN2j6yCnaFCTlapBrEjZ07EFM02cLu5UlvXpr0O2YLeKQqySJlZPiFsZy6iPky8VAIaywxdG4vGtMxVL6Up4OzMueg6OGciJxgdCDn7Jbcn0ZUqHn3K1ym+q5+8vyrxsqmsFB1GWogzupFWDt4RGofVfAoS2bMJ9h+j/OlqIOZ0CcUv709vKKkqEIsu00l4IOoZmX6C5Zd3noH4KZSQ5tAfdJXpP5uiZBR3eX8cVBF0HAQCyY3Erel1ZQ0UzCBMLqd27W+pQvoKQ4CqvObpWlzzj3xtlt+jxiLwH+ZKkGyOeg7Gmnb018jPv6bkNLgPvGyE48yby4y2X43+C/mhKh9gib9m26cHq4bcioT+oSPmn90EvCigfgVy+3RpxEkuZ+9Er4LN91nrNVkLndQxMeBUneW/bnjVEPaAklk5VZZgViEQtZAqC6+wAKPyfQRp7dGgdwKpe0gAQSfo5tdmEBQE8GmA3Plk89UnM/zCCZBQgJoIkEAHk2ynbKiPI2fFEEsp6gsEOnFprXEbm5h9DHRPEffpcudc1+f/Lwiy5bAvwmgww== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:LV2PR12MB5869.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(376002)(366004)(396003)(136003)(346002)(39860400002)(230922051799003)(1800799012)(451199024)(186009)(64100799003)(83380400001)(1191002)(2616005)(26005)(921008)(66476007)(66946007)(66556008)(7406005)(7366002)(7416002)(110136005)(2906002)(8676002)(4326008)(8936002)(86362001)(5660300002)(41300700001)(6506007)(6666004)(6512007)(36756003)(316002)(478600001)(6486002)(202311291699003)(38100700002);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: r3OsdJrBhVIA+ZSfZKD6MQxElvohXeb8xslb73RAKupEeYHmd/CydVrE2+CYUsrVOF42DMuBW55zsqBMyZfs3OztqOw7he9GYAcFZWzjCohoE9tKzYE2FqeWvjKPp6Nf2one0OYjZOr82gRrisxHrTSr9Wz8H6jRtEcoLRAqoQw45RzZytR6L/qzh1ORcI0wqFwIdJX170WWoyymABvPtUsxx8ndY47CWtF9PDXc7JsI2VQnMXPI+t7gfrNqy/b/junKEaltSde2B4oFoN+RLhhF75uEn07pd7Z2coRkUxMd8jtnKfuJ+EmzimuXyl43yk4NgZdNRJIxG5ftLTVndNOGZYDDgoSiLn0KVlaBbXH09SRjC8ktap8vOUrigULSwYkkQLkmFxNjTLO5phGmL302qpMNCuChIQoRiB6fx6oSWImvMPRe38EFmoG1DBXN3S/EMjEmFAmabNOoACaTVUEbFxJs3nsxK/o3M10UhlzCmkgMnapIZOgKG0YulADBN7a0hkP4/0uEqTS9ff8WxMJSqgpZGmWZMxlKu48TmxDe3lzvm6ZoUZAP+s+0afKgfKaC2BO01jB2pHrIqt5paOVUcNLy/8GlmNsrgU3gST+fu1wP99Q4vsfs27xb/8hc8vKkQQTebLIKmy6YuOyp0LWchuAsiIlCQ+ARMHJFND8/JjyoRIJCFzZCT5uVScLUPEAknF1G36sveW68SYquR4aFSMqgGmustnm46nElOaMsD9JxKApJmpCuOyePfWsC1H6HBA5kiGxDl+lSMhX36/lQO2hosmef4wv+g9eMH9WhInszOlcyv0kzlYohlobDGDn5g+3is3cpXZkmmdDjetyzZRH0jo+IInH+0CFZu5hnr70BgM1FomN4k4bxk72unbpxu8US3TckRuZSna1CnHOL8/u69s+zlUY34gWeOi/JKrgKmj9rR9C6qKaqrh81YNmpmk0t2S5nHsrUtHQvU/k30worvyMFLRgJIwKjV7S9jLDijlBR/meGUe0szE35nLA2KoFlQ2w7+rNGUKEd0nlUGYU3CVqHoRjtyaXBWFBSotVufp0RNMip3TqoAzkCGfHDkl6Lj2Bn2xmbsA/+etx8sGi+KYVwdOQXrJV+8+Fe+LuRLLZMdFIfS3Y7iVfYro+LjMjuudXkHKzTvz3ZmR1F7diUEGIsn0whZHpx928lNtBv/o2F0ZXzp+bwI2VEpyrVMdViYLe9JmUzwJeCr5c6RMN4AQFWEtqRRGYZPE9U6sTbxhAns2JwdjZEcW/AvwN7TkVInvdsF7ipvMh4W1WEMOcdJ57rbCqqZAb4ZzKkwVo2nSC5h/Wycs/x4NtJddua7xgmfLB/mdUALnjhVLTkop+qUyI88cUBF3xg2/6N0TbLQvfNtw0tl8p8OXQAHQJG9PzP4wygd2/lUT1RTkFxY/4hzYv1MsbtpUn9s8N/txi65RSuNHz92nwSkUxFZX0DtV2L8vYXWKP7qFP9GDkgieHeUG6FnvNnLSCgIDdL4W7N4/sHJn53Z8AX9avvGuRSJuKR8PK1kVhI9ts7sIUmI716MAo0H1am2tjWz5DvuvRKDkLJNmFhmWnXwUhd X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: f67500fe-40c5-4676-d4a3-08dbf1412d51 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2023 01:10:43.9426 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: TEOSbs4TX0OsynOw7k+u1QMSzSAFEHuPp5BjKVlPQuf9rZ/slvmuhCDeEsWEh4zy X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4484 Now all the iommu drivers can self probe by checking the struct device to see if it has an appropriate FW attached to it. We don't need the concept of "global" drivers with a NULL fwspec, just invoke all the ops. Real systems only have one ops, so this effectively invokes the single op in the system to probe each device. If there are multiple ops we invoke each one once, and drivers that don't understand the struct device should return -ENODEV. Signed-off-by: Jason Gunthorpe --- drivers/iommu/iommu.c | 59 +++++++++++++++++++++++++++++++++++-------- 1 file changed, 48 insertions(+), 11 deletions(-) diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index 7468a64778931b..54e3f14429b3b4 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -241,6 +241,26 @@ static int remove_iommu_group(struct device *dev, void *data) return 0; } +static void iommu_device_add(struct iommu_device *iommu) +{ + struct iommu_device *cur; + + /* + * Keep the iommu_device_list grouped by ops so that + * iommu_find_init_device() works efficiently. + */ + mutex_lock(&iommu_probe_device_lock); + list_for_each_entry(cur, &iommu_device_list, list) { + if (cur->ops == iommu->ops) { + list_add(&iommu->list, &cur->list); + goto out; + } + } + list_add(&iommu->list, &iommu_device_list); +out: + mutex_unlock(&iommu_probe_device_lock); +} + /** * iommu_device_register() - Register an IOMMU hardware instance * @iommu: IOMMU handle for the instance @@ -262,9 +282,7 @@ int iommu_device_register(struct iommu_device *iommu, if (hwdev) iommu->fwnode = dev_fwnode(hwdev); - mutex_lock(&iommu_probe_device_lock); - list_add_tail(&iommu->list, &iommu_device_list); - mutex_unlock(&iommu_probe_device_lock); + iommu_device_add(iommu); for (int i = 0; i < ARRAY_SIZE(iommu_buses) && !err; i++) err = bus_iommu_probe(iommu_buses[i]); @@ -502,6 +520,29 @@ static void iommu_deinit_device(struct device *dev) DEFINE_MUTEX(iommu_probe_device_lock); +static int iommu_find_init_device(struct iommu_probe_info *pinf) +{ + const struct iommu_ops *ops = NULL; + struct iommu_device *iommu; + int ret; + + lockdep_assert_held(&iommu_probe_device_lock); + + /* + * Each unique ops gets a chance to claim the device, -ENODEV means the + * driver does not support the device. + */ + list_for_each_entry(iommu, &iommu_device_list, list) { + if (iommu->ops != ops) { + ops = iommu->ops; + ret = iommu_init_device(pinf, iommu->ops); + if (ret != -ENODEV) + return ret; + } + } + return -ENODEV; +} + static int __iommu_probe_device(struct iommu_probe_info *pinf) { struct device *dev = pinf->dev; @@ -524,13 +565,6 @@ static int __iommu_probe_device(struct iommu_probe_info *pinf) ops = fwspec->ops; if (!ops) return -ENODEV; - } else { - struct iommu_device *iommu; - - iommu = iommu_device_from_fwnode(NULL); - if (!iommu) - return -ENODEV; - ops = iommu->ops; } /* @@ -546,7 +580,10 @@ static int __iommu_probe_device(struct iommu_probe_info *pinf) if (dev->iommu_group) return 0; - ret = iommu_init_device(pinf, ops); + if (ops) + ret = iommu_init_device(pinf, ops); + else + ret = iommu_find_init_device(pinf); if (ret) return ret; From patchwork Thu Nov 30 01:10:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 13473780 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="toxmJ++4" Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2082.outbound.protection.outlook.com [40.107.243.82]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7265910F4; Wed, 29 Nov 2023 17:11:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=jaVXQ/GdiS4/MM01LjYPDi2mOY7bP8E+B4950aBfBhpifZHopNMCkzj0ZxxYzebYkjiyFR7ZxSsZdNq2W/FqkGlKoIu5/6T7AZHB9qn1ntQ80rwhpdmZg0NRwUz9t+qloicLLOizlIrr8dEi49bIxplOTzIsWdTaUbWlVALHshfrk9VaU7j7teeC/RAc6cFh5cOjgqkgps4nVq1J/5E9cC+NTa4FBj9ElRVn3+M2KxdtGwLz1O9NNF4B7qpnO3TV4QXXlRsSiU0t+8CnwciWLqvd3CcMpPJ7M97ZYsdz7INWwwdMgMCfm/k98tX7CFF66f7qdptACgsyp51LkpcKcQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=nT1eA7akm0ounCeP3DFqrDerCBMCleCaGNYkjXyX3iQ=; b=ElT/gvAKgmUdWDv0i5cSo2BsZNYXsXQ+RMVbxEiLl98I2aTuai/kfvVkkJkFlObkimXRIDnPsCz6F/VivlG5HMDlUaC++p4NwwarzSgeXS6Ncx0sFpPAOjRI/3ht0b7gUmSRpyVoPUqCyz3rbCuo5uASMW6RNTlWiVifj3APoY4IY1TV6g0cNxjQcvToRiCh9XpfMewONkhTUCAvdY8DMQdGM78qjt+4nHzaDLgZQEdoSIdE3b631bgvpLa/9oZ5nbdpgmn1khyILeH4kRSYw/IyuvVZN4US/DCmXY/tUD/SsBw8ieK+JC/ydO/GohDYx9iju0IFQNTb/y27SQxSjw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=nT1eA7akm0ounCeP3DFqrDerCBMCleCaGNYkjXyX3iQ=; b=toxmJ++4iznt30DF6x5fUhU13ZRwZ5HHE3qTyFXMVeAKZbnEr27UdqBR3i+anW0rx6qXEeEtDeMByHVRrE//NB0cfGMxYzcdimqZlX+KXjT/Tcot9bFFojwqtFdPllXsbvC0WIaDzzuUkZd4fISWcQFxOITx7ImGBt5lEgiwQL8O7nsPnJKatbN7fuicXU8aWRHRJInQfEtr/KSYY1QPSi7rKA0eUb/EK0hdrQx6ax5IRSXjheFsTstAy+xAKVKVNeHG9+BKAzRas1jEWFVdUgIlJAgofcd4Ig5/+aqUEAH6KOyvzcKWefrzOABlDOULq+c7JKJmAObpTobP+TTKrg== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by PH0PR12MB5484.namprd12.prod.outlook.com (2603:10b6:510:eb::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.24; Thu, 30 Nov 2023 01:10:53 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.7046.015; Thu, 30 Nov 2023 01:10:53 +0000 From: Jason Gunthorpe To: acpica-devel@lists.linux.dev, Andy Gross , Alim Akhtar , Alyssa Rosenzweig , Bjorn Andersson , AngeloGioacchino Del Regno , asahi@lists.linux.dev, Baolin Wang , devicetree@vger.kernel.org, Frank Rowand , Hanjun Guo , "Gustavo A. R. Silva" , Heiko Stuebner , iommu@lists.linux.dev, Jean-Philippe Brucker , Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kees Cook , Konrad Dybcio , Krzysztof Kozlowski , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Lorenzo Pieralisi , Marek Szyprowski , Hector Martin , Matthias Brugger , Orson Zhai , "Rafael J. Wysocki" , Rob Clark , Robert Moore , Rob Herring , Robin Murphy , Samuel Holland , Sudeep Holla , Sven Peter , Thierry Reding , Krishna Reddy , virtualization@lists.linux.dev, Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: =?utf-8?q?Andr=C3=A9_Draszik?= , patches@lists.linux.dev Subject: [PATCH 29/30] iommu: Check for EPROBE_DEFER using the new FW parsers Date: Wed, 29 Nov 2023 21:10:36 -0400 Message-ID: <29-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> In-Reply-To: <0-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> References: X-ClientProxiedBy: SN6PR16CA0037.namprd16.prod.outlook.com (2603:10b6:805:ca::14) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|PH0PR12MB5484:EE_ X-MS-Office365-Filtering-Correlation-Id: 66171c9d-1f9d-4572-1f12-08dbf1412c43 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Ro9hozDsvDBRaqlWAIL453b6IWMtgq8sY73KEXnqBZLfQpodT7lVWkT0fTVHZRCGGHKkSPIwF1yX2Zdu9ChKODkdTWQPKwkE/WCGag0LscHeCf0EudEAla8bJNB95BWP9EGT3TN1aZwo7jTJ+BbDOBMXwhtufEK0pJ1la7h5YvQEOZdFlNGKL40JgVvJJBd+3Or1vrItw+Wr9Fz6XSplY/OU/k3u/uXFNB58Q/AxT2bWHQY5eXyS3sOQcIH5+DC969Nl7HaqHV4WlmUjD+mYJiGGt77A7/kFPfXeY5fDKNeVAIWrN2GtGxKQS9Ee5LemaMBDTjJ+5tTFtuxEH4njgEhz7EZUpAnQIkpJ2/8MVmQYrvn1bXBB8UtSlsjuUM/vjF5TXv3t75V0EBbHsVzLcU7AXZIPxLq8cB4CMygGEHsSPJ2omBAd/XkxV08YT6r/ux6eegC61GXBei+SLo5FvFzeDSNXGRijEobYQP93CnubciRjjNUJhdfVoVHT/LbhRN+Dgq6MUQxz0BCXYmgtqvUYA9gKshw+OYqY+lr3gBI+OPtd7Bke0pj/O+FRWSMQO7MseXVDlqZB4BsX3P6f/dZiQ6NuLBvmd6bwTh8iMb6pNxLYl6NaOBZbII51mQO7M+pPsPDZYII/M+iky53vsQ== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:LV2PR12MB5869.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(366004)(346002)(136003)(396003)(39860400002)(376002)(230922051799003)(451199024)(1800799012)(186009)(64100799003)(1191002)(8936002)(110136005)(8676002)(316002)(66556008)(4326008)(86362001)(66476007)(6486002)(478600001)(66946007)(41300700001)(36756003)(921008)(7416002)(7366002)(2906002)(7406005)(5660300002)(38100700002)(2616005)(6512007)(6506007)(6666004)(83380400001)(26005)(202311291699003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: rhShRIuRt0dRfKgjQd/aw6Vof4e9hin0iG++ZhmNipGFMit3k+Qk7n1F0me6BgKgbo5dBfl8Jcr7Jx1X8k1R4WKspA4U3a6Ltf/SCTrjzSYMYM5mFpb8eLMaZnT00nVPn+5ZNKk2IAYr1HtJjnbJgKCTcWyEEU9ErlGwo35dmj5uLNaAR9JpsNIYmTFLCOCfHSCRtLLJKCBXa4r6eqcPFZLopZO2Px0UGYZlaDy4LcaQlTHs70JTj+fm4g+T1mMJW4qMr1tFrE+q8VadUUFFBS9ZyT/a2ZbPWTkAlYNLxbu9DE/mTWoj2/93i4ccnixcab6U/zVjoved/TWvjIxGXnjBF6NHjnd0JUGCPv8ue0AtzFqIUJUElJ/09GHdrF8vNQJuptZ3/oXu8F0g4/aiA1FRBnEmZW/DwFuPzIgAjlC239tG5co8ziMpKz17OnwSDIxPehpPpe9F/56B0xWHpcL7WnXFgh85tlB1ADhClzU6wcrWd5y9Qm2GbuLFf9s7Lr4y/vhFgxFSw/780y8CZ/Qn8KvYzRo4hJCLhDw6iUfNf5a0pqqetaZJo+bjvW+Of6DhyunIIMGPxI2iU8JNYMhwOdVD97vDE8cXjrNUZ94u0r0MahGNlVtA+7IJ/QvWExsMvdPtP0I/hHl/NcCgNQPScc/T2iRuJ2vU2FST44FutXPZ+fUexcTAJSe5VplFv1iKLh1Dqx8IO/uV0xQUPBuV25giob1FBTvWOpVsZhu1yGmiOtd/Q2XFE0gJaiUEXFqGTVQFJWEHd47FbSr+SNgEZT+9Q+/Pp9EvwOksG2XLvGlkUcELQD9lsUykmopSmgFuP6YElEvyyS+CcZL1dJZ6AoKaEUHLJK1Nhd9nHezWmaiwJXUpJUzkL7vWU0KOYfBt/ABHdbGqCSJCXKR2FqR7gRxOiYuPAgPcMAGX9XmieYkYXFeWbk9YLUW8IDKQS+f74WLDlLBO/4kePRag6k9yKZaP7k0fj7qprxynEp/MJUrfebclcSSFcuMcd1gJ7MGUyWRjKdlU3WMR5z5v2IUClLplM89W+KZQgxQHV+Wh7moy/IObiKkI7GUytZgCZrpOLqPHl3ZXjL7HknHO+437sPQu+CvyXBpWdKz4EiIaM+hjUUlsVelBvi0z/GvHBaxcvmkzPxte4tiGaskSkbr9PsdA7WuOk2Tc+sXJIENyCeTCwmVAanBLVk6tsI73zVPsDGfZ3HUjk/M1PlrdK9X65d6+62e2O4JtawkCDCoOj1xq5IZzeX039+NH60z534g+X72fG6yhaiFVIMZ72KdHWdULgiWG0fxbOsPjF5NVseahXOfyY1WQ0wQXgjqyELgP/Bei7e50KsTQbGj1UUqPDANLRYMR1YAAegI9tnrf1Vy5xvSFrH419F4t9vAFXJs1tKztihpkQlKyW8HghEqxk3q/Y/1rUDGNxV8Cq6wxC+oDjRH5PIcBvtnVXq8n61c02zDGhk603W5bbocMOHmpqXjeampI8g6YSTe8WPoTYTnggi5nTVBbRUe/a/vjucky/xgF9KhEE1Wa6hXQC2Vv7NmPEXh0aya6OuytG/Icqn1IyqqFe4Hd8kjCPNc5 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 66171c9d-1f9d-4572-1f12-08dbf1412c43 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2023 01:10:42.2863 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: eQW+7/rWN+5UNjQSBGx7Wfh2MeJa0w1Iwn+xkWVGL56l/io1FLqeKQfOEjKa/rdP X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5484 The last thing the iommu_fwspec logic is doing is to generate an EPROBE_DEFER if we don't have the iommu driver loaded. The OF side does this by checking for the iommus OF property and the ACPI side does this by checking both VIOT and IORT tables. Duplicate this behavior. If probing gets -ENODEV and we are under a dma_configure then ensure that all the applicable FW parsers are given a chance to run. Keep track of any parsers that may have run during the probe ops call and don't do them again. Signed-off-by: Jason Gunthorpe --- drivers/iommu/iommu.c | 51 +++++++++++++++++++++++++++++++++--- drivers/iommu/iort_iommu.c | 1 + drivers/iommu/of_iommu.c | 2 ++ drivers/iommu/viot_iommu.c | 1 + include/linux/iommu-driver.h | 3 +++ 5 files changed, 55 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index 54e3f14429b3b4..c76edc9061f123 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -518,6 +518,48 @@ static void iommu_deinit_device(struct device *dev) dev_iommu_free(dev); } +/* + * When being called from dma_configure it is necessary to check if an ENODEV + * result indicates that we haven't loaded the driver yet. Since we may not have + * any drivers registered yet we have no way to predict what kind of FW + * description could need to be parsed. Check the widely used ones we have + * common parsers for. + * + * Drivers that use FW descriptions other than these common ones (AMD, Intel, + * etc) must probe the iommus during early boot otherwise they will have + * problems with probe ordering. + * + * The *_get_single_iommu() implementations will generate EPROBE_DEFER if they + * detect a FW description with no registered iommu driver which will cause + * the driver binding from dma_configure to abort and try later. + */ +static int iommu_fw_check_deferred(struct iommu_probe_info *pinf) +{ + struct iommu_device *iommu; + + if (!pinf->is_dma_configure) + return -ENODEV; + + if (!pinf->cached_checked_of && pinf->of_master_np) { + iommu = __iommu_of_get_single_iommu(pinf, NULL, -1); + if (iommu != ERR_PTR(-ENODEV)) + return PTR_ERR(iommu); + } + + if (!pinf->cached_checked_iort && pinf->is_acpi) { + iommu = __iommu_iort_get_single_iommu(pinf, NULL, NULL); + if (iommu != ERR_PTR(-ENODEV)) + return PTR_ERR(iommu); + } + + if (!pinf->cached_checked_viot && pinf->is_acpi) { + iommu = __iommu_viot_get_single_iommu(pinf, NULL); + if (iommu != ERR_PTR(-ENODEV)) + return PTR_ERR(iommu); + } + return -ENODEV; +} + DEFINE_MUTEX(iommu_probe_device_lock); static int iommu_find_init_device(struct iommu_probe_info *pinf) @@ -540,7 +582,7 @@ static int iommu_find_init_device(struct iommu_probe_info *pinf) return ret; } } - return -ENODEV; + return iommu_fw_check_deferred(pinf); } static int __iommu_probe_device(struct iommu_probe_info *pinf) @@ -580,10 +622,13 @@ static int __iommu_probe_device(struct iommu_probe_info *pinf) if (dev->iommu_group) return 0; - if (ops) + if (ops) { ret = iommu_init_device(pinf, ops); - else + if (ret == -ENODEV) + return iommu_fw_check_deferred(pinf); + } else { ret = iommu_find_init_device(pinf); + } if (ret) return ret; diff --git a/drivers/iommu/iort_iommu.c b/drivers/iommu/iort_iommu.c index 9a997b0fd5d5f1..2174ae477486a6 100644 --- a/drivers/iommu/iort_iommu.c +++ b/drivers/iommu/iort_iommu.c @@ -88,6 +88,7 @@ __iommu_iort_get_single_iommu(struct iommu_probe_info *pinf, params = &unused_params; iommu_fw_clear_cache(pinf); + pinf->cached_checked_iort = true; err = iort_iommu_for_each_id(pinf->dev, pinf->acpi_map_id, params, parse_single_iommu, &info); if (err) diff --git a/drivers/iommu/of_iommu.c b/drivers/iommu/of_iommu.c index 6f6e442f899ded..463d17ab5057d6 100644 --- a/drivers/iommu/of_iommu.c +++ b/drivers/iommu/of_iommu.c @@ -367,6 +367,7 @@ struct iommu_device *__iommu_of_get_single_iommu(struct iommu_probe_info *pinf, return ERR_PTR(-ENODEV); iommu_fw_clear_cache(pinf); + pinf->cached_checked_of = true; err = of_iommu_for_each_id(pinf->dev, pinf->of_master_np, pinf->of_map_id, parse_single_iommu, &info); if (err) @@ -412,6 +413,7 @@ int iommu_of_xlate(struct iommu_probe_info *pinf, const struct iommu_ops *ops, .priv = priv }; pinf->num_ids = 0; + pinf->cached_checked_of = true; return of_iommu_for_each_id(pinf->dev, pinf->of_master_np, pinf->of_map_id, parse_of_xlate, &info); } diff --git a/drivers/iommu/viot_iommu.c b/drivers/iommu/viot_iommu.c index e35bd4099e6c6a..32abda73eb3b6c 100644 --- a/drivers/iommu/viot_iommu.c +++ b/drivers/iommu/viot_iommu.c @@ -61,6 +61,7 @@ __iommu_viot_get_single_iommu(struct iommu_probe_info *pinf, return ERR_PTR(-ENODEV); iommu_fw_clear_cache(pinf); + pinf->cached_checked_viot = true; err = viot_iommu_for_each_id(pinf->dev, parse_single_iommu, &info); if (err) return ERR_PTR(err); diff --git a/include/linux/iommu-driver.h b/include/linux/iommu-driver.h index 8f7089d3bb7135..aa4cbf0cb91907 100644 --- a/include/linux/iommu-driver.h +++ b/include/linux/iommu-driver.h @@ -50,6 +50,9 @@ struct iommu_probe_info { bool is_dma_configure : 1; bool is_acpi : 1; bool cached_single_iommu : 1; + bool cached_checked_of : 1; + bool cached_checked_iort : 1; + bool cached_checked_viot : 1; }; static inline void iommu_fw_clear_cache(struct iommu_probe_info *pinf) From patchwork Thu Nov 30 01:10:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 13473768 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="VmCs29sT" Received: from NAM04-DM6-obe.outbound.protection.outlook.com (mail-dm6nam04on2060.outbound.protection.outlook.com [40.107.102.60]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5517BD71; Wed, 29 Nov 2023 17:10:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=PQVJbe/rCdJ0QNzTO9fjlWVPn8w2reM2zsy9Lk4ds+Joe8BfIeuf7rIwUqAHex7638aZRpGC7if5ex//CJh7TBXd1I/lKNQzwOjdq46UZktDECM3CNr5ETXOIb64swXMJFLbz0mYqLDH7jlE5xDGHl1DVWK5vcFaBspC9QsxKUkzfeXotLuKv+bIffsK3JfFwwiaAbRii1j2GsAKuy9axLszrO8pEVJCRTaaUTnxwmGAeGhNjThvbumaEM+9TR8Rs0OvvD8jJXOtRJzaPEcGrwI3z21hoD6qKPJDn6e5PmKPmMXyTGNZRV7suah11BONLu9JeNt+xqa2iLo909Kz8Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=29OOCCTk8mlu6NkZfaPP6EDcpKq/iCHGfu7Wm1bl1pw=; b=VuTdFH5Vnzqr4N/vWdh6krPCmWArzmXzxyStBnwuQQHVLqA71yrd58cyRMmii7codMAHtAcXMU36CqFeVecgzWN7dAXGpDSVZ50+tfgm52boA2Hv69O5lF4kWbH+aG4S/DfGwehWPv7XwyESWPzgg18HLOUXOdZWyBRn1ei07OdL2XmZm3geydE4HVshqgNrD9ucTa2EHgYbe3t+oXZiw8rfu2dBNhBCu5pvkuN4pVc4pfqVc3PS3tJnZ1QEBvDPShMJQNVPlt5c5uW0YTVplIVHB8fuROgKgZtfzjOewks/Og95G9zPIa7GT3W72yUiCWSAT3efK+WHpfshgFamvg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=29OOCCTk8mlu6NkZfaPP6EDcpKq/iCHGfu7Wm1bl1pw=; b=VmCs29sTdloFDU0uhs+zSCQZzL8qNH+Uwx51x51hGtaQCFPdfm2HblS4GrJ+RunCg9tOa1HDXWB7ryWvCSgJMI4qgpz2QM42QPvVYLl4zE5eX0daDQNLy6AAeY7gd5biWcLQfG3G0zfguHgsC5T1/AhzujTRsqwePdFiwjsWRbkShLP5NPqHgbS9Zxw22FO/B5ByG/t0/aj+Hh9BXImPBYqIzatEc6rWDbBGiTtMiFphGAWJplyLs9A2g3Lw/JQCTM2kPqNWRcAyVw9RGzbL/0dz1WIuIqitaRlG64ZTqxq6U0Sx1sscSLfhdYKsbIw9GdonG418uK61J4QV+BtLcg== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) by DS0PR12MB7607.namprd12.prod.outlook.com (2603:10b6:8:13f::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7046.22; Thu, 30 Nov 2023 01:10:41 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::60d4:c1e3:e1aa:8f93%4]) with mapi id 15.20.7046.015; Thu, 30 Nov 2023 01:10:41 +0000 From: Jason Gunthorpe To: acpica-devel@lists.linux.dev, Andy Gross , Alim Akhtar , Alyssa Rosenzweig , Bjorn Andersson , AngeloGioacchino Del Regno , asahi@lists.linux.dev, Baolin Wang , devicetree@vger.kernel.org, Frank Rowand , Hanjun Guo , "Gustavo A. R. Silva" , Heiko Stuebner , iommu@lists.linux.dev, Jean-Philippe Brucker , Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kees Cook , Konrad Dybcio , Krzysztof Kozlowski , Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Lorenzo Pieralisi , Marek Szyprowski , Hector Martin , Matthias Brugger , Orson Zhai , "Rafael J. Wysocki" , Rob Clark , Robert Moore , Rob Herring , Robin Murphy , Samuel Holland , Sudeep Holla , Sven Peter , Thierry Reding , Krishna Reddy , virtualization@lists.linux.dev, Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: =?utf-8?q?Andr=C3=A9_Draszik?= , patches@lists.linux.dev Subject: [PATCH 30/30] iommu: Remove fwspec and related Date: Wed, 29 Nov 2023 21:10:37 -0400 Message-ID: <30-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> In-Reply-To: <0-v1-f82a05539a64+5042-iommu_fwspec_p2_jgg@nvidia.com> References: X-ClientProxiedBy: SA1P222CA0143.NAMP222.PROD.OUTLOOK.COM (2603:10b6:806:3c2::19) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|DS0PR12MB7607:EE_ X-MS-Office365-Filtering-Correlation-Id: c4722f09-b29e-4ff0-a5f6-08dbf1412a45 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 8f8opki8gPRRpfTdVYujbCXeyCwxplHs9x9hdrq8BuaAgkDpjvJlR7HqqrPfZmdQfpfLweQTX9uwHFtAAD1DiFDbqSEbHP+cG4PUX0FPkmFsuFxCOpTnTYkcAImPvAa2C+HChfKoAZs9c+xCkNXFFSGierl3YXHFZXxrhs9bOJjHaDjTE2x4EWMKxYEdogHetTpECZiX+Ybusk+/JrV7/4LvsDSql+eY5vfdn380BpH7j3W7yOlufSKWsslEdAr0lN/Hk+6YCVjNynBnrqkP9tAXDIi3T5xmTlnOcccF0Htqd6zYT9OiJ++143C2HeOutG8PxFd/7thHgahhZLD2wEzFedi0HrmSAKIqMxsa3XMKoIZ3owtcqd12MQlaQDgjv/WWWqtEsL0vZD7eeslouJ3QJppwstEmR1fz45pdHfw6SicSmermQpc3pOKH/jpHamnck1gbgzS0dD+AQHkWZAC+j0aiUWI6/1K9SbpFppgdfqtD4mWmOD5bkTcvVTqVilt6y+AJvhWIeDb4zVE3wt8mJyggE6PpNzTg8up0sVPkZCnXuMcJHxtp4V+aAgOBuEyYZMWKhvKk0QVrBmZGnHXoNMvzR2QuIv142h1Fs5Feol9NEaKq5Ith+1FekCwD7juASAqP6YbF0EJbaXyi/w== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:LV2PR12MB5869.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(396003)(39860400002)(346002)(136003)(366004)(376002)(230922051799003)(186009)(451199024)(64100799003)(1800799012)(38100700002)(202311291699003)(83380400001)(1191002)(5660300002)(110136005)(2906002)(30864003)(86362001)(4326008)(8676002)(8936002)(66556008)(7366002)(7406005)(7416002)(66476007)(66946007)(6486002)(478600001)(6666004)(316002)(36756003)(6506007)(41300700001)(6512007)(921008)(26005)(2616005);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 8DosQRnQZ4Drp1RHA3HtzdluU8KoMiE33yY+19JeIgEY8m6f2yoY4tEpHjRuXemwQkfhXMvxJbdjq8DE1PNQ7i7i2gR1HAPbwzZ4wgGCLhEAZtCDjNO1f1DlX9hPP9kP5rTf7VAMWSixVs1XdMTeggSn3KQS9qwNLMLD30iSRAzpzEAteZc4ed8yqRbSGWbttiocjsOeV38LIIpdDQLXFPKF6jNSQeVehmXMfCkpVi/Yv0UzuemyYMKwvqeT7pgVwuFWDtKh5yKfcZqmjtQ+gEVtxyGD7DwBXwJa4rhECZy31gfjdDtA+hJpS/dBqP6u/Xq0vigTeBEhIGp3nfrkZ1lj0Yq/UOZUYbHRIL2Z3z3rSzsis9soEvs68pGAG91Bf0+PAURlc5DrmnZSLlyo4jiqf0sN0gObFmA+I3dph2bjyZUkRzEeXcwweVV5iwT5YPL33uqAyYIs3z1jvPJq5lQB1LGJkSAWsqe6sg2RM2GvgpBm/F4d6SwlSI8FR4SnXR1Ps+AiTOrFlUuM5XQmT9qcyb8n1wsG/CMGp8eI2Dv+HBX8IDQnPonwEZrLTwDBVBbkAfsemzf8XRaq+UPGmcepyUVvFEThsWzDVLph4k4VIiHa4RMP/LSJxEpViOo2ziTDAW/ZHVaYHIiSgtvKo++2UMjl7rLr5hHHXI3bnhnS2y06aeu/Z+lsYHrfQ7UxsaPB0NSu26ARcPjno8SpIie9RwtvfZfmkFRn6VwwQUVxSfRd+9hEVblBfZAbQoTC8eRgnoe9ca69tG+r1SPU8CQdAYdWNspbnNNHYNoRijxabP3BuKr4XazIr5Mvlm+hX5gYubX5K8LDFNif1Xc0/zezDZGaUo0fv9vSBvpMBCy9UJxeHSG+dYF7JQPk7mmdqCQOe5EOimUQySaSq2g5jobu043y4/AsPD77mnbGJIdBELgG9WVPJ82MiDF34WWI1o5HUFxzZ32xr/Z3vR7vsr/rwNJK4seD/A6ohwJt4B+bQhLApMKdhJvjPL2B1pq9iNTWvdNXoOZ79FjlO6DH1c5A8ml18nnlOwNFdKs8r02iM1s4Q+hKJm+EtEfVb4Q+uzSaKiAIMx2lSwpS2H4q2xnU9OERrO9U2Gh7zI1NtKArmolbAPPKdfx6cU0JnqrCvqoEPgAgOvC/iy+eUJwEjk+Q/RGhEMjdTB8N5vdKKgZwrlAQdhJ7WUFz30js2Z6usksxqiWJzxLqWRrILUjZDiYWHqekiuyONc2cY6CLw37z0OkBvIpcchqxAcsM4u7kjTjLLZErQlGBi2RagHO4AgQPneFZut4VhLgCg4GH7akJvJQWthkSBGyK3rtbtQsKvItOUiNr1EOwwD3Hc0lM4OexL1NWe7nykpKVzBeFltKcpRfxdpvdCtnAlULbN8iM1MRlilyQxMUIidIcYBfQA+BtM6/iTCAOFQ//zvx27n55M1Rvvs8s4jyNQRE6yOMGeCLJtSn5RZBvtYycrdF7u+9AoRefm5pVPbhaZpOiBjKTo9pxj5VR58Wd0P3vQccXTn622oDmxa+f8arPVdSQ+sVL0Kl4G5sXrJNTtUWUsYJDMCLVSbbH/UsLO7hNOY9F X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: c4722f09-b29e-4ff0-a5f6-08dbf1412a45 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2023 01:10:39.0115 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: +jdv7bBgxkvQOVounTyGi/RowmY+Ei9ff0kyyKKUb/aBS+OqSlj4vCLDXJr7s4xt X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7607 Delete all the now unused code connected to fwspec. Remove all IOMMU related FW parsing from the *_dma_configure() functions. Remove no longer needed includes of iommu-driver.h in the ACPI code. Return the iommu_probe_device_lock back to being a static inside iommu.c Make __iommu_probe_device() rely on iommu_find_init_device() for everything. Signed-off-by: Jason Gunthorpe --- drivers/acpi/arm64/iort.c | 76 ---------------- drivers/acpi/scan.c | 52 +---------- drivers/acpi/viot.c | 32 ------- drivers/iommu/apple-dart.c | 1 - drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 1 - drivers/iommu/arm/arm-smmu/arm-smmu.c | 1 - drivers/iommu/arm/arm-smmu/qcom_iommu.c | 1 - drivers/iommu/dma-iommu.c | 24 ----- drivers/iommu/dma-iommu.h | 6 -- drivers/iommu/exynos-iommu.c | 1 - drivers/iommu/iommu.c | 97 +-------------------- drivers/iommu/ipmmu-vmsa.c | 1 - drivers/iommu/msm_iommu.c | 1 - drivers/iommu/mtk_iommu.c | 1 - drivers/iommu/of_iommu.c | 47 ---------- drivers/iommu/rockchip-iommu.c | 1 - drivers/iommu/sprd-iommu.c | 1 - drivers/iommu/sun50i-iommu.c | 1 - drivers/iommu/tegra-smmu.c | 1 - drivers/iommu/virtio-iommu.c | 1 - include/acpi/acpi_bus.h | 3 - include/linux/acpi_iort.h | 3 - include/linux/acpi_viot.h | 5 -- include/linux/iommu-driver.h | 10 --- include/linux/iommu.h | 70 --------------- 25 files changed, 8 insertions(+), 430 deletions(-) diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c index acd2e48590f37a..8457874c789456 100644 --- a/drivers/acpi/arm64/iort.c +++ b/drivers/acpi/arm64/iort.c @@ -796,8 +796,6 @@ void acpi_configure_pmsi_domain(struct device *dev) } #ifdef CONFIG_IOMMU_API -#include - static void iort_rmr_free(struct device *dev, struct iommu_resv_region *region) { @@ -1218,19 +1216,6 @@ void iort_put_rmr_sids(struct fwnode_handle *iommu_fwnode, } EXPORT_SYMBOL_GPL(iort_put_rmr_sids); -static inline bool iort_iommu_driver_enabled(u8 type) -{ - switch (type) { - case ACPI_IORT_NODE_SMMU_V3: - return IS_ENABLED(CONFIG_ARM_SMMU_V3); - case ACPI_IORT_NODE_SMMU: - return IS_ENABLED(CONFIG_ARM_SMMU); - default: - pr_warn("IORT node type %u does not describe an SMMU\n", type); - return false; - } -} - static bool iort_pci_rc_supports_ats(struct acpi_iort_node *node) { struct acpi_iort_root_complex *pci_rc; @@ -1239,36 +1224,6 @@ static bool iort_pci_rc_supports_ats(struct acpi_iort_node *node) return pci_rc->ats_attribute & ACPI_IORT_ATS_SUPPORTED; } -static int iort_iommu_xlate(struct acpi_iort_node *node, u32 streamid, - void *info) -{ - struct device *dev = info; - struct iommu_device *iommu; - struct fwnode_handle *iort_fwnode; - - if (!node) - return -ENODEV; - - iort_fwnode = iort_get_fwnode(node); - if (!iort_fwnode) - return -ENODEV; - - /* - * If the iommu look-up fails, this means that either - * the SMMU drivers have not been probed yet or that - * the SMMU drivers are not built in the kernel; - * Depending on whether the SMMU drivers are built-in - * in the kernel or not, defer the IOMMU configuration - * or just abort it. - */ - iommu = iommu_device_from_fwnode(iort_fwnode); - if (!iommu) - return iort_iommu_driver_enabled(node->type) ? - -EPROBE_DEFER : -ENODEV; - - return acpi_iommu_fwspec_init(dev, streamid, iort_fwnode, iommu->ops); -} - struct iort_pci_alias_info { struct device *dev; struct acpi_iort_node *node; @@ -1380,40 +1335,9 @@ int iort_iommu_for_each_id(struct device *dev, const u32 *id_in, iort_named_component_init(dev, node); return 0; } - -/** - * iort_iommu_configure_id - Set-up IOMMU configuration for a device. - * - * @dev: device to configure - * @id_in: optional input id const value pointer - * - * Returns: 0 on success, <0 on failure - */ -int iort_iommu_configure_id(struct device *dev, const u32 *id_in) -{ - struct iort_params params; - int err; - - err = iort_iommu_for_each_id(dev, id_in, ¶ms, &iort_iommu_xlate, - dev); - if (err) - return err; - - if (params.pci_rc_ats) { - struct iommu_fwspec *fwspec; - - fwspec = dev_iommu_fwspec_get(dev); - if (fwspec) - fwspec->flags |= IOMMU_FWSPEC_PCI_RC_ATS; - } - return 0; -} - #else void iort_iommu_get_resv_regions(struct device *dev, struct list_head *head) { } -int iort_iommu_configure_id(struct device *dev, const u32 *input_id) -{ return -ENODEV; } #endif static int nc_dma_get_range(struct device *dev, u64 *size) diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c index eb7406cdc9a464..c86ac07a7a6420 100644 --- a/drivers/acpi/scan.c +++ b/drivers/acpi/scan.c @@ -1545,29 +1545,9 @@ int acpi_dma_get_range(struct device *dev, const struct bus_dma_region **map) #ifdef CONFIG_IOMMU_API #include -int acpi_iommu_fwspec_init(struct device *dev, u32 id, - struct fwnode_handle *fwnode, - const struct iommu_ops *ops) -{ - int ret = iommu_fwspec_init(dev, fwnode, ops); - - if (!ret) - ret = iommu_fwspec_add_ids(dev, &id, 1); - - return ret; -} - -static inline const struct iommu_ops *acpi_iommu_fwspec_ops(struct device *dev) -{ - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); - - return fwspec ? fwspec->ops : NULL; -} - static int acpi_iommu_configure_id(struct device *dev, const u32 *id_in) { int err; - const struct iommu_ops *ops; struct iommu_probe_info pinf = { .dev = dev, .is_dma_configure = true, @@ -1575,29 +1555,14 @@ static int acpi_iommu_configure_id(struct device *dev, const u32 *id_in) .is_acpi = true, }; - /* Serialise to make dev->iommu stable under our potential fwspec */ - mutex_lock(&iommu_probe_device_lock); - /* - * If we already translated the fwspec there is nothing left to do, - * return the iommu_ops. - */ - ops = acpi_iommu_fwspec_ops(dev); - if (ops) { - mutex_unlock(&iommu_probe_device_lock); - return 0; - } - - err = iort_iommu_configure_id(dev, id_in); - if (err && err != -EPROBE_DEFER) - err = viot_iommu_configure(dev); - mutex_unlock(&iommu_probe_device_lock); - /* * If we have reason to believe the IOMMU driver missed the initial * iommu_probe_device() call for dev, replay it to get things in order. */ - if (!err && dev->bus) - err = iommu_probe_device_pinf(&pinf); + if (!dev->bus) + return 0; + + err = iommu_probe_device_pinf(&pinf); /* Ignore all other errors apart from EPROBE_DEFER */ if (err == -EPROBE_DEFER) { @@ -1606,20 +1571,11 @@ static int acpi_iommu_configure_id(struct device *dev, const u32 *id_in) dev_dbg(dev, "Adding to IOMMU failed: %d\n", err); return -ENODEV; } - if (!acpi_iommu_fwspec_ops(dev)) - return -ENODEV; return 0; } #else /* !CONFIG_IOMMU_API */ -int acpi_iommu_fwspec_init(struct device *dev, u32 id, - struct fwnode_handle *fwnode, - const struct iommu_ops *ops) -{ - return -ENODEV; -} - static int acpi_iommu_configure_id(struct device *dev, const u32 *id_in) { return -ENODEV; diff --git a/drivers/acpi/viot.c b/drivers/acpi/viot.c index 9780b1d477503e..67b7c4e21eeeb3 100644 --- a/drivers/acpi/viot.c +++ b/drivers/acpi/viot.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include @@ -298,26 +297,6 @@ void __init acpi_viot_init(void) acpi_put_table(hdr); } -static int viot_dev_iommu_init(struct viot_iommu *viommu, u32 epid, void *info) -{ - struct iommu_device *iommu; - struct device *dev = info; - - if (!viommu) - return -ENODEV; - - /* We're not translating ourself */ - if (device_match_fwnode(dev, viommu->fwnode)) - return -EINVAL; - - iommu = iommu_device_from_fwnode(viommu->fwnode); - if (!iommu) - return IS_ENABLED(CONFIG_VIRTIO_IOMMU) ? - -EPROBE_DEFER : -ENODEV; - - return acpi_iommu_fwspec_init(dev, epid, viommu->fwnode, iommu->ops); -} - struct viot_pci_iommu_alias_info { struct device *dev; viot_for_each_fn fn; @@ -378,14 +357,3 @@ int viot_iommu_for_each_id(struct device *dev, viot_for_each_fn fn, void *info) return __for_each_platform(to_platform_device(dev), fn, info); return -ENODEV; } - -/** - * viot_iommu_configure - Setup IOMMU ops for an endpoint described by VIOT - * @dev: the endpoint - * - * Return: 0 on success, <0 on failure - */ -int viot_iommu_configure(struct device *dev) -{ - return viot_iommu_for_each_id(dev, viot_dev_iommu_init, dev); -} diff --git a/drivers/iommu/apple-dart.c b/drivers/iommu/apple-dart.c index b796c68ae45ad8..81b129ed81cc03 100644 --- a/drivers/iommu/apple-dart.c +++ b/drivers/iommu/apple-dart.c @@ -987,7 +987,6 @@ static const struct iommu_ops apple_dart_iommu_ops = { .probe_device_pinf = apple_dart_probe_device, .release_device = apple_dart_release_device, .device_group = apple_dart_device_group, - .of_xlate = iommu_dummy_of_xlate, .def_domain_type = apple_dart_def_domain_type, .get_resv_regions = apple_dart_get_resv_regions, .pgsize_bitmap = -1UL, /* Restricted during dart probe */ diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 1a43c677e2feaf..71c47d3a5cdde9 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2840,7 +2840,6 @@ static struct iommu_ops arm_smmu_ops = { .probe_device_pinf = arm_smmu_probe_device, .release_device = arm_smmu_release_device, .device_group = arm_smmu_device_group, - .of_xlate = iommu_dummy_of_xlate, .get_resv_regions = arm_smmu_get_resv_regions, .remove_dev_pasid = arm_smmu_remove_dev_pasid, .dev_enable_feat = arm_smmu_dev_enable_feature, diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c index f18d40532af433..537b47cb0da2b6 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c @@ -1577,7 +1577,6 @@ static struct iommu_ops arm_smmu_ops = { .release_device = arm_smmu_release_device, .probe_finalize = arm_smmu_probe_finalize, .device_group = arm_smmu_device_group, - .of_xlate = iommu_dummy_of_xlate, .get_resv_regions = arm_smmu_get_resv_regions, .def_domain_type = arm_smmu_def_domain_type, .tegra_dev_iommu_get_stream_id = arm_smmu_get_stream_id, diff --git a/drivers/iommu/arm/arm-smmu/qcom_iommu.c b/drivers/iommu/arm/arm-smmu/qcom_iommu.c index 4baca45df99971..308b439b955be6 100644 --- a/drivers/iommu/arm/arm-smmu/qcom_iommu.c +++ b/drivers/iommu/arm/arm-smmu/qcom_iommu.c @@ -597,7 +597,6 @@ static const struct iommu_ops qcom_iommu_ops = { .probe_device_pinf = qcom_iommu_probe_device, .release_device = qcom_iommu_release_device, .device_group = generic_device_group, - .of_xlate = iommu_dummy_of_xlate, .pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M, .default_domain_ops = &(const struct iommu_domain_ops) { .attach_dev = qcom_iommu_attach_dev, diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c index 5a828c92cd38b2..e66aacc12b5ee1 100644 --- a/drivers/iommu/dma-iommu.c +++ b/drivers/iommu/dma-iommu.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #include #include @@ -456,29 +455,6 @@ void iommu_put_dma_cookie(struct iommu_domain *domain) domain->iova_cookie = NULL; } -/** - * iommu_dma_get_resv_regions - Reserved region driver helper - * @dev: Device from iommu_get_resv_regions() - * @list: Reserved region list from iommu_get_resv_regions() - * - * IOMMU drivers can use this to implement their .get_resv_regions callback - * for general non-IOMMU-specific reservations. Currently, this covers GICv3 - * ITS region reservation on ACPI based ARM platforms that may require HW MSI - * reservation. - */ -void iommu_dma_get_resv_regions(struct device *dev, struct list_head *list) -{ - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); - - if (!is_of_node(fwspec->iommu_fwnode)) { - iort_iommu_get_resv_regions(dev, list, fwspec->iommu_fwnode, - fwspec->ids, fwspec->num_ids); - } - - of_iommu_get_resv_regions(dev, list); -} -EXPORT_SYMBOL(iommu_dma_get_resv_regions); - static int cookie_init_hw_msi_region(struct iommu_dma_cookie *cookie, phys_addr_t start, phys_addr_t end) { diff --git a/drivers/iommu/dma-iommu.h b/drivers/iommu/dma-iommu.h index c829f1f82a991c..69196f421b9b10 100644 --- a/drivers/iommu/dma-iommu.h +++ b/drivers/iommu/dma-iommu.h @@ -14,8 +14,6 @@ void iommu_put_dma_cookie(struct iommu_domain *domain); int iommu_dma_init_fq(struct iommu_domain *domain); -void iommu_dma_get_resv_regions(struct device *dev, struct list_head *list); - extern bool iommu_dma_forcedac; static inline void iommu_dma_set_pci_32bit_workaround(struct device *dev) { @@ -38,10 +36,6 @@ static inline void iommu_put_dma_cookie(struct iommu_domain *domain) { } -static inline void iommu_dma_get_resv_regions(struct device *dev, struct list_head *list) -{ -} - static inline void iommu_dma_set_pci_32bit_workaround(struct device *dev) { } diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c index c301aa87fe0ff0..80cca10e8dfdcb 100644 --- a/drivers/iommu/exynos-iommu.c +++ b/drivers/iommu/exynos-iommu.c @@ -1473,7 +1473,6 @@ static const struct iommu_ops exynos_iommu_ops = { .probe_device_pinf = exynos_iommu_probe_device, .release_device = exynos_iommu_release_device, .pgsize_bitmap = SECT_SIZE | LPAGE_SIZE | SPAGE_SIZE, - .of_xlate = iommu_dummy_of_xlate, .default_domain_ops = &(const struct iommu_domain_ops) { .attach_dev = exynos_iommu_attach_device, .map_pages = exynos_iommu_map, diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index c76edc9061f123..ba0c0c7f251ace 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -42,6 +42,7 @@ static struct kset *iommu_group_kset; static DEFINE_IDA(iommu_group_ida); static DEFINE_IDA(iommu_global_pasid_ida); +static DEFINE_MUTEX(iommu_probe_device_lock); static unsigned int iommu_def_domain_type __read_mostly; static bool iommu_dma_strict __read_mostly = IS_ENABLED(CONFIG_IOMMU_DEFAULT_DMA_STRICT); @@ -371,10 +372,6 @@ static void dev_iommu_free(struct device *dev) struct dev_iommu *param = dev->iommu; dev->iommu = NULL; - if (param->fwspec) { - fwnode_handle_put(param->fwspec->iommu_fwnode); - kfree(param->fwspec); - } kfree(param); } @@ -560,8 +557,6 @@ static int iommu_fw_check_deferred(struct iommu_probe_info *pinf) return -ENODEV; } -DEFINE_MUTEX(iommu_probe_device_lock); - static int iommu_find_init_device(struct iommu_probe_info *pinf) { const struct iommu_ops *ops = NULL; @@ -588,27 +583,10 @@ static int iommu_find_init_device(struct iommu_probe_info *pinf) static int __iommu_probe_device(struct iommu_probe_info *pinf) { struct device *dev = pinf->dev; - const struct iommu_ops *ops; - struct iommu_fwspec *fwspec; struct iommu_group *group; struct group_device *gdev; int ret; - /* - * For FDT-based systems and ACPI IORT/VIOT, drivers register IOMMU - * instances with non-NULL fwnodes, and client devices should have been - * identified with a fwspec by this point. Otherwise, we can currently - * assume that only one of Intel, AMD, s390, PAMU or legacy SMMUv2 can - * be present, and that any of their registered instances has suitable - * ops for probing, and thus cheekily co-opt the same mechanism. - */ - fwspec = dev_iommu_fwspec_get(dev); - if (fwspec && fwspec->ops) { - ops = fwspec->ops; - if (!ops) - return -ENODEV; - } - /* * Serialise to avoid races between IOMMU drivers registering in * parallel and/or the "replay" calls from ACPI/OF code via client @@ -622,13 +600,7 @@ static int __iommu_probe_device(struct iommu_probe_info *pinf) if (dev->iommu_group) return 0; - if (ops) { - ret = iommu_init_device(pinf, ops); - if (ret == -ENODEV) - return iommu_fw_check_deferred(pinf); - } else { - ret = iommu_find_init_device(pinf); - } + ret = iommu_find_init_device(pinf); if (ret) return ret; @@ -3085,7 +3057,8 @@ bool iommu_default_passthrough(void) } EXPORT_SYMBOL_GPL(iommu_default_passthrough); -struct iommu_device *iommu_device_from_fwnode(struct fwnode_handle *fwnode) +static struct iommu_device * +iommu_device_from_fwnode(struct fwnode_handle *fwnode) { struct iommu_device *iommu; @@ -3173,68 +3146,6 @@ int iommu_fw_get_u32_ids(struct iommu_probe_info *pinf, u32 *ids) } EXPORT_SYMBOL_GPL(iommu_fw_get_u32_ids); -int iommu_fwspec_init(struct device *dev, struct fwnode_handle *iommu_fwnode, - const struct iommu_ops *ops) -{ - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); - - if (fwspec) - return ops == fwspec->ops ? 0 : -EINVAL; - - if (!dev_iommu_get(dev)) - return -ENOMEM; - - /* Preallocate for the overwhelmingly common case of 1 ID */ - fwspec = kzalloc(struct_size(fwspec, ids, 1), GFP_KERNEL); - if (!fwspec) - return -ENOMEM; - - of_node_get(to_of_node(iommu_fwnode)); - fwspec->iommu_fwnode = iommu_fwnode; - fwspec->ops = ops; - dev_iommu_fwspec_set(dev, fwspec); - return 0; -} -EXPORT_SYMBOL_GPL(iommu_fwspec_init); - -void iommu_fwspec_free(struct device *dev) -{ - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); - - if (fwspec) { - fwnode_handle_put(fwspec->iommu_fwnode); - kfree(fwspec); - dev_iommu_fwspec_set(dev, NULL); - } -} -EXPORT_SYMBOL_GPL(iommu_fwspec_free); - -int iommu_fwspec_add_ids(struct device *dev, u32 *ids, int num_ids) -{ - struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); - int i, new_num; - - if (!fwspec) - return -EINVAL; - - new_num = fwspec->num_ids + num_ids; - if (new_num > 1) { - fwspec = krealloc(fwspec, struct_size(fwspec, ids, new_num), - GFP_KERNEL); - if (!fwspec) - return -ENOMEM; - - dev_iommu_fwspec_set(dev, fwspec); - } - - for (i = 0; i < num_ids; i++) - fwspec->ids[fwspec->num_ids + i] = ids[i]; - - fwspec->num_ids = new_num; - return 0; -} -EXPORT_SYMBOL_GPL(iommu_fwspec_add_ids); - /* * Per device IOMMU features. */ diff --git a/drivers/iommu/ipmmu-vmsa.c b/drivers/iommu/ipmmu-vmsa.c index ba984017065f98..96a6a13538ed77 100644 --- a/drivers/iommu/ipmmu-vmsa.c +++ b/drivers/iommu/ipmmu-vmsa.c @@ -872,7 +872,6 @@ static const struct iommu_ops ipmmu_ops = { .device_group = IS_ENABLED(CONFIG_ARM) && !IS_ENABLED(CONFIG_IOMMU_DMA) ? generic_device_group : generic_single_device_group, .pgsize_bitmap = SZ_1G | SZ_2M | SZ_4K, - .of_xlate = iommu_dummy_of_xlate, .default_domain_ops = &(const struct iommu_domain_ops) { .attach_dev = ipmmu_attach_device, .map_pages = ipmmu_map, diff --git a/drivers/iommu/msm_iommu.c b/drivers/iommu/msm_iommu.c index 6f21eec857c7d7..acb4858032f22e 100644 --- a/drivers/iommu/msm_iommu.c +++ b/drivers/iommu/msm_iommu.c @@ -674,7 +674,6 @@ static struct iommu_ops msm_iommu_ops = { .probe_device_pinf = msm_iommu_probe_device, .device_group = generic_device_group, .pgsize_bitmap = MSM_IOMMU_PGSIZES, - .of_xlate = iommu_dummy_of_xlate, .default_domain_ops = &(const struct iommu_domain_ops) { .attach_dev = msm_iommu_attach_dev, .map_pages = msm_iommu_map, diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 477171e83eaa6e..53099af3908ea3 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -1023,7 +1023,6 @@ static const struct iommu_ops mtk_iommu_ops = { .probe_device_pinf = mtk_iommu_probe_device, .release_device = mtk_iommu_release_device, .device_group = mtk_iommu_device_group, - .of_xlate = iommu_dummy_of_xlate, .get_resv_regions = mtk_iommu_get_resv_regions, .pgsize_bitmap = SZ_4K | SZ_64K | SZ_1M | SZ_16M, .owner = THIS_MODULE, diff --git a/drivers/iommu/of_iommu.c b/drivers/iommu/of_iommu.c index 463d17ab5057d6..1daf16323fdbc3 100644 --- a/drivers/iommu/of_iommu.c +++ b/drivers/iommu/of_iommu.c @@ -19,33 +19,6 @@ #include #include -static int of_iommu_xlate(struct of_phandle_args *iommu_spec, void *info) -{ - struct device *dev = info; - struct iommu_device *iommu; - struct fwnode_handle *fwnode = &iommu_spec->np->fwnode; - int ret; - - iommu = iommu_device_from_fwnode(fwnode); - if ((iommu && !iommu->ops->of_xlate) || - !of_device_is_available(iommu_spec->np)) - return -ENODEV; - - ret = iommu_fwspec_init(dev, &iommu_spec->np->fwnode, iommu->ops); - if (ret) - return ret; - /* - * The otherwise-empty fwspec handily serves to indicate the specific - * IOMMU device we're waiting for, which will be useful if we ever get - * a proper probe-ordering dependency mechanism in future. - */ - if (!iommu) - return driver_deferred_probe_check_state(dev); - - ret = iommu->ops->of_xlate(dev, iommu_spec); - return ret; -} - typedef int (*of_for_each_fn)(struct of_phandle_args *args, void *info); static int __for_each_map_id(struct device_node *master_np, u32 id, @@ -143,34 +116,14 @@ int of_iommu_configure(struct device *dev, struct device_node *master_np, .of_map_id = id, .is_dma_configure = true, }; - struct iommu_fwspec *fwspec; int err; if (!master_np) return -ENODEV; - /* Serialise to make dev->iommu stable under our potential fwspec */ - mutex_lock(&iommu_probe_device_lock); - fwspec = dev_iommu_fwspec_get(dev); - if (fwspec) { - if (fwspec->ops) { - mutex_unlock(&iommu_probe_device_lock); - return 0; - } - /* In the deferred case, start again from scratch */ - iommu_fwspec_free(dev); - } - if (dev_is_pci(dev)) pci_request_acs(); - err = of_iommu_for_each_id(dev, master_np, id, of_iommu_xlate, dev); - mutex_unlock(&iommu_probe_device_lock); - if (err == -ENODEV || err == -EPROBE_DEFER) - return err; - if (err) - goto err_log; - err = iommu_probe_device_pinf(&pinf); if (err) goto err_log; diff --git a/drivers/iommu/rockchip-iommu.c b/drivers/iommu/rockchip-iommu.c index 4cff06a2a24f74..72ee43d3230f5c 100644 --- a/drivers/iommu/rockchip-iommu.c +++ b/drivers/iommu/rockchip-iommu.c @@ -1141,7 +1141,6 @@ static const struct iommu_ops rk_iommu_ops = { .release_device = rk_iommu_release_device, .device_group = generic_single_device_group, .pgsize_bitmap = RK_IOMMU_PGSIZE_BITMAP, - .of_xlate = iommu_dummy_of_xlate, .default_domain_ops = &(const struct iommu_domain_ops) { .attach_dev = rk_iommu_attach_device, .map_pages = rk_iommu_map, diff --git a/drivers/iommu/sprd-iommu.c b/drivers/iommu/sprd-iommu.c index f1b87f8661e199..6e7634872bfcb7 100644 --- a/drivers/iommu/sprd-iommu.c +++ b/drivers/iommu/sprd-iommu.c @@ -404,7 +404,6 @@ static const struct iommu_ops sprd_iommu_ops = { .domain_alloc_paging = sprd_iommu_domain_alloc_paging, .probe_device_pinf = sprd_iommu_probe_device, .device_group = generic_single_device_group, - .of_xlate = iommu_dummy_of_xlate, .pgsize_bitmap = SPRD_IOMMU_PAGE_SIZE, .owner = THIS_MODULE, .default_domain_ops = &(const struct iommu_domain_ops) { diff --git a/drivers/iommu/sun50i-iommu.c b/drivers/iommu/sun50i-iommu.c index 84038705cf657d..e91aacdb7104b6 100644 --- a/drivers/iommu/sun50i-iommu.c +++ b/drivers/iommu/sun50i-iommu.c @@ -845,7 +845,6 @@ static const struct iommu_ops sun50i_iommu_ops = { .pgsize_bitmap = SZ_4K, .device_group = generic_single_device_group, .domain_alloc_paging = sun50i_iommu_domain_alloc_paging, - .of_xlate = iommu_dummy_of_xlate, .probe_device_pinf = sun50i_iommu_probe_device, .release_device = sun50i_iommu_release_device, .default_domain_ops = &(const struct iommu_domain_ops) { diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c index 1daa92f524452b..1c14f8b5ed847d 100644 --- a/drivers/iommu/tegra-smmu.c +++ b/drivers/iommu/tegra-smmu.c @@ -945,7 +945,6 @@ static const struct iommu_ops tegra_smmu_ops = { .probe_device_pinf = tegra_smmu_probe_device, .release_device = tegra_smmu_release_device, .device_group = tegra_smmu_device_group, - .of_xlate = iommu_dummy_of_xlate, .tegra_dev_iommu_get_stream_id = tegra_smmu_get_stream_id, .pgsize_bitmap = SZ_4K, .default_domain_ops = &(const struct iommu_domain_ops) { diff --git a/drivers/iommu/virtio-iommu.c b/drivers/iommu/virtio-iommu.c index 767919bf848999..f6b8e796a792e7 100644 --- a/drivers/iommu/virtio-iommu.c +++ b/drivers/iommu/virtio-iommu.c @@ -1054,7 +1054,6 @@ static struct iommu_ops viommu_ops = { .release_device = viommu_release_device, .device_group = viommu_device_group, .get_resv_regions = viommu_get_resv_regions, - .of_xlate = iommu_dummy_of_xlate, .owner = THIS_MODULE, .default_domain_ops = &(const struct iommu_domain_ops) { .attach_dev = viommu_attach_dev, diff --git a/include/acpi/acpi_bus.h b/include/acpi/acpi_bus.h index 89079787905d40..79dea7bea7a6f0 100644 --- a/include/acpi/acpi_bus.h +++ b/include/acpi/acpi_bus.h @@ -631,9 +631,6 @@ struct iommu_ops; bool acpi_dma_supported(const struct acpi_device *adev); enum dev_dma_attr acpi_get_dma_attr(struct acpi_device *adev); -int acpi_iommu_fwspec_init(struct device *dev, u32 id, - struct fwnode_handle *fwnode, - const struct iommu_ops *ops); int acpi_dma_get_range(struct device *dev, const struct bus_dma_region **map); int acpi_dma_configure_id(struct device *dev, enum dev_dma_attr attr, const u32 *input_id); diff --git a/include/linux/acpi_iort.h b/include/linux/acpi_iort.h index bacba2a76c3acb..9e64a18676a4c7 100644 --- a/include/linux/acpi_iort.h +++ b/include/linux/acpi_iort.h @@ -53,7 +53,6 @@ void iort_put_rmr_sids(struct fwnode_handle *iommu_fwnode, struct list_head *head); /* IOMMU interface */ int iort_dma_get_ranges(struct device *dev, u64 *size); -int iort_iommu_configure_id(struct device *dev, const u32 *id_in); void iort_iommu_get_resv_regions(struct device *dev, struct list_head *head, struct fwnode_handle *iommu_fwnode, const u32 *fw_ids, unsigned int fw_num_ids); @@ -72,8 +71,6 @@ void iort_put_rmr_sids(struct fwnode_handle *iommu_fwnode, struct list_head *hea /* IOMMU interface */ static inline int iort_dma_get_ranges(struct device *dev, u64 *size) { return -ENODEV; } -static inline int iort_iommu_configure_id(struct device *dev, const u32 *id_in) -{ return -ENODEV; } static inline void iort_iommu_get_resv_regions(struct device *dev, struct list_head *head, struct fwnode_handle *iommu_fwnode, diff --git a/include/linux/acpi_viot.h b/include/linux/acpi_viot.h index fce4eefcae4aad..0bc01d456bcb6b 100644 --- a/include/linux/acpi_viot.h +++ b/include/linux/acpi_viot.h @@ -19,14 +19,9 @@ int viot_iommu_for_each_id(struct device *dev, viot_for_each_fn fn, void *info); #ifdef CONFIG_ACPI_VIOT void __init acpi_viot_early_init(void); void __init acpi_viot_init(void); -int viot_iommu_configure(struct device *dev); #else static inline void acpi_viot_early_init(void) {} static inline void acpi_viot_init(void) {} -static inline int viot_iommu_configure(struct device *dev) -{ - return -ENODEV; -} #endif #endif /* __ACPI_VIOT_H__ */ diff --git a/include/linux/iommu-driver.h b/include/linux/iommu-driver.h index aa4cbf0cb91907..7ddd0b94e13c0d 100644 --- a/include/linux/iommu-driver.h +++ b/include/linux/iommu-driver.h @@ -62,7 +62,6 @@ static inline void iommu_fw_clear_cache(struct iommu_probe_info *pinf) } int iommu_probe_device_pinf(struct iommu_probe_info *pinf); -struct iommu_device *iommu_device_from_fwnode(struct fwnode_handle *fwnode); struct iommu_device * iommu_device_from_fwnode_pinf(struct iommu_probe_info *pinf, const struct iommu_ops *ops, @@ -201,15 +200,6 @@ __iommu_fw_alloc_per_device_ids(struct iommu_probe_info *pinf, void *mem, pinf, drv, num_ids, &drv->num_ids, drv->ids); \ }) -/* - * Used temporarily to indicate drivers that have moved to the new probe method. - */ -static inline int iommu_dummy_of_xlate(struct device *dev, - struct of_phandle_args *args) -{ - return 0; -} - #define __iommu_first(a, b) \ ({ \ struct iommu_device *a_dev = a; \ diff --git a/include/linux/iommu.h b/include/linux/iommu.h index 0ba12e0e450705..456b9b16599ce0 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -354,7 +354,6 @@ static inline int __iommu_copy_struct_from_user( * group and attached to the groups domain * @device_group: find iommu group for a particular device * @get_resv_regions: Request list of reserved regions for a device - * @of_xlate: add OF master IDs to iommu grouping * @is_attach_deferred: Check if domain attach should be deferred from iommu * driver init to device driver init (default no) * @dev_enable/disable_feat: per device entries to enable/disable @@ -398,7 +397,6 @@ struct iommu_ops { /* Request/Free a list of reserved regions for a device */ void (*get_resv_regions)(struct device *dev, struct list_head *list); - int (*of_xlate)(struct device *dev, struct of_phandle_args *args); bool (*is_attach_deferred)(struct device *dev); /* Per device IOMMU features */ @@ -534,7 +532,6 @@ struct iommu_fault_param { * * @fault_param: IOMMU detected device fault reporting data * @iopf_param: I/O Page Fault queue and data - * @fwspec: IOMMU fwspec data * @iommu_dev: IOMMU device this device is linked to * @priv: IOMMU Driver private data * @max_pasids: number of PASIDs this device can consume @@ -550,7 +547,6 @@ struct dev_iommu { struct mutex lock; struct iommu_fault_param *fault_param; struct iopf_device_param *iopf_param; - struct iommu_fwspec *fwspec; struct iommu_device *iommu_dev; void *priv; u32 max_pasids; @@ -787,29 +783,6 @@ extern struct iommu_group *generic_device_group(struct device *dev); struct iommu_group *fsl_mc_device_group(struct device *dev); extern struct iommu_group *generic_single_device_group(struct device *dev); -/** - * struct iommu_fwspec - per-device IOMMU instance data - * @ops: ops for this device's IOMMU - * @iommu_fwnode: firmware handle for this device's IOMMU - * @flags: IOMMU_FWSPEC_* flags - * @num_ids: number of associated device IDs - * @ids: IDs which this device may present to the IOMMU - * - * Note that the IDs (and any other information, really) stored in this structure should be - * considered private to the IOMMU device driver and are not to be used directly by IOMMU - * consumers. - */ -struct iommu_fwspec { - const struct iommu_ops *ops; - struct fwnode_handle *iommu_fwnode; - u32 flags; - unsigned int num_ids; - u32 ids[]; -}; - -/* ATS is supported */ -#define IOMMU_FWSPEC_PCI_RC_ATS (1 << 0) - /** * struct iommu_sva - handle to a device-mm bond */ @@ -818,25 +791,6 @@ struct iommu_sva { struct iommu_domain *domain; }; -int iommu_fwspec_init(struct device *dev, struct fwnode_handle *iommu_fwnode, - const struct iommu_ops *ops); -void iommu_fwspec_free(struct device *dev); -int iommu_fwspec_add_ids(struct device *dev, u32 *ids, int num_ids); - -static inline struct iommu_fwspec *dev_iommu_fwspec_get(struct device *dev) -{ - if (dev->iommu) - return dev->iommu->fwspec; - else - return NULL; -} - -static inline void dev_iommu_fwspec_set(struct device *dev, - struct iommu_fwspec *fwspec) -{ - dev->iommu->fwspec = fwspec; -} - static inline void *dev_iommu_priv_get(struct device *dev) { if (dev->iommu) @@ -847,7 +801,6 @@ static inline void *dev_iommu_priv_get(struct device *dev) void dev_iommu_priv_set(struct device *dev, void *priv); -extern struct mutex iommu_probe_device_lock; int iommu_probe_device(struct device *dev); int iommu_dev_enable_feature(struct device *dev, enum iommu_dev_features f); @@ -878,7 +831,6 @@ void iommu_free_global_pasid(ioasid_t pasid); struct iommu_ops {}; struct iommu_group {}; -struct iommu_fwspec {}; struct iommu_device {}; struct iommu_fault_param {}; struct iommu_iotlb_gather {}; @@ -1153,23 +1105,6 @@ static inline void iommu_device_unlink(struct device *dev, struct device *link) { } -static inline int iommu_fwspec_init(struct device *dev, - struct fwnode_handle *iommu_fwnode, - const struct iommu_ops *ops) -{ - return -ENODEV; -} - -static inline void iommu_fwspec_free(struct device *dev) -{ -} - -static inline int iommu_fwspec_add_ids(struct device *dev, u32 *ids, - int num_ids) -{ - return -ENODEV; -} - static inline int iommu_dev_enable_feature(struct device *dev, enum iommu_dev_features feat) { @@ -1182,11 +1117,6 @@ iommu_dev_disable_feature(struct device *dev, enum iommu_dev_features feat) return -ENODEV; } -static inline struct iommu_fwspec *dev_iommu_fwspec_get(struct device *dev) -{ - return NULL; -} - static inline int iommu_device_use_default_domain(struct device *dev) { return 0;