From patchwork Thu Nov 30 11:13:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 13474239 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="MzRXhGDF" Received: from relay4-d.mail.gandi.net (relay4-d.mail.gandi.net [217.70.183.196]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BDEEA1B3 for ; Thu, 30 Nov 2023 03:13:18 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPSA id ECE76E0002; Thu, 30 Nov 2023 11:13:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1701342797; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=gr9l/ohpsYqUsnTKIffKhuISxG6OBCvmKdftALlQWbg=; b=MzRXhGDFx1aKcGw2pj79yJFvsqy0O27rnfTvneb2m0Kgk4OcftiykHGFrrnvcGIx+B6HMC jPMNu1aFu4p5SeD/jz8PTqcBiOwpLsLraEHR6PpUyUIBKCeRuFSZLx3ZzHqByoMuAXgMyc D6Ju4QWDhBxrsThsK1vaAjcnk4BKMZc1hco92ZPpASlYjIVa7xxU7W5TLn4tuwI8iZj26u A8SZVLLx+pRvQMFyHrJxFJ2B3WjYUdBMtFZUY0/NBZtsevD7khGEJEBCJ3qg6RdtYFDF2c 8LBd/PuO9j1MeeDTlTHJhPY/BeJD2a6v4j4srKIenEQzr4FfGnFr7qnUyj8u3g== From: Miquel Raynal To: Lizhi Hou , Brian Xu , Raj Kumar Rampelli , Vinod Koul Cc: Thomas Petazzoni , Michal Simek , dmaengine@vger.kernel.org, Miquel Raynal Subject: [PATCH v2 1/4] dmaengine: xilinx: xdma: Fix the count of elapsed periods in cyclic mode Date: Thu, 30 Nov 2023 12:13:12 +0100 Message-Id: <20231130111315.729430-2-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231130111315.729430-1-miquel.raynal@bootlin.com> References: <20231130111315.729430-1-miquel.raynal@bootlin.com> Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: miquel.raynal@bootlin.com Xilinx DMA engine is capable of keeping track of the number of elapsed periods and this is an increasing 32-bit counter which is only reset when turning off the engine. No need to add this value to our local counter. Fixes: cd8c732ce1a5 ("dmaengine: xilinx: xdma: Support cyclic transfers") Signed-off-by: Miquel Raynal --- Hello, so far all my testing was performed by looping the playback output to the recording input and comparing the files using FFTs. Unfortunately, when the DMA engine suffers from the same issue on both sides, some issues may appear un-noticed, which is likely what happened here as the tooling did not report any issue while analyzing the output until I actually listened to real audio now that I have in my hands the relevant hardware/connectors to do so. --- drivers/dma/xilinx/xdma.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/dma/xilinx/xdma.c b/drivers/dma/xilinx/xdma.c index 84a88029226f..2c9c72d4b5a2 100644 --- a/drivers/dma/xilinx/xdma.c +++ b/drivers/dma/xilinx/xdma.c @@ -754,9 +754,9 @@ static irqreturn_t xdma_channel_isr(int irq, void *dev_id) if (ret) goto out; - desc->completed_desc_num += complete_desc_num; - if (desc->cyclic) { + desc->completed_desc_num = complete_desc_num; + ret = regmap_read(xdev->rmap, xchan->base + XDMA_CHAN_STATUS, &st); if (ret) @@ -768,6 +768,8 @@ static irqreturn_t xdma_channel_isr(int irq, void *dev_id) goto out; } + desc->completed_desc_num += complete_desc_num; + /* * if all data blocks are transferred, remove and complete the request */ From patchwork Thu Nov 30 11:13:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 13474241 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="Q8UHR8wp" Received: from relay4-d.mail.gandi.net (relay4-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::224]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A8067D54 for ; Thu, 30 Nov 2023 03:13:19 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPSA id B5DD6E000B; Thu, 30 Nov 2023 11:13:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1701342798; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=XClNDtyud7j7WgjvCaT6bz7tPpueCUv3M+YJKIhqVZU=; b=Q8UHR8wpehZGD+c07ORJulu8+guUSHLgAAZ1FiFV7KzzZN2rGHDL5OeMIf7UqG9ix+/LOs gdp0amtwKHCBI8S15LN6jxXGqTq7zCRyTXhGdYCEU/sxqUalAPNt4mt9hhhX+lPWngYcVr lZ/e0F3refEP5/qe5fb62M7lE9VyWvH6msZ/kh/UMeADV8lN4X2EpleAtAd3QdSHRd1kBL qRtzUaMs17Pbt/VFOoeI4owLFpe3eBKREShiKXHJsRx+Pg3GWYtdd3niHsdDOUQTJYBDyL Aa5Wd6K5Qa49KYRofIE79ggkUGrH8XVcT40Nm4r8O2SudrzbYJ3gtjfzpGhNWg== From: Miquel Raynal To: Lizhi Hou , Brian Xu , Raj Kumar Rampelli , Vinod Koul Cc: Thomas Petazzoni , Michal Simek , dmaengine@vger.kernel.org, Miquel Raynal Subject: [PATCH v2 2/4] dmaengine: xilinx: xdma: Clarify the logic between cyclic/sg modes Date: Thu, 30 Nov 2023 12:13:13 +0100 Message-Id: <20231130111315.729430-3-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231130111315.729430-1-miquel.raynal@bootlin.com> References: <20231130111315.729430-1-miquel.raynal@bootlin.com> Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: miquel.raynal@bootlin.com We support both modes, but they perform totally different taks in the interrupt handler. Clarify what shall be done in each case. Signed-off-by: Miquel Raynal --- drivers/dma/xilinx/xdma.c | 31 ++++++++++++++----------------- 1 file changed, 14 insertions(+), 17 deletions(-) diff --git a/drivers/dma/xilinx/xdma.c b/drivers/dma/xilinx/xdma.c index 2c9c72d4b5a2..4efef1b5f89c 100644 --- a/drivers/dma/xilinx/xdma.c +++ b/drivers/dma/xilinx/xdma.c @@ -765,26 +765,23 @@ static irqreturn_t xdma_channel_isr(int irq, void *dev_id) regmap_write(xdev->rmap, xchan->base + XDMA_CHAN_STATUS, st); vchan_cyclic_callback(vd); - goto out; - } - - desc->completed_desc_num += complete_desc_num; + } else { + desc->completed_desc_num += complete_desc_num; - /* - * if all data blocks are transferred, remove and complete the request - */ - if (desc->completed_desc_num == desc->desc_num) { - list_del(&vd->node); - vchan_cookie_complete(vd); - goto out; - } + /* if all data blocks are transferred, remove and complete the request */ + if (desc->completed_desc_num == desc->desc_num) { + list_del(&vd->node); + vchan_cookie_complete(vd); + goto out; + } - if (desc->completed_desc_num > desc->desc_num || - complete_desc_num != XDMA_DESC_BLOCK_NUM * XDMA_DESC_ADJACENT) - goto out; + if (desc->completed_desc_num > desc->desc_num || + complete_desc_num != XDMA_DESC_BLOCK_NUM * XDMA_DESC_ADJACENT) + goto out; - /* transfer the rest of data (SG only) */ - xdma_xfer_start(xchan); + /* transfer the rest of data */ + xdma_xfer_start(xchan); + } out: spin_unlock(&xchan->vchan.lock); From patchwork Thu Nov 30 11:13:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 13474242 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="EOaQ/YOT" Received: from relay4-d.mail.gandi.net (relay4-d.mail.gandi.net [217.70.183.196]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 593CED66 for ; Thu, 30 Nov 2023 03:13:20 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPSA id 7EE65E000E; Thu, 30 Nov 2023 11:13:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1701342799; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=o8VXs0i35kKTRXex7h+fTtLNSteHQdcsxDHFDj7VLIA=; b=EOaQ/YOT7w6JPe1KPaOJDduIloEBJTVTL8nbud2X5EXTlxPHZ5rAMmJh1FRU3DfU/hfEAz AS4ux0xX2fMwcV3zTW6SOuqtP+hehQwHAzL29IBcyHJOC0CXyyFSlbfeiFXh9xolYXEOux OjUjin9aRED3OU4Fkj1nZxEdmvDY1leW+mrk9Mbyydixm+cgCaEihy/5yJ/2XjsUy7OgHZ TCArMKdbDl0xKtHwAB0z/WJUxHepDaAzcIMAoA/BhobpNiiTmTR8OUo/VHDZlKj6berm+K 7bTFUhIJk8OqGDOnLWS5X2xLqp96qCUm4Us6VRwzQpDwDBEaeNawl2X7Nixn0A== From: Miquel Raynal To: Lizhi Hou , Brian Xu , Raj Kumar Rampelli , Vinod Koul Cc: Thomas Petazzoni , Michal Simek , dmaengine@vger.kernel.org, Miquel Raynal Subject: [PATCH v2 3/4] dmaengine: xilinx: xdma: Better handling of the busy variable Date: Thu, 30 Nov 2023 12:13:14 +0100 Message-Id: <20231130111315.729430-4-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231130111315.729430-1-miquel.raynal@bootlin.com> References: <20231130111315.729430-1-miquel.raynal@bootlin.com> Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: miquel.raynal@bootlin.com The driver internal scatter-gather logic is: * set busy to true * start transfer * set busy to false * trigger next transfer if any * set busy to true Setting busy to false in cyclic transfers does not make any sense and is conceptually wrong. In order to ease the integration of additional callbacks let's move this change to the scatter-gather path. Signed-off-by: Miquel Raynal --- --- drivers/dma/xilinx/xdma.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/dma/xilinx/xdma.c b/drivers/dma/xilinx/xdma.c index 4efef1b5f89c..e931ff42209c 100644 --- a/drivers/dma/xilinx/xdma.c +++ b/drivers/dma/xilinx/xdma.c @@ -745,7 +745,6 @@ static irqreturn_t xdma_channel_isr(int irq, void *dev_id) if (!vd) goto out; - xchan->busy = false; desc = to_xdma_desc(vd); xdev = xchan->xdev_hdl; @@ -766,6 +765,7 @@ static irqreturn_t xdma_channel_isr(int irq, void *dev_id) vchan_cyclic_callback(vd); } else { + xchan->busy = false; desc->completed_desc_num += complete_desc_num; /* if all data blocks are transferred, remove and complete the request */ From patchwork Thu Nov 30 11:13:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 13474243 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="TSGUGq39" Received: from relay4-d.mail.gandi.net (relay4-d.mail.gandi.net [217.70.183.196]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2286ED7F for ; Thu, 30 Nov 2023 03:13:20 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPSA id 450DCE000C; Thu, 30 Nov 2023 11:13:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1701342799; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=t0ykNUJ2kFDm3k5yqNT/ynxXgE8XMTUj76b31z5S5mM=; b=TSGUGq39CatfWi5MY3kNjIq9/5S2nf0uMAT4QwvhkTggVZrUy9d3GTNtEFUE/wCAbCKKDD fJAD1Vkmsybk75OQ8QxzazEBSNUxI9Z19icWP2+1OSiNMzsWKfW6tHpDoKon8Xk1iGApcx a0GRzO33LgP/irW1OAs5mVFolVAxIksI7uw68ISNXZhSuHgWqAW0xRAcKP0gZ8cabiqvMf H+7ujWJQ3yrXdqOzXLPS/Z68Gr4n5Vu97rTUEtE9kN/TbXs5IUv2rUfxxizUbtfJpo4V2v lbxvpwHZN9/CieALiHBEfoznebfLrqJreY1GovqRMD55OulcA2Ra/QLRla0mVg== From: Miquel Raynal To: Lizhi Hou , Brian Xu , Raj Kumar Rampelli , Vinod Koul Cc: Thomas Petazzoni , Michal Simek , dmaengine@vger.kernel.org, Miquel Raynal Subject: [PATCH v2 4/4] dmaengine: xilinx: xdma: Add terminate_all/synchronize callbacks Date: Thu, 30 Nov 2023 12:13:15 +0100 Message-Id: <20231130111315.729430-5-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231130111315.729430-1-miquel.raynal@bootlin.com> References: <20231130111315.729430-1-miquel.raynal@bootlin.com> Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: miquel.raynal@bootlin.com The driver is capable of starting scatter-gather transfers and needs to wait until their end. It is also capable of starting cyclic transfers and will only be "reset" next time the channel will be reused. In practice most of the time we hear no audio glitch because the sound card stops the flow on its side so the DMA transfers are just discarded. There are however some cases (when playing a bit with a number of frames and with a discontinuous sound file) when the sound card seems to be slightly too slow at stopping the flow, leading to a glitch that can be heard. In all cases, we need to earn better control of the DMA engine and adding proper ->device_terminate_all() and ->device_synchronize() callbacks feels totally relevant. With these two callbacks, no glitch can be heard anymore. Fixes: cd8c732ce1a5 ("dmaengine: xilinx: xdma: Support cyclic transfers") Signed-off-by: Miquel Raynal Tested-by: Lizhi Hou --- This was only tested with cyclic transfers. --- drivers/dma/xilinx/xdma.c | 68 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/drivers/dma/xilinx/xdma.c b/drivers/dma/xilinx/xdma.c index e931ff42209c..290bb5d2d1e2 100644 --- a/drivers/dma/xilinx/xdma.c +++ b/drivers/dma/xilinx/xdma.c @@ -371,6 +371,31 @@ static int xdma_xfer_start(struct xdma_chan *xchan) return ret; xchan->busy = true; + + return 0; +} + +/** + * xdma_xfer_stop - Stop DMA transfer + * @xchan: DMA channel pointer + */ +static int xdma_xfer_stop(struct xdma_chan *xchan) +{ + struct virt_dma_desc *vd = vchan_next_desc(&xchan->vchan); + struct xdma_device *xdev = xchan->xdev_hdl; + int ret; + + if (!vd || !xchan->busy) + return -EINVAL; + + /* clear run stop bit to prevent any further auto-triggering */ + ret = regmap_write(xdev->rmap, xchan->base + XDMA_CHAN_CONTROL_W1C, + CHAN_CTRL_RUN_STOP); + if (ret) + return ret; + + xchan->busy = false; + return 0; } @@ -475,6 +500,47 @@ static void xdma_issue_pending(struct dma_chan *chan) spin_unlock_irqrestore(&xdma_chan->vchan.lock, flags); } +/** + * xdma_terminate_all - Terminate all transactions + * @chan: DMA channel pointer + */ +static int xdma_terminate_all(struct dma_chan *chan) +{ + struct xdma_chan *xdma_chan = to_xdma_chan(chan); + struct xdma_desc *desc = NULL; + struct virt_dma_desc *vd; + unsigned long flags; + LIST_HEAD(head); + + spin_lock_irqsave(&xdma_chan->vchan.lock, flags); + xdma_xfer_stop(xdma_chan); + + vd = vchan_next_desc(&xdma_chan->vchan); + if (vd) + desc = to_xdma_desc(vd); + if (desc) { + dma_cookie_complete(&desc->vdesc.tx); + vchan_terminate_vdesc(&desc->vdesc); + } + + vchan_get_all_descriptors(&xdma_chan->vchan, &head); + spin_unlock_irqrestore(&xdma_chan->vchan.lock, flags); + vchan_dma_desc_free_list(&xdma_chan->vchan, &head); + + return 0; +} + +/** + * xdma_synchronize - Synchronize terminated transactions + * @chan: DMA channel pointer + */ +static void xdma_synchronize(struct dma_chan *chan) +{ + struct xdma_chan *xdma_chan = to_xdma_chan(chan); + + vchan_synchronize(&xdma_chan->vchan); +} + /** * xdma_prep_device_sg - prepare a descriptor for a DMA transaction * @chan: DMA channel pointer @@ -1088,6 +1154,8 @@ static int xdma_probe(struct platform_device *pdev) xdev->dma_dev.device_prep_slave_sg = xdma_prep_device_sg; xdev->dma_dev.device_config = xdma_device_config; xdev->dma_dev.device_issue_pending = xdma_issue_pending; + xdev->dma_dev.device_terminate_all = xdma_terminate_all; + xdev->dma_dev.device_synchronize = xdma_synchronize; xdev->dma_dev.filter.map = pdata->device_map; xdev->dma_dev.filter.mapcnt = pdata->device_map_cnt; xdev->dma_dev.filter.fn = xdma_filter_fn;