From patchwork Thu Nov 30 11:50:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shradha Todi X-Patchwork-Id: 13474397 X-Patchwork-Delegate: manivannanece23@gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="GC9o/zEq" Received: from mailout4.samsung.com (mailout4.samsung.com [203.254.224.34]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EC42110F4 for ; Thu, 30 Nov 2023 05:51:52 -0800 (PST) Received: from epcas5p2.samsung.com (unknown [182.195.41.40]) by mailout4.samsung.com (KnoxPortal) with ESMTP id 20231130135150epoutp04ff0b42cde7e45a38203ea79899c52566~cauml_dwq3057730577epoutp04O for ; Thu, 30 Nov 2023 13:51:50 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout4.samsung.com 20231130135150epoutp04ff0b42cde7e45a38203ea79899c52566~cauml_dwq3057730577epoutp04O DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; 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Thu, 30 Nov 2023 11:51:03 +0000 (GMT) Received: from epsmgms1p1new.samsung.com (unknown [182.195.42.41]) by epsmtrp2.samsung.com (KnoxPortal) with ESMTP id 20231130115103epsmtrp280fad264f85e09862a67fa59f2715f6b~cZFJJ17vo1512515125epsmtrp2s; Thu, 30 Nov 2023 11:51:03 +0000 (GMT) X-AuditID: b6c32a4a-261fd70000002719-40-656893742661 Received: from epsmtip1.samsung.com ( [182.195.34.30]) by epsmgms1p1new.samsung.com (Symantec Messaging Gateway) with SMTP id 79.A6.08755.72778656; Thu, 30 Nov 2023 20:51:03 +0900 (KST) Received: from cheetah.sa.corp.samsungelectronics.net (unknown [107.109.115.53]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20231130115101epsmtip1a2fd41eec6508250484bdcbf17ed971a~cZFHOOs4e1251512515epsmtip1U; Thu, 30 Nov 2023 11:51:01 +0000 (GMT) From: Shradha Todi To: manivannan.sadhasivam@linaro.org, lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, bhelgaas@google.com, jingoohan1@gmail.com, gustavo.pimentel@synopsys.com, josh@joshtriplett.org, lukas.bulwahn@gmail.com, hongxing.zhu@nxp.com, pankaj.dubey@samsung.com Cc: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Shradha Todi Subject: [PATCH v2 1/3] PCI: dwc: Add support for vendor specific capability search Date: Thu, 30 Nov 2023 17:20:42 +0530 Message-Id: <20231130115044.53512-2-shradha.t@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231130115044.53512-1-shradha.t@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprBJsWRmVeSWpSXmKPExsWy7bCmpm7J5IxUg6Ob+CyWNGVY7LrbwW4x a9tcRosVX2ayW/xfkG/R0POb1eLyrjlsFmfnHWezaPnTwmLRcrSdxeJuSyerxaKtX4DK9uxg t+g9XOvA57Fz1l12jwWbSj1uvbb12LSqk83jzrU9bB5Prkxn8tj4bgeTR9+WVYweW/Z/ZvT4 vEkugCsq2yYjNTEltUghNS85PyUzL91WyTs43jne1MzAUNfQ0sJcSSEvMTfVVsnFJ0DXLTMH 6HolhbLEnFKgUEBicbGSvp1NUX5pSapCRn5xia1SakFKToFJgV5xYm5xaV66Xl5qiZWhgYGR KVBhQnbGtSkTmAve8FVcX3GDrYHxFU8XIweHhICJxJ/X8V2MXBxCArsZJXY938IO4XxilPiz fyMThPMNyPn3kLWLkROs49rCHawQib2MEmc+fIJqaWWSeDBjFjNIFZuAlkTj1y5mkISIQBeT xKMVJ9lBEswCyRLz+u8wgdjCAqESbQuugNksAqoSi7ofgNm8AlYSK/f9hlonL7F6wwGwoZwC 1hLPVl1hBBkqITCVQ2Jl8102iCIXicfPW1kgbGGJV8e3sEPYUhKf3+2FqkmXWLl5BjOEnSPx bfMSJgjbXuLAlTksoNBgFtCUWL9LHyIsKzH11DomiJv5JHp/P4Eq55XYMQ/GVpb48ncP1FpJ iXnHLkPd7CHx5dIzaNj1MUocen+XeQKj3CyEFQsYGVcxSqYWFOempxabFhjlpZbDoy05P3cT IziJanntYHz44IPeIUYmDsZDjBIczEoivNefpqcK8aYkVlalFuXHF5XmpBYfYjQFBuBEZinR 5HxgGs8riTc0sTQwMTMzM7E0NjNUEud93To3RUggPbEkNTs1tSC1CKaPiYNTqoEpzslu02rV KYacJz+8m8o+u/bqvYy8NKu3C7clM2zZeXzntheNF332cy5/5H7xjRL3KdOy9XMOnqyMbKjs 37LKdo7cBRYV28mSep3OxlenFH+J/H81deJTQZfauxNZNdWUl+X/evGpT72ba1t1ubll2NEr 1+R1PkRKPQ0JuiDXlyMvyDNn36o3h5yXCBo1FXz/dinsYNNDrUkObGZfLYX2ly6ZX3mZ+9HU G497HLx2WIRlXFVZ993hHpuY2RPO7acFOJ5yXqr2XMy9b5/M3hvf58QJ35j0UvzD4pkfGNZN 1dLeeMNAxbl2OrfUwTy2O6teqLNYcdvcvOOe+EWbx1NsomZF5+Sz4ZlrkjXWm6TqKrEUZyQa ajEXFScCAPOmaHMrBAAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrHLMWRmVeSWpSXmKPExsWy7bCSnK56eUaqwdb1uhZLmjIsdt3tYLeY tW0uo8WKLzPZLf4vyLdo6PnNanF51xw2i7PzjrNZtPxpYbFoOdrOYnG3pZPVYtHWL0Ble3aw W/QernXg89g56y67x4JNpR63Xtt6bFrVyeZx59oeNo8nV6YzeWx8t4PJo2/LKkaPLfs/M3p8 3iQXwBXFZZOSmpNZllqkb5fAlXFtygTmgjd8FddX3GBrYHzF08XIySEhYCJxbeEOVhBbSGA3 o0TjczaIuKTE54vrmCBsYYmV/56zdzFyAdU0M0kcPXeTBSTBJqAl0fi1ixkkISIwg0mipfs+ WIJZIFXi9uE5YJOEBYIldnddZASxWQRUJRZ1PwCbyitgJbFy329WiA3yEqs3HGAGsTkFrCWe rbrCCHGRlcSiXz+YJzDyLWBkWMUomVpQnJueW2xYYJiXWq5XnJhbXJqXrpecn7uJERzkWpo7 GLev+qB3iJGJg/EQowQHs5II7/Wn6alCvCmJlVWpRfnxRaU5qcWHGKU5WJTEecVf9KYICaQn lqRmp6YWpBbBZJk4OKUamExu5+59F6d83XNBwTe5zscvH19unht7P+eof5Y6Q/CyNNWN2gFR da9+8O6r+yx5+1WWO0f8A2XFo12VZkIn4jfWfA+c9ajdPYX3I1slv4//G+t4s0MHvp63MLDa 8tbJYqtf+rc/Wh+PZ3x7t+tNi+P0jvO7lzdNDlR9VMyu6cfoaXY1O6rlNrvFKZ255gcFHt2t dzkn+VjjZfyu/1OvP9odvel6DAPDs4Rlyn0JPyXEE6dmv5ge0R2rKKr4LeHUabOlB12m9R+O 9TxXt23O1dTS4AyfL9yFm83NhOTWcm1MV2AX2nq7Opdvq99V3/5Es92rJd+x7c9uuv1E3/5s eYRbbcSrmK61TqqV1y9nKrEUZyQaajEXFScCAEY3aIzhAgAA X-CMS-MailID: 20231130115103epcas5p19a56bf80e3c7cb062dba9e60d7363039 X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20231130115103epcas5p19a56bf80e3c7cb062dba9e60d7363039 References: <20231130115044.53512-1-shradha.t@samsung.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Add vendor specific extended configuration space capability search API using struct dw_pcie pointer for DW controllers. Signed-off-by: Shradha Todi --- drivers/pci/controller/dwc/pcie-designware.c | 16 ++++++++++++++++ drivers/pci/controller/dwc/pcie-designware.h | 1 + 2 files changed, 17 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 1c1c7348972b..064b4951afd8 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -275,6 +275,22 @@ static u16 dw_pcie_find_next_ext_capability(struct dw_pcie *pci, u16 start, return 0; } +u16 dw_pcie_find_vsec_capability(struct dw_pcie *pci, u8 vsec_cap) +{ + u16 vsec = 0; + u32 header; + + while ((vsec = dw_pcie_find_next_ext_capability(pci, vsec, + PCI_EXT_CAP_ID_VNDR))) { + header = dw_pcie_readl_dbi(pci, vsec + PCI_VNDR_HEADER); + if (PCI_VNDR_HEADER_ID(header) == vsec_cap) + return vsec; + } + + return 0; +} +EXPORT_SYMBOL_GPL(dw_pcie_find_vsec_capability); + u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap) { return dw_pcie_find_next_ext_capability(pci, 0, cap); diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index ef0b2efa9f93..b7ea1db14f6a 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -419,6 +419,7 @@ void dw_pcie_version_detect(struct dw_pcie *pci); u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap); u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap); +u16 dw_pcie_find_vsec_capability(struct dw_pcie *pci, u8 vsec_cap); int dw_pcie_read(void __iomem *addr, int size, u32 *val); int dw_pcie_write(void __iomem *addr, int size, u32 val); From patchwork Thu Nov 30 11:50:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shradha Todi X-Patchwork-Id: 13474398 X-Patchwork-Delegate: manivannanece23@gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="tNywrz5C" Received: from mailout4.samsung.com (mailout4.samsung.com [203.254.224.34]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6F0AEC4 for ; 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Thu, 30 Nov 2023 20:51:08 +0900 (KST) Received: from cheetah.sa.corp.samsungelectronics.net (unknown [107.109.115.53]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20231130115106epsmtip1e8bf73fc5b021d813fd5fc2c7c3a7050~cZFL1358T1476714767epsmtip1k; Thu, 30 Nov 2023 11:51:06 +0000 (GMT) From: Shradha Todi To: manivannan.sadhasivam@linaro.org, lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, bhelgaas@google.com, jingoohan1@gmail.com, gustavo.pimentel@synopsys.com, josh@joshtriplett.org, lukas.bulwahn@gmail.com, hongxing.zhu@nxp.com, pankaj.dubey@samsung.com Cc: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Shradha Todi Subject: [PATCH v2 2/3] PCI: debugfs: Add support for RASDES framework in DWC Date: Thu, 30 Nov 2023 17:20:43 +0530 Message-Id: <20231130115044.53512-3-shradha.t@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231130115044.53512-1-shradha.t@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprFJsWRmVeSWpSXmKPExsWy7bCmpm7n5IxUg0n/NCyWNGVY7LrbwW4x a9tcRosVX2ayW/xfkG/R0POb1eLyrjlsFmfnHWezaPnTwmLRcrSdxeJuSyerxaKtX4DK9uxg t+g9XOvA57Fz1l12jwWbSj1uvbb12LSqk83jzrU9bB5Prkxn8tj4bgeTR9+WVYweW/Z/ZvT4 vEkugCsq2yYjNTEltUghNS85PyUzL91WyTs43jne1MzAUNfQ0sJcSSEvMTfVVsnFJ0DXLTMH 6HolhbLEnFKgUEBicbGSvp1NUX5pSapCRn5xia1SakFKToFJgV5xYm5xaV66Xl5qiZWhgYGR KVBhQnbG+pXnWAtWdTNWnOzvY2tgXFncxcjJISFgInHlSAc7iC0ksIdR4tF9jy5GLiD7E6NE /4JuVgjnG6PEvm1XGWE6vk7dB5XYyyjxZkUjC4TTyiQx9XgPC0gVm4CWROPXLmaQhIhAF5PE oxUnwZYwCyRLzOu/wwRiCwv4S8xeuZ0ZxGYRUJVo/fGcDcTmFbCSWD1jKzPEOnmJ1RsOgNmc AtYSz1ZdYQQZKiEwlUNiY/MpqCIXibYTt6FsYYlXx7ewQ9hSEp/f7WWDsNMlVm6eAVWTI/Ft 8xImCNte4sCVOUBXcwAdpymxfpc+RFhWYuqpdUwQN/NJ9P5+AlXOK7FjHoytLPHl7x4WCFtS Yt6xy6wQtofE2btL2SCh0sco8eP3OrYJjHKzEFYsYGRcxSiVWlCcm56abFpgqJuXWg6PuOT8 3E2M4ESqFbCDcfWGv3qHGJk4GA8xSnAwK4nwXn+anirEm5JYWZValB9fVJqTWnyI0RQYghOZ pUST84GpPK8k3tDE0sDEzMzMxNLYzFBJnPd169wUIYH0xJLU7NTUgtQimD4mDk6pBqaNH8t7 hSVbbh52WFa2YNly7cbsttKK227Pw7adfZd8oKDj/rk586PVzX9scHbottBL+FC/J778sLlp iZGIyS6B3K9f/XZOcLQLkhUz1ue5rvVng6ybj77B1rJJKtK782Js60rPeMg7Zufk92xniHqZ IXPMzTnhSMuhM17c890+LQqeP0tUn/tsJv97r28zYkWYTFY9Dn3b7BxkueXAFk4/tt17OpKv v1Q7slXxpmGg2k+uz9OU9jWdVw5TLpFs/5GvFjA3cZ+5ePqTww8vnzw+g/nv9s/ac7oicozW C2g88dr6/vm2vA694/xHw//saWs+18m36sfzT4aOGnN0tJ43Rqj8tlzxckNZ7ON7LEosxRmJ hlrMRcWJAA+ii38tBAAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrALMWRmVeSWpSXmKPExsWy7bCSnK5OeUaqwaMTmhZLmjIsdt3tYLeY tW0uo8WKLzPZLf4vyLdo6PnNanF51xw2i7PzjrNZtPxpYbFoOdrOYnG3pZPVYtHWL0Ble3aw W/QernXg89g56y67x4JNpR63Xtt6bFrVyeZx59oeNo8nV6YzeWx8t4PJo2/LKkaPLfs/M3p8 3iQXwBXFZZOSmpNZllqkb5fAlbF+5TnWglXdjBUn+/vYGhhXFncxcnJICJhIfJ26j7WLkYtD SGA3o8SFZR/YIRKSEp8vrmOCsIUlVv57zg5R1MwkceTXLTaQBJuAlkTj1y5mkISIwAwmiZbu +ywgCWaBVInbh+eAFQkL+ErMOPkZzGYRUJVo/fEczOYVsJJYPWMrM8QGeYnVGw6A2ZwC1hLP Vl1hBLGFgGoW/frBPIGRbwEjwypGydSC4tz03GTDAsO81HK94sTc4tK8dL3k/NxNjOBA19LY wXhv/j+9Q4xMHIyHGCU4mJVEeK8/TU8V4k1JrKxKLcqPLyrNSS0+xCjNwaIkzms4Y3aKkEB6 YklqdmpqQWoRTJaJg1OqgSle+2Pv3NaQ7x8ChaJ+vfpqsOi79ap7H9OTJ3Uvurg8PD5x5b2j /S4PXk7tvRaXvqk5YP450ehFh9s7PUX3TI6eLLkuL2xehtxze2aNfXO0f82Le1651Cnuo9Fm jnP+YWl/PBXV31RPjmgI8ZI/tfqufetCpi8MNcZ3C63e7592Z33sprxZzmJCqtGXwvhtWJpy 7vYLesvHHYpZvOSvlMPh+9/DP1uvNPn6unXJQwXmRB4e82s8Czgf75GP+iKtsyLI/nlCb4Zg R6H946uvP15N/qXVO8PwZeVj/U9FSh7J2Ue+LAz9xlX7v4zlqeOsNFe/pzHGVQ/6uw1PXGEr SmCbaW6SdKeddfeMs9ZnuZVYijMSDbWYi4oTAVTatVbjAgAA X-CMS-MailID: 20231130115108epcas5p1b874d14bc1e306a0860c6671b149a35c X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20231130115108epcas5p1b874d14bc1e306a0860c6671b149a35c References: <20231130115044.53512-1-shradha.t@samsung.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Add support to use the RASDES feature of DesignWare PCIe controller using debugfs entries. RASDES is a vendor specific extended PCIe capability which reads the current hardware internal state of PCIe device. Following primary features are provided to userspace via debugfs: - Debug registers - Error injection - Statistical counters Signed-off-by: Shradha Todi --- drivers/pci/controller/dwc/Kconfig | 8 + drivers/pci/controller/dwc/Makefile | 1 + .../controller/dwc/pcie-designware-debugfs.c | 476 ++++++++++++++++++ .../controller/dwc/pcie-designware-debugfs.h | 0 drivers/pci/controller/dwc/pcie-designware.h | 17 + 5 files changed, 502 insertions(+) create mode 100644 drivers/pci/controller/dwc/pcie-designware-debugfs.c create mode 100644 drivers/pci/controller/dwc/pcie-designware-debugfs.h diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig index ab96da43e0c2..fc84ba03b20e 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -6,6 +6,14 @@ menu "DesignWare-based PCIe controllers" config PCIE_DW bool +config PCIE_DW_DEBUGFS + bool "DWC PCIe debugfs entries" + help + Enables debugfs entries for the DWC PCIe Controller. + These entries make use of the RAS features in the DW + controller to help in debug, error injection and statistical + counters + config PCIE_DW_HOST bool select PCIE_DW diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile index bf5c311875a1..cbd1618b0b20 100644 --- a/drivers/pci/controller/dwc/Makefile +++ b/drivers/pci/controller/dwc/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_PCIE_DW) += pcie-designware.o +obj-$(CONFIG_PCIE_DW_DEBUGFS) += pcie-designware-debugfs.o obj-$(CONFIG_PCIE_DW_HOST) += pcie-designware-host.o obj-$(CONFIG_PCIE_DW_EP) += pcie-designware-ep.o obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o diff --git a/drivers/pci/controller/dwc/pcie-designware-debugfs.c b/drivers/pci/controller/dwc/pcie-designware-debugfs.c new file mode 100644 index 000000000000..46481650ed6b --- /dev/null +++ b/drivers/pci/controller/dwc/pcie-designware-debugfs.c @@ -0,0 +1,476 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Synopsys DesignWare PCIe controller debugfs driver + * + * Copyright (C) 2023 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Author: Shradha Todi + */ + +#include + +#include "pcie-designware.h" + +#define RAS_DES_EVENT_COUNTER_CTRL_REG 0x8 +#define RAS_DES_EVENT_COUNTER_DATA_REG 0xc +#define SD_STATUS_L1LANE_REG 0xb0 +#define ERR_INJ_ENABLE_REG 0x30 +#define ERR_INJ0_OFF 0x34 + +#define LANE_DETECT_SHIFT 17 +#define LANE_DETECT_MASK 0x1 +#define PIPE_RXVALID_SHIFT 18 +#define PIPE_RXVALID_MASK 0x1 + +#define LANE_SELECT_SHIFT 8 +#define LANE_SELECT_MASK 0xf +#define EVENT_COUNTER_STATUS_SHIFT 7 +#define EVENT_COUNTER_STATUS_MASK 0x1 +#define EVENT_COUNTER_ENABLE (0x7 << 2) +#define PER_EVENT_OFF (0x1 << 2) +#define PER_EVENT_ON (0x3 << 2) + +#define EINJ_COUNT_MASK 0xff +#define EINJ_TYPE_MASK 0xf +#define EINJ_TYPE_SHIFT 8 +#define EINJ_INFO_MASK 0xfffff +#define EINJ_INFO_SHIFT 12 + +#define DWC_DEBUGFS_MAX 128 + +struct rasdes_info { + /* to store rasdes capability offset */ + u32 ras_cap; + struct mutex dbg_mutex; + struct dentry *rasdes; +}; + +struct rasdes_priv { + struct dw_pcie *pci; + int idx; +}; + +struct event_counter { + const char *name; + /* values can be between 0-15 */ + u32 group_no; + /* values can be between 0-32 */ + u32 event_no; +}; + +static const struct event_counter event_counters[] = { + {"ebuf_overflow", 0x0, 0x0}, + {"ebuf_underrun", 0x0, 0x1}, + {"decode_err", 0x0, 0x2}, + {"running_disparity_err", 0x0, 0x3}, + {"skp_os_parity_err", 0x0, 0x4}, + {"sync_header_err", 0x0, 0x5}, + {"detect_ei_infer", 0x1, 0x5}, + {"receiver_err", 0x1, 0x6}, + {"rx_recovery_req", 0x1, 0x7}, + {"framing_err", 0x1, 0x9}, + {"deskew_err", 0x1, 0xa}, + {"bad_tlp", 0x2, 0x0}, + {"lcrc_err", 0x2, 0x1}, + {"bad_dllp", 0x2, 0x2}, +}; + +struct err_inj { + const char *name; + /* values can be from group 0 - 6 */ + u32 err_inj_group; + /* within each group there can be types */ + u32 err_inj_type; + /* More details about the error */ + u32 err_inj_12_31; +}; + +static const struct err_inj err_inj_list[] = { + {"tx_lcrc", 0x0, 0x0, 0x0}, + {"tx_ecrc", 0x0, 0x3, 0x0}, + {"rx_lcrc", 0x0, 0x8, 0x0}, + {"rx_ecrc", 0x0, 0xb, 0x0}, +}; + +static ssize_t dbg_lane_detect_read(struct file *file, char __user *buf, + size_t count, loff_t *ppos) +{ + struct dw_pcie *pci = file->private_data; + struct rasdes_info *rinfo = pci->dump_info; + u32 val; + ssize_t off = 0; + char debugfs_buf[DWC_DEBUGFS_MAX]; + + val = dw_pcie_readl_dbi(pci, rinfo->ras_cap + SD_STATUS_L1LANE_REG); + val = (val >> LANE_DETECT_SHIFT) & LANE_DETECT_MASK; + if (val) + off += scnprintf(debugfs_buf, DWC_DEBUGFS_MAX - off, + "Detected\n"); + else + off += scnprintf(debugfs_buf, DWC_DEBUGFS_MAX - off, + "Undetected\n"); + + return simple_read_from_buffer(buf, count, ppos, debugfs_buf, off); +} + +static ssize_t dbg_lane_detect_write(struct file *file, const char __user *buf, + size_t count, loff_t *ppos) +{ + struct dw_pcie *pci = file->private_data; + struct rasdes_info *rinfo = pci->dump_info; + u32 val; + u32 lane; + + val = kstrtou32_from_user(buf, count, 0, &lane); + if (val) + return val; + + if (lane > 15) + return -EINVAL; + + val = dw_pcie_readl_dbi(pci, rinfo->ras_cap + SD_STATUS_L1LANE_REG); + val &= ~LANE_SELECT_MASK; + val |= lane; + dw_pcie_writel_dbi(pci, rinfo->ras_cap + SD_STATUS_L1LANE_REG, val); + + return count; +} + +static ssize_t dbg_rx_valid_read(struct file *file, char __user *buf, + size_t count, loff_t *ppos) +{ + struct dw_pcie *pci = file->private_data; + struct rasdes_info *rinfo = pci->dump_info; + u32 val; + ssize_t off = 0; + char debugfs_buf[DWC_DEBUGFS_MAX]; + + val = dw_pcie_readl_dbi(pci, rinfo->ras_cap + SD_STATUS_L1LANE_REG); + val = (val >> PIPE_RXVALID_SHIFT) & PIPE_RXVALID_MASK; + if (val) + off += scnprintf(debugfs_buf, DWC_DEBUGFS_MAX - off, + "Valid\n"); + else + off += scnprintf(debugfs_buf, DWC_DEBUGFS_MAX - off, + "Invalid\n"); + + return simple_read_from_buffer(buf, count, ppos, debugfs_buf, off); +} + +static ssize_t dbg_rx_valid_write(struct file *file, const char __user *buf, + size_t count, loff_t *ppos) +{ + return dbg_lane_detect_write(file, buf, count, ppos); +} + +static void set_event_number(struct rasdes_priv *pdata, struct dw_pcie *pci, + struct rasdes_info *rinfo) +{ + u32 val; + + val = dw_pcie_readl_dbi(pci, rinfo->ras_cap + + RAS_DES_EVENT_COUNTER_CTRL_REG); + val &= ~EVENT_COUNTER_ENABLE; + val &= ~(0xFFF << 16); + val |= (event_counters[pdata->idx].group_no << 24); + val |= (event_counters[pdata->idx].event_no << 16); + dw_pcie_writel_dbi(pci, rinfo->ras_cap + + RAS_DES_EVENT_COUNTER_CTRL_REG, val); +} + +static ssize_t cnt_en_read(struct file *file, char __user *buf, size_t count, + loff_t *ppos) +{ + struct rasdes_priv *pdata = file->private_data; + struct dw_pcie *pci = pdata->pci; + struct rasdes_info *rinfo = pci->dump_info; + u32 val; + ssize_t off = 0; + char debugfs_buf[DWC_DEBUGFS_MAX]; + + mutex_lock(&rinfo->dbg_mutex); + set_event_number(pdata, pci, rinfo); + val = dw_pcie_readl_dbi(pci, rinfo->ras_cap + + RAS_DES_EVENT_COUNTER_CTRL_REG); + mutex_unlock(&rinfo->dbg_mutex); + val = (val >> EVENT_COUNTER_STATUS_SHIFT) & EVENT_COUNTER_STATUS_MASK; + if (val) + off += scnprintf(debugfs_buf, DWC_DEBUGFS_MAX - off, + "Enabled\n"); + else + off += scnprintf(debugfs_buf, DWC_DEBUGFS_MAX - off, + "Disabled\n"); + + return simple_read_from_buffer(buf, count, ppos, debugfs_buf, off); +} + +static ssize_t cnt_en_write(struct file *file, const char __user *buf, + size_t count, loff_t *ppos) +{ + struct rasdes_priv *pdata = file->private_data; + struct dw_pcie *pci = pdata->pci; + struct rasdes_info *rinfo = pci->dump_info; + u32 val; + u32 enable; + + val = kstrtou32_from_user(buf, count, 0, &enable); + if (val) + return val; + + mutex_lock(&rinfo->dbg_mutex); + set_event_number(pdata, pci, rinfo); + val = dw_pcie_readl_dbi(pci, rinfo->ras_cap + + RAS_DES_EVENT_COUNTER_CTRL_REG); + if (enable) + val |= PER_EVENT_ON; + else + val |= PER_EVENT_OFF; + + dw_pcie_writel_dbi(pci, rinfo->ras_cap + + RAS_DES_EVENT_COUNTER_CTRL_REG, val); + mutex_unlock(&rinfo->dbg_mutex); + + return count; +} + +static ssize_t cnt_lane_read(struct file *file, char __user *buf, size_t count, + loff_t *ppos) +{ + struct rasdes_priv *pdata = file->private_data; + struct dw_pcie *pci = pdata->pci; + struct rasdes_info *rinfo = pci->dump_info; + u32 val; + ssize_t off = 0; + char debugfs_buf[DWC_DEBUGFS_MAX]; + + mutex_lock(&rinfo->dbg_mutex); + set_event_number(pdata, pci, rinfo); + val = dw_pcie_readl_dbi(pci, rinfo->ras_cap + + RAS_DES_EVENT_COUNTER_CTRL_REG); + mutex_unlock(&rinfo->dbg_mutex); + val = (val >> LANE_SELECT_SHIFT) & LANE_SELECT_MASK; + off += scnprintf(debugfs_buf, DWC_DEBUGFS_MAX - off, + "Lane: %d\n", val); + + return simple_read_from_buffer(buf, count, ppos, debugfs_buf, off); +} + +static ssize_t cnt_lane_write(struct file *file, const char __user *buf, + size_t count, loff_t *ppos) +{ + struct rasdes_priv *pdata = file->private_data; + struct dw_pcie *pci = pdata->pci; + struct rasdes_info *rinfo = pci->dump_info; + u32 val; + u32 lane; + + val = kstrtou32_from_user(buf, count, 0, &lane); + if (val) + return val; + + if (lane > 15) + return -EINVAL; + + mutex_lock(&rinfo->dbg_mutex); + set_event_number(pdata, pci, rinfo); + val = dw_pcie_readl_dbi(pci, rinfo->ras_cap + + RAS_DES_EVENT_COUNTER_CTRL_REG); + val &= ~(LANE_SELECT_MASK << LANE_SELECT_SHIFT); + val |= (lane << LANE_SELECT_SHIFT); + dw_pcie_writel_dbi(pci, rinfo->ras_cap + + RAS_DES_EVENT_COUNTER_CTRL_REG, val); + mutex_unlock(&rinfo->dbg_mutex); + + return count; +} + +static ssize_t cnt_val_read(struct file *file, char __user *buf, size_t count, + loff_t *ppos) +{ + struct rasdes_priv *pdata = file->private_data; + struct dw_pcie *pci = pdata->pci; + struct rasdes_info *rinfo = pci->dump_info; + u32 val; + ssize_t off = 0; + char debugfs_buf[DWC_DEBUGFS_MAX]; + + mutex_lock(&rinfo->dbg_mutex); + set_event_number(pdata, pci, rinfo); + val = dw_pcie_readl_dbi(pci, rinfo->ras_cap + + RAS_DES_EVENT_COUNTER_DATA_REG); + mutex_unlock(&rinfo->dbg_mutex); + off += scnprintf(debugfs_buf, DWC_DEBUGFS_MAX - off, + "Value: %d\n", val); + + return simple_read_from_buffer(buf, count, ppos, debugfs_buf, off); +} + +static ssize_t err_inj_read(struct file *file, char __user *buf, + size_t count, loff_t *ppos) +{ + struct rasdes_priv *pdata = file->private_data; + struct dw_pcie *pci = pdata->pci; + struct rasdes_info *rinfo = pci->dump_info; + u32 val; + ssize_t off = 0; + char debugfs_buf[DWC_DEBUGFS_MAX]; + + val = dw_pcie_readl_dbi(pci, rinfo->ras_cap + ERR_INJ0_OFF + + (0x4 * err_inj_list[pdata->idx].err_inj_group)); + val &= EINJ_COUNT_MASK; + off += scnprintf(debugfs_buf, DWC_DEBUGFS_MAX - off, + "Count: %d\n", val); + + return simple_read_from_buffer(buf, count, ppos, debugfs_buf, off); +} + +static ssize_t err_inj_write(struct file *file, const char __user *buf, + size_t count, loff_t *ppos) +{ + struct rasdes_priv *pdata = file->private_data; + struct dw_pcie *pci = pdata->pci; + struct rasdes_info *rinfo = pci->dump_info; + u32 val; + u32 counter; + + val = kstrtou32_from_user(buf, count, 0, &counter); + if (val) + return val; + + val = dw_pcie_readl_dbi(pci, rinfo->ras_cap + ERR_INJ0_OFF + + (0x4 * err_inj_list[pdata->idx].err_inj_group)); + val &= ~(EINJ_TYPE_MASK << EINJ_TYPE_SHIFT); + val |= err_inj_list[pdata->idx].err_inj_type << EINJ_TYPE_SHIFT; + val &= ~(EINJ_INFO_MASK << EINJ_INFO_SHIFT); + val |= err_inj_list[pdata->idx].err_inj_12_31 << EINJ_INFO_SHIFT; + val &= ~EINJ_COUNT_MASK; + val |= counter; + dw_pcie_writel_dbi(pci, rinfo->ras_cap + ERR_INJ0_OFF + + (0x4 * err_inj_list[pdata->idx].err_inj_group), val); + dw_pcie_writel_dbi(pci, rinfo->ras_cap + ERR_INJ_ENABLE_REG, + (0x1 << err_inj_list[pdata->idx].err_inj_group)); + + return count; +} + +#define dwc_debugfs_create(name) \ +debugfs_create_file(#name, 0644, rasdes_debug, pci, \ + &dbg_ ## name ## _fops) + +#define DWC_DEBUGFS_FOPS(name) \ +static const struct file_operations dbg_ ## name ## _fops = { \ + .read = dbg_ ## name ## _read, \ + .write = dbg_ ## name ## _write \ +} + +DWC_DEBUGFS_FOPS(lane_detect); +DWC_DEBUGFS_FOPS(rx_valid); + +static const struct file_operations cnt_en_ops = { + .open = simple_open, + .read = cnt_en_read, + .write = cnt_en_write, +}; + +static const struct file_operations cnt_lane_ops = { + .open = simple_open, + .read = cnt_lane_read, + .write = cnt_lane_write, +}; + +static const struct file_operations cnt_val_ops = { + .open = simple_open, + .read = cnt_val_read, +}; + +static const struct file_operations err_inj_ops = { + .open = simple_open, + .read = err_inj_read, + .write = err_inj_write, +}; + +void dwc_pcie_rasdes_debugfs_deinit(struct dw_pcie *pci) +{ + struct rasdes_info *rinfo = pci->dump_info; + + debugfs_remove_recursive(rinfo->rasdes); + mutex_destroy(&rinfo->dbg_mutex); +} + +int dwc_pcie_rasdes_debugfs_init(struct dw_pcie *pci) +{ + struct device *dev = pci->dev; + int ras_cap; + struct rasdes_info *dump_info; + char dirname[DWC_DEBUGFS_MAX]; + struct dentry *dir, *rasdes_debug, *rasdes_err_inj; + struct dentry *rasdes_event_counter, *rasdes_events; + int i; + struct rasdes_priv *priv_tmp; + + ras_cap = dw_pcie_find_vsec_capability(pci, DW_PCIE_RAS_DES_CAP); + if (!ras_cap) { + dev_err(dev, "No RASDES capability available\n"); + return -ENODEV; + } + + dump_info = devm_kzalloc(dev, sizeof(*dump_info), GFP_KERNEL); + if (!dump_info) + return -ENOMEM; + + /* Create main directory for each platform driver */ + sprintf(dirname, "pcie_dwc_%s", dev_name(dev)); + dir = debugfs_create_dir(dirname, NULL); + + /* Create subdirectories for Debug, Error injection, Statistics */ + rasdes_debug = debugfs_create_dir("rasdes_debug", dir); + rasdes_err_inj = debugfs_create_dir("rasdes_err_inj", dir); + rasdes_event_counter = debugfs_create_dir("rasdes_event_counter", dir); + + mutex_init(&dump_info->dbg_mutex); + dump_info->ras_cap = ras_cap; + dump_info->rasdes = dir; + pci->dump_info = dump_info; + + /* Create debugfs files for Debug subdirectory */ + dwc_debugfs_create(lane_detect); + dwc_debugfs_create(rx_valid); + + /* Create debugfs files for Error injection subdirectory */ + for (i = 0; i < ARRAY_SIZE(err_inj_list); i++) { + priv_tmp = devm_kzalloc(dev, sizeof(*priv_tmp), GFP_KERNEL); + if (!priv_tmp) + goto err; + + priv_tmp->idx = i; + priv_tmp->pci = pci; + debugfs_create_file(err_inj_list[i].name, 0644, + rasdes_err_inj, priv_tmp, &err_inj_ops); + } + + /* Create debugfs files for Statistical counter subdirectory */ + for (i = 0; i < ARRAY_SIZE(event_counters); i++) { + priv_tmp = devm_kzalloc(dev, sizeof(*priv_tmp), GFP_KERNEL); + if (!priv_tmp) + goto err; + + priv_tmp->idx = i; + priv_tmp->pci = pci; + rasdes_events = debugfs_create_dir(event_counters[i].name, + rasdes_event_counter); + if (event_counters[i].group_no == 0) { + debugfs_create_file("lane_select", 0644, rasdes_events, + priv_tmp, &cnt_lane_ops); + } + debugfs_create_file("counter_value", 0644, rasdes_events, priv_tmp, + &cnt_val_ops); + debugfs_create_file("counter_enable", 0444, rasdes_events, priv_tmp, + &cnt_en_ops); + } + + return 0; +err: + dwc_pcie_rasdes_debugfs_deinit(pci); + return -ENOMEM; +} diff --git a/drivers/pci/controller/dwc/pcie-designware-debugfs.h b/drivers/pci/controller/dwc/pcie-designware-debugfs.h new file mode 100644 index 000000000000..e69de29bb2d1 diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index b7ea1db14f6a..d3453db34c1f 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -222,6 +222,8 @@ #define PCIE_RAS_DES_EVENT_COUNTER_DATA 0xc +#define DW_PCIE_RAS_DES_CAP 0x2 + /* * The default address offset between dbi_base and atu_base. Root controller * drivers are not required to initialize atu_base if the offset matches this @@ -406,6 +408,7 @@ struct dw_pcie { struct reset_control_bulk_data core_rsts[DW_PCIE_NUM_CORE_RSTS]; struct gpio_desc *pe_rst; bool suspended; + void *dump_info; }; #define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp) @@ -643,4 +646,18 @@ dw_pcie_ep_get_func_from_ep(struct dw_pcie_ep *ep, u8 func_no) return NULL; } #endif + +#ifdef CONFIG_PCIE_DW_DEBUGFS +int dwc_pcie_rasdes_debugfs_init(struct dw_pcie *pci); +void dwc_pcie_rasdes_debugfs_deinit(struct dw_pcie *pci); +#else +static inline int dwc_pcie_rasdes_debugfs_init(struct dw_pcie *pci) +{ + return 0; +} +static inline void dwc_pcie_rasdes_debugfs_deinit(struct dw_pcie *pci) +{ +} +#endif + #endif /* _PCIE_DESIGNWARE_H */ From patchwork Thu Nov 30 11:50:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shradha Todi X-Patchwork-Id: 13474399 X-Patchwork-Delegate: manivannanece23@gmail.com Authentication-Results: smtp.subspace.kernel.org; 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Thu, 30 Nov 2023 20:51:13 +0900 (KST) Received: from cheetah.sa.corp.samsungelectronics.net (unknown [107.109.115.53]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20231130115111epsmtip1e774433553d715866892e41b465dc782~cZFQJB3Yi1251512515epsmtip1Y; Thu, 30 Nov 2023 11:51:11 +0000 (GMT) From: Shradha Todi To: manivannan.sadhasivam@linaro.org, lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, bhelgaas@google.com, jingoohan1@gmail.com, gustavo.pimentel@synopsys.com, josh@joshtriplett.org, lukas.bulwahn@gmail.com, hongxing.zhu@nxp.com, pankaj.dubey@samsung.com Cc: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Shradha Todi Subject: [PATCH v2 3/3] PCI: dwc: Create debugfs files in DWC driver Date: Thu, 30 Nov 2023 17:20:44 +0530 Message-Id: <20231130115044.53512-4-shradha.t@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231130115044.53512-1-shradha.t@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprGJsWRmVeSWpSXmKPExsWy7bCmpu6MyRmpBk/2slssacqw2HW3g91i 1ra5jBYrvsxkt/i/IN+ioec3q8XlXXPYLM7OO85m0fKnhcWi5Wg7i8Xdlk5Wi0VbvwCV7dnB btF7uNaBz2PnrLvsHgs2lXrcem3rsWlVJ5vHnWt72DyeXJnO5LHx3Q4mj74tqxg9tuz/zOjx eZNcAFdUtk1GamJKapFCal5yfkpmXrqtkndwvHO8qZmBoa6hpYW5kkJeYm6qrZKLT4CuW2YO 0PVKCmWJOaVAoYDE4mIlfTubovzSklSFjPziElul1IKUnAKTAr3ixNzi0rx0vbzUEitDAwMj U6DChOyMP+u72AomsVccut3I3MDYydbFyMEhIWAicb3ZtYuRi0NIYDejxLm+LjYI5xOjxOnF m5jgnMbJ94EcTrCON9snsIHYQgI7GSU2rS+HKGplkrgw8RQLSIJNQEui8WsXM0hCRKCLSeLR ipPsIAlmgWSJef13mEB2Cwu4SKy9awwSZhFQlejcdAZsAa+AlcSexT/ZIJbJS6zecIAZxOYU sJZ4tuoKI8hMCYFeDonzu56wQxS5SPRufcsCYQtLvDq+BSouJfGyvw3KTpdYuXkGM4SdI/Ft 8xKob+wlDlyZwwJyD7OApsT6XfoQYVmJqafWMUGczCfR+/sJVDmvxI55MLayxJe/e6DWSkrM O3aZFcL2kHiy/j005PoYJRbs3M04gVFuFsKKBYyMqxglUwuKc9NTi00LjPJSy+GRlpyfu4kR nEC1vHYwPnzwQe8QIxMH4yFGCQ5mJRHe60/TU4V4UxIrq1KL8uOLSnNSiw8xmgIDcCKzlGhy PjCF55XEG5pYGpiYmZmZWBqbGSqJ875unZsiJJCeWJKanZpakFoE08fEwSnVwFQXOMkg27v5 yepL3QfjLm5Kq1A+dvPBv6x7M1TOcRvn37nieed31va750s75a8znbvxaIfmPZ9bp3nYm2z0 u1inWP1N8tR8/6VEP1GwcumuiyJPHRp2cTROX/xOd9bM6089QtV3dVy6+anzjmjFD9ulKi+N 9bIPhvpUXWhU6zaaqHGo0kfvguU7F/0FSQITWqZyXbnsdPhQ4rOPJnv1LNc6aRbHNO6o3yX+ dXHqGu7c+k7vJpftXOfYog9c86svt15r/FNmvl2ywcvXE0NyH23cuMU7SfnKkycJ51wXSHyu SBH/lPO8/rdRxdfp29+ktlY9K157SC35eL+J9uMTMy4lH7q1TGGzyT92yUImlSQlluKMREMt 5qLiRADiCo8TKQQAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrBLMWRmVeSWpSXmKPExsWy7bCSnK5heUaqwdoOMYslTRkWu+52sFvM 2jaX0WLFl5nsFv8X5Fs09Pxmtbi8aw6bxdl5x9ksWv60sFi0HG1nsbjb0slqsWjrF6CyPTvY LXoP1zrweeycdZfdY8GmUo9br209Nq3qZPO4c20Pm8eTK9OZPDa+28Hk0bdlFaPHlv2fGT0+ b5IL4IrisklJzcksSy3St0vgyvizvoutYBJ7xaHbjcwNjJ1sXYycHBICJhJvtk8As4UEtjNK LN8uBhGXlPh8cR0ThC0ssfLfc3aImmYmiXcvPEFsNgEticavXcxdjFwcIgIzmCRauu+zgCSY BVIlbh+eAzSUg0NYwEVi7V1jkDCLgKpE56YzYDN5Bawk9iz+CXWDvMTqDQeYQWxOAWuJZ6uu MELsspJY9OsH8wRGvgWMDKsYRVMLinPTc5MLDPWKE3OLS/PS9ZLzczcxggNbK2gH47L1f/UO MTJxMB5ilOBgVhLhvf40PVWINyWxsiq1KD++qDQntfgQozQHi5I4r3JOZ4qQQHpiSWp2ampB ahFMlomDU6qBqV12n9he159ys6eyTuRr5Eyp3hd6TVqkX9D7s81Wdq5LR6afmsefEHdkNbP4 /+jc6ef+/vxXYefzIn97cLvWtLsaJ/pmPEs8J5t7WDF6UtOxCcxJtvLXp+tLvHFg1bKVdn63 3f7UrGtpjjeq3iavqO43u1PzeQIvb7AJ20z7h9GvDir/33rkt2f3//OfH+3kWaJ8UF1d4u9s Xf38bdJi9rO3HE+9qLmff313/SeW8xkXNLovMn3JOmCnnllu9Zdx/a7DmyyX3EjRb/mXknmy /LSCvdqy1EnTPon8ujvzwPNd+UFBp+dfTxKf59ca6plclrE6ymC3C094mfLmmmlOde4FLUVc 6Xcy1Vctfm5uocRSnJFoqMVcVJwIABe/IhXbAgAA X-CMS-MailID: 20231130115113epcas5p4bcd4ffb2baac60a0be51d6a3cb15c2a6 X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20231130115113epcas5p4bcd4ffb2baac60a0be51d6a3cb15c2a6 References: <20231130115044.53512-1-shradha.t@samsung.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Add call to initialize debugfs from DWC driver and create the RASDES debugfs hierarchy for each platform driver. Since it can be used for both DW HOST controller as well as DW EP controller, add it in the common setup function. Signed-off-by: Shradha Todi --- drivers/pci/controller/dwc/pcie-designware.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 064b4951afd8..16c9018c2ada 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -1074,4 +1074,8 @@ void dw_pcie_setup(struct dw_pcie *pci) break; } dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); + + val = dwc_pcie_rasdes_debugfs_init(pci); + if (val) + dev_err(pci->dev, "Couldn't create debugfs files\n"); }