From patchwork Thu Nov 30 21:31:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Almahallawy, Khaled" X-Patchwork-Id: 13475075 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F27FCC07CA9 for ; Thu, 30 Nov 2023 21:31:10 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 40D9B10E77B; Thu, 30 Nov 2023 21:31:10 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9954510E77B for ; Thu, 30 Nov 2023 21:31:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1701379868; x=1732915868; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=IKUDCPZLNvV9XjBYqwOJoA6rSOV5igAKs9aWoYuoLQI=; b=ggED0shyq1/xOjbFdDmkoaW2SdvHE9c93rk3nkXnlcUYKGbsneY+pOIW Ts4HaIovzOBPk1XNRf4oiqorORjufGOUgQ9JQmnUSAisicfFoRBuDfg4h FS70YDg7LM3U6uXCuirjPHYi+zxddxdEMJDEE14xy8xrLhLpWOk6TpuYa fpoGkO1+kuUsIwv1pIsdejm+0GnJh8bqtgRv1pkPEdf70AnO2t2h7wmcY Q0YdSndRblo655zQv/rEliYSUdVLfYs1AfSEkwT26L7BWwAZ6J6VFHJGc XvTUdEr/QmtRoE/SpFXNBkS0adnlywrLyyoMKZOgrxUw6bsXi2TMUBrmV Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10910"; a="392369" X-IronPort-AV: E=Sophos;i="6.04,240,1695711600"; d="scan'208";a="392369" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Nov 2023 13:31:08 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10910"; a="892956376" X-IronPort-AV: E=Sophos;i="6.04,240,1695711600"; d="scan'208";a="892956376" Received: from kialmah1-mobl1.jf.intel.com ([10.24.12.142]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Nov 2023 13:31:07 -0800 From: Khaled Almahallawy To: intel-gfx@lists.freedesktop.org Date: Thu, 30 Nov 2023 13:31:02 -0800 Message-Id: <20231130213103.214915-1-khaled.almahallawy@intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 1/2] drm/i915/dp: Use LINK_QUAL_PATTERN_* Phy test pattern names X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Starting from DP2.0 specs, DPCD 248h is renamed LINK_QUAL_PATTERN_SELECT and it has the same values of registers DPCD 10Bh-10Eh. Use the PHY pattern names defined for DPCD 10Bh-10Eh in order to add CP2520 Pattern 3 (TPS4) phy pattern support in the next patch of this series and DP2.1 PHY patterns for future series. v2: rebase Cc: Jani Nikula Cc: Imre Deak Cc: Lee Shawn C Signed-off-by: Khaled Almahallawy Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_dp.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 3b2482bf683f..a1e63ab5761b 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -4683,27 +4683,27 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp, u32 pattern_val; switch (data->phy_pattern) { - case DP_PHY_TEST_PATTERN_NONE: + case DP_LINK_QUAL_PATTERN_DISABLE: drm_dbg_kms(&dev_priv->drm, "Disable Phy Test Pattern\n"); intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0); break; - case DP_PHY_TEST_PATTERN_D10_2: + case DP_LINK_QUAL_PATTERN_D10_2: drm_dbg_kms(&dev_priv->drm, "Set D10.2 Phy Test Pattern\n"); intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2); break; - case DP_PHY_TEST_PATTERN_ERROR_COUNT: + case DP_LINK_QUAL_PATTERN_ERROR_RATE: drm_dbg_kms(&dev_priv->drm, "Set Error Count Phy Test Pattern\n"); intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_SCRAMBLED_0); break; - case DP_PHY_TEST_PATTERN_PRBS7: + case DP_LINK_QUAL_PATTERN_PRBS7: drm_dbg_kms(&dev_priv->drm, "Set PRBS7 Phy Test Pattern\n"); intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7); break; - case DP_PHY_TEST_PATTERN_80BIT_CUSTOM: + case DP_LINK_QUAL_PATTERN_80BIT_CUSTOM: /* * FIXME: Ideally pattern should come from DPCD 0x250. As * current firmware of DPR-100 could not set it, so hardcoding @@ -4721,7 +4721,7 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp, DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_CUSTOM80); break; - case DP_PHY_TEST_PATTERN_CP2520: + case DP_LINK_QUAL_PATTERN_CP2520_PAT_1: /* * FIXME: Ideally pattern should come from DPCD 0x24A. As * current firmware of DPR-100 could not set it, so hardcoding From patchwork Thu Nov 30 21:31:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Almahallawy, Khaled" X-Patchwork-Id: 13475076 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 699C5C4167B for ; Thu, 30 Nov 2023 21:31:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C51DA10E77D; Thu, 30 Nov 2023 21:31:14 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 85BEC10E77B for ; Thu, 30 Nov 2023 21:31:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1701379869; x=1732915869; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=6SnXCZvhZnJsmY1n5C4QzVxhQZ+y8NN9Yn/GFoNjw9o=; b=M5X/mfvMXk5JfjANBNOeH8FHSDOutkRTavS9RXwrxy+CO0tbT3vuo8+K eVfXr7dVNjXKXXMDclZ9nEtLYD3YXPf83+cncJBrKQPAvWVkRaBTo8C+E x8jdGpBIuxfRQrm+xeKi9KHACOILj56HzTXYYxhumuJMfJqLWrg3PVVVA neHJd53i+oMWGBQgOZqlNPmbwZSHBmnXflrARZlzg9tMeMnMEgZRrlVLJ /myVKvsHiA2Vjl7dAGPd0/MNk1+3a7SXfl4zfi0GKfd9CbzO2IC7dTOUD alNF31j5IDXezWaQ8zxGlmDCmsFXt3/WHr1xPZXqOi8jHNuwXp4Ddprz1 A==; X-IronPort-AV: E=McAfee;i="6600,9927,10910"; a="392373" X-IronPort-AV: E=Sophos;i="6.04,240,1695711600"; d="scan'208";a="392373" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Nov 2023 13:31:09 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10910"; a="892956382" X-IronPort-AV: E=Sophos;i="6.04,240,1695711600"; d="scan'208";a="892956382" Received: from kialmah1-mobl1.jf.intel.com ([10.24.12.142]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Nov 2023 13:31:09 -0800 From: Khaled Almahallawy To: intel-gfx@lists.freedesktop.org Date: Thu, 30 Nov 2023 13:31:03 -0800 Message-Id: <20231130213103.214915-2-khaled.almahallawy@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231130213103.214915-1-khaled.almahallawy@intel.com> References: <20231130213103.214915-1-khaled.almahallawy@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 2/2] drm/i915/dp: Add TPS4 PHY test pattern support X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Adding support for TPS4 (CP2520 Pattern 3) PHY pattern source tests. v2: rebase Bspec: 50482, 50484 Cc: Jani Nikula Cc: Imre Deak Cc: Lee Shawn C Signed-off-by: Khaled Almahallawy --- drivers/gpu/drm/i915/display/intel_dp.c | 11 +++++++++++ drivers/gpu/drm/i915/i915_reg.h | 4 ++++ 2 files changed, 15 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index a1e63ab5761b..8908221edfa9 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -4679,6 +4679,7 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp, struct drm_dp_phy_test_params *data = &intel_dp->compliance.test_data.phytest; struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; enum pipe pipe = crtc->pipe; u32 pattern_val; @@ -4686,6 +4687,9 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp, case DP_LINK_QUAL_PATTERN_DISABLE: drm_dbg_kms(&dev_priv->drm, "Disable Phy Test Pattern\n"); intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0); + intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), + DP_TP_CTL_TRAIN_PAT4_SEL_MASK | DP_TP_CTL_LINK_TRAIN_MASK, + DP_TP_CTL_LINK_TRAIN_NORMAL); break; case DP_LINK_QUAL_PATTERN_D10_2: drm_dbg_kms(&dev_priv->drm, "Set D10.2 Phy Test Pattern\n"); @@ -4733,6 +4737,13 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp, DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 | pattern_val); break; + case DP_LINK_QUAL_PATTERN_CP2520_PAT_3: + drm_dbg_kms(&dev_priv->drm, "Set TPS4 compliance Phy Test Pattern\n"); + intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0); + intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), + DP_TP_CTL_TRAIN_PAT4_SEL_MASK | DP_TP_CTL_LINK_TRAIN_MASK, + DP_TP_CTL_TRAIN_PAT4_SEL_TP4a | DP_TP_CTL_LINK_TRAIN_PAT4); + break; default: WARN(1, "Invalid Phy Test Pattern\n"); } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 27dc903f0553..7feb1e1478ee 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5652,6 +5652,10 @@ enum skl_power_gate { #define DP_TP_CTL_MODE_SST (0 << 27) #define DP_TP_CTL_MODE_MST (1 << 27) #define DP_TP_CTL_FORCE_ACT (1 << 25) +#define DP_TP_CTL_TRAIN_PAT4_SEL_MASK (3 << 19) +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4a (0 << 19) +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4b (1 << 19) +#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4c (2 << 19) #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1 << 18) #define DP_TP_CTL_FDI_AUTOTRAIN (1 << 15) #define DP_TP_CTL_LINK_TRAIN_MASK (7 << 8)