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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 192dW7QJOVcsM+SLyFS68RhyUfE3soq5dZAB2etvStBq8rcDVU/JvgxGOGGM+/pzW3WmqmL4AYaK7/xnwitkF5S0LpWxOZyEj7WQtz/hHy7b4PQKphloI0bHe2/PlXZ57rfhs73nUZR9a7VSqLTs8QSZa8+Jamhv4j+ATTaxJZclJOd/cH8OkGNygyev3rDGolP0+iSZn6ar16v4O5xAtNvWiyXPEOkW22yxrrvECbmR79sa6q1KGYff+pAqhxKmKz2meZO/luX49eEoS8B4i+1RnUT6+Y6S20AEX3arArhZypBcQ7ysaWP1GbGEzqyigDO4PWKN0PbNWdoiofBhMyA+XN6Chmt3DmqwLxRWow45nIwUHcKo4QNiLDtKbWU9BtP86zfRWGFTOCVDETlTXix2GtWqQKFcra6D2EuaqaQTnPi6FjsvfHJLzKe+TB7aLIIR7S3khFzQuADGwQpwzUDkX7IdzvHaX7K0tWZhxgkfadcvZ6QtVfCbcTTL8vNdNIgw7VUAH9+oyhgJ0Rzq+g38Ugr4dMBe9wjWu2d6e2eX+0nM95uTOfRZgBevHCwbpa7jf6f1nlwepo1Kl4AxNmX0K7SoY6IouLavDb7AQLSNy2q8Or9mGdiD3s3iyEuYydp5zDaCF3nyBQeJD0G7OIE5AheEA/lxsdKMEG6nvmcCM+4TaU26jq6ftcG3KwZBrztpo1GjNXIaEDOrslVnbVPsS4TmiGnRa8nfFyfM4+K6aRyUdMNT/7qn2esO3rkJRmSJrfa72bg9jI2PzAGgyt9Ehr2SKvi3QSHi5T9RiuD6rXJdvL+Wl7hjT1IFfbXeFEyLKl7YEzSRTh2zWHjjQ3bHHS118NjW0RWZ7Us2liTrFHDBDQnktrMl7Ha5TnScftwf/YhktfV5qDepvM/yRE+IOHBxe/rvGLw3WJ5YZwmxzmrk6w5DOZptUNUowqn6ltuWr8JjPzWjMbXJC1mrUhUa0pifjjI9vl/ddI+6kX+sxixe5Na0BJrfu2aUE6+W4YX8bKmunVdB43bkIu4hlQVmFKZsmam3MWTG6ehvWhNkgagCPyoYM8JDqN+ZBS+t/47v5LIaqUD5Ur1ruypBJ7/5HgHraMgv9QCQw3mRrMMqjL0QnOX0byiIjJ+ktLSSIhVNbx9gSlSR0oF49/2EwgGI9yRphr7KMFMJoPP/q523j/Da9K9Wq1Ut3uG9meiN8Z105CdJEEKHNIaKAwFxT++w3SXfB7ewkrttDMWfY7azejmouTBPsi+6ke5SD3oWLmQP5G/UAbFgnhBxStNQPbi4rICdvUo0yme+ypp71FPAS/nZXdethn9503RybDr1LV83N/y0mmGc2tGC/99ehcERrHoG1rBVaA6P+oX4Zfhhs9gD2x2wVd7LH5hSXzAX3OL7cjgdC60vmDqR7BUKZYqt4M3ZLrLf4UCjklAb3sugPo8RRBBLz/ifIHyyZ8qZcK9QF4ld/9TmWpA5dXeLzmdKVxqI24zDYRhMG+TSzfEKd6MnZmcgidzhU6EsVOfM0w1fX8+ZqJSDdm+OdWasAfTIKrhK11++C3IZUo55gS8kxy1/NjQRX5XB85ALry1o X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5a8db370-fd28-49b8-88f4-08dbf289072f X-MS-Exchange-CrossTenant-AuthSource: AM6PR04MB4838.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Dec 2023 16:17:34.9604 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: YQyO7d91WG7DJl2l3dfmgSWitYsRDhLV6iYWZ9ezB6nUxomjpLWwlXRe5PRSSjTGXIAwxM8mCDN+a3zhCTQi9g== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU2PR04MB8695 Since difference SoCs require different sequence for exiting L2, let's add a separate "exit_from_l2()" callback. This callback can be used to execute SoC specific sequence. Change ls_pcie_exit_from_l2() return value from void to int. Return error if exit_from_l2() failure at exit resume flow. Reviewed-by: Manivannan Sadhasivam Signed-off-by: Frank Li Acked-by: Roy Zang --- Notes: Change from v4 to v5 - none Change from v3 to v4 - update commit message Add mani's review by tag Change from v2 to v3 - fixed according to mani's feedback 1. update commit message 2. move dw_pcie_host_ops to next patch 3. check return value from exit_from_l2() Change from v1 to v2 - change subject 'a' to 'A' Change from v1 to v2 - change subject 'a' to 'A' drivers/pci/controller/dwc/pci-layerscape.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-layerscape.c b/drivers/pci/controller/dwc/pci-layerscape.c index 37956e09c65bd..aea89926bcc4f 100644 --- a/drivers/pci/controller/dwc/pci-layerscape.c +++ b/drivers/pci/controller/dwc/pci-layerscape.c @@ -39,6 +39,7 @@ struct ls_pcie_drvdata { const u32 pf_off; + int (*exit_from_l2)(struct dw_pcie_rp *pp); bool pm_support; }; @@ -125,7 +126,7 @@ static void ls_pcie_send_turnoff_msg(struct dw_pcie_rp *pp) dev_err(pcie->pci->dev, "PME_Turn_off timeout\n"); } -static void ls_pcie_exit_from_l2(struct dw_pcie_rp *pp) +static int ls_pcie_exit_from_l2(struct dw_pcie_rp *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct ls_pcie *pcie = to_ls_pcie(pci); @@ -150,6 +151,8 @@ static void ls_pcie_exit_from_l2(struct dw_pcie_rp *pp) 10000); if (ret) dev_err(pcie->pci->dev, "L2 exit timeout\n"); + + return ret; } static int ls_pcie_host_init(struct dw_pcie_rp *pp) @@ -180,6 +183,7 @@ static const struct ls_pcie_drvdata ls1021a_drvdata = { static const struct ls_pcie_drvdata layerscape_drvdata = { .pf_off = 0xc0000, .pm_support = true, + .exit_from_l2 = ls_pcie_exit_from_l2, }; static const struct of_device_id ls_pcie_of_match[] = { @@ -247,11 +251,14 @@ static int ls_pcie_suspend_noirq(struct device *dev) static int ls_pcie_resume_noirq(struct device *dev) { struct ls_pcie *pcie = dev_get_drvdata(dev); + int ret; if (!pcie->drvdata->pm_support) return 0; - ls_pcie_exit_from_l2(&pcie->pci->pp); + ret = pcie->drvdata->exit_from_l2(&pcie->pci->pp); + if (ret) + return ret; return dw_pcie_resume_noirq(pcie->pci); } From patchwork Fri Dec 1 16:17:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 13476132 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=nxp.com header.i=@nxp.com header.b="Y9Zem0cm" Received: from EUR02-AM0-obe.outbound.protection.outlook.com (mail-am0eur02on2073.outbound.protection.outlook.com [40.107.247.73]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C89431FCA; Fri, 1 Dec 2023 08:17:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=TC5e8cu8Ox7RFbjvEp6+SKUv2FsXhhlsu6h1gcAwdICmuSSqklsODJvTc7P6FU5dUoJc6SnuiqJFrtdOIjr+pdciVRJB8Wsad/aUNZeKY3kcsSJeUEO2WBWby7K4BwnWRlzAa0GK7pndwgWAe1llkgoDhB6iD1VWWuvPLXwFzq6kSQhahZsgeqwEjat1Pb5uEHGKCzNdYeCsFt2Ah/lgf1/GK84Bte3B51lRdyQGvNRBxg2h+CwMFu/q2OA1OeLZ3eAWMzbEi/C6hWfVApES0gTUIk8nab+ki6Yla95ehB4aZuPCr5CKh6Ao3WH4vwxvWMx71e27NVUUN/Gm0bOvEQ== ARC-Message-Signature: i=1; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: z5xVGM/wt5MohXrtOqaXw1HrEvhRP3c3g6b9tZSzs9y7gN4IuPYND6mKttGNai0NqjB/+4vq+LxR/hwYEukSTh/mjxThm1x8dv3npDFJd2s5ZvlpTZ+WUgP+tZnu1RYMjXEGlDYGFKKArGpuw77Fuy5vXhHbFK4Ly8ldRS1SUjZg6rtyYesJ06m3EJ7RsF9DGdcm2xl3P2W6yv7U2DiCcyEhc4jhQ857S/sGRBk6SOMwz8dTJdg7ZoQpZQkUdlr7xOrpmUiNxhvp5L3bJCOi98DmSzA7bHgNmcjhKK+otPnh9kULUp5z8rBYqXyImt3NyvBW1fLPDZboX9h3k/nVz8mlsApPZOAnLivRAwU02htSVjGO93bVCJgRRY7z8r4KC9lVXk+kvh24CvJnIF5/d54yqrzesRI109qWj8tcvAcrd0V/9afvo2FojAhE49LhQihODIHNmaw0AK0NLEZv4Hi2aT20fn7FdjaSjQdoR6gxSuNiZ9Riw7fUxuifgvnuLgaO23je2z7Sgl4xfy5vC7QFLX+B/M3EJ9SPmLtP5sS44CBi7f66Pk5qSK3UU2BV3dCcFWuyZkKapqPvjDLJ8e33+RL7SKY9LoRq/wF2KJck8E56s+Gq+1OfQJ5TUNa7dfhEYz875cp1WgQjCxOuZXa2iCd9SHpTJs0nFvdtnIoQBXEXz4ychS5Xkjjfdbmy2EN96acLjJy69GUf+j4LhqguLc/iaJtaqGZpsSQ4xpGXnYvjn4SQCICkfWStzxNQen19Bn5Uy8Vwl0E7U+jY3rYs4cYMWHXaZaCbo9HUzAVGqR9Agqwn/SIl0iMb7lLeqoHuZT6jgCIYFug+/rpBoPlz5wAe61swJqqmrxTXw9ybG35TPVRvks5oMfMtckm/2BKbAlizpTBBMsbznLRA4Nb+/GAjJybRnxHT582E1aSF4LWoz59sCs7UcqqK6dMcUSYFowevHkqTWHjXprSb/IhctmUb+597EiHJ6lQCQ0S9kqjnVU5wFmZlEo6lqmu0mBqlghnBWmAZBTT2Tr9ctdncz4a/yx1AjBtNo+RBkHuD56mtT18i66S+RVU/ejclo5iz7ukIYFeuMbx9ToJaLBU1/xzpBPuvBgMFGOqWj+1de16aEKv9f9JE2YPASuzrw0HS7+JVp/0AhMcCGC74A8aYb0cBrYBKwiJ9MM8yDfF7lDEBEqIUX0BZ1S7WpVYfcQIKowlCYRs2S7vpEvTH+AWEeAuDREKYQ3a6bBMGIbegUQcMO27iU8dWd9Cp9YDP2xIyFtrb8+/gn9g7Ds7FH8pAEsUvXc4BDHUYHX8ELl8L0EzVTKwr4xI5X0WHg2XT2LIfY/MB+7MbsGtqcPcAqQ+t+y4RQTFczlWvmTb2YZCTsLq8Sie0NsYL63W+IDPzbVhF9sg9fiTisYuZ57Jgb6+k9I9nUQAkGJNAQRFYawvHZfwgdn6tFcbwRnPiAnivxweEnUKd9jAadE2ZhSA4vxVG35oA86Yq3VtKIUpiQNs5Da/P7Rn2NYGn0AnMQYFaHLxZWD9fjc9oKHxJ+Oc3lUTR3FXeOeaafK8efIXbTvKLEw0Jn3PYnB2lz4s8ys+t X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 83dd3b3a-4767-4b68-3484-08dbf2890943 X-MS-Exchange-CrossTenant-AuthSource: AM6PR04MB4838.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Dec 2023 16:17:38.4525 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: gA50gslnAgngHUkENUoprOamOTDmqLmQrnmfDIFMYeiagyubmF/uN9OMXEIELPpu+0Y8sPiy2EJaHzh4k4XjDg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU2PR04MB8695 Add suspend/resume support for Layerscape LS1021a. In the suspend path, PME_Turn_Off message is sent to the endpoint to transition the link to L2/L3_Ready state. In this SoC, there is no way to check if the controller has received the PME_To_Ack from the endpoint or not. So to be on the safer side, the driver just waits for PCIE_PME_TO_L2_TIMEOUT_US before asserting the SoC specific PMXMTTURNOFF bit to complete the PME_Turn_Off handshake. Then the link would enter L2/L3 state depending on the VAUX supply. In the resume path, the link is brought back from L2 to L0 by doing a software reset. Signed-off-by: Frank Li Acked-by: Roy Zang Reviewed-by: Manivannan Sadhasivam --- Notes: Change from v4 to v5 - update comit message - remove a empty line - use comments /* Reset the PEX wrapper to bring the link out of L2 */ - pci->pp.ops = pcie->drvdata->ops, ls_pcie_host_ops to the "ops" member of layerscape_drvdata. - don't set pcie->scfg = NULL at error path Change from v3 to v4 - update commit message. - it is reset a glue logic part for PCI controller. - use regmap_write_bits() to reduce code change. Change from v2 to v3 - update according to mani's feedback change from v1 to v2 - change subject 'a' to 'A' drivers/pci/controller/dwc/pci-layerscape.c | 81 ++++++++++++++++++++- 1 file changed, 80 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pci-layerscape.c b/drivers/pci/controller/dwc/pci-layerscape.c index aea89926bcc4f..8bdaae9be7d56 100644 --- a/drivers/pci/controller/dwc/pci-layerscape.c +++ b/drivers/pci/controller/dwc/pci-layerscape.c @@ -35,11 +35,19 @@ #define PF_MCR_PTOMR BIT(0) #define PF_MCR_EXL2S BIT(1) +/* LS1021A PEXn PM Write Control Register */ +#define SCFG_PEXPMWRCR(idx) (0x5c + (idx) * 0x64) +#define PMXMTTURNOFF BIT(31) +#define SCFG_PEXSFTRSTCR 0x190 +#define PEXSR(idx) BIT(idx) + #define PCIE_IATU_NUM 6 struct ls_pcie_drvdata { const u32 pf_off; + const struct dw_pcie_host_ops *ops; int (*exit_from_l2)(struct dw_pcie_rp *pp); + bool scfg_support; bool pm_support; }; @@ -47,6 +55,8 @@ struct ls_pcie { struct dw_pcie *pci; const struct ls_pcie_drvdata *drvdata; void __iomem *pf_base; + struct regmap *scfg; + int index; bool big_endian; }; @@ -171,18 +181,70 @@ static int ls_pcie_host_init(struct dw_pcie_rp *pp) return 0; } +static void scfg_pcie_send_turnoff_msg(struct regmap *scfg, u32 reg, u32 mask) +{ + /* Send PME_Turn_Off message */ + regmap_write_bits(scfg, reg, mask, mask); + + /* + * There is no specific register to check for PME_To_Ack from endpoint. + * So on the safe side, wait for PCIE_PME_TO_L2_TIMEOUT_US. + */ + mdelay(PCIE_PME_TO_L2_TIMEOUT_US/1000); + + /* + * Layerscape hardware reference manual recommends clearing the PMXMTTURNOFF bit + * to complete the PME_Turn_Off handshake. + */ + regmap_write_bits(scfg, reg, mask, 0); +} + +static void ls1021a_pcie_send_turnoff_msg(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct ls_pcie *pcie = to_ls_pcie(pci); + + scfg_pcie_send_turnoff_msg(pcie->scfg, SCFG_PEXPMWRCR(pcie->index), PMXMTTURNOFF); +} + +static int scfg_pcie_exit_from_l2(struct regmap *scfg, u32 reg, u32 mask) +{ + /* Reset the PEX wrapper to bring the link out of L2 */ + regmap_write_bits(scfg, reg, mask, mask); + regmap_write_bits(scfg, reg, mask, 0); + + return 0; +} + +static int ls1021a_pcie_exit_from_l2(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct ls_pcie *pcie = to_ls_pcie(pci); + + return scfg_pcie_exit_from_l2(pcie->scfg, SCFG_PEXSFTRSTCR, PEXSR(pcie->index)); +} + static const struct dw_pcie_host_ops ls_pcie_host_ops = { .host_init = ls_pcie_host_init, .pme_turn_off = ls_pcie_send_turnoff_msg, }; +static const struct dw_pcie_host_ops ls1021a_pcie_host_ops = { + .host_init = ls_pcie_host_init, + .pme_turn_off = ls1021a_pcie_send_turnoff_msg, +}; + static const struct ls_pcie_drvdata ls1021a_drvdata = { - .pm_support = false, + .pm_support = true, + .scfg_support = true, + .ops = &ls1021a_pcie_host_ops, + .exit_from_l2 = ls1021a_pcie_exit_from_l2, }; static const struct ls_pcie_drvdata layerscape_drvdata = { .pf_off = 0xc0000, .pm_support = true, + .ops = &ls_pcie_host_ops; .exit_from_l2 = ls_pcie_exit_from_l2, }; @@ -205,6 +267,8 @@ static int ls_pcie_probe(struct platform_device *pdev) struct dw_pcie *pci; struct ls_pcie *pcie; struct resource *dbi_base; + u32 index[2]; + int ret; pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); if (!pcie) @@ -220,6 +284,7 @@ static int ls_pcie_probe(struct platform_device *pdev) pci->pp.ops = &ls_pcie_host_ops; pcie->pci = pci; + pci->pp.ops = pcie->drvdata->ops; dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs"); pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base); @@ -230,6 +295,20 @@ static int ls_pcie_probe(struct platform_device *pdev) pcie->pf_base = pci->dbi_base + pcie->drvdata->pf_off; + if (pcie->drvdata->scfg_support) { + pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node, "fsl,pcie-scfg"); + if (IS_ERR(pcie->scfg)) { + dev_err(dev, "No syscfg phandle specified\n"); + return PTR_ERR(pcie->scfg); + } + + ret = of_property_read_u32_array(dev->of_node, "fsl,pcie-scfg", index, 2); + if (ret) + return ret; + + pcie->index = index[1]; + } + if (!ls_pcie_is_bridge(pcie)) return -ENODEV; From patchwork Fri Dec 1 16:17:11 2023 Content-Type: text/plain; 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Received: from AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) by DU2PR04MB8695.eurprd04.prod.outlook.com (2603:10a6:10:2de::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7068.13; Fri, 1 Dec 2023 16:17:42 +0000 Received: from AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::95f5:5118:258f:ee40]) by AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::95f5:5118:258f:ee40%6]) with mapi id 15.20.7046.015; Fri, 1 Dec 2023 16:17:42 +0000 From: Frank Li To: manivannan.sadhasivam@linaro.org Cc: Frank.Li@nxp.com, bhelgaas@google.com, imx@lists.linux.dev, kw@linux.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, lpieralisi@kernel.org, minghuan.Lian@nxp.com, mingkai.hu@nxp.com, robh@kernel.org, roy.zang@nxp.com Subject: [PATCH v5 3/4] PCI: layerscape(ep): Rename pf_* as pf_lut_* Date: Fri, 1 Dec 2023 11:17:11 -0500 Message-Id: <20231201161712.1645987-4-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231201161712.1645987-1-Frank.Li@nxp.com> References: <20231201161712.1645987-1-Frank.Li@nxp.com> X-ClientProxiedBy: BY5PR17CA0070.namprd17.prod.outlook.com (2603:10b6:a03:167::47) To AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM6PR04MB4838:EE_|DU2PR04MB8695:EE_ X-MS-Office365-Filtering-Correlation-Id: 4632ae41-e9b8-4158-42a6-08dbf2890b59 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: +F+QMf4RXYgr63OXxr6tTj+ICUrmVGQBAo8ZyyCU+1MJh1HxMuOzKtoBK/MuJErtiyijwHwQOVXV6CBQY/LD+FJE84rxTskRmAxd3sRK6bMWc92TTf8vnro8jzYBag3Mr6DEOEezioz9RQgm6VLumT99BMmAAUVZ7hkAZhPwmyIN/mqhim92DroIlB13pefbiwcm+t/dJ2+dFQdSF08DfHy0YUi5RByhlhNSj0YCRqWDtb2ALyx14/SeRRlFnV1a6GFFC8UCa/q06QxT+3I43dAzrQqkoO0I73n20wGPU7DVEs2fMgr/An5Swh2X4QpkCCUPjFabvlEJGe8G0HCabVSOVBCNEcqylu1zMG2T9FpFw1BpPdkyqeX4tpetwu3RJtLWMQzPSrvmLevIBepoIATpiHiaNCfcnR9Oya5xSyZeZrgyWh73If+rqjOZzeBuipdyzeQ+4W8cJVh6BRJfRsP7Q2NvC0Ed91Aym888V943B6wXVj8G+BT3xdvvTvWVqbA5dntA+SZ+Kj0FLJUlgKcpFM5NCtkuOXKVCAqh8kTlrjRM4ZWTpWctpJQ6T7FgNfjtdFiBwdE0Q2TAcxiQ8YedWr+EsOk8BXaE4tq5CRrHWcfMlhL9sJIKDIqSVsn6V8565RshCyGJcEZHecpVUULavjAxv4X7lOyF2imtPzY8Pgdm4D5Nyr1hoRr7s+Qgc/PvwPUSH2eFS7RMSbJcM8aPBa13laWefFsL1cYKF7hPd/q1xMV6e/aoK+50/Xzqmvh7kFpA/8z/KtgiOcpCESVmrRNlYf/MyyMU4bMBtnCEehHzmjAWf84ObC6TOiutzj70ZQ63PlqlRff+IYcmoTXvTcXgEeS3CuaQ0L9SjvK4HmghgmvBgL553kyvG8DaXT6Pd5Pz0vpYcX9307XIXFj3643+VSVdiIdh7+McLrIyq4WMIbFnM9Jvloml8KzeW9+HHEnTvzCFLa7EiJMgRiUnPpcN9bqrrnJrRXhWu8LYtdmMS184bZJWVPSvJA7jfNh8MGGVdiuAgxRuQClVcOWH+dMdLxP8eTwJAPooquENe+NIxp6eSjz0EhrAkafIRwRC/m7BSoOcJAlJp8SdLdkJh/Lq2U7GEDrtRAPFsCwXx8liqHELeFFlFpLlLKMy/dNU1X3jC/9jOtHyMphDQrrEWX0pT+9wi12dkEWn80vWXFT5aIJmuaJ1JjlfE/CAhRvlgilX/FvLmxSEQTUYMzHDV6KvDROWig2yn/ABJhd2aGTjhiYfr+QxfEF5dRQTf/mECRLYSrVGEnwglQKk4FUk5hEOLrVKeelN3mcpor10B0CXq3c6OzhRYpIpZ+CxDYAwz1rG+RjH++3lHdLIdnaGb7VQT67N4p6tMIlspesS/dNljDDngTMxnEC0mPF3o/HAL5wxqXyrcpTOiPfa3MgH7G4YaISsFyYdQ1GwVwGBlrjKJV5oBeOcN2yz/F0F68t2m6j5jdOdwLaYG/UYguPHyD9p9yVkYZ4qjtI8X2pG5pfCXb81TXPvraB9Xfso1AeO/Jle5QEWso0UkImT3CZ0dX+GUr1v/cXOzNbPwryia5K4e76VqyQqrdtf+R8z X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4632ae41-e9b8-4158-42a6-08dbf2890b59 X-MS-Exchange-CrossTenant-AuthSource: AM6PR04MB4838.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Dec 2023 16:17:42.0043 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: mBjY+WYS5G8LC8HraXhuwGa0yuUUJel2vx0QYfRtMF7igLGoILSt0esViwZ1rl0Y6jKEld1IT6jvKElbAAGrfQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU2PR04MB8695 'pf' and 'lut' is just difference name in difference chips, but basic it is a MMIO base address plus an offset. Rename it to avoid duplicate pf_* and lut_* in driver. Signed-off-by: Frank Li Acked-by: Roy Zang Reviewed-by: Manivannan Sadhasivam --- Notes: pf_lut is better than pf_* or lut* because some chip use 'pf', some chip use 'lut'. Change from v4 to v5 - rename layerscape-ep code also change from v1 to v4 - new patch at v3 .../pci/controller/dwc/pci-layerscape-ep.c | 16 ++++----- drivers/pci/controller/dwc/pci-layerscape.c | 36 +++++++++---------- 2 files changed, 26 insertions(+), 26 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c index 3d3c50ef4b6ff..2ca339f938a86 100644 --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c @@ -49,7 +49,7 @@ struct ls_pcie_ep { bool big_endian; }; -static u32 ls_lut_readl(struct ls_pcie_ep *pcie, u32 offset) +static u32 ls_pcie_pf_lut_readl(struct ls_pcie_ep *pcie, u32 offset) { struct dw_pcie *pci = pcie->pci; @@ -59,7 +59,7 @@ static u32 ls_lut_readl(struct ls_pcie_ep *pcie, u32 offset) return ioread32(pci->dbi_base + offset); } -static void ls_lut_writel(struct ls_pcie_ep *pcie, u32 offset, u32 value) +static void ls_pcie_pf_lut_writel(struct ls_pcie_ep *pcie, u32 offset, u32 value) { struct dw_pcie *pci = pcie->pci; @@ -76,8 +76,8 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id) u32 val, cfg; u8 offset; - val = ls_lut_readl(pcie, PEX_PF0_PME_MES_DR); - ls_lut_writel(pcie, PEX_PF0_PME_MES_DR, val); + val = ls_pcie_pf_lut_readl(pcie, PEX_PF0_PME_MES_DR); + ls_pcie_pf_lut_writel(pcie, PEX_PF0_PME_MES_DR, val); if (!val) return IRQ_NONE; @@ -96,9 +96,9 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id) dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, pcie->lnkcap); dw_pcie_dbi_ro_wr_dis(pci); - cfg = ls_lut_readl(pcie, PEX_PF0_CONFIG); + cfg = ls_pcie_pf_lut_readl(pcie, PEX_PF0_CONFIG); cfg |= PEX_PF0_CFG_READY; - ls_lut_writel(pcie, PEX_PF0_CONFIG, cfg); + ls_pcie_pf_lut_writel(pcie, PEX_PF0_CONFIG, cfg); dw_pcie_ep_linkup(&pci->ep); dev_dbg(pci->dev, "Link up\n"); @@ -130,10 +130,10 @@ static int ls_pcie_ep_interrupt_init(struct ls_pcie_ep *pcie, } /* Enable interrupts */ - val = ls_lut_readl(pcie, PEX_PF0_PME_MES_IER); + val = ls_pcie_pf_lut_readl(pcie, PEX_PF0_PME_MES_IER); val |= PEX_PF0_PME_MES_IER_LDDIE | PEX_PF0_PME_MES_IER_HRDIE | PEX_PF0_PME_MES_IER_LUDIE; - ls_lut_writel(pcie, PEX_PF0_PME_MES_IER, val); + ls_pcie_pf_lut_writel(pcie, PEX_PF0_PME_MES_IER, val); return 0; } diff --git a/drivers/pci/controller/dwc/pci-layerscape.c b/drivers/pci/controller/dwc/pci-layerscape.c index 8bdaae9be7d56..a9151e98fde6f 100644 --- a/drivers/pci/controller/dwc/pci-layerscape.c +++ b/drivers/pci/controller/dwc/pci-layerscape.c @@ -44,7 +44,7 @@ #define PCIE_IATU_NUM 6 struct ls_pcie_drvdata { - const u32 pf_off; + const u32 pf_lut_off; const struct dw_pcie_host_ops *ops; int (*exit_from_l2)(struct dw_pcie_rp *pp); bool scfg_support; @@ -54,13 +54,13 @@ struct ls_pcie_drvdata { struct ls_pcie { struct dw_pcie *pci; const struct ls_pcie_drvdata *drvdata; - void __iomem *pf_base; + void __iomem *pf_lut_base; struct regmap *scfg; int index; bool big_endian; }; -#define ls_pcie_pf_readl_addr(addr) ls_pcie_pf_readl(pcie, addr) +#define ls_pcie_pf_lut_readl_addr(addr) ls_pcie_pf_lut_readl(pcie, addr) #define to_ls_pcie(x) dev_get_drvdata((x)->dev) static bool ls_pcie_is_bridge(struct ls_pcie *pcie) @@ -101,20 +101,20 @@ static void ls_pcie_fix_error_response(struct ls_pcie *pcie) iowrite32(PCIE_ABSERR_SETTING, pci->dbi_base + PCIE_ABSERR); } -static u32 ls_pcie_pf_readl(struct ls_pcie *pcie, u32 off) +static u32 ls_pcie_pf_lut_readl(struct ls_pcie *pcie, u32 off) { if (pcie->big_endian) - return ioread32be(pcie->pf_base + off); + return ioread32be(pcie->pf_lut_base + off); - return ioread32(pcie->pf_base + off); + return ioread32(pcie->pf_lut_base + off); } -static void ls_pcie_pf_writel(struct ls_pcie *pcie, u32 off, u32 val) +static void ls_pcie_pf_lut_writel(struct ls_pcie *pcie, u32 off, u32 val) { if (pcie->big_endian) - iowrite32be(val, pcie->pf_base + off); + iowrite32be(val, pcie->pf_lut_base + off); else - iowrite32(val, pcie->pf_base + off); + iowrite32(val, pcie->pf_lut_base + off); } static void ls_pcie_send_turnoff_msg(struct dw_pcie_rp *pp) @@ -124,11 +124,11 @@ static void ls_pcie_send_turnoff_msg(struct dw_pcie_rp *pp) u32 val; int ret; - val = ls_pcie_pf_readl(pcie, LS_PCIE_PF_MCR); + val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_PF_MCR); val |= PF_MCR_PTOMR; - ls_pcie_pf_writel(pcie, LS_PCIE_PF_MCR, val); + ls_pcie_pf_lut_writel(pcie, LS_PCIE_PF_MCR, val); - ret = readx_poll_timeout(ls_pcie_pf_readl_addr, LS_PCIE_PF_MCR, + ret = readx_poll_timeout(ls_pcie_pf_lut_readl_addr, LS_PCIE_PF_MCR, val, !(val & PF_MCR_PTOMR), PCIE_PME_TO_L2_TIMEOUT_US/10, PCIE_PME_TO_L2_TIMEOUT_US); @@ -147,15 +147,15 @@ static int ls_pcie_exit_from_l2(struct dw_pcie_rp *pp) * Set PF_MCR_EXL2S bit in LS_PCIE_PF_MCR register for the link * to exit L2 state. */ - val = ls_pcie_pf_readl(pcie, LS_PCIE_PF_MCR); + val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_PF_MCR); val |= PF_MCR_EXL2S; - ls_pcie_pf_writel(pcie, LS_PCIE_PF_MCR, val); + ls_pcie_pf_lut_writel(pcie, LS_PCIE_PF_MCR, val); /* * L2 exit timeout of 10ms is not defined in the specifications, * it was chosen based on empirical observations. */ - ret = readx_poll_timeout(ls_pcie_pf_readl_addr, LS_PCIE_PF_MCR, + ret = readx_poll_timeout(ls_pcie_pf_lut_readl_addr, LS_PCIE_PF_MCR, val, !(val & PF_MCR_EXL2S), 1000, 10000); @@ -242,9 +242,9 @@ static const struct ls_pcie_drvdata ls1021a_drvdata = { }; static const struct ls_pcie_drvdata layerscape_drvdata = { - .pf_off = 0xc0000, + .pf_lut_off = 0xc0000, .pm_support = true, - .ops = &ls_pcie_host_ops; + .ops = &ls_pcie_host_ops, .exit_from_l2 = ls_pcie_exit_from_l2, }; @@ -293,7 +293,7 @@ static int ls_pcie_probe(struct platform_device *pdev) pcie->big_endian = of_property_read_bool(dev->of_node, "big-endian"); - pcie->pf_base = pci->dbi_base + pcie->drvdata->pf_off; + pcie->pf_lut_base = pci->dbi_base + pcie->drvdata->pf_lut_off; if (pcie->drvdata->scfg_support) { pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node, "fsl,pcie-scfg"); From patchwork Fri Dec 1 16:17:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 13476134 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=nxp.com header.i=@nxp.com header.b="TRSvzROO" Received: from EUR02-AM0-obe.outbound.protection.outlook.com (mail-am0eur02on2073.outbound.protection.outlook.com [40.107.247.73]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4969A1FD8; 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Fri, 1 Dec 2023 16:17:45 +0000 From: Frank Li To: manivannan.sadhasivam@linaro.org Cc: Frank.Li@nxp.com, bhelgaas@google.com, imx@lists.linux.dev, kw@linux.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, lpieralisi@kernel.org, minghuan.Lian@nxp.com, mingkai.hu@nxp.com, robh@kernel.org, roy.zang@nxp.com Subject: [PATCH v5 4/4] PCI: layerscape: Add suspend/resume for ls1043a Date: Fri, 1 Dec 2023 11:17:12 -0500 Message-Id: <20231201161712.1645987-5-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231201161712.1645987-1-Frank.Li@nxp.com> References: <20231201161712.1645987-1-Frank.Li@nxp.com> X-ClientProxiedBy: BY5PR17CA0070.namprd17.prod.outlook.com (2603:10b6:a03:167::47) To AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM6PR04MB4838:EE_|DU2PR04MB8695:EE_ X-MS-Office365-Filtering-Correlation-Id: bef8c711-36c9-443a-1a8f-08dbf2890d74 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: j/UcZxrp+TpWsNdxFTZpVAywkGk0XHhDmLfWJNtdjIymhFiX3bmsUwGJwQdVE7tYCKFZo/idG2SNWMiiwdJqzEkZF0mpTgO3hDwipk56YesJfXFUPqvEijddu/RBfINLIbjClw2vn03xb3J8CiNzMugimKB12XOr8v11BHrAhga2ZsoMqYJigUHCCflTsyW8JnWfQV+SUA8d2DnKSZ6p+IfCHsZ1xoKgh6dchKD/lSxVosEwpAtOecrp0H9HdzpVgtES9hhMksUUMELJcDZ+ei2JjQJBbKVuILnEj/ov5eB33gGyHmOZL0Cl85ozgNAdxW5HIfy0+BUn02ibcoJLmAxqJ+DotjHKwQ8ElpksKEsGqBkpMfx9gjbi7Ah3uM2tBIsOZy7fHxNEv5JtCJr88I3plllD2Xg/JESVXxjeV9qCXhu8mh2BGb//7k/Zq6g4lBZoe5uGZiCFE8q+cG6jv9lfGTrrexeEaWTfRkUSt36d4r9tuE+ZmulDs1aTazq+UVNGfBWR0c5xOynxWx9XwyHSehnsxkekNiyMgOADqEAh24eKBIAjNsJVBfc0rvcbb5mEVfwrB3uk6Nkz5+nXFH1xbBf3L/RCndoSMLbUHRqfcuH2OvMto05mgiwpqnUtCDZdfBQ0ibNtsEtPzuMJqZzLEW2j1HnF95z0WNy1u+7HUd1jFwAVV04FIqjnhpY68Q+bjxLBRIIvdW22GMP7lc8uRfKU8JGSMzFrIJcyJnyBc6AL+xGLQq3O+HffnbFQL+hfG4KXgmbWSLRfPJ/yGmBZqHSzGEwOfijWmzCqlH/UTNqmjmAnF499uMw88Hy1HYlDLrALWyYQ8fGYgm8407625kSj7de1PG8IdrI9SBwtJOz0WnhTfxVFZJURcuI8g9h1Y3z8otIF4EI6d04lCKFbjpQQNoLwML6MphRMMeH/a+sfBS1eEYLAOu9fqtRV/+gh5roUldQsQSeDAqWzeSR4pHb6mELHVns2jU9+1fKQf2XEY0yX3EkLePYNL/tj6WivoDxAD+hwvVcHm5LncbSmfBh0uNw5us+bvv9wDrhexTpBQwyx/ooVkMfhx4kFOyom34kVxqR+/Yp9I1vmX4guNAIGeLCvvPaNbPHq22HDjijoeudBx8nvHX/R3JznFtzcI6w3JhyjykcWOnvhrSQbUdp9nzVaQWaa7xlGJOql9LPQP0BoG400l5GNLQQkw1wnZHotLow4ghPuMDna4p3JGp2Y7KNkTyP6eNmlYbm150HYmkTa+azfnLSfEhKBtklud9DqGQrc4VlbMvkEyo6euozHOYho8/iNs4xBwfPCPzOxpkbOVqCuelShzSKPE+sAZIjPVXOcjkL/8jb+1XiL/za2i7/zyNdAPSUlb0PvkJXXJ8yVsfuFP1ji5ed2w/v06vVvEArBI9xwrLmla3jZvEZuK5gEmK+QbJ1GLWgruvN0HMfgj54ZDZRd4kmfTwYRfAMqB6wWBBt1paaZ9r/c34cBp2i2+LWPjYJav9/8KcsBvbC3essB9sVo/JyYvEMdoXXqShiwCjt9kFCZDms7nz2dg2hUBxyN6xHZ+/ojHBHnv49f0SfniFrkg0m5 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: bef8c711-36c9-443a-1a8f-08dbf2890d74 X-MS-Exchange-CrossTenant-AuthSource: AM6PR04MB4838.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Dec 2023 16:17:45.4793 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 69YYGyPL8EkMJM79V/u0Fm/HT5/tQFxhbjGkSDdtoqfMtRKuSJmiGHJXXYYGHsBGB2pg1AWoS4DMNSWEr3AReQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU2PR04MB8695 Add suspend/resume support for Layerscape LS1043a. In the suspend path, PME_Turn_Off message is sent to the endpoint to transition the link to L2/L3_Ready state. In this SoC, there is no way to check if the controller has received the PME_To_Ack from the endpoint or not. So to be on the safer side, the driver just waits for PCIE_PME_TO_L2_TIMEOUT_US before asserting the SoC specific PMXMTTURNOFF bit to complete the PME_Turn_Off handshake. Then the link would enter L2/L3 state depending on the VAUX supply. In the resume path, the link is brought back from L2 to L0 by doing a software reset. Signed-off-by: Frank Li Acked-by: Roy Zang Reviewed-by: Manivannan Sadhasivam --- Notes: Change from v4 to v5 - update commit message - use comments /* Reset the PEX wrapper to bring the link out of L2 */ Change from v3 to v4 - Call scfg_pcie_send_turnoff_msg() shared with ls1021a - update commit message Change from v2 to v3 - Remove ls_pcie_lut_readl(writel) function Change from v1 to v2 - Update subject 'a' to 'A' drivers/pci/controller/dwc/pci-layerscape.c | 63 ++++++++++++++++++++- 1 file changed, 62 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pci-layerscape.c b/drivers/pci/controller/dwc/pci-layerscape.c index a9151e98fde6f..715365e91f8ef 100644 --- a/drivers/pci/controller/dwc/pci-layerscape.c +++ b/drivers/pci/controller/dwc/pci-layerscape.c @@ -41,6 +41,15 @@ #define SCFG_PEXSFTRSTCR 0x190 #define PEXSR(idx) BIT(idx) +/* LS1043A PEX PME control register */ +#define SCFG_PEXPMECR 0x144 +#define PEXPME(idx) BIT(31 - (idx) * 4) + +/* LS1043A PEX LUT debug register */ +#define LS_PCIE_LDBG 0x7fc +#define LDBG_SR BIT(30) +#define LDBG_WE BIT(31) + #define PCIE_IATU_NUM 6 struct ls_pcie_drvdata { @@ -224,6 +233,45 @@ static int ls1021a_pcie_exit_from_l2(struct dw_pcie_rp *pp) return scfg_pcie_exit_from_l2(pcie->scfg, SCFG_PEXSFTRSTCR, PEXSR(pcie->index)); } +static void ls1043a_pcie_send_turnoff_msg(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct ls_pcie *pcie = to_ls_pcie(pci); + + scfg_pcie_send_turnoff_msg(pcie->scfg, SCFG_PEXPMECR, PEXPME(pcie->index)); +} + +static int ls1043a_pcie_exit_from_l2(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct ls_pcie *pcie = to_ls_pcie(pci); + u32 val; + + /* + * Reset the PEX wrapper to bring the link out of L2. + * LDBG_WE: allows the user to have write access to the PEXDBG[SR] for both setting and + * clearing the soft reset on the PEX module. + * LDBG_SR: When SR is set to 1, the PEX module enters soft reset. + */ + val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_LDBG); + val |= LDBG_WE; + ls_pcie_pf_lut_writel(pcie, LS_PCIE_LDBG, val); + + val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_LDBG); + val |= LDBG_SR; + ls_pcie_pf_lut_writel(pcie, LS_PCIE_LDBG, val); + + val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_LDBG); + val &= ~LDBG_SR; + ls_pcie_pf_lut_writel(pcie, LS_PCIE_LDBG, val); + + val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_LDBG); + val &= ~LDBG_WE; + ls_pcie_pf_lut_writel(pcie, LS_PCIE_LDBG, val); + + return 0; +} + static const struct dw_pcie_host_ops ls_pcie_host_ops = { .host_init = ls_pcie_host_init, .pme_turn_off = ls_pcie_send_turnoff_msg, @@ -241,6 +289,19 @@ static const struct ls_pcie_drvdata ls1021a_drvdata = { .exit_from_l2 = ls1021a_pcie_exit_from_l2, }; +static const struct dw_pcie_host_ops ls1043a_pcie_host_ops = { + .host_init = ls_pcie_host_init, + .pme_turn_off = ls1043a_pcie_send_turnoff_msg, +}; + +static const struct ls_pcie_drvdata ls1043a_drvdata = { + .pf_lut_off = 0x10000, + .pm_support = true, + .scfg_support = true, + .ops = &ls1043a_pcie_host_ops, + .exit_from_l2 = ls1043a_pcie_exit_from_l2, +}; + static const struct ls_pcie_drvdata layerscape_drvdata = { .pf_lut_off = 0xc0000, .pm_support = true, @@ -252,7 +313,7 @@ static const struct of_device_id ls_pcie_of_match[] = { { .compatible = "fsl,ls1012a-pcie", .data = &layerscape_drvdata }, { .compatible = "fsl,ls1021a-pcie", .data = &ls1021a_drvdata }, { .compatible = "fsl,ls1028a-pcie", .data = &layerscape_drvdata }, - { .compatible = "fsl,ls1043a-pcie", .data = &ls1021a_drvdata }, + { .compatible = "fsl,ls1043a-pcie", .data = &ls1043a_drvdata }, { .compatible = "fsl,ls1046a-pcie", .data = &layerscape_drvdata }, { .compatible = "fsl,ls2080a-pcie", .data = &layerscape_drvdata }, { .compatible = "fsl,ls2085a-pcie", .data = &layerscape_drvdata },