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Sun, 3 Dec 2023 07:40:25 -0500 (EST) Received: by feathertop.org (sSMTP sendmail emulation); Sun, 03 Dec 2023 23:40:22 +1100 From: Tim Lunn To: linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org Cc: Jagan Teki , Conor Dooley , linux-arm-kernel@lists.infradead.org, Rob Herring , Heiko Stuebner , Krzysztof Kozlowski , Tim Lunn Subject: [PATCH v3 1/8] ARM: dts: rockchip: rv1126: Add alternate UART pins Date: Sun, 3 Dec 2023 23:39:57 +1100 Message-Id: <20231203124004.2676174-2-tim@feathertop.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231203124004.2676174-1-tim@feathertop.org> References: <20231203124004.2676174-1-tim@feathertop.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231203_044031_548167_CC2D112C X-CRM114-Status: UNSURE ( 9.51 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add uart3m2_xfer and uart4m2_xfer pins for Rockchip RV1126. These are used as serial ports for the indicator and Zigbee radio on the iHost. Signed-off-by: Tim Lunn --- (no changes since v1) arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi b/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi index bb34b0c9cb4a..4f85b7b3fc4c 100644 --- a/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi +++ b/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi @@ -263,6 +263,14 @@ uart3m0_xfer: uart3m0-xfer { /* uart3_tx_m0 */ <3 RK_PC6 4 &pcfg_pull_up>; }; + /omit-if-no-ref/ + uart3m2_xfer: uart3m2-xfer { + rockchip,pins = + /* uart3_rx_m2 */ + <3 RK_PA1 4 &pcfg_pull_up>, + /* uart3_tx_m2 */ + <3 RK_PA0 4 &pcfg_pull_up>; + }; }; uart4 { /omit-if-no-ref/ @@ -273,6 +281,14 @@ uart4m0_xfer: uart4m0-xfer { /* uart4_tx_m0 */ <3 RK_PA4 4 &pcfg_pull_up>; }; + /omit-if-no-ref/ + uart4m2_xfer: uart4m2-xfer { + rockchip,pins = + /* uart4_rx_m2 */ + <1 RK_PD4 3 &pcfg_pull_up>, + /* uart4_tx_m2 */ + <1 RK_PD5 3 &pcfg_pull_up>; + }; }; uart5 { /omit-if-no-ref/ From patchwork Sun Dec 3 12:39:58 2023 Content-Type: text/plain; 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Sun, 3 Dec 2023 07:40:34 -0500 (EST) Received: by feathertop.org (sSMTP sendmail emulation); Sun, 03 Dec 2023 23:40:31 +1100 From: Tim Lunn To: linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org Cc: Jagan Teki , Conor Dooley , linux-arm-kernel@lists.infradead.org, Rob Herring , Heiko Stuebner , Krzysztof Kozlowski , Tim Lunn Subject: [PATCH v3 2/8] ARM: dts: rockchip: rv1126: Serial aliases Date: Sun, 3 Dec 2023 23:39:58 +1100 Message-Id: <20231203124004.2676174-3-tim@feathertop.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231203124004.2676174-1-tim@feathertop.org> References: <20231203124004.2676174-1-tim@feathertop.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231203_044040_094700_4D39BC1B X-CRM114-Status: UNSURE ( 8.73 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add serial aliases for uart nodes so that serial devices are created Signed-off-by: Tim Lunn --- Changes in v3: - Add missing serial5 alias arch/arm/boot/dts/rockchip/rv1126.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rv1126.dtsi b/arch/arm/boot/dts/rockchip/rv1126.dtsi index 9ccd1bad6229..adb11a43c5db 100644 --- a/arch/arm/boot/dts/rockchip/rv1126.dtsi +++ b/arch/arm/boot/dts/rockchip/rv1126.dtsi @@ -21,6 +21,12 @@ / { aliases { i2c0 = &i2c0; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; }; cpus { From patchwork Sun Dec 3 12:39:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tim Lunn X-Patchwork-Id: 13477302 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 374D9C4167B for ; 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Sun, 3 Dec 2023 07:40:42 -0500 (EST) Received: by feathertop.org (sSMTP sendmail emulation); Sun, 03 Dec 2023 23:40:39 +1100 From: Tim Lunn To: linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org Cc: Jagan Teki , Conor Dooley , linux-arm-kernel@lists.infradead.org, Rob Herring , Heiko Stuebner , Krzysztof Kozlowski , Tim Lunn , Andi Shyti , linux-i2c@vger.kernel.org Subject: [PATCH v3 3/8] i2c: rk3x: Adjust mask/value offset for i2c2 on rv1126 Date: Sun, 3 Dec 2023 23:39:59 +1100 Message-Id: <20231203124004.2676174-4-tim@feathertop.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231203124004.2676174-1-tim@feathertop.org> References: <20231203124004.2676174-1-tim@feathertop.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231203_044049_440042_A0C53865 X-CRM114-Status: GOOD ( 13.26 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Rockchip RV1126 is using old style i2c controller, the i2c2 bus uses a non-sequential offset in the grf register for the mask/value bits for this bus. This patch fixes i2c2 bus on rv1126 SoCs. Signed-off-by: Tim Lunn Acked-by: Heiko Stuebner Reviewed-by: Andi Shyti --- Changes in v3: - i2c: add code comment and clarify commit message further - i2c: Collect ack by Heiko Changes in v2: - i2c: clarify commit message drivers/i2c/busses/i2c-rk3x.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/i2c/busses/i2c-rk3x.c b/drivers/i2c/busses/i2c-rk3x.c index a044ca0c35a1..06fec2344575 100644 --- a/drivers/i2c/busses/i2c-rk3x.c +++ b/drivers/i2c/busses/i2c-rk3x.c @@ -1288,8 +1288,12 @@ static int rk3x_i2c_probe(struct platform_device *pdev) return -EINVAL; } - /* 27+i: write mask, 11+i: value */ - value = BIT(27 + bus_nr) | BIT(11 + bus_nr); + /* rv1126 i2c2 uses non-sequential write mask 20, value 4 */ + if (i2c->soc_data == &rv1126_soc_data && bus_nr == 2) + value = BIT(20) | BIT(4); + else + /* 27+i: write mask, 11+i: value */ + value = BIT(27 + bus_nr) | BIT(11 + bus_nr); ret = regmap_write(grf, i2c->soc_data->grf_offset, value); if (ret != 0) { From patchwork Sun Dec 3 12:40:00 2023 Content-Type: text/plain; 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Sun, 3 Dec 2023 07:40:52 -0500 (EST) Received: by feathertop.org (sSMTP sendmail emulation); Sun, 03 Dec 2023 23:40:49 +1100 From: Tim Lunn To: linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org Cc: Jagan Teki , Conor Dooley , linux-arm-kernel@lists.infradead.org, Rob Herring , Heiko Stuebner , Krzysztof Kozlowski , Tim Lunn Subject: [PATCH v3 4/8] ARM: dts: rockchip: rv1126: Add i2c2 nodes Date: Sun, 3 Dec 2023 23:40:00 +1100 Message-Id: <20231203124004.2676174-5-tim@feathertop.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231203124004.2676174-1-tim@feathertop.org> References: <20231203124004.2676174-1-tim@feathertop.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231203_044057_879398_52C72D2A X-CRM114-Status: GOOD ( 10.06 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add i2c2 node and i2c2_xfer pinctrl for Rockchip RV1126 Signed-off-by: Tim Lunn --- (no changes since v1) arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi | 10 ++++++++++ arch/arm/boot/dts/rockchip/rv1126.dtsi | 15 +++++++++++++++ 2 files changed, 25 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi b/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi index 4f85b7b3fc4c..167a48afa3a4 100644 --- a/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi +++ b/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi @@ -87,6 +87,16 @@ i2c0_xfer: i2c0-xfer { <0 RK_PB5 1 &pcfg_pull_none_drv_level_0_smt>; }; }; + i2c2 { + /omit-if-no-ref/ + i2c2_xfer: i2c2-xfer { + rockchip,pins = + /* i2c2_scl */ + <0 RK_PC2 1 &pcfg_pull_none_drv_level_0_smt>, + /* i2c2_sda */ + <0 RK_PC3 1 &pcfg_pull_none_drv_level_0_smt>; + }; + }; pwm2 { /omit-if-no-ref/ pwm2m0_pins: pwm2m0-pins { diff --git a/arch/arm/boot/dts/rockchip/rv1126.dtsi b/arch/arm/boot/dts/rockchip/rv1126.dtsi index adb11a43c5db..bb603cae13df 100644 --- a/arch/arm/boot/dts/rockchip/rv1126.dtsi +++ b/arch/arm/boot/dts/rockchip/rv1126.dtsi @@ -21,6 +21,7 @@ / { aliases { i2c0 = &i2c0; + i2c2 = &i2c2; serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; @@ -237,6 +238,20 @@ i2c0: i2c@ff3f0000 { status = "disabled"; }; + i2c2: i2c@ff400000 { + compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c"; + reg = <0xff400000 0x1000>; + interrupts = ; + rockchip,grf = <&pmugrf>; + clocks = <&pmucru CLK_I2C2>, <&pmucru PCLK_I2C2>; + clock-names = "i2c", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + uart1: serial@ff410000 { compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; reg = <0xff410000 0x100>; From patchwork Sun Dec 3 12:40:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tim Lunn X-Patchwork-Id: 13477304 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E3233C4167B for ; Sun, 3 Dec 2023 12:41:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Sun, 3 Dec 2023 07:41:00 -0500 (EST) Received: by feathertop.org (sSMTP sendmail emulation); Sun, 03 Dec 2023 23:40:57 +1100 From: Tim Lunn To: linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org Cc: Jagan Teki , Conor Dooley , linux-arm-kernel@lists.infradead.org, Rob Herring , Heiko Stuebner , Krzysztof Kozlowski , Tim Lunn Subject: [PATCH v3 5/8] ARM: dts: rockchip: rv1126: Split up rgmii1 pinctrl Date: Sun, 3 Dec 2023 23:40:01 +1100 Message-Id: <20231203124004.2676174-6-tim@feathertop.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231203124004.2676174-1-tim@feathertop.org> References: <20231203124004.2676174-1-tim@feathertop.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231203_044106_352511_2A6D4501 X-CRM114-Status: GOOD ( 10.79 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Split up the pinctrl definitions for rgmii1 so it can be shared with devices using an RMII PHY. Signed-off-by: Tim Lunn --- (no changes since v1) .../dts/rockchip/rv1126-edgeble-neu2-io.dts | 2 +- .../arm/boot/dts/rockchip/rv1126-pinctrl.dtsi | 46 +++++++++++++------ 2 files changed, 34 insertions(+), 14 deletions(-) diff --git a/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io.dts b/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io.dts index f09be8405964..0c2396b8f8db 100644 --- a/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io.dts +++ b/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io.dts @@ -61,7 +61,7 @@ &gmac { phy-mode = "rgmii"; phy-supply = <&vcc_3v3>; pinctrl-names = "default"; - pinctrl-0 = <&rgmiim1_pins &clk_out_ethernetm1_pins>; + pinctrl-0 = <&rgmiim1_miim &rgmiim1_bus2 &rgmiim1_bus4 &clk_out_ethernetm1_pins>; tx_delay = <0x2a>; rx_delay = <0x1a>; status = "okay"; diff --git a/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi b/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi index 167a48afa3a4..06b1d7f2d858 100644 --- a/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi +++ b/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi @@ -115,36 +115,56 @@ pwm11m0_pins: pwm11m0-pins { }; rgmii { /omit-if-no-ref/ - rgmiim1_pins: rgmiim1-pins { + rgmiim1_miim: rgmiim1-miim { rockchip,pins = /* rgmii_mdc_m1 */ <2 RK_PC2 2 &pcfg_pull_none>, /* rgmii_mdio_m1 */ - <2 RK_PC1 2 &pcfg_pull_none>, - /* rgmii_rxclk_m1 */ - <2 RK_PD3 2 &pcfg_pull_none>, + <2 RK_PC1 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rgmiim1_rxer: rgmiim1-rxer { + rockchip,pins = + /* rgmii_rxer_m1 */ + <2 RK_PC0 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rgmiim1_bus2: rgmiim1-bus2 { + rockchip,pins = /* rgmii_rxd0_m1 */ <2 RK_PB5 2 &pcfg_pull_none>, /* rgmii_rxd1_m1 */ <2 RK_PB6 2 &pcfg_pull_none>, - /* rgmii_rxd2_m1 */ - <2 RK_PC7 2 &pcfg_pull_none>, - /* rgmii_rxd3_m1 */ - <2 RK_PD0 2 &pcfg_pull_none>, /* rgmii_rxdv_m1 */ <2 RK_PB4 2 &pcfg_pull_none>, - /* rgmii_txclk_m1 */ - <2 RK_PD2 2 &pcfg_pull_none_drv_level_3>, /* rgmii_txd0_m1 */ <2 RK_PC3 2 &pcfg_pull_none_drv_level_3>, /* rgmii_txd1_m1 */ <2 RK_PC4 2 &pcfg_pull_none_drv_level_3>, + /* rgmii_txen_m1 */ + <2 RK_PC6 2 &pcfg_pull_none_drv_level_3>; + }; + /omit-if-no-ref/ + rgmiim1_bus4: rgmiim1-bus4 { + rockchip,pins = + /* rgmii_rxclk_m1 */ + <2 RK_PD3 2 &pcfg_pull_none>, + /* rgmii_rxd2_m1 */ + <2 RK_PC7 2 &pcfg_pull_none>, + /* rgmii_rxd3_m1 */ + <2 RK_PD0 2 &pcfg_pull_none>, + /* rgmii_txclk_m1 */ + <2 RK_PD2 2 &pcfg_pull_none_drv_level_3>, /* rgmii_txd2_m1 */ <2 RK_PD1 2 &pcfg_pull_none_drv_level_3>, /* rgmii_txd3_m1 */ - <2 RK_PA4 2 &pcfg_pull_none_drv_level_3>, - /* rgmii_txen_m1 */ - <2 RK_PC6 2 &pcfg_pull_none_drv_level_3>; + <2 RK_PA4 2 &pcfg_pull_none_drv_level_3>; + }; + /omit-if-no-ref/ + rgmiim1_mclkinout: rgmiim1-mclkinout { + rockchip,pins = + /* rgmii_clk_m1 */ + <2 RK_PB7 2 &pcfg_pull_none>; }; }; sdmmc0 { From patchwork Sun Dec 3 12:40:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tim Lunn X-Patchwork-Id: 13477305 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 30310C10DCE for ; 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Sun, 3 Dec 2023 07:41:09 -0500 (EST) Received: by feathertop.org (sSMTP sendmail emulation); Sun, 03 Dec 2023 23:41:06 +1100 From: Tim Lunn To: linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org Cc: Jagan Teki , Conor Dooley , linux-arm-kernel@lists.infradead.org, Rob Herring , Heiko Stuebner , Krzysztof Kozlowski , Tim Lunn Subject: [PATCH v3 6/8] ARM: dts: rockchip: Add rv1109 SoC Date: Sun, 3 Dec 2023 23:40:02 +1100 Message-Id: <20231203124004.2676174-7-tim@feathertop.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231203124004.2676174-1-tim@feathertop.org> References: <20231203124004.2676174-1-tim@feathertop.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231203_044114_702689_B04EB9D4 X-CRM114-Status: GOOD ( 12.53 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The Rockchip rv1109 SoC is a dual core version of the rv1126. It is otherwise identical and shares the same device tree config. This patch introduces a dtsi file to drop the additional cpu nodes. Taken from Rockchip BSP kernel. Signed-off-by: Tim Lunn --- (no changes since v2) Changes in v2: - new patch arch/arm/boot/dts/rockchip/rv1109.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 arch/arm/boot/dts/rockchip/rv1109.dtsi diff --git a/arch/arm/boot/dts/rockchip/rv1109.dtsi b/arch/arm/boot/dts/rockchip/rv1109.dtsi new file mode 100644 index 000000000000..9cbaa08ab1b8 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rv1109.dtsi @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include "rv1126.dtsi" + +/ { + compatible = "rockchip,rv1109"; + + cpus { + /delete-node/ cpu@f02; + /delete-node/ cpu@f03; + }; + + arm-pmu { + interrupts = , + ; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; +}; From patchwork Sun Dec 3 12:40:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tim Lunn X-Patchwork-Id: 13477306 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B4209C4167B for ; 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Sun, 3 Dec 2023 07:41:17 -0500 (EST) Received: by feathertop.org (sSMTP sendmail emulation); Sun, 03 Dec 2023 23:41:14 +1100 From: Tim Lunn To: linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org Cc: Jagan Teki , Conor Dooley , linux-arm-kernel@lists.infradead.org, Rob Herring , Heiko Stuebner , Krzysztof Kozlowski , Tim Lunn Subject: [PATCH v3 7/8] ARM: dts: Add Sonoff iHost Smart Home Hub Date: Sun, 3 Dec 2023 23:40:03 +1100 Message-Id: <20231203124004.2676174-8-tim@feathertop.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231203124004.2676174-1-tim@feathertop.org> References: <20231203124004.2676174-1-tim@feathertop.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231203_044123_514158_9CCDD3E7 X-CRM114-Status: GOOD ( 16.91 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Sonoff iHost is gateway device designed to provide a Smart Home Hub, it is based on Rockchip RV1126. There is also a version with 2GB RAM based off the RV1109 dual core SoC. Features: - Rockchip RV1126 - 4GB DDR4 - 8GB eMMC - microSD slot - RMII Ethernet PHY - 1x USB 2.0 Host - 1x USB 2.0 OTG - Realtek RTL8723DS WiFi/BT - EFR32MG21 Silabs Zigbee radio - Speaker/Microphone This patch adds the initial device tree for this device, it is largely based off the device trees for mainline Edgeble Neu2 and downstream Rockchip rv1126-evb-v13 configs. It has been adapted with relevant peripheral and GPIO pins for the iHost. Signed-off-by: Tim Lunn --- Changes in v3: - Move ethernet alias from rv1126.dtsi to board dtsi Changes in v2: - Address review comments from Heiko - Split out rv1109.dtsi to new patch arch/arm/boot/dts/rockchip/Makefile | 2 + .../boot/dts/rockchip/rv1109-sonoff-ihost.dts | 13 + .../boot/dts/rockchip/rv1126-sonoff-ihost.dts | 13 + .../dts/rockchip/rv1126-sonoff-ihost.dtsi | 408 ++++++++++++++++++ 4 files changed, 436 insertions(+) create mode 100644 arch/arm/boot/dts/rockchip/rv1109-sonoff-ihost.dts create mode 100644 arch/arm/boot/dts/rockchip/rv1126-sonoff-ihost.dts create mode 100644 arch/arm/boot/dts/rockchip/rv1126-sonoff-ihost.dtsi diff --git a/arch/arm/boot/dts/rockchip/Makefile b/arch/arm/boot/dts/rockchip/Makefile index 0f46e18fe275..4d4533d6f407 100644 --- a/arch/arm/boot/dts/rockchip/Makefile +++ b/arch/arm/boot/dts/rockchip/Makefile @@ -2,7 +2,9 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rv1108-elgin-r1.dtb \ rv1108-evb.dtb \ + rv1109-sonoff-ihost.dtb \ rv1126-edgeble-neu2-io.dtb \ + rv1126-sonoff-ihost.dtb \ rk3036-evb.dtb \ rk3036-kylin.dtb \ rk3066a-bqcurie2.dtb \ diff --git a/arch/arm/boot/dts/rockchip/rv1109-sonoff-ihost.dts b/arch/arm/boot/dts/rockchip/rv1109-sonoff-ihost.dts new file mode 100644 index 000000000000..3bfdb00ac8e1 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rv1109-sonoff-ihost.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; +#include "rv1109.dtsi" +#include "rv1126-sonoff-ihost.dtsi" + +/ { + model = "Sonoff iHost 2G"; + compatible = "itead,sonoff-ihost", "rockchip,rv1109"; +}; diff --git a/arch/arm/boot/dts/rockchip/rv1126-sonoff-ihost.dts b/arch/arm/boot/dts/rockchip/rv1126-sonoff-ihost.dts new file mode 100644 index 000000000000..106d1e42f285 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rv1126-sonoff-ihost.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; +#include "rv1126.dtsi" +#include "rv1126-sonoff-ihost.dtsi" + +/ { + model = "Sonoff iHost 4G"; + compatible = "itead,sonoff-ihost", "rockchip,rv1126"; +}; diff --git a/arch/arm/boot/dts/rockchip/rv1126-sonoff-ihost.dtsi b/arch/arm/boot/dts/rockchip/rv1126-sonoff-ihost.dtsi new file mode 100644 index 000000000000..543b4ec8d244 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rv1126-sonoff-ihost.dtsi @@ -0,0 +1,408 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. + */ + +/ { + aliases { + ethernet0 = &gmac; + mmc0 = &emmc; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + vcc5v0_sys: regulator-vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + sdio_pwrseq: pwrseq-sdio { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + reset-gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk &emmc_rstnout>; + rockchip,default-sample-phase = <90>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + status = "okay"; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = ; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc_buck5>; + vcc6-supply = <&vcc_buck5>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + + regulators { + vdd_npu_vepu: DCDC_REG1 { + regulator-name = "vdd_npu_vepu"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc3v3_sys: DCDC_REG4 { + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_buck5: DCDC_REG5 { + regulator-name = "vcc_buck5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2200000>; + }; + }; + + vcc_0v8: LDO_REG1 { + regulator-name = "vcc_0v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_pmu: LDO_REG2 { + regulator-name = "vcc1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd0v8_pmu: LDO_REG3 { + regulator-name = "vcc0v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <800000>; + }; + }; + + vcc_1v8: LDO_REG4 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_dovdd: LDO_REG5 { + regulator-name = "vcc_dovdd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_dvdd: LDO_REG6 { + regulator-name = "vcc_dvdd"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_avdd: LDO_REG7 { + regulator-name = "vcc_avdd"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG8 { + regulator-name = "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: LDO_REG9 { + regulator-name = "vcc3v3_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_5v0: SWITCH_REG1 { + regulator-name = "vcc_5v0"; + }; + + vcc_3v3: SWITCH_REG2 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +&i2c2 { + status = "okay"; + clock-frequency = <400000>; + + pcf8563: rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + #clock-cells = <0>; + interrupt-parent = <&gpio0>; + interrupts = ; + clock-output-names = "xin32k"; + }; +}; + +&gmac { + assigned-clocks = <&cru CLK_GMAC_SRC_M1>, <&cru CLK_GMAC_SRC>, + <&cru CLK_GMAC_TX_RX>; + assigned-clock-parents = <&cru CLK_GMAC_RGMII_M1>, <&cru CLK_GMAC_SRC_M1>, + <&cru RMII_MODE_CLK>; + assigned-clock-rates = <0>, <50000000>; + clock_in_out = "output"; + phy-handle = <&phy>; + phy-mode = "rmii"; + phy-supply = <&vcc_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmiim1_miim &rgmiim1_rxer &rgmiim1_bus2 &rgmiim1_mclkinout>; + status = "okay"; +}; + +&mdio { + phy: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + pinctrl-names = "default"; + pinctrl-0 = <ð_phy_rst>; + reset-active-low; + reset-assert-us = <50000>; + reset-deassert-us = <10000>; + reset-gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + ethernet { + eth_phy_rst: eth-phy-rst { + rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + bt { + bt_enable: bt-enable { + rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_dev: bt-wake-dev { + rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_host: bt-wake-host { + rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + wifi { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + pmuio0-supply = <&vcc1v8_pmu>; + pmuio1-supply = <&vcc3v3_sys>; + vccio1-supply = <&vcc_1v8>; + vccio2-supply = <&vccio_sd>; + vccio3-supply = <&vcc_1v8>; + vccio4-supply = <&vcc_dovdd>; + vccio5-supply = <&vcc_1v8>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_dovdd>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdio { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + max-frequency = <100000000>; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_clk &sdmmc1_cmd &sdmmc1_bus4>; + rockchip,default-sample-phase = <90>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sys>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_bus4 &sdmmc0_det>; + rockchip,default-sample-phase = <90>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr104; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_ctsn &uart0_rtsn>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "realtek,rtl8723ds-bt"; + device-wake-gpios = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>; /* BT_WAKE */ + enable-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; /* BT_RST */ + host-wake-gpios = <&gpio1 RK_PC5 GPIO_ACTIVE_HIGH>; /* BT_WAKE_HOST */ + max-speed = <2000000>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_enable>, <&bt_wake_dev>, <&bt_wake_host>; + }; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3m2_xfer>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4m2_xfer>; + status = "okay"; +}; From patchwork Sun Dec 3 12:40:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tim Lunn X-Patchwork-Id: 13477307 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 12E28C4167B for ; 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Sun, 3 Dec 2023 07:41:26 -0500 (EST) Received: by feathertop.org (sSMTP sendmail emulation); Sun, 03 Dec 2023 23:41:23 +1100 From: Tim Lunn To: linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org Cc: Jagan Teki , Conor Dooley , linux-arm-kernel@lists.infradead.org, Rob Herring , Heiko Stuebner , Krzysztof Kozlowski , Tim Lunn , Rob Herring Subject: [PATCH v3 8/8] dt-bindings: arm: rockchip: Add Sonoff iHost Date: Sun, 3 Dec 2023 23:40:04 +1100 Message-Id: <20231203124004.2676174-9-tim@feathertop.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231203124004.2676174-1-tim@feathertop.org> References: <20231203124004.2676174-1-tim@feathertop.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231203_044132_726647_1643D49E X-CRM114-Status: UNSURE ( 8.13 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Sonoff iHost is a smart home hub with built in radios for wifi/bt and Zigbee. It is based off the Rockchip RV1126 (or RV1109) SoC. Signed-off-by: Tim Lunn Acked-by: Rob Herring --- (no changes since v2) Changes in v2: - Collect Robh Ack for dt-bindings patch Documentation/devicetree/bindings/arm/rockchip.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 5f7c6c4aad8f..a26bbcd00deb 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -922,6 +922,13 @@ properties: - const: rockchip,rk3568-bpi-r2pro - const: rockchip,rk3568 + - description: Sonoff iHost Smart Home Hub + items: + - const: itead,sonoff-ihost + - enum: + - rockchip,rv1126 + - rockchip,rv1109 + additionalProperties: true ...