From patchwork Mon Dec 4 16:08:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 13478735 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=nxp.com header.i=@nxp.com header.b="LYVeTANI" Received: from EUR02-AM0-obe.outbound.protection.outlook.com (mail-am0eur02on2077.outbound.protection.outlook.com [40.107.247.77]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ED383CA; Mon, 4 Dec 2023 08:08:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=X46SCRsdphmXwLSOw+SYfxOp9j1C65IKvKlLx48tKRADZz2G5aZIjLi9NiPWei+bh5QSfTAZOGl0pyTJUd22vMCiLqCANbyUbffU9ItW7E1noy3wg2Xw6ymb3EcDH51ncwwS/sMVwE/xRkDRySKllvyfoen73iByCtak5fg6sC6pz8NnncbjJfWOk5POtUhFBBVJFrNehyreu0POBAN8P9+0o4pdX1j4oAQkc7cyzQKxmDEiwpZlZc10B8MA6XfQ2fwI06XuHl7JQawjbQwHhzqB1xqjWQU3TPDKCcZO/jrE1Q6i8jIBFj51gIosn64vpbSJa5nUBNvQRJ4NHYiccA== ARC-Message-Signature: i=1; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: KkiYNH/8GcLG+Pvsct5JMAYbvxWeMN0yHgYItaNXfaFBwnHzsmM+MxM7mOvmjN+03Xhiq98cmDFZWsQsa1ReCfIJuK0pfQCEjS/bgzGKPbyeZEaGC/3vCUlOSbq38ItNpTw/gJavNLVYwtZQExn61xBlCWhRlZVEA98y2WvqZ+BkjZddWx2qgC1/QiW6Jv53slFvsoyFJOii2JbG0PWLshGFyumfXiIKXiVBvAEzg6PGjUBeWTqqCbsqkoTFRaVIEyysrQHtq6oSjfNR409VayIuwcDwUIZ8OHiZelhkpOdUcaAEdLxIT9FJy4SZuqNOgWBMQJVCPhTFWZDujvnDC3dK2HUIJNp7udQWXeTZUDLvFbWaubl9119CJsqevOY8RgqIZ9S6AAEyzMkQ+fkjPxp1FxFsyKfE7up+Mpym4YmDUOJHUhzwlzaD3b8hXB80sODAqsuj0a9LrOTnp12JLn9x7gH7VU7GAyjiZXe5sQbcZvNhN12hPp0y0REgGRYJdYGGn7KYIf1c5eD2e+YmNoSP0eoOOgWhmXIK7UkkHBiCdEb8bLucr/GSe4tG+u29eaH6UU86X3oK1RpBHL/ea8P6Udj7XANktBqxinUyk543ufaJJA3wmDINLKHq5M8rguivzvu0zk5NPHeUOvyHMXkzOmuXsCIs9nAcPORUA27uYgjLZ87UAagXMKGenYlEBpZPHbj2whb62ms0ToSLQZNkmddM8fMejBLOQ6nR673F5kHA+XxDPDG9X8TXeTAGRTqXgjQxyMMB6Dq9W6lnWmNI2xvwJKn1dCvQPnvKTZ+hx/jG5CPIsiG9IV+gPvFdAeyrkDzgibUNQ9ikq38FXZeBGRBgqem7F6iTuAS3A7FCR1xL7/H6qOJmVuDprREodW09NeTppNxUWLqniBYuFPeFbvyj2O41KfFPshbA5EdFwixPR1YMOIgBNq4RhRb0ryhYIec34HseftDZ2ac6H4gFCKkU7QhMZDFnMsOrljsNWm/myZ4/pyt5Ipj2mMy2QVEpES8XWTfXSPre1im5rcThnRaBr3ov5VdVhM4kHV9Ykmss0npqPIsLejwIdhdWo4fnujgYQCdzP5lGHiVOlAxtDnyduWco6B3/Vk+Mh0slQzfvEutX1KbPSmtXTYJfT4ag6Lkcohtdma+3aLuqkc2ISQqWWGnIpQ/2AarNlSWUM4zW79hgu8Jk9hFjh8sjsy2ggOGEkfThgHql38F/suRZIUkDmu85oku9ALaHLbscZN9/zj2DD2KWeyJ6oUp2i7eifDoJoyFPClPK3K+OZJorf81efdqm+D0FE9NCzwMAUTDdCXhrtZqCaO0DS+uVunGdSVcpiZz21UqOQmo0GX1fv7+rTEofOAKVjwtGSaC8JIfZ9tcGDcVtWRS2LAC0sFd5s5fSmozBvzrVSgTOING4WZF/6MJDEi0ZrSJqj0t/Omt6sNm0DvytCCrbq2kH1IzUwEhpxaVC2f9PtLM/18Y6m3sZYr277/NXLRQU23q7IHYD0uYzVjgHKXE6EuPje2rdGB0YpRveFFxJE9UiIAiTO7aFoaR7XeaYf7BITexuG9Dnxw5djgt+5pMHjgec X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: a297a239-6e34-491c-fef5-08dbf4e34ef6 X-MS-Exchange-CrossTenant-AuthSource: AM6PR04MB4838.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Dec 2023 16:08:52.4875 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 4WT6ZXki8n3zg+fyUngGpN2+dRd90lSYd0+rKnE7uOYK72/KQsk0jT6f61yaIb4xPQSPc6fvd/tyUyjV85YEqw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBBPR04MB8057 Since difference SoCs require different sequence for exiting L2, let's add a separate "exit_from_l2()" callback. This callback can be used to execute SoC specific sequence. Change ls_pcie_exit_from_l2() return value from void to int. Return error if exit_from_l2() failure at exit resume flow. Acked-by: Roy Zang Reviewed-by: Manivannan Sadhasivam Signed-off-by: Frank Li --- Notes: Change from v4 to v6 - none Change from v3 to v4 - update commit message Add mani's review by tag Change from v2 to v3 - fixed according to mani's feedback 1. update commit message 2. move dw_pcie_host_ops to next patch 3. check return value from exit_from_l2() Change from v1 to v2 - change subject 'a' to 'A' Change from v1 to v2 - change subject 'a' to 'A' drivers/pci/controller/dwc/pci-layerscape.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-layerscape.c b/drivers/pci/controller/dwc/pci-layerscape.c index 37956e09c65bd..aea89926bcc4f 100644 --- a/drivers/pci/controller/dwc/pci-layerscape.c +++ b/drivers/pci/controller/dwc/pci-layerscape.c @@ -39,6 +39,7 @@ struct ls_pcie_drvdata { const u32 pf_off; + int (*exit_from_l2)(struct dw_pcie_rp *pp); bool pm_support; }; @@ -125,7 +126,7 @@ static void ls_pcie_send_turnoff_msg(struct dw_pcie_rp *pp) dev_err(pcie->pci->dev, "PME_Turn_off timeout\n"); } -static void ls_pcie_exit_from_l2(struct dw_pcie_rp *pp) +static int ls_pcie_exit_from_l2(struct dw_pcie_rp *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct ls_pcie *pcie = to_ls_pcie(pci); @@ -150,6 +151,8 @@ static void ls_pcie_exit_from_l2(struct dw_pcie_rp *pp) 10000); if (ret) dev_err(pcie->pci->dev, "L2 exit timeout\n"); + + return ret; } static int ls_pcie_host_init(struct dw_pcie_rp *pp) @@ -180,6 +183,7 @@ static const struct ls_pcie_drvdata ls1021a_drvdata = { static const struct ls_pcie_drvdata layerscape_drvdata = { .pf_off = 0xc0000, .pm_support = true, + .exit_from_l2 = ls_pcie_exit_from_l2, }; static const struct of_device_id ls_pcie_of_match[] = { @@ -247,11 +251,14 @@ static int ls_pcie_suspend_noirq(struct device *dev) static int ls_pcie_resume_noirq(struct device *dev) { struct ls_pcie *pcie = dev_get_drvdata(dev); + int ret; if (!pcie->drvdata->pm_support) return 0; - ls_pcie_exit_from_l2(&pcie->pci->pp); + ret = pcie->drvdata->exit_from_l2(&pcie->pci->pp); + if (ret) + return ret; return dw_pcie_resume_noirq(pcie->pci); } From patchwork Mon Dec 4 16:08:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 13478736 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=nxp.com header.i=@nxp.com header.b="Boy/edya" Received: from EUR02-AM0-obe.outbound.protection.outlook.com (mail-am0eur02on2077.outbound.protection.outlook.com [40.107.247.77]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3DC0C102; Mon, 4 Dec 2023 08:08:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=MxH4iqlC+Gllr+SdAZTwmzJZsSXUmWcuaE6kE7rmtq0IVxUj7HY0mjlJU5hY3eEDU9C4/oW2WHZJFJqrJ6AAI6BL89NKSYhhPEOY1YDYWkbs9xEZcazAKZxp8k/G+PXF3QOa9Al5BGJ7zcGGPGY3UqjAKHaszhqQISnPJlr0zm3JM+n56B5wM6kqf/E08kW6WYBWIXhz0Ceq6ivGsUWyXzuzrRcF9quDq703jkf53ABxfEGiXLWdZX+/fb9no4V+vckYFwJVLtUJCm26voXxdMLPSM3i6H6pishPvG8a2hcaW61H6DS9pF+9efRxOzKgp6bDJAQVKN4jGuo2kkEfGw== ARC-Message-Signature: i=1; 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b=Boy/edya7aoXKLEmU22wagGx3zTWi/aUfJBTowL2mwlwqcjuv7BRhiw5vUaHj/1p86MwRei0iRyf/HY8cOYe2m14Bgea/x85L6M2NWc6nhYullT1Z+Q2/clGr7qkfdvR+ymTDrE5H81heJ0gHoxdOI/Gf63/R/IvtaU06wcxJW0= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) by DBBPR04MB8057.eurprd04.prod.outlook.com (2603:10a6:10:1f1::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7068.22; Mon, 4 Dec 2023 16:08:56 +0000 Received: from AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::95f5:5118:258f:ee40]) by AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::95f5:5118:258f:ee40%6]) with mapi id 15.20.7068.022; Mon, 4 Dec 2023 16:08:56 +0000 From: Frank Li To: manivannan.sadhasivam@linaro.org Cc: Frank.Li@nxp.com, bhelgaas@google.com, imx@lists.linux.dev, kw@linux.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, lpieralisi@kernel.org, minghuan.Lian@nxp.com, mingkai.hu@nxp.com, robh@kernel.org, roy.zang@nxp.com Subject: [PATCH v6 2/4] PCI: layerscape: Add suspend/resume for ls1021a Date: Mon, 4 Dec 2023 11:08:27 -0500 Message-Id: <20231204160829.2498703-3-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231204160829.2498703-1-Frank.Li@nxp.com> References: <20231204160829.2498703-1-Frank.Li@nxp.com> X-ClientProxiedBy: BYAPR21CA0027.namprd21.prod.outlook.com (2603:10b6:a03:114::37) To AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM6PR04MB4838:EE_|DBBPR04MB8057:EE_ X-MS-Office365-Filtering-Correlation-Id: c32978ae-40cb-4e11-9511-08dbf4e35135 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: mDdPMbmMSOcHYKEo7vGOnWxzTS++2BbXjrvRfBsk0qt5idOag21jauwdplWowwbKpxXqK/XliiEj+TG5jLpDvi7R/Y39wTbs+Om0SzuzunKHJwndo0aDKcAi8GtknFNi/a9xkA8yUR4kzmSYk1c7phyYU/OV0HGWUpGklwh6NzQQNnXQAvi9JvZAavM3tm1o5ZjLI5K7783a0hlo/UbCtBKyjy44zKrKdtUUvUF2nfjd+VvMgSWmzBwOj/cnOfZmAbT/mbgvrPptIRbYoqMB+CKh3L3JU3Mv2Ix+Dt/N7jerboZCt6g3F2f8zOiG7AF+nfWjb0Q/Lg2Y7Kwmlk+4fG2mEl8mZT9KzAG+AYlN8V4uh1PiF38YGlDz25s1fKwXr8Af+2tPgRI+f6Uj6EWSoeP+wfPJxxc7z7zYhtc/UWWW4HioLP2yjOBxnkNXk2hR8RcoVB44ukOoZX7lNuAqztwJBZ9wU87f8i8pNjWMZ31G3LFABwHXTSFBCcXRD2iHf/gTVAJk6lk7cnyps8Gg/D4y904497vuqvk8KBix1P7hJwEljeo9KFsqsBjPtaiTxqxvlAhZfFzCuvwbbxVO2vrT1TIIfKlGitSNh258TLBFfuRQmT5WJ7bqaNquYcJDGBT0srXA4c8+95gVQTj8Djo8VtWeJRXG1mK1XdyXYNqsJkv58pX3JMmBsVugp4lIBmBbXkB0FlC6U71w+adN90t9ie32BpXixUFWJ3nBdasHxw4ZDGsRxX0eJjy7EZy2nP0rGGsFu/HqHIpgAF61kI+RglKeggm3CgL0xxuJ+ffEbhV7oCYHKTqTpLgtlSsMJfpQG3veTrk+9DoAldClDT1K9ux3ecK7RCt/k710UbKZaxDrLNevXFMTnyDOPDD3+l/G9fMKy6HrAqM4FtclF93b1Jb1eTK+MFD1ShTpurHMQwuHcfrfQ9H2J0CpgTVpcZ2MTTskP/Rg5uN0xVI7Q4P4PfsrC9029pWNc8WPR0dDkfg+vyhHsHZ4ZS+scmvj7Vhw3N19/b6bIEKMJOHZfBrMf9/n0Vmvan7A2aPYPDM7rdap3BzhdN7oum6KElqHeQA+4i4KeXoVKLkoJms4EMfYpjYutbRPoMc1cuxEAM2ZnjpJiSvzbuvwxbydVTHfxd2k/YudDUBaG1XgIEE7qYzKAudvIc/nIKmqNhoW5TLaj0z/tE/LdG6439W4r4EQNqsrnzi8F+SRxwbUad3zw5UwBsBpq170yS8x42nmSDu99sR9UV9DCbbn1P/B4tvxViIfwtNGFgwMDgl8flF360sPtNyB9GGuKu8I460tuyRuWXSt6+ELP/g66MpEUbNE3LOLdOCuOWdlEjNsJi+TyPyGxpPSyIQEqiLUX4GfhtcJfT9LUJltxKkxmK6m6p1MQE53/EBHJicqAKVLZawtNZIIQtWiV2SJPmSd4O2YOkiv7r0jAEzPuuNqL8Dl9WTdEgr6ckF41R5KMZMlJvDBXWxVVj4mnjkBDyOHdmp6x9X5GRGeXG9NztHe1/haxJir4OMAo3zWE2BWvZTwtgOWeCpSn515uDveIxsfjxmpGk4RHuGWkwQBl9oX2Vj0jPQE X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: c32978ae-40cb-4e11-9511-08dbf4e35135 X-MS-Exchange-CrossTenant-AuthSource: AM6PR04MB4838.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Dec 2023 16:08:56.2185 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 8t3aJfPrbmn8FfH2xo75WxxLD+Lo+LVezPPFLy1vSyc30UmkxqZu/8Mcjp84cL76cntvldwz5zIenhRl37f0Bw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBBPR04MB8057 Add suspend/resume support for Layerscape LS1021a. In the suspend path, PME_Turn_Off message is sent to the endpoint to transition the link to L2/L3_Ready state. In this SoC, there is no way to check if the controller has received the PME_To_Ack from the endpoint or not. So to be on the safer side, the driver just waits for PCIE_PME_TO_L2_TIMEOUT_US before asserting the SoC specific PMXMTTURNOFF bit to complete the PME_Turn_Off handshake. Then the link would enter L2/L3 state depending on the VAUX supply. In the resume path, the link is brought back from L2 to L0 by doing a software reset. Acked-by: Roy Zang Reviewed-by: Manivannan Sadhasivam Signed-off-by: Frank Li --- Notes: Change from v5 to v6 - remove reduntant pci->pp.ops = &ls_pcie_host_ops; Change from v4 to v5 - update comit message - remove a empty line - use comments /* Reset the PEX wrapper to bring the link out of L2 */ - pci->pp.ops = pcie->drvdata->ops, ls_pcie_host_ops to the "ops" member of layerscape_drvdata. - don't set pcie->scfg = NULL at error path Change from v3 to v4 - update commit message. - it is reset a glue logic part for PCI controller. - use regmap_write_bits() to reduce code change. Change from v2 to v3 - update according to mani's feedback change from v1 to v2 - change subject 'a' to 'A' drivers/pci/controller/dwc/pci-layerscape.c | 83 ++++++++++++++++++++- 1 file changed, 80 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-layerscape.c b/drivers/pci/controller/dwc/pci-layerscape.c index aea89926bcc4f..711563777aeba 100644 --- a/drivers/pci/controller/dwc/pci-layerscape.c +++ b/drivers/pci/controller/dwc/pci-layerscape.c @@ -35,11 +35,19 @@ #define PF_MCR_PTOMR BIT(0) #define PF_MCR_EXL2S BIT(1) +/* LS1021A PEXn PM Write Control Register */ +#define SCFG_PEXPMWRCR(idx) (0x5c + (idx) * 0x64) +#define PMXMTTURNOFF BIT(31) +#define SCFG_PEXSFTRSTCR 0x190 +#define PEXSR(idx) BIT(idx) + #define PCIE_IATU_NUM 6 struct ls_pcie_drvdata { const u32 pf_off; + const struct dw_pcie_host_ops *ops; int (*exit_from_l2)(struct dw_pcie_rp *pp); + bool scfg_support; bool pm_support; }; @@ -47,6 +55,8 @@ struct ls_pcie { struct dw_pcie *pci; const struct ls_pcie_drvdata *drvdata; void __iomem *pf_base; + struct regmap *scfg; + int index; bool big_endian; }; @@ -171,18 +181,70 @@ static int ls_pcie_host_init(struct dw_pcie_rp *pp) return 0; } +static void scfg_pcie_send_turnoff_msg(struct regmap *scfg, u32 reg, u32 mask) +{ + /* Send PME_Turn_Off message */ + regmap_write_bits(scfg, reg, mask, mask); + + /* + * There is no specific register to check for PME_To_Ack from endpoint. + * So on the safe side, wait for PCIE_PME_TO_L2_TIMEOUT_US. + */ + mdelay(PCIE_PME_TO_L2_TIMEOUT_US/1000); + + /* + * Layerscape hardware reference manual recommends clearing the PMXMTTURNOFF bit + * to complete the PME_Turn_Off handshake. + */ + regmap_write_bits(scfg, reg, mask, 0); +} + +static void ls1021a_pcie_send_turnoff_msg(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct ls_pcie *pcie = to_ls_pcie(pci); + + scfg_pcie_send_turnoff_msg(pcie->scfg, SCFG_PEXPMWRCR(pcie->index), PMXMTTURNOFF); +} + +static int scfg_pcie_exit_from_l2(struct regmap *scfg, u32 reg, u32 mask) +{ + /* Reset the PEX wrapper to bring the link out of L2 */ + regmap_write_bits(scfg, reg, mask, mask); + regmap_write_bits(scfg, reg, mask, 0); + + return 0; +} + +static int ls1021a_pcie_exit_from_l2(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct ls_pcie *pcie = to_ls_pcie(pci); + + return scfg_pcie_exit_from_l2(pcie->scfg, SCFG_PEXSFTRSTCR, PEXSR(pcie->index)); +} + static const struct dw_pcie_host_ops ls_pcie_host_ops = { .host_init = ls_pcie_host_init, .pme_turn_off = ls_pcie_send_turnoff_msg, }; +static const struct dw_pcie_host_ops ls1021a_pcie_host_ops = { + .host_init = ls_pcie_host_init, + .pme_turn_off = ls1021a_pcie_send_turnoff_msg, +}; + static const struct ls_pcie_drvdata ls1021a_drvdata = { - .pm_support = false, + .pm_support = true, + .scfg_support = true, + .ops = &ls1021a_pcie_host_ops, + .exit_from_l2 = ls1021a_pcie_exit_from_l2, }; static const struct ls_pcie_drvdata layerscape_drvdata = { .pf_off = 0xc0000, .pm_support = true, + .ops = &ls_pcie_host_ops, .exit_from_l2 = ls_pcie_exit_from_l2, }; @@ -205,6 +267,8 @@ static int ls_pcie_probe(struct platform_device *pdev) struct dw_pcie *pci; struct ls_pcie *pcie; struct resource *dbi_base; + u32 index[2]; + int ret; pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); if (!pcie) @@ -217,9 +281,8 @@ static int ls_pcie_probe(struct platform_device *pdev) pcie->drvdata = of_device_get_match_data(dev); pci->dev = dev; - pci->pp.ops = &ls_pcie_host_ops; - pcie->pci = pci; + pci->pp.ops = pcie->drvdata->ops; dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs"); pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base); @@ -230,6 +293,20 @@ static int ls_pcie_probe(struct platform_device *pdev) pcie->pf_base = pci->dbi_base + pcie->drvdata->pf_off; + if (pcie->drvdata->scfg_support) { + pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node, "fsl,pcie-scfg"); + if (IS_ERR(pcie->scfg)) { + dev_err(dev, "No syscfg phandle specified\n"); + return PTR_ERR(pcie->scfg); + } + + ret = of_property_read_u32_array(dev->of_node, "fsl,pcie-scfg", index, 2); + if (ret) + return ret; + + pcie->index = index[1]; + } + if (!ls_pcie_is_bridge(pcie)) return -ENODEV; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: wMvVQSWTE8yBqx7NUabTWVcF7qsXGDSU8fTv2Q3JDIZMl3+zNdNPM/rBnehH080eGFtV3jI3PgqIoAbelTfoK2f7jeP0Sr3dlNrhqNM0DtfjwjxIbdGwBEUAqoN7ikSWijLBtCg55i5rzlmS4SEOfXgCQq5lmsz4VVt8kJaTRJScl3uTLa16DjxwHV9YxR0/WBwsv35yEe8SKGug4QDcm6ULFjX1He0CAe0Z5s14sBrotbpeF1RCqFd7oaSonTDnIOpT2x+F4xtzUT6rYjm6dS8PDybiRbjLGiQTRqDyYNg5Ld/Y3+fdSlQFVf/g/S3fQPmw6CTy4MF3NPPxQPuBY5Otb9JscGUDSdXzl8gDrc15WqUFU6sRJXx2kOLEYCQZnIygdxr0fvtN4LLxmFNvwADIbtowZTQrU7hqMdq+xGan49H/PX5hsh9HO0tiqLJp4n8/S+FDdUbbLgGKVspJeM2j4tJ+5Q4K0+ckHtUA9bQkn+jsBNv+9TUa+d1wbBMNOzGgAiQe/FFirxdo8LIYYW5ceOrweEeFnOKg4itSZBo0BwZCyhMvRqM1tKlQsWSXb3BtWPk7jfPM5Tn+oD9v9HLOogCvwjJ0Qfssbpm0dNlf/s/ISQgRM29fdTLMpdA9Lr468qls7EgUrGjwVW6kqD8gCM1576vDBNfxBvh0aB25X1525VVZzaMwkD5hvDBsZP5+TdsZ9nHAYJDT9BLllBtP3CcFUsAIWu66ImYpZB8jLMprVikawkUcV0EzamskNmFecNVssMDQ0OoMRl+3/8SF3vY2zMwoGAenVg6xHE+AQW4i9yFBLyparu1Wio3jTMNhgqdMtDdC/5NGj59fI0RtxLWSnUa8FezjIGdGpr7vmCa8P7rqeZGvwvfpWkdYtkqfOoPtpv04RrQHEQo/i5uGjeMIpgTYc7QKEtaf4LJTxR/eGKrvnw/GbpLHl25JJZCnV6ydAVMFeOq1IVb4czB9gkQkV0D3i1hxWunwlJyJH5ZsW9BH6RR+bLRRNyIOHIe3DleQtwy6F9jgKnFShI/i9cBiNkrxni+8sGl0LCudwPSy6yyLZTBlkHEVSoxIUN3jXYJNTzZCJCiueelxJcaPVxxSgGLt98PeA7zRI72KJBZrmsKGe9iX7PqomZk6dRn4GynWV0nifWlvdTHMux4eUygNhh07K5UE3q3srpmlSv8yQCRjnudlGSfyYKHqvD3Fs5OcyuqIBVUfrT7f/np+qibebED7kTyTUWiJjrxgdbZc2SXopDJBx6y7SQoJM+PMvw3/pvwPdaiNH/wUTE0dak/SuNgBZffAA8HOG3F8mysy+qJyjR/MAFK9tLiDEslvEBiUVlwkQlHQ2iXNW/XTcUoEPZcaSNLLEF6VhrP/GVPPaRUyPNoL4c51Q+g8Eoj4nTwBlSGPip0k8bNX8nVjycYiLMyPKW00kdkHqW5DsWiCPlyarTZ/gMVmV2vHTo5Kxng2EighlTvETH/tKXe95QoeZeoHSqSy7Gp3osJ/8nFiiV6mNt6vl4QTgbp232r52/60titDPmRIGgVwA8SPO6/P1hHimWFqeonG6yv6gB7VMZOyPD+mxRfqUnMp X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: f52cf39d-ed16-4188-b624-08dbf4e3535e X-MS-Exchange-CrossTenant-AuthSource: AM6PR04MB4838.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Dec 2023 16:08:59.9161 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: BAIpsGIz1lTj94lUaMKDU+5yJMu0LeW937R/iULioVCB0HSyVhAIj84ixYDwuEpfv92Ln5DedB8LhKNGC9GWNg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBBPR04MB8057 'pf' and 'lut' is just difference name in difference chips, but basic it is a MMIO base address plus an offset. Rename it to avoid duplicate pf_* and lut_* in driver. Reviewed-by: Manivannan Sadhasivam Acked-by: Roy Zang Signed-off-by: Frank Li --- Notes: pf_lut is better than pf_* or lut* because some chip use 'pf', some chip use 'lut'. Change from v5 to v6 move to previous patch -> - .ops = &ls_pcie_host_ops; > + .ops = &ls_pcie_host_ops, Change from v4 to v5 - rename layerscape-ep code also change from v1 to v4 - new patch at v3 .../pci/controller/dwc/pci-layerscape-ep.c | 16 ++++----- drivers/pci/controller/dwc/pci-layerscape.c | 34 +++++++++---------- 2 files changed, 25 insertions(+), 25 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c index 3d3c50ef4b6ff..2ca339f938a86 100644 --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c @@ -49,7 +49,7 @@ struct ls_pcie_ep { bool big_endian; }; -static u32 ls_lut_readl(struct ls_pcie_ep *pcie, u32 offset) +static u32 ls_pcie_pf_lut_readl(struct ls_pcie_ep *pcie, u32 offset) { struct dw_pcie *pci = pcie->pci; @@ -59,7 +59,7 @@ static u32 ls_lut_readl(struct ls_pcie_ep *pcie, u32 offset) return ioread32(pci->dbi_base + offset); } -static void ls_lut_writel(struct ls_pcie_ep *pcie, u32 offset, u32 value) +static void ls_pcie_pf_lut_writel(struct ls_pcie_ep *pcie, u32 offset, u32 value) { struct dw_pcie *pci = pcie->pci; @@ -76,8 +76,8 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id) u32 val, cfg; u8 offset; - val = ls_lut_readl(pcie, PEX_PF0_PME_MES_DR); - ls_lut_writel(pcie, PEX_PF0_PME_MES_DR, val); + val = ls_pcie_pf_lut_readl(pcie, PEX_PF0_PME_MES_DR); + ls_pcie_pf_lut_writel(pcie, PEX_PF0_PME_MES_DR, val); if (!val) return IRQ_NONE; @@ -96,9 +96,9 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id) dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, pcie->lnkcap); dw_pcie_dbi_ro_wr_dis(pci); - cfg = ls_lut_readl(pcie, PEX_PF0_CONFIG); + cfg = ls_pcie_pf_lut_readl(pcie, PEX_PF0_CONFIG); cfg |= PEX_PF0_CFG_READY; - ls_lut_writel(pcie, PEX_PF0_CONFIG, cfg); + ls_pcie_pf_lut_writel(pcie, PEX_PF0_CONFIG, cfg); dw_pcie_ep_linkup(&pci->ep); dev_dbg(pci->dev, "Link up\n"); @@ -130,10 +130,10 @@ static int ls_pcie_ep_interrupt_init(struct ls_pcie_ep *pcie, } /* Enable interrupts */ - val = ls_lut_readl(pcie, PEX_PF0_PME_MES_IER); + val = ls_pcie_pf_lut_readl(pcie, PEX_PF0_PME_MES_IER); val |= PEX_PF0_PME_MES_IER_LDDIE | PEX_PF0_PME_MES_IER_HRDIE | PEX_PF0_PME_MES_IER_LUDIE; - ls_lut_writel(pcie, PEX_PF0_PME_MES_IER, val); + ls_pcie_pf_lut_writel(pcie, PEX_PF0_PME_MES_IER, val); return 0; } diff --git a/drivers/pci/controller/dwc/pci-layerscape.c b/drivers/pci/controller/dwc/pci-layerscape.c index 711563777aeba..f3dfb70066fb7 100644 --- a/drivers/pci/controller/dwc/pci-layerscape.c +++ b/drivers/pci/controller/dwc/pci-layerscape.c @@ -44,7 +44,7 @@ #define PCIE_IATU_NUM 6 struct ls_pcie_drvdata { - const u32 pf_off; + const u32 pf_lut_off; const struct dw_pcie_host_ops *ops; int (*exit_from_l2)(struct dw_pcie_rp *pp); bool scfg_support; @@ -54,13 +54,13 @@ struct ls_pcie_drvdata { struct ls_pcie { struct dw_pcie *pci; const struct ls_pcie_drvdata *drvdata; - void __iomem *pf_base; + void __iomem *pf_lut_base; struct regmap *scfg; int index; bool big_endian; }; -#define ls_pcie_pf_readl_addr(addr) ls_pcie_pf_readl(pcie, addr) +#define ls_pcie_pf_lut_readl_addr(addr) ls_pcie_pf_lut_readl(pcie, addr) #define to_ls_pcie(x) dev_get_drvdata((x)->dev) static bool ls_pcie_is_bridge(struct ls_pcie *pcie) @@ -101,20 +101,20 @@ static void ls_pcie_fix_error_response(struct ls_pcie *pcie) iowrite32(PCIE_ABSERR_SETTING, pci->dbi_base + PCIE_ABSERR); } -static u32 ls_pcie_pf_readl(struct ls_pcie *pcie, u32 off) +static u32 ls_pcie_pf_lut_readl(struct ls_pcie *pcie, u32 off) { if (pcie->big_endian) - return ioread32be(pcie->pf_base + off); + return ioread32be(pcie->pf_lut_base + off); - return ioread32(pcie->pf_base + off); + return ioread32(pcie->pf_lut_base + off); } -static void ls_pcie_pf_writel(struct ls_pcie *pcie, u32 off, u32 val) +static void ls_pcie_pf_lut_writel(struct ls_pcie *pcie, u32 off, u32 val) { if (pcie->big_endian) - iowrite32be(val, pcie->pf_base + off); + iowrite32be(val, pcie->pf_lut_base + off); else - iowrite32(val, pcie->pf_base + off); + iowrite32(val, pcie->pf_lut_base + off); } static void ls_pcie_send_turnoff_msg(struct dw_pcie_rp *pp) @@ -124,11 +124,11 @@ static void ls_pcie_send_turnoff_msg(struct dw_pcie_rp *pp) u32 val; int ret; - val = ls_pcie_pf_readl(pcie, LS_PCIE_PF_MCR); + val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_PF_MCR); val |= PF_MCR_PTOMR; - ls_pcie_pf_writel(pcie, LS_PCIE_PF_MCR, val); + ls_pcie_pf_lut_writel(pcie, LS_PCIE_PF_MCR, val); - ret = readx_poll_timeout(ls_pcie_pf_readl_addr, LS_PCIE_PF_MCR, + ret = readx_poll_timeout(ls_pcie_pf_lut_readl_addr, LS_PCIE_PF_MCR, val, !(val & PF_MCR_PTOMR), PCIE_PME_TO_L2_TIMEOUT_US/10, PCIE_PME_TO_L2_TIMEOUT_US); @@ -147,15 +147,15 @@ static int ls_pcie_exit_from_l2(struct dw_pcie_rp *pp) * Set PF_MCR_EXL2S bit in LS_PCIE_PF_MCR register for the link * to exit L2 state. */ - val = ls_pcie_pf_readl(pcie, LS_PCIE_PF_MCR); + val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_PF_MCR); val |= PF_MCR_EXL2S; - ls_pcie_pf_writel(pcie, LS_PCIE_PF_MCR, val); + ls_pcie_pf_lut_writel(pcie, LS_PCIE_PF_MCR, val); /* * L2 exit timeout of 10ms is not defined in the specifications, * it was chosen based on empirical observations. */ - ret = readx_poll_timeout(ls_pcie_pf_readl_addr, LS_PCIE_PF_MCR, + ret = readx_poll_timeout(ls_pcie_pf_lut_readl_addr, LS_PCIE_PF_MCR, val, !(val & PF_MCR_EXL2S), 1000, 10000); @@ -242,7 +242,7 @@ static const struct ls_pcie_drvdata ls1021a_drvdata = { }; static const struct ls_pcie_drvdata layerscape_drvdata = { - .pf_off = 0xc0000, + .pf_lut_off = 0xc0000, .pm_support = true, .ops = &ls_pcie_host_ops, .exit_from_l2 = ls_pcie_exit_from_l2, @@ -291,7 +291,7 @@ static int ls_pcie_probe(struct platform_device *pdev) pcie->big_endian = of_property_read_bool(dev->of_node, "big-endian"); - pcie->pf_base = pci->dbi_base + pcie->drvdata->pf_off; + pcie->pf_lut_base = pci->dbi_base + pcie->drvdata->pf_lut_off; if (pcie->drvdata->scfg_support) { pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node, "fsl,pcie-scfg"); From patchwork Mon Dec 4 16:08:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 13478738 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=nxp.com header.i=@nxp.com header.b="PAkSx8ec" Received: from EUR02-AM0-obe.outbound.protection.outlook.com (mail-am0eur02on2080.outbound.protection.outlook.com [40.107.247.80]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1E614106; Mon, 4 Dec 2023 08:09:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=K1LswuWNSbw0GnM4DGZ9h+gKTzFA2398BAcR0njB6i6MSl0jmKC7CJDa3EspBEZzoY8YMVUvCp7vYh9njaM34M0RagwgtRlaJfz2446yQiax+Q/W8F0/7KdPPk3dXGvcscOOGN4r39kM9SxasAfP3xvvw6JA1x9WZMqD2xH+tysrGOW5aQezzNjMsGiqu3NR3L8/wURcyQoSu8B+H0KbivLkgvMgx1vO1dI/xxkhwxCwVXBhU140iZAtPhY8h4ttdZW8aWR5bHHUdPc+2Gu1KSM98Ga9DRKrHZ5ARcOZRJ5fYTNv+sJdwSwFPaTczEKBQs2pa5w3RfRY3w5hQWZxKw== ARC-Message-Signature: i=1; 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b=PAkSx8ecZHqqW4FxWgl5rlKhc8w5y/q9nmvtHtApt3bP67frT3i9n1kgsp+Fcr2IH1DyJFxeC3kFnxxXE2JT4O3TVIx7s7kwGYCMky5mE/tBQBuTNJ+0zWIN2CWODWWvSbMXIejnn1OmJYwX4/y/sgd+/2JAymVrnqHZma6d+Jk= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) by DBBPR04MB8057.eurprd04.prod.outlook.com (2603:10a6:10:1f1::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7068.22; Mon, 4 Dec 2023 16:09:03 +0000 Received: from AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::95f5:5118:258f:ee40]) by AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::95f5:5118:258f:ee40%6]) with mapi id 15.20.7068.022; Mon, 4 Dec 2023 16:09:03 +0000 From: Frank Li To: manivannan.sadhasivam@linaro.org Cc: Frank.Li@nxp.com, bhelgaas@google.com, imx@lists.linux.dev, kw@linux.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, lpieralisi@kernel.org, minghuan.Lian@nxp.com, mingkai.hu@nxp.com, robh@kernel.org, roy.zang@nxp.com Subject: [PATCH v6 4/4] PCI: layerscape: Add suspend/resume for ls1043a Date: Mon, 4 Dec 2023 11:08:29 -0500 Message-Id: <20231204160829.2498703-5-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231204160829.2498703-1-Frank.Li@nxp.com> References: <20231204160829.2498703-1-Frank.Li@nxp.com> X-ClientProxiedBy: BYAPR21CA0027.namprd21.prod.outlook.com (2603:10b6:a03:114::37) To AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM6PR04MB4838:EE_|DBBPR04MB8057:EE_ X-MS-Office365-Filtering-Correlation-Id: c9d7ed75-10f3-475c-c2a7-08dbf4e35593 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: wazukdBV3FKFMAbcBiDbf33+ZJ/ToHfcd5dBck4iULRsBYSFUVAaWo5ehD0+lhwLD09mZSLQwIQUL8kpPxG9yfs1wy+6Q3izdI+M7Ed681uWMYX3Csso9+zPo056DY/sxkz68bH5t7W07XVwzAPJWZHtjQ1Ivw6e9oLZOlCiSVZZtpUPGFVJJcrkzwhZGwtQiMWVLiZJQji7IaDrNVxvjaRoaY844sm2jHB+22xY4pzBmNDUm69WeUokuSJnxM4d7Ac/11LP/7K8rZqMQwm7+OaOxOHuSEMTAfyY/tvJQNdMYFZHL+g5GIV2UNyo9M+UYpQXfXl9/okLJzY5lF3ImbBThdTX8u9oFWx4A//VGP0xZiBdR+OQfW4lY22QbfYLP8cbh3e8sqmUNouLHPsSMzm+dFwHD1d3CZKrVnoYXyVOnH9UaiPBTeYfyBtQLXD9sMLBA/Uc7wtMA/n8qiZ7pycTM9GuDCn/l6Q2Um1yRu8+gFn+GwBukx54c137fB9TNmt9FJSVieUPPlvg3/8L63OOXNh0TCzuOL10m98MrTp+4iQOQmRy6H3nuWtDkfzx9AzF65YdFCLNhmFrVDyvpxR8n46HNx9w9wIKEeI4aDjjj5JVzbsuun9f76k1EpL1SaxIksRmL/jg9yttWvo95P2AvXfqbUoQ502bxh5Dh8TQbmKrpXPy+lO5gumhh3cwxyf8OkdpEooikfNcOKTi2vFD57Rfu2LGqPiVi8MDo51nV44/7YMgIB8FvSD/Wk7tSmKATilp+mXasZOGQJXiu8E4zoVzTOLaVqeWKpgdqDb138jE0EIU9Fj8O6pvpT3+qDLBt2fRG94TA3RVllZHOC9BtWZGDqU/lUOpqpufvVPmBO6cosqZcGYhWrdmAjhpF9o5WkpRtYGjzVRI0p/SfiVeFMh2whpcjec615b7jEce273CMWy3hKlqgWkEIsydlY2JBtCM0lj0Dg5FYfH5YijZhbkM3VJffl2MQtk3x9JT2OTCEYq0TTd2YX8urKOnkBG5Yvcl/O2IutzNCtZf3r/K7sNdYAGTmPFNlhIVbNuKxJRAyW/HT9h7JDI/LnAs9/ey9fF/8H2ZqKdEYZOlUEuly3106SgGxfBndEAqvena05H/z3XKEAnmVMMfDmldcjJpsDUY/1UZuL/mnDAdtrlNb8TwdsDccHY2pOrX/B5Ons9oyGkaS952+yfu57uEXz+bchMNE6RhyVkjV0ElVgRtJkd3WinGz5tFvBfDXt7OOZBUXKFqpW2Ve6Vvdh6bUdgELtgZ18/QiZQCIz6tLwKVSGitu9iAP4iABE8RxTHi04G5I+bTaqYQIW2JiLiZHkszc+rpZ7YeJI6AlfChF3fi5D81bXqrDlzJI6OTJGpaPzfUJ5WE3V1ExBOJ+9SvBRSS0hSjgdWOFQSwuEm2EMaZoyHsfkKFmeS+kl/opOq1qBYHSJ/W6hI3yjqtldJbhat8cyy6pBvtMREWnHn3cJYfC1vDACUoMUdDWvR/EamoefD5/KfkLACdQwkA2yg4ZfhFHqWifs072eXUlI/n5dVVB0Uc14g5H/2F9kuEjDUJ6SSAGNw3/66K7M1xWayb X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: c9d7ed75-10f3-475c-c2a7-08dbf4e35593 X-MS-Exchange-CrossTenant-AuthSource: AM6PR04MB4838.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Dec 2023 16:09:03.5363 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: warSZXDLyiFS6+GMyL6cXJVfI9dplmdgqUFKMCbgiXF0kVDPGOJE21Jwusp0hS1UNGWcweShiAl3HuXgciEz9g== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBBPR04MB8057 Add suspend/resume support for Layerscape LS1043a. In the suspend path, PME_Turn_Off message is sent to the endpoint to transition the link to L2/L3_Ready state. In this SoC, there is no way to check if the controller has received the PME_To_Ack from the endpoint or not. So to be on the safer side, the driver just waits for PCIE_PME_TO_L2_TIMEOUT_US before asserting the SoC specific PMXMTTURNOFF bit to complete the PME_Turn_Off handshake. Then the link would enter L2/L3 state depending on the VAUX supply. In the resume path, the link is brought back from L2 to L0 by doing a software reset. Acked-by: Roy Zang Reviewed-by: Manivannan Sadhasivam Signed-off-by: Frank Li --- Notes: Chagne from v5 to v6 - none Change from v4 to v5 - update commit message - use comments /* Reset the PEX wrapper to bring the link out of L2 */ Change from v3 to v4 - Call scfg_pcie_send_turnoff_msg() shared with ls1021a - update commit message Change from v2 to v3 - Remove ls_pcie_lut_readl(writel) function Change from v1 to v2 - Update subject 'a' to 'A' drivers/pci/controller/dwc/pci-layerscape.c | 63 ++++++++++++++++++++- 1 file changed, 62 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pci-layerscape.c b/drivers/pci/controller/dwc/pci-layerscape.c index f3dfb70066fb7..7cdada200de7e 100644 --- a/drivers/pci/controller/dwc/pci-layerscape.c +++ b/drivers/pci/controller/dwc/pci-layerscape.c @@ -41,6 +41,15 @@ #define SCFG_PEXSFTRSTCR 0x190 #define PEXSR(idx) BIT(idx) +/* LS1043A PEX PME control register */ +#define SCFG_PEXPMECR 0x144 +#define PEXPME(idx) BIT(31 - (idx) * 4) + +/* LS1043A PEX LUT debug register */ +#define LS_PCIE_LDBG 0x7fc +#define LDBG_SR BIT(30) +#define LDBG_WE BIT(31) + #define PCIE_IATU_NUM 6 struct ls_pcie_drvdata { @@ -224,6 +233,45 @@ static int ls1021a_pcie_exit_from_l2(struct dw_pcie_rp *pp) return scfg_pcie_exit_from_l2(pcie->scfg, SCFG_PEXSFTRSTCR, PEXSR(pcie->index)); } +static void ls1043a_pcie_send_turnoff_msg(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct ls_pcie *pcie = to_ls_pcie(pci); + + scfg_pcie_send_turnoff_msg(pcie->scfg, SCFG_PEXPMECR, PEXPME(pcie->index)); +} + +static int ls1043a_pcie_exit_from_l2(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct ls_pcie *pcie = to_ls_pcie(pci); + u32 val; + + /* + * Reset the PEX wrapper to bring the link out of L2. + * LDBG_WE: allows the user to have write access to the PEXDBG[SR] for both setting and + * clearing the soft reset on the PEX module. + * LDBG_SR: When SR is set to 1, the PEX module enters soft reset. + */ + val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_LDBG); + val |= LDBG_WE; + ls_pcie_pf_lut_writel(pcie, LS_PCIE_LDBG, val); + + val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_LDBG); + val |= LDBG_SR; + ls_pcie_pf_lut_writel(pcie, LS_PCIE_LDBG, val); + + val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_LDBG); + val &= ~LDBG_SR; + ls_pcie_pf_lut_writel(pcie, LS_PCIE_LDBG, val); + + val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_LDBG); + val &= ~LDBG_WE; + ls_pcie_pf_lut_writel(pcie, LS_PCIE_LDBG, val); + + return 0; +} + static const struct dw_pcie_host_ops ls_pcie_host_ops = { .host_init = ls_pcie_host_init, .pme_turn_off = ls_pcie_send_turnoff_msg, @@ -241,6 +289,19 @@ static const struct ls_pcie_drvdata ls1021a_drvdata = { .exit_from_l2 = ls1021a_pcie_exit_from_l2, }; +static const struct dw_pcie_host_ops ls1043a_pcie_host_ops = { + .host_init = ls_pcie_host_init, + .pme_turn_off = ls1043a_pcie_send_turnoff_msg, +}; + +static const struct ls_pcie_drvdata ls1043a_drvdata = { + .pf_lut_off = 0x10000, + .pm_support = true, + .scfg_support = true, + .ops = &ls1043a_pcie_host_ops, + .exit_from_l2 = ls1043a_pcie_exit_from_l2, +}; + static const struct ls_pcie_drvdata layerscape_drvdata = { .pf_lut_off = 0xc0000, .pm_support = true, @@ -252,7 +313,7 @@ static const struct of_device_id ls_pcie_of_match[] = { { .compatible = "fsl,ls1012a-pcie", .data = &layerscape_drvdata }, { .compatible = "fsl,ls1021a-pcie", .data = &ls1021a_drvdata }, { .compatible = "fsl,ls1028a-pcie", .data = &layerscape_drvdata }, - { .compatible = "fsl,ls1043a-pcie", .data = &ls1021a_drvdata }, + { .compatible = "fsl,ls1043a-pcie", .data = &ls1043a_drvdata }, { .compatible = "fsl,ls1046a-pcie", .data = &layerscape_drvdata }, { .compatible = "fsl,ls2080a-pcie", .data = &layerscape_drvdata }, { .compatible = "fsl,ls2085a-pcie", .data = &layerscape_drvdata },