From patchwork Tue Dec 5 17:45:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13480515 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="WDBNWqql" Received: from mail-pl1-x632.google.com (mail-pl1-x632.google.com [IPv6:2607:f8b0:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EAA87122 for ; Tue, 5 Dec 2023 09:45:26 -0800 (PST) Received: by mail-pl1-x632.google.com with SMTP id d9443c01a7336-1d0b2752dc6so18722755ad.3 for ; Tue, 05 Dec 2023 09:45:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1701798326; x=1702403126; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Kw9lx7rfek+Fyxn9H19uerjKbw2z7hmkxzJlnytvErY=; b=WDBNWqql9NiU4jkiHD9ELllh/11U0sprAf8mGDETKohzMidA7U/9wHS5jqMN2P/jTD jpoizCzKx+aVuF3IfEwLj4JEMO76lH/TbraMr5Hm8c2oB0AmQczveHk3WGt3LUgEQED0 g1YHijGF96hbLH/8X+Ltj1FS3itYAzqS1colNkPujDTpNKzEQL50DFhpA8sSnnQLpGnH WINQ4Zcafg0Jk3WRpjLOaGN3k5TSzsS0cjrxeTkt8vaTBqiaZI9jplgeOMkBAIG9Jpby V2tAZ+IFShgxlFiMScfetBTwxgJBlyup8YCTJh443st8rTT7DA68mSEqU1uTznO1Ouro J5Ew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701798326; x=1702403126; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Kw9lx7rfek+Fyxn9H19uerjKbw2z7hmkxzJlnytvErY=; b=f+WAAxJbPR2ApcZTRV3vndy35Mx6M3WYnKZNhDN1IGHV6phUULtjPZOVziRTwtHOSq IUinrJXwpfmYzUyT94n4xFlQPRfD2HUdau7cT6KiUmcEp+Q/bhYTU8/gZPP+OkPeb+Xe gzRMk1IQ/SS7dI+Lr6ChjQav838Z7/lb7r+qD6hg5cSDmRuFQ20WNsJlxdPkIE1/pux9 +MjTTaRrMUwp6PbWNA23VUbioigxmUlLg484F8k46mWrmrKqTlaAm+LS/mGUnithMagR ZKOu6ys5ozaZEg1PqmTjyTAhoxmg/t1iPaRBavTaenSrQRYDkabDwrglBg0fC0DN7XEP 373w== X-Gm-Message-State: AOJu0Yy4w3G97Q48r/rV9pWRAGsROS/U+fNulIHJPLszLoEjq14MZIXE avRfrqss9u+nGEfMu+LLvbiX9eYP6xhtZqFLK8M= X-Google-Smtp-Source: AGHT+IF7Y/RolGBXnpDHkOsMt/rkm/fe03CCbMCd5KOY+xnFrO9TY+7df1EdMH6EfJJh7i6FHHqd2Q== X-Received: by 2002:a17:902:e804:b0:1d0:98db:6fd4 with SMTP id u4-20020a170902e80400b001d098db6fd4mr4578699plg.56.1701798326243; Tue, 05 Dec 2023 09:45:26 -0800 (PST) Received: from grind.. ([152.234.124.8]) by smtp.gmail.com with ESMTPSA id j20-20020a170902759400b001c74df14e6fsm10465705pll.284.2023.12.05.09.45.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Dec 2023 09:45:25 -0800 (PST) From: Daniel Henrique Barboza To: kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: anup@brainfault.org, atishp@atishpatra.org, palmer@dabbelt.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v3 1/3] RISC-V: KVM: set 'vlenb' in kvm_riscv_vcpu_alloc_vector_context() Date: Tue, 5 Dec 2023 14:45:07 -0300 Message-ID: <20231205174509.2238870-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231205174509.2238870-1-dbarboza@ventanamicro.com> References: <20231205174509.2238870-1-dbarboza@ventanamicro.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 'vlenb', added to riscv_v_ext_state by commit c35f3aa34509 ("RISC-V: vector: export VLENB csr in __sc_riscv_v_state"), isn't being initialized in guest_context. If we export 'vlenb' as a KVM CSR, something we want to do in the next patch, it'll always return 0. Set 'vlenb' to riscv_v_size/32. Signed-off-by: Daniel Henrique Barboza --- arch/riscv/kvm/vcpu_vector.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/kvm/vcpu_vector.c b/arch/riscv/kvm/vcpu_vector.c index b339a2682f25..530e49c588d6 100644 --- a/arch/riscv/kvm/vcpu_vector.c +++ b/arch/riscv/kvm/vcpu_vector.c @@ -76,6 +76,7 @@ int kvm_riscv_vcpu_alloc_vector_context(struct kvm_vcpu *vcpu, cntx->vector.datap = kmalloc(riscv_v_vsize, GFP_KERNEL); if (!cntx->vector.datap) return -ENOMEM; + cntx->vector.vlenb = riscv_v_vsize / 32; vcpu->arch.host_context.vector.datap = kzalloc(riscv_v_vsize, GFP_KERNEL); if (!vcpu->arch.host_context.vector.datap) From patchwork Tue Dec 5 17:45:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13480516 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="A+qQp/ju" Received: from mail-pl1-x62d.google.com (mail-pl1-x62d.google.com [IPv6:2607:f8b0:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 64F45122 for ; Tue, 5 Dec 2023 09:45:30 -0800 (PST) Received: by mail-pl1-x62d.google.com with SMTP id d9443c01a7336-1d0c94397c0so6193075ad.2 for ; Tue, 05 Dec 2023 09:45:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1701798330; x=1702403130; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xDmx5prnNC5GcsIkGu5R3qOSAEa8hCYanFPPTHn90qw=; b=A+qQp/jusDzJjFMMnN5+QTKEgABCTB+AYukhP4UK0fBkRFnqwg/XWQ4WZgHH7r7N10 ifLnmqc5kB3/JcrvxOfbsZs4V8ASZpyrPJDeSbv1N+dmGd48OUlKTsYNZL+IeiUaumUF M+v4a+AB8nqkA9xdhJ6alBzmGI0Pw6FojG8FzvEehY9OnwHb417IRm9C7+nt1TKx89CG O/C0ITvitesZOKoJXjqnHc04Aye6Mcd/8Q43JgvaLJ3NZZeAN0BEmXuyM3CUD92rgGst wV0uPP7CfGpvnzLj0h+M/xfWb/dXruoeoesxRbYIsAe4/I3BYnamsosrLknaEDdX4P1q 5TNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701798330; x=1702403130; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xDmx5prnNC5GcsIkGu5R3qOSAEa8hCYanFPPTHn90qw=; b=Ie4NjY4K7dHC1f8iojpzSunIgxJwAwPf2+JnbHliJjNByFFN82x7GSD6wypaLPsesG bvOyB0WXGtvEqE2OhH2MSwii/u/GoFRAJ4RuAq5F2Fw9u0MGS74NvdSuT8RNDdHjXrkk VElSIZsS99f7Q1Mfy8YFi5XXsvCc4IHGNWznlGFrBFlkdeSH4wxaYpsRPqV22CY1aBRk a9E9wiwb4zq3wjQ5P88/OcGS9mDOXp1d6hqZlNiUNVAZiQwEDgw8FuBU8sBi7slv/syy 1hUw/o0bx68o/aZevts0Q4oSmc5j4SHbo+aGmsegi7/v25gkqauIYa3bfGIpejwsMAFo sVvQ== X-Gm-Message-State: AOJu0Yxf1OUqg6VPXtdBp9hQt+YBQKdkE/LZO6ciaXHMKKwbLfrHA8D+ H62n8PkZPKj/aSWurUYXYe1xOg== X-Google-Smtp-Source: AGHT+IF1UZLtbstXiLGAqb3dZPBrPK0Kg5I3E3SNIV6kA8JjlJ2QhfhiGUU2Udk2N9DtQEvBJyDFVw== X-Received: by 2002:a17:902:748c:b0:1d0:b033:4a98 with SMTP id h12-20020a170902748c00b001d0b0334a98mr2747236pll.17.1701798329723; Tue, 05 Dec 2023 09:45:29 -0800 (PST) Received: from grind.. ([152.234.124.8]) by smtp.gmail.com with ESMTPSA id j20-20020a170902759400b001c74df14e6fsm10465705pll.284.2023.12.05.09.45.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Dec 2023 09:45:29 -0800 (PST) From: Daniel Henrique Barboza To: kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: anup@brainfault.org, atishp@atishpatra.org, palmer@dabbelt.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v3 2/3] RISC-V: KVM: add 'vlenb' Vector CSR Date: Tue, 5 Dec 2023 14:45:08 -0300 Message-ID: <20231205174509.2238870-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231205174509.2238870-1-dbarboza@ventanamicro.com> References: <20231205174509.2238870-1-dbarboza@ventanamicro.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Userspace requires 'vlenb' to be able to encode it in reg ID. Otherwise it is not possible to retrieve any vector reg since we're returning EINVAL if reg_size isn't vlenb (see kvm_riscv_vcpu_vreg_addr()). Signed-off-by: Daniel Henrique Barboza --- arch/riscv/kvm/vcpu_vector.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/riscv/kvm/vcpu_vector.c b/arch/riscv/kvm/vcpu_vector.c index 530e49c588d6..d92d1348045c 100644 --- a/arch/riscv/kvm/vcpu_vector.c +++ b/arch/riscv/kvm/vcpu_vector.c @@ -116,6 +116,9 @@ static int kvm_riscv_vcpu_vreg_addr(struct kvm_vcpu *vcpu, case KVM_REG_RISCV_VECTOR_CSR_REG(vcsr): *reg_addr = &cntx->vector.vcsr; break; + case KVM_REG_RISCV_VECTOR_CSR_REG(vlenb): + *reg_addr = &cntx->vector.vlenb; + break; case KVM_REG_RISCV_VECTOR_CSR_REG(datap): default: return -ENOENT; @@ -174,6 +177,18 @@ int kvm_riscv_vcpu_set_reg_vector(struct kvm_vcpu *vcpu, if (!riscv_isa_extension_available(isa, v)) return -ENOENT; + if (reg_num == KVM_REG_RISCV_VECTOR_CSR_REG(vlenb)) { + struct kvm_cpu_context *cntx = &vcpu->arch.guest_context; + unsigned long reg_val; + + if (copy_from_user(®_val, uaddr, reg_size)) + return -EFAULT; + if (reg_val != cntx->vector.vlenb) + return -EINVAL; + + return 0; + } + rc = kvm_riscv_vcpu_vreg_addr(vcpu, reg_num, reg_size, ®_addr); if (rc) return rc; From patchwork Tue Dec 5 17:45:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13480517 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="aqS9wvDu" Received: from mail-pl1-x62d.google.com (mail-pl1-x62d.google.com [IPv6:2607:f8b0:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D1E22122 for ; Tue, 5 Dec 2023 09:45:33 -0800 (PST) Received: by mail-pl1-x62d.google.com with SMTP id d9443c01a7336-1d08a924fcfso25350485ad.2 for ; Tue, 05 Dec 2023 09:45:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1701798333; x=1702403133; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Xh660VR+cynL5ByMmnyvYALQkVg9X3nzQmC84j+D7MQ=; b=aqS9wvDuiFhyqcSWngWp8Zz45DTTvxkgi7l845MuMa7XY9irFXPAtB8am8FcPy5+lU p248AMjjgkLIHttlBTpExWal5g6/LFfgVvFt95Aio+mhMhM4jb4W0g01A61rfrIB9Hlj RsSVbk8OX3SwemXG51KCxQ7wNhksTBYtNwM5bKW6zJrWGlz88oQCF2Vl0B/Vzz1wYiuI AD1sx6WpNBzinW1LwZoQtDJZZ4NLCYYa3fJrYrNl/0QiW/uzna9Jnf3aq8NgSs3Zyee9 7eW8tQDO97zEXVAXxM3cHmBSmYNaH41dyrLO3yEp9HL3R5xyNLBText4Y9vQUttZGCrl YQrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701798333; x=1702403133; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Xh660VR+cynL5ByMmnyvYALQkVg9X3nzQmC84j+D7MQ=; b=dec2at6TY81SScLQWwzVPwZscMzCd7LDN5Nth6kPDbLLD9TzYF1FWL6DV6z7DAj7aL 5u+FUD6NkljLVmqusM0mX3WsloOBjxgSNt7n5z5suTDK7Q6c9237be4e9xnX0gkHrpG1 K/fubocjHqeV9BRHzG+GzVeo5d90fK171bD1zu3JUJ0JpTI4h8xdKDol1zb2q+OYRO7n B5iDcmbmKn56d97Y8LJflAHGxbIRBpZT8NjIWOUgryeBySSB2d1x6BmBKhr/rGAg785k NCw3kFBTgKXrWBQ/YQnIEBPordK+Mtntb4rKIUyQuJlm6ToiGj6i1elLNJGqwzF/1+K4 8bXA== X-Gm-Message-State: AOJu0YwzfCpA+Mf+fzTWT72fBxIz0tL1If8o3XPpDFciqtAFGsoHOodJ cGkatoErzwQ95fra16zMfPDarA== X-Google-Smtp-Source: AGHT+IHmxq3UYJ5ZQx5exhCrZrdLX5Q8e34CNi9nSp70tBpb4whX5/If4GYuXq2EXsnqnTsBq5YwzQ== X-Received: by 2002:a17:903:1c7:b0:1d0:9c53:9cca with SMTP id e7-20020a17090301c700b001d09c539ccamr4076817plh.96.1701798333325; Tue, 05 Dec 2023 09:45:33 -0800 (PST) Received: from grind.. ([152.234.124.8]) by smtp.gmail.com with ESMTPSA id j20-20020a170902759400b001c74df14e6fsm10465705pll.284.2023.12.05.09.45.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Dec 2023 09:45:32 -0800 (PST) From: Daniel Henrique Barboza To: kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: anup@brainfault.org, atishp@atishpatra.org, palmer@dabbelt.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v3 3/3] RISC-V: KVM: add vector CSRs in KVM_GET_REG_LIST Date: Tue, 5 Dec 2023 14:45:09 -0300 Message-ID: <20231205174509.2238870-4-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231205174509.2238870-1-dbarboza@ventanamicro.com> References: <20231205174509.2238870-1-dbarboza@ventanamicro.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add all vector CSRs (vstart, vl, vtype, vcsr, vlenb) in get-reg-list. Signed-off-by: Daniel Henrique Barboza --- arch/riscv/kvm/vcpu_onereg.c | 55 ++++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c index f8c9fa0c03c5..2eb4980295ae 100644 --- a/arch/riscv/kvm/vcpu_onereg.c +++ b/arch/riscv/kvm/vcpu_onereg.c @@ -986,6 +986,55 @@ static int copy_sbi_ext_reg_indices(u64 __user *uindices) return num_sbi_ext_regs(); } +static inline unsigned long num_vector_regs(const struct kvm_vcpu *vcpu) +{ + if (!riscv_isa_extension_available(vcpu->arch.isa, v)) + return 0; + + /* vstart, vl, vtype, vcsr, vlenb and 32 vector regs */ + return 37; +} + +static int copy_vector_reg_indices(const struct kvm_vcpu *vcpu, + u64 __user *uindices) +{ + const struct kvm_cpu_context *cntx = &vcpu->arch.guest_context; + int n = num_vector_regs(vcpu); + u64 reg, size; + int i; + + if (n == 0) + return 0; + + /* copy vstart, vl, vtype, vcsr and vlenb */ + size = IS_ENABLED(CONFIG_32BIT) ? KVM_REG_SIZE_U32 : KVM_REG_SIZE_U64; + for (i = 0; i < 5; i++) { + reg = KVM_REG_RISCV | size | KVM_REG_RISCV_VECTOR | i; + + if (uindices) { + if (put_user(reg, uindices)) + return -EFAULT; + uindices++; + } + } + + /* vector_regs have a variable 'vlenb' size */ + size = __builtin_ctzl(cntx->vector.vlenb); + size <<= KVM_REG_SIZE_SHIFT; + for (i = 0; i < 32; i++) { + reg = KVM_REG_RISCV | KVM_REG_RISCV_VECTOR | size | + KVM_REG_RISCV_VECTOR_REG(i); + + if (uindices) { + if (put_user(reg, uindices)) + return -EFAULT; + uindices++; + } + } + + return n; +} + /* * kvm_riscv_vcpu_num_regs - how many registers do we present via KVM_GET/SET_ONE_REG * @@ -1001,6 +1050,7 @@ unsigned long kvm_riscv_vcpu_num_regs(struct kvm_vcpu *vcpu) res += num_timer_regs(); res += num_fp_f_regs(vcpu); res += num_fp_d_regs(vcpu); + res += num_vector_regs(vcpu); res += num_isa_ext_regs(vcpu); res += num_sbi_ext_regs(); @@ -1045,6 +1095,11 @@ int kvm_riscv_vcpu_copy_reg_indices(struct kvm_vcpu *vcpu, return ret; uindices += ret; + ret = copy_vector_reg_indices(vcpu, uindices); + if (ret < 0) + return ret; + uindices += ret; + ret = copy_isa_ext_reg_indices(vcpu, uindices); if (ret < 0) return ret;