From patchwork Wed Dec 6 00:57:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhangfei Gao X-Patchwork-Id: 13480903 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="zzdzN9X0" Received: from mail-oi1-x22b.google.com (mail-oi1-x22b.google.com [IPv6:2607:f8b0:4864:20::22b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 87E641BC for ; Tue, 5 Dec 2023 16:57:37 -0800 (PST) Received: by mail-oi1-x22b.google.com with SMTP id 5614622812f47-3b2e330033fso3691232b6e.3 for ; Tue, 05 Dec 2023 16:57:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1701824257; x=1702429057; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=15PtUMzm1CCv273Hbndys2UZ7tBEJDNkUXj6E0nA6q4=; b=zzdzN9X0wYgI7bU788cMONfZeYWGQdoZixtZQTFRKPuZlWy1Evsad3idByUApFqjo+ grH6fsjW6WnqzXgwhevN5SPB1Sp5cNLo+8EXEI8p9btiDOwj5AYOTTDT4LZR0d9PvQhP W79ht6sK/V2c0/fUfxL6NU5VlRc6VOg71e9+Ina5yV6d8A9Ufwd69xUdsaGUtJcsL3xE Ixrz5PybaF//fw3yrwQXIt/VuAaKefeNCT2ySVvNfh+hsK/EBvpENY+tdbHzukiFBGK2 QuUh9Mr7MXwmEwFyaKQt1AHPnTqbREdoy8oHyPeo4aqqJuEiRlzGCi1cQe1Lb1mGyoUk QaWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701824257; x=1702429057; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=15PtUMzm1CCv273Hbndys2UZ7tBEJDNkUXj6E0nA6q4=; b=vJYqEh7GIBeWrpqWg3U+aMdkU3a0PTWusf0CmzoklGnEbuSGsSyXxSBSwxOx6XCj2b 8TWqRhuZQK8ogHo1Gxsb0dMCeZxRr7i+xxXy/Fbya/4oLavmobbi4RGWoswFjxPNem8r PrFGAT/pvPPeW6g5PD69VqO/eFVW99eEogN5WTHN4ppO0SflT2Zv+8ETSzgVhKo1tOED 6hERI4gve/hXDCla4NpNG81mf0/mC6DDCDx0r/eBoyswkgCsqmltS60Q4onTTd3Ik7IU PLY9Y4jg5pfrYv6WJjBUSoz6qU9So6GtqJDQCR5Ks6KO00rM60VdJpDry5rsQf4NGIbx eeCA== X-Gm-Message-State: AOJu0Yzc/wsn4HSxegKS9te0tNN8+/gFe3Ejwh4G7ja0AuA/HtdDHuYi p589979oR4WwbX2mMuDdWgtdA0jyrlYEUVtiCjSGvHD+ X-Google-Smtp-Source: AGHT+IE5ulwG4V0s2m8jeafUFyOjHpVi+hGh+noPkhcaG114A6cDiNvh20aA9d+SEUvHswrSwKpRqQ== X-Received: by 2002:a05:6808:319b:b0:3b8:b063:6bb8 with SMTP id cd27-20020a056808319b00b003b8b0636bb8mr185810oib.103.1701824256810; Tue, 05 Dec 2023 16:57:36 -0800 (PST) Received: from localhost.localdomain ([36.5.194.73]) by smtp.gmail.com with ESMTPSA id fe18-20020a056a002f1200b006cddecbf432sm3569583pfb.96.2023.12.05.16.57.33 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 05 Dec 2023 16:57:36 -0800 (PST) From: Zhangfei Gao To: Joerg Roedel , Will Deacon , jean-philippe , Jason Gunthorpe Cc: iommu@lists.linux.dev, kvm@vger.kernel.org, Wenkai Lin , Zhangfei Gao Subject: [PATCH] iommu/arm-smmu-v3: disable stall for quiet_cd Date: Wed, 6 Dec 2023 08:57:27 +0800 Message-Id: <20231206005727.46150-1-zhangfei.gao@linaro.org> X-Mailer: git-send-email 2.39.3 (Apple Git-145) Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Wenkai Lin In the stall model, invalid transactions were expected to be stalled and aborted by the IOPF handler. However, when killing a test case with a huge amount of data, the accelerator streamline can not stop until all data is consumed even if the page fault handler reports errors. As a result, the kill may take a long time, about 10 seconds with numerous iopf interrupts. So disable stall for quiet_cd in the non-force stall model, since force stall model (STALL_MODEL==0b10) requires CD.S must be 1. Signed-off-by: Zhangfei Gao Signed-off-by: Wenkai Lin Suggested-by: Jean-Philippe Brucker Reviewed-by: Jason Gunthorpe Reviewed-by: Jean-Philippe Brucker --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 7445454c2af2..7086e5fa41ff 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1063,6 +1063,7 @@ int arm_smmu_write_ctx_desc(struct arm_smmu_master *master, int ssid, bool cd_live; __le64 *cdptr; struct arm_smmu_ctx_desc_cfg *cd_table = &master->cd_table; + struct arm_smmu_device *smmu = master->smmu; if (WARN_ON(ssid >= (1 << cd_table->s1cdmax))) return -E2BIG; @@ -1077,6 +1078,8 @@ int arm_smmu_write_ctx_desc(struct arm_smmu_master *master, int ssid, if (!cd) { /* (5) */ val = 0; } else if (cd == &quiet_cd) { /* (4) */ + if (!(smmu->features & ARM_SMMU_FEAT_STALL_FORCE)) + val &= ~(CTXDESC_CD_0_S | CTXDESC_CD_0_R); val |= CTXDESC_CD_0_TCR_EPD0; } else if (cd_live) { /* (3) */ val &= ~CTXDESC_CD_0_ASID;