From patchwork Wed Dec 6 13:55:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13481803 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="rcGjNgMh" Received: from mail-pf1-x435.google.com (mail-pf1-x435.google.com [IPv6:2607:f8b0:4864:20::435]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 99FB118D for ; Wed, 6 Dec 2023 05:55:58 -0800 (PST) Received: by mail-pf1-x435.google.com with SMTP id d2e1a72fcca58-6ce94f62806so301936b3a.1 for ; Wed, 06 Dec 2023 05:55:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1701870958; x=1702475758; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=G/GG08EU0jxNkkKUCidTdbhniPCzW7PlAscumj7h9J4=; b=rcGjNgMhn4E9Lr1j2wB5mI0hnxTwNdnxQj3v1AcKksdt2uQ38fRwFiOpMDlAXLYPlG B8xsSQLSKtEJ3UJt8qOU2ZUe61t6n0wfTsL1vICNpXHfbzp180n02Qm8tToZb2awCQDq WcjgF4M9Fa9DaoQJIeYdAscXua93mWMcU83ag0GIAMOoNGWlkfHgYihN63ZLlJEmyq8l +1zd/fHudFJUDsLAk8tSAzRRKk/BRSJ7IntTlAjnpXke7iVPV+XOO1b0mTSqDIVGoO/x ePUFbO3dPy81sHmf6fOM3weayM+xqf5v0KxTBy8pahpoXIyEs+qcrjfaMz8pLvFewhY9 LMeg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701870958; x=1702475758; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=G/GG08EU0jxNkkKUCidTdbhniPCzW7PlAscumj7h9J4=; b=iE9q+y9VO01/C/bNMBKAnCHNFPQhH+/xa446EZrKha56S7xBGCNTSaUE02jeyyrmH1 oVa6miLYhbawgy3n1IF0oB6GUo2QTJUTjsNMnxh2BE3HyBQ9OaQJlYJc0QJIj595BrT9 nmVOXofv6mnu07x3Lp/kXvMQZlNm1Y0E4Q05DWLoobvmqchU2Lz8dhbeVWqCM7PsNhPV 6cI6TgsGvhsshWPCd/lZly/3qS5q4TuYDx0ylgfC61xae3azk8f62yz25B+HiwVtqxGk Wg7HjTc0h1sidtULheykltRKaJNg4MRoRyLfyt1fo8ULlZo6mkpHWJ6EAoxr3iZzQCWd tYcw== X-Gm-Message-State: AOJu0YzpR6uSkhEKe+9ZbB7nFEx6nsc5QmvisAgoaAPGAq/Jomf+j0F7 efQ6GS93Qeq/oPZzsTDc++gh X-Google-Smtp-Source: AGHT+IEYj6PxW5OwqK1BCLicNLKZlz98ScmeI30pYPwjQqRCo1HKvD012fhsCDVxxUfV58CUVy2xYg== X-Received: by 2002:a05:6a00:2da1:b0:6ce:6cf3:38b4 with SMTP id fb33-20020a056a002da100b006ce6cf338b4mr779742pfb.1.1701870957926; Wed, 06 Dec 2023 05:55:57 -0800 (PST) Received: from localhost.localdomain ([117.202.188.104]) by smtp.gmail.com with ESMTPSA id n38-20020a056a000d6600b006ce91cdb1c4sm1366056pfv.188.2023.12.06.05.55.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Dec 2023 05:55:57 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, konrad.dybcio@linaro.org, conor+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 1/3] ARM: dts: qcom: Use "pcie" as the node name instead of "pci" Date: Wed, 6 Dec 2023 19:25:38 +0530 Message-Id: <20231206135540.17068-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231206135540.17068-1-manivannan.sadhasivam@linaro.org> References: <20231206135540.17068-1-manivannan.sadhasivam@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Qcom SoCs doesn't support the legacy PCI, but only PCIe. So use the correct node name for the controller instances. Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 2 +- arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk04.1.dtsi | 2 +- arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi | 2 +- arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi | 6 +++--- 4 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi index 59fd86b9fb47..fa3a0f72a18e 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi @@ -1472,7 +1472,7 @@ gfx3d1: iommu@7d00000 { qcom,ncb = <3>; }; - pcie: pci@1b500000 { + pcie: pcie@1b500000 { compatible = "qcom,pcie-apq8064"; reg = <0x1b500000 0x1000>, <0x1b502000 0x80>, diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk04.1.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk04.1.dtsi index 468ebc40d2ad..374af6dd360a 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk04.1.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk04.1.dtsi @@ -98,7 +98,7 @@ flash@0 { }; }; - pci@40000000 { + pcie@40000000 { status = "okay"; perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi index 9844e0b7cff9..6cbbccda5cf5 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi @@ -417,7 +417,7 @@ restart@4ab000 { reg = <0x4ab000 0x4>; }; - pcie0: pci@40000000 { + pcie0: pcie@40000000 { compatible = "qcom,pcie-ipq4019"; reg = <0x40000000 0xf1d>, <0x40000f20 0xa8>, diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi index 6198f42f6a9c..7c233b00a2dd 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi @@ -1076,7 +1076,7 @@ sata_phy: sata-phy@1b400000 { status = "disabled"; }; - pcie0: pci@1b500000 { + pcie0: pcie@1b500000 { compatible = "qcom,pcie-ipq8064"; reg = <0x1b500000 0x1000 0x1b502000 0x80 @@ -1127,7 +1127,7 @@ pcie0: pci@1b500000 { perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>; }; - pcie1: pci@1b700000 { + pcie1: pcie@1b700000 { compatible = "qcom,pcie-ipq8064"; reg = <0x1b700000 0x1000 0x1b702000 0x80 @@ -1178,7 +1178,7 @@ pcie1: pci@1b700000 { perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>; }; - pcie2: pci@1b900000 { + pcie2: pcie@1b900000 { compatible = "qcom,pcie-ipq8064"; reg = <0x1b900000 0x1000 0x1b902000 0x80 From patchwork Wed Dec 6 13:55:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13481804 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="FZm1jy6R" Received: from mail-pg1-x52f.google.com (mail-pg1-x52f.google.com [IPv6:2607:f8b0:4864:20::52f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A9F2ED4B for ; Wed, 6 Dec 2023 05:56:03 -0800 (PST) Received: by mail-pg1-x52f.google.com with SMTP id 41be03b00d2f7-5bdb0be3591so4430030a12.2 for ; Wed, 06 Dec 2023 05:56:03 -0800 (PST) DKIM-Signature: v=1; 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Wed, 06 Dec 2023 05:56:03 -0800 (PST) Received: from localhost.localdomain ([117.202.188.104]) by smtp.gmail.com with ESMTPSA id n38-20020a056a000d6600b006ce91cdb1c4sm1366056pfv.188.2023.12.06.05.55.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Dec 2023 05:56:01 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, konrad.dybcio@linaro.org, conor+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 2/3] arm64: dts: qcom: Use "pcie" as the node name instead of "pci" Date: Wed, 6 Dec 2023 19:25:39 +0530 Message-Id: <20231206135540.17068-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231206135540.17068-1-manivannan.sadhasivam@linaro.org> References: <20231206135540.17068-1-manivannan.sadhasivam@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Qcom SoCs doesn't support the legacy PCI, but only PCIe. So use the correct node name for the controller instances. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/msm8998.dtsi | 2 +- arch/arm64/boot/dts/qcom/qcs404.dtsi | 2 +- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 8 ++++---- arch/arm64/boot/dts/qcom/sdm845.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/sm8150.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/sm8250.dtsi | 6 +++--- arch/arm64/boot/dts/qcom/sm8350.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/sm8450.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/sm8550.dtsi | 4 ++-- 13 files changed, 25 insertions(+), 25 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index e59b9df96c7e..c649744e8751 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -731,7 +731,7 @@ qrtr_requests { }; }; - pcie0: pci@20000000 { + pcie0: pcie@20000000 { compatible = "qcom,pcie-ipq6018"; reg = <0x0 0x20000000 0x0 0xf1d>, <0x0 0x20000f20 0x0 0xa8>, diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 2f275c84e566..c6a96d8c9856 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -781,7 +781,7 @@ frame@b128000 { }; }; - pcie1: pci@10000000 { + pcie1: pcie@10000000 { compatible = "qcom,pcie-ipq8074"; reg = <0x10000000 0xf1d>, <0x10000f20 0xa8>, @@ -842,7 +842,7 @@ IRQ_TYPE_LEVEL_HIGH>, /* int_c */ status = "disabled"; }; - pcie0: pci@20000000 { + pcie0: pcie@20000000 { compatible = "qcom,pcie-ipq8074-gen3"; reg = <0x20000000 0xf1d>, <0x20000f20 0xa8>, diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index b485bf925ce6..b6a3e6afaefd 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -933,7 +933,7 @@ anoc2_smmu: iommu@16c0000 { ; }; - pcie0: pci@1c00000 { + pcie0: pcie@1c00000 { compatible = "qcom,pcie-msm8998", "qcom,pcie-msm8996"; reg = <0x01c00000 0x2000>, <0x1b000000 0xf1d>, diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 2721f32dfb71..6ac64ce9bb68 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -1461,7 +1461,7 @@ glink-edge { }; }; - pcie: pci@10000000 { + pcie: pcie@10000000 { compatible = "qcom,pcie-qcs404"; reg = <0x10000000 0xf1d>, <0x10000f20 0xa8>, diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index b6a93b11cbbd..d73fc3983709 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -2409,7 +2409,7 @@ arch_timer: timer { ; }; - pcie0: pci@1c00000{ + pcie0: pcie@1c00000{ compatible = "qcom,pcie-sa8775p"; reg = <0x0 0x01c00000 0x0 0x3000>, <0x0 0x40000000 0x0 0xf20>, @@ -2509,7 +2509,7 @@ pcie0_phy: phy@1c04000 { status = "disabled"; }; - pcie1: pci@1c10000{ + pcie1: pcie@1c10000{ compatible = "qcom,pcie-sa8775p"; reg = <0x0 0x01c10000 0x0 0x3000>, <0x0 0x60000000 0x0 0xf20>, diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 66f1eb83cca7..fb5e735247e7 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2126,7 +2126,7 @@ wifi: wifi@17a10040 { qcom,smem-state-names = "wlan-smp2p-out"; }; - pcie1: pci@1c08000 { + pcie1: pcie@1c08000 { compatible = "qcom,pcie-sc7280"; reg = <0 0x01c08000 0 0x3000>, <0 0x40000000 0 0xf1d>, diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index a34f438ef2d9..8bcc8c0bb0d0 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -1684,7 +1684,7 @@ mmss_noc: interconnect@1740000 { qcom,bcm-voters = <&apps_bcm_voter>; }; - pcie0: pci@1c00000 { + pcie0: pcie@1c00000 { compatible = "qcom,pcie-sc8180x"; reg = <0 0x01c00000 0 0x3000>, <0 0x60000000 0 0xf1d>, @@ -1781,7 +1781,7 @@ pcie0_phy: phy@1c06000 { status = "disabled"; }; - pcie3: pci@1c08000 { + pcie3: pcie@1c08000 { compatible = "qcom,pcie-sc8180x"; reg = <0 0x01c08000 0 0x3000>, <0 0x40000000 0 0xf1d>, @@ -1879,7 +1879,7 @@ pcie3_phy: phy@1c0c000 { status = "disabled"; }; - pcie1: pci@1c10000 { + pcie1: pcie@1c10000 { compatible = "qcom,pcie-sc8180x"; reg = <0 0x01c10000 0 0x3000>, <0 0x68000000 0 0xf1d>, @@ -1977,7 +1977,7 @@ pcie1_phy: phy@1c16000 { status = "disabled"; }; - pcie2: pci@1c18000 { + pcie2: pcie@1c18000 { compatible = "qcom,pcie-sc8180x"; reg = <0 0x01c18000 0 0x3000>, <0 0x70000000 0 0xf1d>, diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index bf5e6eb9d313..cb3bfd262851 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2306,7 +2306,7 @@ opp-4 { }; }; - pcie0: pci@1c00000 { + pcie0: pcie@1c00000 { compatible = "qcom,pcie-sdm845"; reg = <0 0x01c00000 0 0x2000>, <0 0x60000000 0 0xf1d>, @@ -2405,7 +2405,7 @@ pcie0_phy: phy@1c06000 { status = "disabled"; }; - pcie1: pci@1c08000 { + pcie1: pcie@1c08000 { compatible = "qcom,pcie-sdm845"; reg = <0 0x01c08000 0 0x2000>, <0 0x40000000 0 0xf1d>, diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 97623af13464..43d56968a382 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1824,7 +1824,7 @@ dma@10a2000 { <0x0 0x010ad000 0x0 0x3000>; }; - pcie0: pci@1c00000 { + pcie0: pcie@1c00000 { compatible = "qcom,pcie-sm8150"; reg = <0 0x01c00000 0 0x3000>, <0 0x60000000 0 0xf1d>, @@ -1915,7 +1915,7 @@ pcie0_phy: phy@1c06000 { status = "disabled"; }; - pcie1: pci@1c08000 { + pcie1: pcie@1c08000 { compatible = "qcom,pcie-sm8150"; reg = <0 0x01c08000 0 0x3000>, <0 0x40000000 0 0xf1d>, diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index be970472f6c4..c1b7f9620ec6 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2123,7 +2123,7 @@ mmss_noc: interconnect@1740000 { qcom,bcm-voters = <&apps_bcm_voter>; }; - pcie0: pci@1c00000 { + pcie0: pcie@1c00000 { compatible = "qcom,pcie-sm8250"; reg = <0 0x01c00000 0 0x3000>, <0 0x60000000 0 0xf1d>, @@ -2227,7 +2227,7 @@ pcie0_phy: phy@1c06000 { status = "disabled"; }; - pcie1: pci@1c08000 { + pcie1: pcie@1c08000 { compatible = "qcom,pcie-sm8250"; reg = <0 0x01c08000 0 0x3000>, <0 0x40000000 0 0xf1d>, @@ -2328,7 +2328,7 @@ pcie1_phy: phy@1c0e000 { status = "disabled"; }; - pcie2: pci@1c10000 { + pcie2: pcie@1c10000 { compatible = "qcom,pcie-sm8250"; reg = <0 0x01c10000 0 0x3000>, <0 0x64000000 0 0xf1d>, diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index b46236235b7f..f4b8439200f5 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -1498,7 +1498,7 @@ mmss_noc: interconnect@1740000 { qcom,bcm-voters = <&apps_bcm_voter>; }; - pcie0: pci@1c00000 { + pcie0: pcie@1c00000 { compatible = "qcom,pcie-sm8350"; reg = <0 0x01c00000 0 0x3000>, <0 0x60000000 0 0xf1d>, @@ -1591,7 +1591,7 @@ pcie0_phy: phy@1c06000 { status = "disabled"; }; - pcie1: pci@1c08000 { + pcie1: pcie@1c08000 { compatible = "qcom,pcie-sm8350"; reg = <0 0x01c08000 0 0x3000>, <0 0x40000000 0 0xf1d>, diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 1783fa78bdbc..44a61fa2cc49 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1739,7 +1739,7 @@ spi14: spi@a98000 { }; }; - pcie0: pci@1c00000 { + pcie0: pcie@1c00000 { compatible = "qcom,pcie-sm8450-pcie0"; reg = <0 0x01c00000 0 0x3000>, <0 0x60000000 0 0xf1d>, @@ -1848,7 +1848,7 @@ pcie0_phy: phy@1c06000 { status = "disabled"; }; - pcie1: pci@1c08000 { + pcie1: pcie@1c08000 { compatible = "qcom,pcie-sm8450-pcie1"; reg = <0 0x01c08000 0 0x3000>, <0 0x40000000 0 0xf1d>, diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 7b9ddde0b2c9..baa8540868a4 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -1677,7 +1677,7 @@ mmss_noc: interconnect@1780000 { qcom,bcm-voters = <&apps_bcm_voter>; }; - pcie0: pci@1c00000 { + pcie0: pcie@1c00000 { device_type = "pci"; compatible = "qcom,pcie-sm8550"; reg = <0 0x01c00000 0 0x3000>, @@ -1768,7 +1768,7 @@ pcie0_phy: phy@1c06000 { status = "disabled"; }; - pcie1: pci@1c08000 { + pcie1: pcie@1c08000 { device_type = "pci"; compatible = "qcom,pcie-sm8550"; reg = <0x0 0x01c08000 0x0 0x3000>, From patchwork Wed Dec 6 13:55:40 2023 Content-Type: text/plain; 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Wed, 06 Dec 2023 05:56:07 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, konrad.dybcio@linaro.org, conor+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 3/3] arm64: dts: qcom: sa8775p: Add missing space between node name and braces Date: Wed, 6 Dec 2023 19:25:40 +0530 Message-Id: <20231206135540.17068-4-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231206135540.17068-1-manivannan.sadhasivam@linaro.org> References: <20231206135540.17068-1-manivannan.sadhasivam@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add missing space between node name and braces to match the style. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index d73fc3983709..8ba6785038fa 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -2409,7 +2409,7 @@ arch_timer: timer { ; }; - pcie0: pcie@1c00000{ + pcie0: pcie@1c00000 { compatible = "qcom,pcie-sa8775p"; reg = <0x0 0x01c00000 0x0 0x3000>, <0x0 0x40000000 0x0 0xf20>, @@ -2509,7 +2509,7 @@ pcie0_phy: phy@1c04000 { status = "disabled"; }; - pcie1: pcie@1c10000{ + pcie1: pcie@1c10000 { compatible = "qcom,pcie-sa8775p"; reg = <0x0 0x01c10000 0x0 0x3000>, <0x0 0x60000000 0x0 0xf20>,