From patchwork Fri Dec 8 10:51:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 13485300 X-Patchwork-Delegate: kw@linux.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="NbuRrBrT" Received: from mail-ed1-x535.google.com (mail-ed1-x535.google.com [IPv6:2a00:1450:4864:20::535]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B8D7B172E for ; Fri, 8 Dec 2023 02:52:03 -0800 (PST) Received: by mail-ed1-x535.google.com with SMTP id 4fb4d7f45d1cf-54cde11d0f4so2845752a12.2 for ; Fri, 08 Dec 2023 02:52:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1702032722; x=1702637522; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=11veHRxQhePRmTa5CrJ3aUmZgsLlL/GI3AnVt9qonDk=; b=NbuRrBrTa3g7wYBGRmnyliJ0l2qBse6XpnP/d4+rlSS3MzgMC85XNu9b+wCu6TWgXT imtUQObgZw9O8jkWCioJ0DJf6tn9lRZ1i3XpcmnehOtl+nqmIzAJ8QHH8n/OGDZ6T32i z5qHrxaq5ddfRyzJJiC3EcIl/acbrL1dLjhZiX9G98xXh2ywznkmj2cDxJMOvOi+5yPR UYuNS9mYoX0MFALjnKiVL3KedAUzGmaItX4/0M7iKXLaEmdQTY4eqBma07Zgp/OkO8wO OW0rx5sIyzOAP02MSo0uJJlC7AYEWu+HGYC7Mf2G7OONEtFN9BYoKyH2RGRgCDuFElUO ZDQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702032722; x=1702637522; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=11veHRxQhePRmTa5CrJ3aUmZgsLlL/GI3AnVt9qonDk=; b=cXBSrYniCvWZXSIisGBAaVEo/UMf4fA5UGC1qkvcodDDVz0XymPZ5Tku04KaSg2yvK Bn5zSXNiTlVqLfwFsCaq90tykrmWH5SdzyZgh7O7lhhtrMyiIhz10PZxbWAu3xw/oL3y pXq3r362fjjB6OB6wnLJl7c1uqS3JzDIp/o/AblsHhTk1P+3pdghxYov9voKO5Y88/fF nTVslqnWT0CuUGX9Yrfhb39MkuebqW4arAmCE6du2DtE5/ilxgxpg1j8MAzlqSEdvOXL ho73PbWo9qd/UjgOq49BxCeu4bF+Sm/4rUgFhzYvMikgneFiK6z5K2oyCyll52UFepMh Eofw== X-Gm-Message-State: AOJu0YxDTrJqqe9d6g11yRr0AOeh1S5iyi584rYQz0pN4Hs9FckY5X1I UzpcMqLYW9n9mgqjXEQOJmeg4A== X-Google-Smtp-Source: AGHT+IFy/oY2zqBZqwRcRdiTxU/NBEEy892xMZAtSwzJby17iOVNew42umLhhA8HnKertNw0LYCfyw== X-Received: by 2002:a17:907:9518:b0:a1c:cd3b:4c2a with SMTP id ew24-20020a170907951800b00a1ccd3b4c2amr2129103ejc.72.1702032722112; Fri, 08 Dec 2023 02:52:02 -0800 (PST) Received: from krzk-bin.. ([178.197.218.27]) by smtp.gmail.com with ESMTPSA id tx17-20020a1709078e9100b00a1b75e0e061sm849976ejc.130.2023.12.08.02.52.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Dec 2023 02:52:01 -0800 (PST) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Manivannan Sadhasivam , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski , Manivannan Sadhasivam , Conor Dooley Subject: [PATCH v3 1/4] dt-bindings: PCI: qcom: adjust iommu-map for different SoC Date: Fri, 8 Dec 2023 11:51:52 +0100 Message-Id: <20231208105155.36097-1-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The PCIe controller on SDX55 has five entries in its iommu-map, MSM8998 has one and SDM845 has sixteen, so allow wider number of items to fix dtbs_check warnings like: qcom-sdx55-mtp.dtb: pcie@1c00000: iommu-map: [[0, 21, 512, 1], [256, 21, 513, 1], [512, 21, 514, 1], [768, 21, 515, 1], [1024, 21, 516, 1]] is too long Reviewed-by: Manivannan Sadhasivam Acked-by: Conor Dooley Signed-off-by: Krzysztof Kozlowski --- Please take the patch via PCI tree. Changes in v3: 1. None Changes in v2: 1. Add Acs/Rb. --- Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 9dbc07dfd48f..5056da499f04 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -66,7 +66,8 @@ properties: maxItems: 8 iommu-map: - maxItems: 2 + minItems: 1 + maxItems: 16 # Common definitions for clocks, clock-names and reset. # Platform constraints are described later. From patchwork Fri Dec 8 10:51:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 13485301 X-Patchwork-Delegate: kw@linux.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="EWpUv5Fz" Received: from mail-ej1-x635.google.com (mail-ej1-x635.google.com [IPv6:2a00:1450:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 65DD61733 for ; Fri, 8 Dec 2023 02:52:05 -0800 (PST) Received: by mail-ej1-x635.google.com with SMTP id a640c23a62f3a-a1f47f91fc0so178299266b.0 for ; Fri, 08 Dec 2023 02:52:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1702032724; x=1702637524; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TAfB7XP9qswfZDmppuZfzA/p4yR5CeCNI9dzwHD6WP4=; b=EWpUv5Fzt18xugwIn2mWF5ktL1004rnxGtKahBcRghb/hJvFh5kOlr9ecEIzN32/A6 WVDxeOkDAWBHFRGb8AXp1Vvvs4tGfr02G+zZnEbSrlV/DJB3ubM5mUzw/UwSwI5Qebau VW0Q2kEnU7dqt/KL6vN8WwlN9mluY0pVw+xvqIy+HpxNhanp7M3JceRMtxwrU1lXfNq2 egaNVk68E0ZqihF93hxLSZlTtepmnZoTuiH8SrCIBL2owkIo59TxpBokOw9B74MK3IGG 0qq8xO/2j9bHkV3kS74NRXNBpe/Dck/AuO2D/9EL3AAFCbrEagGpU2lssxP8KfSd6mKn XwUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702032724; x=1702637524; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TAfB7XP9qswfZDmppuZfzA/p4yR5CeCNI9dzwHD6WP4=; b=HjKnjK/cMZSOwE9+fqT5CME0/uHSWahttjk47EHFLO4PoiXBDikpJSzqD7FU67JdJs qQt8aVeo4JmyzS/By9RcCGECZdF/reTBWZy7Q9M72vVs2OyCarCm3y8P8xE2A3M8E3I0 4drLX1dmpLkne2K+jwlk0i4QhankDadVUbpaLkpAGjO75Xp5vNy2ZjmKKrdFjJoYc7iR mi3ScHiPUQiOiOjTlWMUMnbYpjE+gJR4q/1r8YtYBdvedQTuUIqZuziYxLBHgtWkLnHo U90SNCI3JOw77c9y+ZCjnVS2e/niKV6q5zG/heSVB+yPDqYnDu9QX+vcTOQRlGiMj7o4 0hvA== X-Gm-Message-State: AOJu0Yy0UvxrVJTNsb/8EelwwXEOs+zSGUh+f82SB/YGb0PAeA0k8RN8 Dmj9xwuWWjUqtQVOUudTfybmmw== X-Google-Smtp-Source: AGHT+IHQWFvI3cUlx05L62in4j7p7qC1FH/YrW2thF2CuQ0R9iAKMY25cPEvsPV2B+Moh/dQko+f6Q== X-Received: by 2002:a17:906:f88f:b0:a19:a19b:55e7 with SMTP id lg15-20020a170906f88f00b00a19a19b55e7mr2336374ejb.119.1702032723901; Fri, 08 Dec 2023 02:52:03 -0800 (PST) Received: from krzk-bin.. ([178.197.218.27]) by smtp.gmail.com with ESMTPSA id tx17-20020a1709078e9100b00a1b75e0e061sm849976ejc.130.2023.12.08.02.52.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Dec 2023 02:52:03 -0800 (PST) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Manivannan Sadhasivam , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH v3 2/4] dt-bindings: PCI: qcom: correct clocks for SC8180x Date: Fri, 8 Dec 2023 11:51:53 +0100 Message-Id: <20231208105155.36097-2-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231208105155.36097-1-krzysztof.kozlowski@linaro.org> References: <20231208105155.36097-1-krzysztof.kozlowski@linaro.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 PCI node in Qualcomm SC8180x DTS has 8 clocks: sc8180x-primus.dtb: pci@1c00000: 'oneOf' conditional failed, one must be fixed: ['pipe', 'aux', 'cfg', 'bus_master', 'bus_slave', 'slave_q2a', 'ref', 'tbu'] is too short Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring --- Please take the patch via PCI tree. Changes in v3: 1. Split from sm8150 change. Due to split/changes around sm8150, drop Mani's Rb tag. 2. Drop unneeded oneOf for clocks. Changes in v2: 1. Add Acs/Rb. 2. Correct error message for sm8150. --- .../devicetree/bindings/pci/qcom,pcie.yaml | 28 ++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 5056da499f04..5214bf7a9045 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -483,6 +483,33 @@ allOf: items: - const: pci # PCIe core reset + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-sc8180x + then: + properties: + clocks: + minItems: 8 + maxItems: 8 + clock-names: + items: + - const: pipe # PIPE clock + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: ref # REFERENCE clock + - const: tbu # PCIe TBU clock + resets: + maxItems: 1 + reset-names: + items: + - const: pci # PCIe core reset + - if: properties: compatible: @@ -531,7 +558,6 @@ allOf: compatible: contains: enum: - - qcom,pcie-sc8180x - qcom,pcie-sm8150 - qcom,pcie-sm8250 then: From patchwork Fri Dec 8 10:51:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 13485302 X-Patchwork-Delegate: kw@linux.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="TTRXK3Ue" Received: from mail-ej1-x62b.google.com (mail-ej1-x62b.google.com [IPv6:2a00:1450:4864:20::62b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 524B6115 for ; Fri, 8 Dec 2023 02:52:07 -0800 (PST) Received: by mail-ej1-x62b.google.com with SMTP id a640c23a62f3a-a1e35c2807fso258021366b.3 for ; Fri, 08 Dec 2023 02:52:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1702032726; x=1702637526; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RN5mp7wTS0ZL9oWDzM8c7WSR4Kqr0x4UsxjvnOwJZ54=; b=TTRXK3UezIiAx6CURgAyfKdfnAWG79eP5axjv9MqgTiiRvp6GpE4cgm2gYMVt3FsMF bSmyw34J1GSDpK7XsjbjPyLyCYTK8BVNlyodMla1LF2EtQldSF8mSikKI/R3W+YGm66z Q/HrBCRY4m/6nieSk5cqhggdfhHe4jMYeAtyYEHlKP5LrcjHwpKduQfGJvpqoohXYp0D 4Yfi7IcR+bo5aHBv7Gkm9LvtXzb7A0T2mG4KGJ00PORrQTWnN3xxXYYuyTSBzPbThQzh vY1QVDpDDFVjFEH1QT0UBS1yOEhAh2k1u0I2/kwcbR50wGHqP+JDv8UBaGpKP011qYQN UVRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702032726; x=1702637526; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RN5mp7wTS0ZL9oWDzM8c7WSR4Kqr0x4UsxjvnOwJZ54=; b=Rur1hZCiGZW2tLEaNaNu0wWvEu1yi5/xKsFGUaY8H7TVL5hXaiXByh/rLFb4xCr+R3 YM/N8mo5fixpN4IsWXXi/Dp8ABSo/7e8KfuLyhfjScn/Hu+1P73rASzM1VeWW0kLoxD5 CLw0znWgxTMCXJTFTcuJP82gKRQ1gAn+fCgGaDcLvMKsS+3lSa89pZP1apM8WCxikaTj MB8V1dega41Y3DNS9eM7NH/tm6/00Z98H1/+mCCS21Vq1GxYMDwf4tdZMIurY+6gIF1z OaTemoL6CZXXwPwdVJWaoEdKeQ3MtYOxSF1Lz5mkTxvIYVKyh+avs+pB6OcMq/KrQLai 7yeQ== X-Gm-Message-State: AOJu0Yy3OmgQliKoDbaB4RNrUUJ0XAEwIVRknjob9ycgkxeibEV6iSaX RSocaIhgLYtn1fjmh470zYOCsg== X-Google-Smtp-Source: AGHT+IFa3yE/mQVHSrkLKmIRUVYN9Uw84CyOj2njdjyXU/h65hwehtnmy3fIse4e3d36lkIR9h7FOg== X-Received: by 2002:a17:906:560c:b0:a19:a1ba:da51 with SMTP id f12-20020a170906560c00b00a19a1bada51mr2668011ejq.120.1702032725770; Fri, 08 Dec 2023 02:52:05 -0800 (PST) Received: from krzk-bin.. ([178.197.218.27]) by smtp.gmail.com with ESMTPSA id tx17-20020a1709078e9100b00a1b75e0e061sm849976ejc.130.2023.12.08.02.52.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Dec 2023 02:52:05 -0800 (PST) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Manivannan Sadhasivam , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski , Manivannan Sadhasivam Subject: [PATCH v3 3/4] dt-bindings: PCI: qcom: correct clocks for SM8150 Date: Fri, 8 Dec 2023 11:51:54 +0100 Message-Id: <20231208105155.36097-3-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231208105155.36097-1-krzysztof.kozlowski@linaro.org> References: <20231208105155.36097-1-krzysztof.kozlowski@linaro.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 PCI node in Qualcomm SM8150 should have exactly 8 clocks, including the ref clock. Suggested-by: Manivannan Sadhasivam Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring --- Please take the patch via PCI tree. Changes in v3: 1. New patch: Split from sc8180x change. 2. Add refclk as explained here: https://lore.kernel.org/all/20231121065440.GB3315@thinkpad/ --- .../devicetree/bindings/pci/qcom,pcie.yaml | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 5214bf7a9045..a93ab3b54066 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -559,6 +559,32 @@ allOf: contains: enum: - qcom,pcie-sm8150 + then: + properties: + clocks: + minItems: 8 + maxItems: 8 + clock-names: + items: + - const: pipe # PIPE clock + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: tbu # PCIe TBU clock + - const: ref # REFERENCE clock + resets: + maxItems: 1 + reset-names: + items: + - const: pci # PCIe core reset + + - if: + properties: + compatible: + contains: + enum: - qcom,pcie-sm8250 then: oneOf: From patchwork Fri Dec 8 10:51:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 13485303 X-Patchwork-Delegate: kw@linux.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="M0Rz45jh" Received: from mail-ej1-x62b.google.com (mail-ej1-x62b.google.com [IPv6:2a00:1450:4864:20::62b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0D5731712 for ; Fri, 8 Dec 2023 02:52:09 -0800 (PST) Received: by mail-ej1-x62b.google.com with SMTP id a640c23a62f3a-a1e2ded3d9fso236539866b.0 for ; Fri, 08 Dec 2023 02:52:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1702032727; x=1702637527; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3yFkfEp12aI+6U4wU/tq2gheT7TJS/3Q4MuYssvsV5A=; b=M0Rz45jhRNrG+xtYKkVM6CRyO6pyceWKHaE6n+QuV0gBqAjk9meLRq4zCCqMcfSjkS 6hB5SvwddqVNQ6NSVVkSSlj2l4UIXHkYvQmjMNNauDhLDq5wYee1Jvwa2YzHDsKcUOyd r9MWgzAuTQyIGyN0fBYwTYd9xGJYYNuvRYi3S4dZGJDOuW9O2UUM9eoDp3WxYl0S/UgJ qZlLdh4YJY4rpWzftbmyRB76lDmLL8RvGMIfwrY+hoZxakVHNjrE1HSHsIxBQ0Ux9LfG HVXbMiVAAa/vQfHwNFNFPtfVeIvku6gI0tW9MLkkedR+Z4/ZxPxkfKNW13U0A5SeDaj8 cZmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702032727; x=1702637527; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3yFkfEp12aI+6U4wU/tq2gheT7TJS/3Q4MuYssvsV5A=; b=jLXiDdIt7F/GgZEcVmIFmKpmv4bSWRHNJ12/apcA0JbkRhJa6OpWAjxDtp1okn8H5p noDj1E64Fsbalcv7thc5I6JKkTUnv1pP7ilmM3DHT5Z7nAJM2F5rO7T9e1d/BzcunM0f oQbmct0IdKayIYRvrLDIugCtg3YA74wCqgO7RLhPjgMmlzyqOPZrNlVaUEDSv7Mqw/RA WcN3BqPNlDOONn6Ds1mPtnkETuj5PtI2PSrY2D+R7sIbTtC83TyixyEQhT7rdSc/nKHB SmSyYlBBpy3Dpm1N7i11KnZZtWKcBIVhHcBaj80rTUBP1CSYcR5o+M3GthvWcP+y9mPx WuQA== X-Gm-Message-State: AOJu0Yw8ltjiiwCPIwfPnmdO8rjW+8g99rPOuoPrkzJ2KyECSLDmJfSf NkBBwNawj4M1Y+Hb/8+d8W6/bA== X-Google-Smtp-Source: AGHT+IFVGSGWzV2Nk5abJTsBLjnttS05N2wFp85PjCkHQOAwQbKVVnCvVck7KrGQlppIg477ctFxeg== X-Received: by 2002:a17:906:a856:b0:9e0:4910:166a with SMTP id dx22-20020a170906a85600b009e04910166amr2681680ejb.32.1702032727601; Fri, 08 Dec 2023 02:52:07 -0800 (PST) Received: from krzk-bin.. ([178.197.218.27]) by smtp.gmail.com with ESMTPSA id tx17-20020a1709078e9100b00a1b75e0e061sm849976ejc.130.2023.12.08.02.52.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Dec 2023 02:52:07 -0800 (PST) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Manivannan Sadhasivam , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH v3 4/4] arm64: dts: qcom: sm8150: add necessary ref clock to PCIe Date: Fri, 8 Dec 2023 11:51:55 +0100 Message-Id: <20231208105155.36097-4-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231208105155.36097-1-krzysztof.kozlowski@linaro.org> References: <20231208105155.36097-1-krzysztof.kozlowski@linaro.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The PCIe nodes should get the ref clock, according to information from Qualcomm. Link: https://lore.kernel.org/all/20231121065440.GB3315@thinkpad/ Signed-off-by: Krzysztof Kozlowski --- Patch should go via Qcom tree, if the bindings get accepted. Changes in v3: 1. New patch --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 5edc557ba04a..22ee3cd5549d 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1858,14 +1858,16 @@ pcie0: pci@1c00000 { <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, <&gcc GCC_PCIE_0_SLV_AXI_CLK>, <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, - <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&rpmhcc RPMH_CXO_CLK>; clock-names = "pipe", "aux", "cfg", "bus_master", "bus_slave", "slave_q2a", - "tbu"; + "tbu", + "ref"; iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, <0x100 &apps_smmu 0x1d81 0x1>; @@ -1949,14 +1951,16 @@ pcie1: pci@1c08000 { <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, <&gcc GCC_PCIE_1_SLV_AXI_CLK>, <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, - <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&rpmhcc RPMH_CXO_CLK>; clock-names = "pipe", "aux", "cfg", "bus_master", "bus_slave", "slave_q2a", - "tbu"; + "tbu", + "ref"; assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; assigned-clock-rates = <19200000>;