From patchwork Mon Dec 11 08:01:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suraj Jaiswal X-Patchwork-Id: 13486762 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="T/76lJ0Z" Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 533D6107; Mon, 11 Dec 2023 00:02:40 -0800 (PST) Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BB3u1j7017255; Mon, 11 Dec 2023 08:02:26 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=F1dvCu31Go4iODMevg5gumxXIA00ejjefDfCvFXuExg=; b=T/ 76lJ0ZyraFug80UO47Ak4pmd7AGY6lEvIG2r0As7T98NaMlRt98V+nM8yOSqIGt+ m4oU/fwgLQEHEtjWHZQs6C6HAVXJM5spwD3qeCF8fG2UXWzo5k+2LM3mNj5aaMeu syXuu5SvasjfIQ1n12ueGQNMV9P0TSWnc2ndON5qBOMnu28E5Qii3tN9dkRyImY6 SE4TTxUiEWh60skltGR7k8gRLPdnSeFvP+SOTQmzaq0GCos2/O2NXM20+RLirxdb uKz8IOLs9z038V2pYJoYD7YISZ2dPAjPIoT4qWQW3dT6jXwEdMRuuOz8riWz/2/j bh6TvV6l+o0iaJERJUrg== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3uvnfjamrb-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 11 Dec 2023 08:02:26 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BB82PW5007882 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 11 Dec 2023 08:02:25 GMT Received: from hu-jsuraj-hyd.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Mon, 11 Dec 2023 00:02:15 -0800 From: Suraj Jaiswal To: , Vinod Koul , Bhupesh Sharma , Andy Gross , Bjorn Andersson , Konrad Dybcio , "David S. Miller" , Eric Dumazet , "Jakub Kicinski" , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Alexandre Torgue , "Jose Abreu" , Maxime Coquelin , , , , , , Prasad Sodagudi , Andrew Halaney , Rob Herring CC: Subject: [PATCH net-next v5 1/3] dt-bindings: net: qcom,ethqos: add binding doc for safety IRQ for sa8775p Date: Mon, 11 Dec 2023 13:31:51 +0530 Message-ID: <20231211080153.3005122-2-quic_jsuraj@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231211080153.3005122-1-quic_jsuraj@quicinc.com> References: <20231211080153.3005122-1-quic_jsuraj@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: W9rhH4rFLWKYZsz1rOeVFxX3_g4MnVvm X-Proofpoint-GUID: W9rhH4rFLWKYZsz1rOeVFxX3_g4MnVvm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 phishscore=0 spamscore=0 adultscore=0 clxscore=1015 impostorscore=0 priorityscore=1501 bulkscore=0 mlxlogscore=999 lowpriorityscore=0 malwarescore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312110066 Add binding doc for safety IRQ. The safety IRQ will be triggered for ECC(error correction code), DPP(data path parity), FSM(finite state machine) error. Signed-off-by: Suraj Jaiswal --- Documentation/devicetree/bindings/net/qcom,ethqos.yaml | 9 ++++++--- Documentation/devicetree/bindings/net/snps,dwmac.yaml | 6 ++++-- 2 files changed, 10 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/net/qcom,ethqos.yaml b/Documentation/devicetree/bindings/net/qcom,ethqos.yaml index 7bdb412a0185..93d21389e518 100644 --- a/Documentation/devicetree/bindings/net/qcom,ethqos.yaml +++ b/Documentation/devicetree/bindings/net/qcom,ethqos.yaml @@ -37,12 +37,14 @@ properties: items: - description: Combined signal for various interrupt events - description: The interrupt that occurs when Rx exits the LPI state + - description: The interrupt that occurs when HW safety error triggered interrupt-names: minItems: 1 items: - const: macirq - - const: eth_lpi + - enum: [eth_lpi, safety] + - const: safety clocks: maxItems: 4 @@ -89,8 +91,9 @@ examples: <&gcc GCC_ETH_PTP_CLK>, <&gcc GCC_ETH_RGMII_CLK>; interrupts = , - ; - interrupt-names = "macirq", "eth_lpi"; + , + ; + interrupt-names = "macirq", "eth_lpi", "safety"; rx-fifo-depth = <4096>; tx-fifo-depth = <4096>; diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml index 5c2769dc689a..3b46d69ea97d 100644 --- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml +++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml @@ -107,13 +107,15 @@ properties: - description: Combined signal for various interrupt events - description: The interrupt to manage the remote wake-up packet detection - description: The interrupt that occurs when Rx exits the LPI state + - description: The interrupt that occurs when HW safety error triggered interrupt-names: minItems: 1 items: - const: macirq - - enum: [eth_wake_irq, eth_lpi] - - const: eth_lpi + - enum: [eth_wake_irq, eth_lpi, safety] + - enum: [eth_wake_irq, eth_lpi, safety] + - enum: [eth_wake_irq, eth_lpi, safety] clocks: minItems: 1 From patchwork Mon Dec 11 08:01:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suraj Jaiswal X-Patchwork-Id: 13486763 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="gODWvx/A" Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 225BE113; Mon, 11 Dec 2023 00:02:47 -0800 (PST) Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BB7vqKj020801; Mon, 11 Dec 2023 08:02:33 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=NxM4Hzj0Zu7rwaDjip3vlG09i1StZxhDtyXhLRHX4Jk=; b=gO DWvx/A1DGlCxoa5swNwFDOLdBMudtCE7LEQ9Maleu9GWNCIvJa/svUmIm6x6DQf9 dx1SwCyPutHwcSMTP0VjO0JVqkInIbIa0z2yB5asbZUCGTUsJpDEtED6EsVrHRM2 tSbBPNja0fax0+I36JelkgmO6ebLU5xA/ovmAWm3EYOWGo3SWXk3rwMJcD2+WNmr o9Gb86arV4Lu7r8zLUNiuHswsaSLgjkuzMF73E0zCUS76o9oeHn3RkkbGe6BoNMj 1+xZNhwiJ9ue5zAonVtUjurrNn87X9kLUfp7wFgfvqzne2TPQ4kRWtpUj/3iqLzD 1gB0i9gZsEWQVHeuHX7A== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3uvney2nas-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 11 Dec 2023 08:02:33 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BB82WId003088 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 11 Dec 2023 08:02:32 GMT Received: from hu-jsuraj-hyd.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Mon, 11 Dec 2023 00:02:22 -0800 From: Suraj Jaiswal To: , Vinod Koul , Bhupesh Sharma , Andy Gross , Bjorn Andersson , Konrad Dybcio , "David S. Miller" , Eric Dumazet , "Jakub Kicinski" , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Alexandre Torgue , "Jose Abreu" , Maxime Coquelin , , , , , , Prasad Sodagudi , Andrew Halaney , Rob Herring CC: Subject: [PATCH net-next v5 2/3] arm64: dts: qcom: sa8775p: enable safety IRQ Date: Mon, 11 Dec 2023 13:31:52 +0530 Message-ID: <20231211080153.3005122-3-quic_jsuraj@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231211080153.3005122-1-quic_jsuraj@quicinc.com> References: <20231211080153.3005122-1-quic_jsuraj@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: K6Jhpl5AWdelnIsUh5p0pYG7zW7XKIxm X-Proofpoint-ORIG-GUID: K6Jhpl5AWdelnIsUh5p0pYG7zW7XKIxm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 bulkscore=0 impostorscore=0 mlxlogscore=653 mlxscore=0 phishscore=0 spamscore=0 malwarescore=0 lowpriorityscore=0 clxscore=1015 suspectscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312110066 Add changes to support safety IRQ handling support for ethernet. Signed-off-by: Suraj Jaiswal Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 6b92f9083104..a3ed75a1314c 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -2394,8 +2394,9 @@ ethernet1: ethernet@23000000 { <0x0 0x23016000 0x0 0x100>; reg-names = "stmmaceth", "rgmii"; - interrupts = ; - interrupt-names = "macirq"; + interrupts = , + ; + interrupt-names = "macirq", "safety"; clocks = <&gcc GCC_EMAC1_AXI_CLK>, <&gcc GCC_EMAC1_SLV_AHB_CLK>, @@ -2427,8 +2428,9 @@ ethernet0: ethernet@23040000 { <0x0 0x23056000 0x0 0x100>; reg-names = "stmmaceth", "rgmii"; - interrupts = ; - interrupt-names = "macirq"; + interrupts = , + ; + interrupt-names = "macirq", "safety"; clocks = <&gcc GCC_EMAC0_AXI_CLK>, <&gcc GCC_EMAC0_SLV_AHB_CLK>, From patchwork Mon Dec 11 08:01:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suraj Jaiswal X-Patchwork-Id: 13486764 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="jaoQqXLk" Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DA385101; Mon, 11 Dec 2023 00:02:54 -0800 (PST) Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BB7aoV9013723; Mon, 11 Dec 2023 08:02:41 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=+FEzrFKs6ZPhCQRBlfYnh24zV5xaPlV/IKpddkGjXTw=; b=ja oQqXLkSUd5O5JXVKrGhXAYK5sZ/4VSVYd3xR7Iknkbqi8y3vIR3OPp/FxBNu+XC5 aXMgVwVDIDU1UWeCU1Lh2Pkk97hCi8l/p94KLqE3knOPklp6nP+fApnGoRYsfR4X kLx4kiXqTuyqsvqDciG/tQdCnbi1hyUxyReQ/eG8dtroTxDpmLTg770IVUXzaTnN 0+/8umhD3ToL0IcAuiEKSajMadLigc9F5vuH2eNqbzmiiCmUPpWxR5TZTvjsk+65 IXak+PtHVomGeN1ytfsPqi27ma93Wzjd19bw/9gHkeSpk8gTwYJSqZ+VyL2InmCW hxM2QwA4dQoXlWYOy9uA== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3uwjyjrynx-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 11 Dec 2023 08:02:41 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BB82eYp003204 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 11 Dec 2023 08:02:40 GMT Received: from hu-jsuraj-hyd.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Mon, 11 Dec 2023 00:02:30 -0800 From: Suraj Jaiswal To: , Vinod Koul , Bhupesh Sharma , Andy Gross , Bjorn Andersson , Konrad Dybcio , "David S. Miller" , Eric Dumazet , "Jakub Kicinski" , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Alexandre Torgue , "Jose Abreu" , Maxime Coquelin , , , , , , Prasad Sodagudi , Andrew Halaney , Rob Herring CC: Subject: [PATCH net-next v5 3/3] net: stmmac: Add driver support for DWMAC5 safety IRQ support Date: Mon, 11 Dec 2023 13:31:53 +0530 Message-ID: <20231211080153.3005122-4-quic_jsuraj@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231211080153.3005122-1-quic_jsuraj@quicinc.com> References: <20231211080153.3005122-1-quic_jsuraj@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: x5JuBftQhK7WbrtJsDHr2lL8fsUiMgXn X-Proofpoint-ORIG-GUID: x5JuBftQhK7WbrtJsDHr2lL8fsUiMgXn X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 mlxscore=0 bulkscore=0 priorityscore=1501 impostorscore=0 malwarescore=0 adultscore=0 clxscore=1015 lowpriorityscore=0 mlxlogscore=999 phishscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312110066 Add IRQ support to listen HW safety IRQ like ECC(error correction code), DPP(data path parity), FSM(finite state machine) fault and print the fault information in the kernel log. Signed-off-by: Suraj Jaiswal --- drivers/net/ethernet/stmicro/stmmac/common.h | 1 + drivers/net/ethernet/stmicro/stmmac/stmmac.h | 2 ++ .../net/ethernet/stmicro/stmmac/stmmac_main.c | 18 ++++++++++++++++++ .../ethernet/stmicro/stmmac/stmmac_platform.c | 9 +++++++++ 4 files changed, 30 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h b/drivers/net/ethernet/stmicro/stmmac/common.h index 721c1f8e892f..cb9645fe16d8 100644 --- a/drivers/net/ethernet/stmicro/stmmac/common.h +++ b/drivers/net/ethernet/stmicro/stmmac/common.h @@ -347,6 +347,7 @@ enum request_irq_err { REQ_IRQ_ERR_SFTY_UE, REQ_IRQ_ERR_SFTY_CE, REQ_IRQ_ERR_LPI, + REQ_IRQ_ERR_SAFETY, REQ_IRQ_ERR_WOL, REQ_IRQ_ERR_MAC, REQ_IRQ_ERR_NO, diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac.h b/drivers/net/ethernet/stmicro/stmmac/stmmac.h index 9f89acf31050..aa2eda6fb927 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac.h +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac.h @@ -33,6 +33,7 @@ struct stmmac_resources { int irq; int sfty_ce_irq; int sfty_ue_irq; + int safety_common_irq; int rx_irq[MTL_MAX_RX_QUEUES]; int tx_irq[MTL_MAX_TX_QUEUES]; }; @@ -299,6 +300,7 @@ struct stmmac_priv { unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; int sfty_ce_irq; int sfty_ue_irq; + int safety_common_irq; int rx_irq[MTL_MAX_RX_QUEUES]; int tx_irq[MTL_MAX_TX_QUEUES]; /*irq name */ diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c index 47de466e432c..e4a0d9ec8b3f 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -3592,6 +3592,10 @@ static void stmmac_free_irq(struct net_device *dev, if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) free_irq(priv->wol_irq, dev); fallthrough; + case REQ_IRQ_ERR_SAFETY: + if (priv->safety_common_irq > 0 && priv->safety_common_irq != dev->irq) + free_irq(priv->safety_common_irq, dev); + fallthrough; case REQ_IRQ_ERR_WOL: free_irq(dev->irq, dev); fallthrough; @@ -3798,6 +3802,18 @@ static int stmmac_request_irq_single(struct net_device *dev) } } + if (priv->safety_common_irq > 0 && priv->safety_common_irq != dev->irq) { + ret = request_irq(priv->safety_common_irq, stmmac_safety_interrupt, + 0, "safety", dev); + if (unlikely(ret < 0)) { + netdev_err(priv->dev, + "%s: alloc safety failed %d (error: %d)\n", + __func__, priv->safety_common_irq, ret); + irq_err = REQ_IRQ_ERR_SAFETY; + goto irq_error; + } + } + return 0; irq_error: @@ -7464,6 +7480,8 @@ int stmmac_dvr_probe(struct device *device, priv->lpi_irq = res->lpi_irq; priv->sfty_ce_irq = res->sfty_ce_irq; priv->sfty_ue_irq = res->sfty_ue_irq; + priv->safety_common_irq = res->safety_common_irq; + for (i = 0; i < MTL_MAX_RX_QUEUES; i++) priv->rx_irq[i] = res->rx_irq[i]; for (i = 0; i < MTL_MAX_TX_QUEUES; i++) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c index 1ffde555da47..41a4a253d75b 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c @@ -726,6 +726,15 @@ int stmmac_get_platform_resources(struct platform_device *pdev, dev_info(&pdev->dev, "IRQ eth_lpi not found\n"); } + stmmac_res->safety_common_irq = + platform_get_irq_byname_optional(pdev, "safety"); + + if (stmmac_res->safety_common_irq < 0) { + if (stmmac_res->safety_common_irq == -EPROBE_DEFER) + return -EPROBE_DEFER; + dev_info(&pdev->dev, "IRQ safety IRQ not found\n"); + } + stmmac_res->addr = devm_platform_ioremap_resource(pdev, 0); return PTR_ERR_OR_ZERO(stmmac_res->addr);