From patchwork Mon Dec 11 12:23:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 13487163 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 66FDBC4167B for ; Mon, 11 Dec 2023 12:23:44 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.651731.1017515 (Exim 4.92) (envelope-from ) id 1rCfJo-0005SH-UE; Mon, 11 Dec 2023 12:23:28 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 651731.1017515; Mon, 11 Dec 2023 12:23:28 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rCfJo-0005SA-RR; Mon, 11 Dec 2023 12:23:28 +0000 Received: by outflank-mailman (input) for mailman id 651731; Mon, 11 Dec 2023 12:23:28 +0000 Received: from mail.xenproject.org ([104.130.215.37]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rCfJo-0005Ns-7E for xen-devel@lists.xenproject.org; Mon, 11 Dec 2023 12:23:28 +0000 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rCfJo-0003oL-4I; Mon, 11 Dec 2023 12:23:28 +0000 Received: from 54-240-197-224.amazon.com ([54.240.197.224] helo=dev-dsk-jgrall-1b-035652ec.eu-west-1.amazon.com) by xenbits.xenproject.org with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.92) (envelope-from ) id 1rCfJn-0001JH-RT; Mon, 11 Dec 2023 12:23:28 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=QmraDL7EiHJusNTBmKq404QcRHhqD9isCoOntnGhREE=; b=GKlSyZyKaUErUVPD3/b/wo3VRI Ea/Rg0Z7cfOrv8KgD7ghQWyKdv0s+nW3opDztPJxWuvaiRKtEpE1k0AFVPgkeiYND7hiX70isu5l4 FsM38YbIgSBo7N8XEff+MvBosePnJCktGRQtIf2bvQeEyRBjgoC7OQCMc1ha/bM13EQo=; From: Julien Grall To: xen-devel@lists.xenproject.org Cc: julien@xen.org, Julien Grall , Andrew Cooper , George Dunlap , Jan Beulich , Stefano Stabellini , Wei Liu , =?utf-8?q?Roger_Pau_Monn=C3=A9?= Subject: [PATCH v2 1/2] xen/x86: io_apic: Introduce a command line option to skip timer check Date: Mon, 11 Dec 2023 12:23:21 +0000 Message-Id: <20231211122322.15815-2-julien@xen.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231211122322.15815-1-julien@xen.org> References: <20231211122322.15815-1-julien@xen.org> MIME-Version: 1.0 From: Julien Grall Currently, Xen will spend ~100ms to check if the timer works. If the Admin knows their platform have a working timer, then it would be handy to be able to bypass the check. Introduce a command line option 'pit-irq-works' for this purpose. Signed-off-by: Julien Grall --- Changelog since v1: - Rename the command line option. I went with pit-irq-works rather than timer-irq-works because Roger thought it would be better suited - Rework the command line description --- docs/misc/xen-command-line.pandoc | 11 +++++++++++ xen/arch/x86/io_apic.c | 11 +++++++++++ 2 files changed, 22 insertions(+) diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line.pandoc index 8e65f8bd18bf..c382b061b302 100644 --- a/docs/misc/xen-command-line.pandoc +++ b/docs/misc/xen-command-line.pandoc @@ -2535,6 +2535,17 @@ pages) must also be specified via the tbuf_size parameter. ### tickle_one_idle_cpu > `= ` +### pit-irq-works (x86) +> `=` + +> Default: `false` + +Disables the code which tests for broken timer IRQ sources. Enabling +this option will reduce boot time on HW where the timer works properly. + +If the system is unstable when enabling the option, then it means you +may have a broken HW and therefore the testing cannot be be skipped. + ### timer_slop > `= ` diff --git a/xen/arch/x86/io_apic.c b/xen/arch/x86/io_apic.c index d11c880544e6..238b6c1c2837 100644 --- a/xen/arch/x86/io_apic.c +++ b/xen/arch/x86/io_apic.c @@ -57,6 +57,14 @@ bool __initdata ioapic_ack_forced; int __read_mostly nr_ioapic_entries[MAX_IO_APICS]; int __read_mostly nr_ioapics; +/* + * The logic to check if the timer is working is expensive. So allow + * the admin to bypass it if they know their platform doesn't have + * a buggy timer. + */ +static bool __initdata pit_irq_works; +boolean_param("pit-irq-works", pit_irq_works); + /* * Rough estimation of how many shared IRQs there are, can * be changed anytime. @@ -1502,6 +1510,9 @@ static int __init timer_irq_works(void) { unsigned long t1, flags; + if ( pit_irq_works ) + return 1; + t1 = ACCESS_ONCE(pit0_ticks); local_save_flags(flags); From patchwork Mon Dec 11 12:23:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 13487164 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BC05BC10F07 for ; Mon, 11 Dec 2023 12:23:45 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.651732.1017524 (Exim 4.92) (envelope-from ) id 1rCfJq-0005hG-5E; Mon, 11 Dec 2023 12:23:30 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 651732.1017524; Mon, 11 Dec 2023 12:23:30 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rCfJq-0005h7-2e; Mon, 11 Dec 2023 12:23:30 +0000 Received: by outflank-mailman (input) for mailman id 651732; Mon, 11 Dec 2023 12:23:29 +0000 Received: from mail.xenproject.org ([104.130.215.37]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rCfJp-0005bX-AO for xen-devel@lists.xenproject.org; Mon, 11 Dec 2023 12:23:29 +0000 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1rCfJp-0003oZ-6F; Mon, 11 Dec 2023 12:23:29 +0000 Received: from 54-240-197-224.amazon.com ([54.240.197.224] helo=dev-dsk-jgrall-1b-035652ec.eu-west-1.amazon.com) by xenbits.xenproject.org with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.92) (envelope-from ) id 1rCfJo-0001JH-Uo; Mon, 11 Dec 2023 12:23:29 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=NOACs3hSf5sKsZ7DYPVi4JzNRj9JzZlqiodDxK0OPX8=; b=EA01PHDn8HByG6wWZ8jGzHOTUX XCWj3mgtucLQyaQglvRujJ7l7x1xPwTRPRDDr5yE6umdBm/hyJULEZRWXj/2pdIoARPdhVCu0Ady5 b3BUJrCiZGz8ZYpYvVl57L4/y4skwStKOXBzU0AjiLjhwS50kCcCBZaVCEK1Gfx7g6/A=; From: Julien Grall To: xen-devel@lists.xenproject.org Cc: julien@xen.org, Julien Grall , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu Subject: [PATCH v2 2/2] xen/x86: ioapic: Bail out from timer_irq_works() as soon as possible Date: Mon, 11 Dec 2023 12:23:22 +0000 Message-Id: <20231211122322.15815-3-julien@xen.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231211122322.15815-1-julien@xen.org> References: <20231211122322.15815-1-julien@xen.org> MIME-Version: 1.0 From: Julien Grall Currently timer_irq_works() will wait the full 100ms before checking that pit0_ticks has been incremented at least 4 times. However, the bulk of the BIOS/platform should not have a buggy timer. So waiting for the full 100ms is a bit harsh. Rework the logic to only wait until 100ms passed or we saw more than 4 ticks. So now, in the good case, this will reduce the wait time to ~50ms. Take the opportunity to change the prototype of timer_irq_works() to return a bool rather than int (which was already acting as a bool because only 0/1 could be returned). Signed-off-by: Julien Grall Reviewed-by: Jan Beulich --- Note that local_irq_restore() cannot be replaced with local_irq_disable() because the function is not consistently called with IRQs off. Changes in v2: - Return bool rather than int - Have a single return path - Use 'unsigned int' rather than 'unsigned long' for msec --- xen/arch/x86/io_apic.c | 39 ++++++++++++++++++++++++--------------- 1 file changed, 24 insertions(+), 15 deletions(-) diff --git a/xen/arch/x86/io_apic.c b/xen/arch/x86/io_apic.c index 238b6c1c2837..c89fbed8d675 100644 --- a/xen/arch/x86/io_apic.c +++ b/xen/arch/x86/io_apic.c @@ -1506,32 +1506,41 @@ static void __init setup_ioapic_ids_from_mpc(void) * - if this function detects that timer IRQs are defunct, then we fall * back to ISA timer IRQs */ -static int __init timer_irq_works(void) +static bool __init timer_irq_works(void) { unsigned long t1, flags; + /* Wait for maximum 10 ticks */ + unsigned int msec = (10 * 1000) / HZ; + bool works = false; if ( pit_irq_works ) - return 1; + return true; t1 = ACCESS_ONCE(pit0_ticks); local_save_flags(flags); local_irq_enable(); - /* Let ten ticks pass... */ - mdelay((10 * 1000) / HZ); - local_irq_restore(flags); - /* - * Expect a few ticks at least, to be sure some possible - * glue logic does not lock up after one or two first - * ticks in a non-ExtINT mode. Also the local APIC - * might have cached one ExtINT interrupt. Finally, at - * least one tick may be lost due to delays. - */ - if ( (ACCESS_ONCE(pit0_ticks) - t1) > 4 ) - return 1; + while ( msec-- ) + { + mdelay(1); + /* + * Expect a few ticks at least, to be sure some possible + * glue logic does not lock up after one or two first + * ticks in a non-ExtINT mode. Also the local APIC + * might have cached one ExtINT interrupt. Finally, at + * least one tick may be lost due to delays. + */ + if ( (ACCESS_ONCE(pit0_ticks) - t1) <= 4 ) + continue; - return 0; + works = true; + break; + } + + local_irq_restore(flags); + + return works; } /*