From patchwork Mon Dec 11 19:23:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 13488008 X-Patchwork-Delegate: kuba@kernel.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="XO2GCzu2" Received: from mail-wr1-x42b.google.com (mail-wr1-x42b.google.com [IPv6:2a00:1450:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 350B1DB; Mon, 11 Dec 2023 11:23:49 -0800 (PST) Received: by mail-wr1-x42b.google.com with SMTP id ffacd0b85a97d-33622099f23so1083364f8f.0; Mon, 11 Dec 2023 11:23:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1702322627; x=1702927427; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:message-id:date:subject:to :from:from:to:cc:subject:date:message-id:reply-to; bh=FMAmnGozTmnOuA6RhURhtT7TCK/lSA6JNDgFDLoxOaM=; b=XO2GCzu2aKGwSH59OF95+AMmxDmdW5F40llusnpBoYk+VsIf+BdnKzTNfnM19Vb2U6 S/1oAbH7BEAECd2ZpHrTV717E0hzMRMuNLF8u555PdsB2S1i7XR0B9EaBCLTltXDrCeW zbjyGz5NUTgWN+DNQYXpEtZYOTnqOK0MFqmRXz0B/+N5F8SzbV21YPPGJ4yM1pagff9T LftoB4OcxbHdCKiAaxhK+bIYUu7q4bZW8W5p8mqK3yz/P0/0GML+GLBEOlviy+0UTkHI Mg3J72dKDLs5ph28RCa50t+VPvJNfvobeKRk1hyj4iDgesI17txUtfrn2hKyIMHg9pdU Lvzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702322627; x=1702927427; h=content-transfer-encoding:mime-version:message-id:date:subject:to :from:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=FMAmnGozTmnOuA6RhURhtT7TCK/lSA6JNDgFDLoxOaM=; b=WTahHYYgRlphN24LAQvSZbN3QM7jjvukapGj7/Qja/TLPTLPz6EoIkbyBBtygNqJVA EQk9Vru52JRqhr8APOwJ5E4wzHwk59lHme08D/LJfnu7u5OzaDqXWBnxOkc7rUdOKAW+ gGsGwMg6THnhcrj7mzE2Sl27s9t+JR4BxyFinvCqh+7WmEDA2rDzFwYNekI5fGoHGOlc gWCU/I0Z9XezjJWbyWgREWSYjwIVfU2+jYtIz0DqExcO8R25iISLE6D7oo0JzA/qhp3m WxLVAIVeqF/bZOX0k7YKUdFL0saI/n/wpKIR1tz/5+2g29dBV6zHbYf7V5NceH6r2Nua GgTA== X-Gm-Message-State: AOJu0YxnNn1n8sSXIneCnv+BuTDclVy4DhIL/yIV2+AYBdPhrAxpfubO nmwxcuAWcWVgk8pDNk9HM9w= X-Google-Smtp-Source: AGHT+IFtdmo7V/lmVkSCPQOJpqTTDOnuKNEbSMdpyKAg5ARSKciKs28W9+CZtYd0k9trC6ofTaFqMQ== X-Received: by 2002:a1c:7213:0:b0:40c:25c8:12e1 with SMTP id n19-20020a1c7213000000b0040c25c812e1mr2282910wmc.12.1702322627280; Mon, 11 Dec 2023 11:23:47 -0800 (PST) Received: from localhost.localdomain (93-34-89-13.ip49.fastwebnet.it. [93.34.89.13]) by smtp.googlemail.com with ESMTPSA id d16-20020a5d4f90000000b0033349bccac6sm9325197wru.1.2023.12.11.11.23.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Dec 2023 11:23:46 -0800 (PST) From: Christian Marangi To: Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Christian Marangi , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [net-next RFC PATCH v2 1/4] dt-bindings: net: phy: Document new LEDs active-low property Date: Mon, 11 Dec 2023 20:23:15 +0100 Message-Id: <20231211192318.16450-1-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.40.1 Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org X-Patchwork-State: RFC Document new LEDs active-low property to define if the LED require to be set low to be turned on. active-low can be defined in the leds node for PHY that apply the LED polarity globally for each attached LED or in the specific led node for PHY that supports setting the LED polarity per LED. Declaring both way is not supported and will result in the schema getting rejected. Signed-off-by: Christian Marangi --- Changes v2: - Add this patch .../devicetree/bindings/net/ethernet-phy.yaml | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/Documentation/devicetree/bindings/net/ethernet-phy.yaml b/Documentation/devicetree/bindings/net/ethernet-phy.yaml index 8fb2a6ee7e5b..9cb3981fed2a 100644 --- a/Documentation/devicetree/bindings/net/ethernet-phy.yaml +++ b/Documentation/devicetree/bindings/net/ethernet-phy.yaml @@ -213,6 +213,11 @@ properties: '#size-cells': const: 0 + 'active-low': + type: boolean + description: + This define whether all LEDs needs to be low to be turned on. + patternProperties: '^led@[a-f0-9]+$': $ref: /schemas/leds/common.yaml# @@ -225,11 +230,26 @@ properties: driver dependent and required for ports that define multiple LED for the same port. + 'active-low': + type: boolean + description: + This define whether the LED needs to be low to be turned on. + required: - reg unevaluatedProperties: false + allOf: + - if: + required: + - active-low + then: + patternProperties: + '^led@[a-f0-9]+$': + properties: + 'active-low': false + additionalProperties: false required: From patchwork Mon Dec 11 19:23:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 13488009 X-Patchwork-Delegate: kuba@kernel.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="iyRODSwH" Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 45274C2; Mon, 11 Dec 2023 11:23:50 -0800 (PST) Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-3331752d2b9so3372723f8f.3; Mon, 11 Dec 2023 11:23:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1702322629; x=1702927429; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=EYjdgCjBy1xjm4sq4b9MMKYSKuGQZYYU7V1q9tmiNVY=; b=iyRODSwHj+iNxEJoXBB09Gp+sMj2d1nsu1voEj16V554A7qEIP6FGYYqKdyM9xXeVU eB6y/983sQXCTPF/2EveRpA/Wg2aE816tKjGeqtYviJvC5mF03yHHiC5JH6F5Gb8E3oE o1CuwV10oWJzXC3kpisgVq769mnxMQSBhW6o0JegkwsqK/GsFI7SuehEjOafkVFKiPIc v3MJzAXzPqDauwfQ3iBm4kz4cHRjlx+Dq/Q2pOqTQgeAsYYIoBLN9rlg6ws2eB8fTgYY 4vUTKGQ09jjin5Kqtkan2OFCwo/V3unbzDb9pbfy5se9bPBaPeXul+r7QTj6dNlw/+xG lxxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702322629; x=1702927429; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EYjdgCjBy1xjm4sq4b9MMKYSKuGQZYYU7V1q9tmiNVY=; b=gL9iGcwEBhWqC6TjFHGh+6goZ+Y/3D4qs1vbyf/sfDGt9N84wlYSa1wU3bROt/3m28 miz7uN45QRvO0OOVcVFstRq05EsG/7EgGcr0pE5nOmJrPrA8ftMLfj7s4Hk1JqvQCUhh LyB9e0Y4kcy6ifOb3EuW/tY8DyvlJEj08K1GvEt1GKLrcPPFPYHI3YvD7H0efqqOl7p7 h3ycU2IQpe1s5Dsl+CZgUf1DX4vglKO56RsV4tr44h0VvYNlTMKYAX8lzqqSJnmv7cu+ AExR8qnXwnlVV0d5cgm39u6F6B3Af5YUc30g7hr4ghRBrZPVy3T3PZuT78Mmqlc+g2Af 5FRg== X-Gm-Message-State: AOJu0YyiMwUFRl1pLjsRaSNytpAFP5oFPGoaquowb1wPu1Z9ggTIfrQa AIzmBbQ0ObPWa5tt9LDVOTg= X-Google-Smtp-Source: AGHT+IErC/unZPo5UcQrreZvu9jhxCd5GdZE+uC3hpS1AMZTVYN5pCWLuq6a2T7oisJT3dEeFtl4dg== X-Received: by 2002:adf:ebc4:0:b0:333:2fd2:8146 with SMTP id v4-20020adfebc4000000b003332fd28146mr3226090wrn.99.1702322628469; Mon, 11 Dec 2023 11:23:48 -0800 (PST) Received: from localhost.localdomain (93-34-89-13.ip49.fastwebnet.it. [93.34.89.13]) by smtp.googlemail.com with ESMTPSA id d16-20020a5d4f90000000b0033349bccac6sm9325197wru.1.2023.12.11.11.23.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Dec 2023 11:23:48 -0800 (PST) From: Christian Marangi To: Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Christian Marangi , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [net-next RFC PATCH v2 2/4] net: phy: add support for PHY LEDs active-low Date: Mon, 11 Dec 2023 20:23:16 +0100 Message-Id: <20231211192318.16450-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231211192318.16450-1-ansuelsmth@gmail.com> References: <20231211192318.16450-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org X-Patchwork-State: RFC Add support for PHY LEDs active-low. Some PHY require LED to be set to active low to be turned on. Adds support for this by declaring active-low property in DT. Active-low can be defined in 2 different way: - In leds node to apply the active low setting globally for every LED. - In each led to apply the active low setting per LED (if supported). PHY driver needs to declare .led_polarity_set() to configure LED polarity. Index will be -1 if the option is set globally or will indicate the LED to apply the polarity settings. Function finally pass a bool to indicate if LED has to be set active low. .led_polarity_set() is called for both leds node and for each led subnode. PHY driver will ignore the additional call based on the passed index value if global setting or per LED setting is supported. Signed-off-by: Christian Marangi --- Changes v2: - Add this patch drivers/net/phy/phy_device.c | 18 ++++++++++++++++++ include/linux/phy.h | 15 +++++++++++++++ 2 files changed, 33 insertions(+) diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c index d8e9335d415c..a9f5d250abff 100644 --- a/drivers/net/phy/phy_device.c +++ b/drivers/net/phy/phy_device.c @@ -3093,6 +3093,7 @@ static int of_phy_led(struct phy_device *phydev, struct led_init_data init_data = {}; struct led_classdev *cdev; struct phy_led *phyled; + bool active_low; u32 index; int err; @@ -3109,6 +3110,13 @@ static int of_phy_led(struct phy_device *phydev, if (index > U8_MAX) return -EINVAL; + active_low = of_property_read_bool(led, "active-low"); + if (phydev->drv->led_polarity_set) { + err = phydev->drv->led_polarity_set(phydev, index, active_low); + if (err) + return err; + } + phyled->index = index; if (phydev->drv->led_brightness_set) cdev->brightness_set_blocking = phy_led_set_brightness; @@ -3145,6 +3153,7 @@ static int of_phy_leds(struct phy_device *phydev) { struct device_node *node = phydev->mdio.dev.of_node; struct device_node *leds, *led; + bool active_low; int err; if (!IS_ENABLED(CONFIG_OF_MDIO)) @@ -3157,6 +3166,15 @@ static int of_phy_leds(struct phy_device *phydev) if (!leds) return 0; + active_low = of_property_read_bool(leds, "active-low"); + if (phydev->drv->led_polarity_set) { + err = phydev->drv->led_polarity_set(phydev, -1, active_low); + if (err) { + of_node_put(leds); + return err; + } + } + for_each_available_child_of_node(leds, led) { err = of_phy_led(phydev, led); if (err) { diff --git a/include/linux/phy.h b/include/linux/phy.h index 6e7ebcc50b85..cbdebf174361 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -1145,6 +1145,21 @@ struct phy_driver { int (*led_hw_control_get)(struct phy_device *dev, u8 index, unsigned long *rules); + /** + * @led_polarity_set: Set the LED polarity if active low + * @dev: PHY device which has the LED + * @index: Which LED of the PHY device or -1 + * @active_low: LED needs to be set low to turn on + * + * Set the PHY to require the LED low to turn on. + * index can be the LED of the PHY device or -1 whether the + * LED polatiry is global and applied to every LED or polarity + * is set per LED. + * + * Returns 0, or an error code. + */ + int (*led_polarity_set)(struct phy_device *dev, int index, + bool active_low); }; #define to_phy_driver(d) container_of(to_mdio_common_driver(d), \ struct phy_driver, mdiodrv) From patchwork Mon Dec 11 19:23:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 13488010 X-Patchwork-Delegate: kuba@kernel.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="AIE9IMlm" Received: from mail-wm1-x333.google.com (mail-wm1-x333.google.com [IPv6:2a00:1450:4864:20::333]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A206FCF; Mon, 11 Dec 2023 11:23:51 -0800 (PST) Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-40c2bb872e2so44963955e9.3; Mon, 11 Dec 2023 11:23:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1702322630; x=1702927430; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; 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[93.34.89.13]) by smtp.googlemail.com with ESMTPSA id d16-20020a5d4f90000000b0033349bccac6sm9325197wru.1.2023.12.11.11.23.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Dec 2023 11:23:49 -0800 (PST) From: Christian Marangi To: Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Christian Marangi , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [net-next RFC PATCH v2 3/4] dt-bindings: net: Document QCA808x PHYs Date: Mon, 11 Dec 2023 20:23:17 +0100 Message-Id: <20231211192318.16450-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231211192318.16450-1-ansuelsmth@gmail.com> References: <20231211192318.16450-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org X-Patchwork-State: RFC Add Documentation for QCA808x PHYs for the additional LED configuration for this PHY. Signed-off-by: Christian Marangi --- Changes v2: - Fix License warning from checkpatch - Drop redundant Description phrase - Improve commit tile - Drop special property (generalized) .../devicetree/bindings/net/qca,qca808x.yaml | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/qca,qca808x.yaml diff --git a/Documentation/devicetree/bindings/net/qca,qca808x.yaml b/Documentation/devicetree/bindings/net/qca,qca808x.yaml new file mode 100644 index 000000000000..ec8b31324df5 --- /dev/null +++ b/Documentation/devicetree/bindings/net/qca,qca808x.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/qca,qca808x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Atheros QCA808X PHY + +maintainers: + - Christian Marangi + +description: + QCA808X PHYs can have up to 3 LEDs attached. + All 3 LEDs are disabled by default. + 2 LEDs have dedicated pins with the 3rd LED having the + double function of Interrupt LEDs/GPIO or additional LED. + + By default this special PIN is set to LED function. + +allOf: + - $ref: ethernet-phy.yaml# + +select: + properties: + compatible: + contains: + enum: + - ethernet-phy-id004d.d101 + required: + - compatible + +unevaluatedProperties: false + +examples: + - | + #include + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy@0 { + compatible = "ethernet-phy-id004d.d101"; + reg = <0>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_WAN; + default-state = "keep"; + }; + }; + }; + }; From patchwork Mon Dec 11 19:23:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 13488011 X-Patchwork-Delegate: kuba@kernel.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Blz6OpUJ" Received: from mail-wm1-x334.google.com (mail-wm1-x334.google.com [IPv6:2a00:1450:4864:20::334]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E606ABD; Mon, 11 Dec 2023 11:23:52 -0800 (PST) Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-40c2bb872e2so44964235e9.3; Mon, 11 Dec 2023 11:23:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1702322631; x=1702927431; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=IZKiTX9BD+LjmXPy11VkmgehaPi+FcKU4VbiOrCP5N8=; b=Blz6OpUJd3H+IQPqUSF8yYRe9yrqpX0ZCEZlIqWY2767CGNUyI+47P+Dr0T5sO3jcR zUQVm27kP7tuSwruu3kKa/owGFcHQlE6cHFDZCW8d+CSZpk/7rsfJccVlXD5S+FMRD/K sLz4ssRhnvUuUV3A3BtZnHtcufxu+GcEjkhwWOdbMA5rZ0V2X3jkFeBLSs247D5LNWGx u01I6b3IkUbgMomdWoY1zw2J40kCShan6arbxrlciALiFD07WDBxH4zCk/ta4iPREBHW 28GsCxhxXiv4yLgEgXUBz8omft7NzneW8NdOHcVx3OLGW2FgwAyRF3Fs6NA5NSlYXjOz KHhg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702322631; x=1702927431; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IZKiTX9BD+LjmXPy11VkmgehaPi+FcKU4VbiOrCP5N8=; b=iR5LZt36V5A6xNGbru/0shO/fhyQvpSAdDr12BBYwsvrOEIqLh3/scoLxVMjCQjZT5 Lfrtau1+GwUb75JG71vkFowHCACbCHPWmYrh/MJnztjU3xIs22kUKYrNO3uGdjcz3VlL 7R3rJjB+Ua8jjHXNs9jfM4hRGMRy5brq4UtxMMOlGEJdBfJNcFgMe88lqXZn1lQcjbPh XAOKBhwgblZDS3E8+N6+NfcFrOJa3VBOvBz/nOn+PmTV2qGoOZzbmVp79t47xjk96mcz 1X4sbuyJrp6h1h63xXEw5JdRyV3oKb5zYbs+iglFgDobjKPIzaNBhmljSCJzdSswPrVX jNyA== X-Gm-Message-State: AOJu0Yx6/a0ztkubHs5wHSBNP1sH02UqkigTGqpHakixEsSFFO1y9gJi M9tqVyDLisIEGGpN/mGZ/hc= X-Google-Smtp-Source: AGHT+IFuRj9yy+mZXTIua18Df33OUT5QGECOae+sphV38pFicAsmXS0a+ZHS5hXdabCRy5GXcfCXog== X-Received: by 2002:a05:600c:1ca9:b0:40b:5f03:b3b1 with SMTP id k41-20020a05600c1ca900b0040b5f03b3b1mr1453422wms.211.1702322631111; Mon, 11 Dec 2023 11:23:51 -0800 (PST) Received: from localhost.localdomain (93-34-89-13.ip49.fastwebnet.it. [93.34.89.13]) by smtp.googlemail.com with ESMTPSA id d16-20020a5d4f90000000b0033349bccac6sm9325197wru.1.2023.12.11.11.23.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Dec 2023 11:23:50 -0800 (PST) From: Christian Marangi To: Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Christian Marangi , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [net-next RFC PATCH v2 4/4] net: phy: at803x: add LED support for qca808x Date: Mon, 11 Dec 2023 20:23:18 +0100 Message-Id: <20231211192318.16450-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231211192318.16450-1-ansuelsmth@gmail.com> References: <20231211192318.16450-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org X-Patchwork-State: RFC Add LED support for QCA8081 PHY. Documentation for this LEDs PHY is very scarce even with NDA access to Documentation for OEMs. Only the blink pattern are documented and are very confusing most of the time. No documentation is present about forcing the LED on/off or to always blink. Those settings were reversed by poking the regs and trying to find the correct bits to trigger these modes. Some bits mode are not clear and maybe the documentation option are not 100% correct. For the sake of LED support the reversed option are enough to add support for current LED APIs. Supported HW control modes are: - tx - rx - link10 - link100 - link1000 - link2500 - half_duplex - full_duplex Also add support for LED polarity set to set LED polarity to active high or low. QSDK sets this value to high by default but PHY reset value doesn't have this enabled by default. QSDK also sets 2 additional bits but their usage is not clear, info about this is added in the header. It was verified that for correct function of the LED if active high is needed, only BIT 6 is needed. Signed-off-by: Christian Marangi --- This depends on a recent commit megred in Lee LEDs repository that adds additional link speed mode to the netdev trigger Changes v2: - Move to new led_polarity_set implementation - Drop special probe drivers/net/phy/at803x.c | 283 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 283 insertions(+) diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index 37fb033e1c29..78c87eea76cc 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -272,6 +272,69 @@ #define QCA808X_CDT_STATUS_STAT_OPEN 2 #define QCA808X_CDT_STATUS_STAT_SHORT 3 +#define QCA808X_MMD7_LED2_CTRL 0x8074 +#define QCA808X_MMD7_LED2_FORCE_CTRL 0x8075 +#define QCA808X_MMD7_LED1_CTRL 0x8076 +#define QCA808X_MMD7_LED1_FORCE_CTRL 0x8077 +#define QCA808X_MMD7_LED0_CTRL 0x8078 +#define QCA808X_MMD7_LED_CTRL(x) (0x8078 - ((x) * 2)) + +/* LED hw control pattern is the same for every LED */ +#define QCA808X_LED_PATTERN_MASK GENMASK(15, 0) +#define QCA808X_LED_SPEED2500_ON BIT(15) +#define QCA808X_LED_SPEED2500_BLINK BIT(14) +/* Follow blink trigger even if duplex or speed condition doesn't match */ +#define QCA808X_LED_BLINK_CHECK_BYPASS BIT(13) +#define QCA808X_LED_FULL_DUPLEX_ON BIT(12) +#define QCA808X_LED_HALF_DUPLEX_ON BIT(11) +#define QCA808X_LED_TX_BLINK BIT(10) +#define QCA808X_LED_RX_BLINK BIT(9) +#define QCA808X_LED_TX_ON_10MS BIT(8) +#define QCA808X_LED_RX_ON_10MS BIT(7) +#define QCA808X_LED_SPEED1000_ON BIT(6) +#define QCA808X_LED_SPEED100_ON BIT(5) +#define QCA808X_LED_SPEED10_ON BIT(4) +#define QCA808X_LED_COLLISION_BLINK BIT(3) +#define QCA808X_LED_SPEED1000_BLINK BIT(2) +#define QCA808X_LED_SPEED100_BLINK BIT(1) +#define QCA808X_LED_SPEED10_BLINK BIT(0) + +#define QCA808X_MMD7_LED0_FORCE_CTRL 0x8079 +#define QCA808X_MMD7_LED_FORCE_CTRL(x) (0x8079 - ((x) * 2)) + +/* LED force ctrl is the same for every LED + * No documentation exist for this, not even internal one + * with NDA as QCOM gives only info about configuring + * hw control pattern rules and doesn't indicate any way + * to force the LED to specific mode. + * These define comes from reverse and testing and maybe + * lack of some info or some info are not entirely correct. + * For the basic LED control and hw control these finding + * are enough to support LED control in all the required APIs. + */ +#define QCA808X_LED_FORCE_MASK GENMASK(15, 13) +#define QCA808X_LED_FORCE_BLINK_8HZ FIELD_PREP(QCA808X_LED_FORCE_MASK, 0x7) +#define QCA808X_LED_FORCE_BLINK_4HZ FIELD_PREP(QCA808X_LED_FORCE_MASK, 0x6) +#define QCA808X_LED_FORCE_ON FIELD_PREP(QCA808X_LED_FORCE_MASK, 0x5) +#define QCA808X_LED_FORCE_OFF FIELD_PREP(QCA808X_LED_FORCE_MASK, 0x4) +/* HW control option are confusing: + * - 0x3 is 50% on 50% off at 4hz + * - 0x2 is 75% on 25% off at 4hz + * - 0x1 is 25% on 75% off at 4hz + * - 0x0 is 50% on 50% off at 8hz and is set by default + * This comes from visual check and may not be 100% correct. + */ +#define QCA808X_LED_HW_CONTROL_50_50_4HZ FIELD_PREP(QCA808X_LED_FORCE_MASK, 0x3) +#define QCA808X_LED_HW_CONTROL_75_25 FIELD_PREP(QCA808X_LED_FORCE_MASK, 0x2) +#define QCA808X_LED_HW_CONTROL_25_75 FIELD_PREP(QCA808X_LED_FORCE_MASK, 0x1) +#define QCA808X_LED_HW_CONTROL_50_50_8HZ FIELD_PREP(QCA808X_LED_FORCE_MASK, 0x0) + +#define QCA808X_MMD7_LED_POLARITY_CTRL 0x901a +/* QSDK sets by default 0x46 to this reg that sets BIT 6 for + * LED to active high. It's not clear what BIT 3 and BIT 4 does. + */ +#define QCA808X_LED_ACTIVE_HIGH BIT(6) + /* QCA808X 1G chip type */ #define QCA808X_PHY_MMD7_CHIP_TYPE 0x901d #define QCA808X_PHY_CHIP_TYPE_1G BIT(0) @@ -2050,6 +2113,220 @@ static void qca808x_link_change_notify(struct phy_device *phydev) QCA8081_PHY_FIFO_RSTN, phydev->link ? QCA8081_PHY_FIFO_RSTN : 0); } +static int qca808x_led_parse_netdev(struct phy_device *phydev, unsigned long rules, + u16 *offload_trigger) +{ + /* Parsing specific to netdev trigger */ + if (test_bit(TRIGGER_NETDEV_TX, &rules)) + *offload_trigger |= QCA808X_LED_TX_BLINK; + if (test_bit(TRIGGER_NETDEV_RX, &rules)) + *offload_trigger |= QCA808X_LED_RX_BLINK; + if (test_bit(TRIGGER_NETDEV_LINK_10, &rules)) + *offload_trigger |= QCA808X_LED_SPEED10_ON; + if (test_bit(TRIGGER_NETDEV_LINK_100, &rules)) + *offload_trigger |= QCA808X_LED_SPEED100_ON; + if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules)) + *offload_trigger |= QCA808X_LED_SPEED1000_ON; + if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules)) + *offload_trigger |= QCA808X_LED_SPEED2500_ON; + if (test_bit(TRIGGER_NETDEV_HALF_DUPLEX, &rules)) + *offload_trigger |= QCA808X_LED_HALF_DUPLEX_ON; + if (test_bit(TRIGGER_NETDEV_FULL_DUPLEX, &rules)) + *offload_trigger |= QCA808X_LED_FULL_DUPLEX_ON; + + if (rules && !*offload_trigger) + return -EOPNOTSUPP; + + /* Enable BLINK_CHECK_BYPASS by default to make the LED + * blink even with duplex or speed mode not enabled. + */ + *offload_trigger |= QCA808X_LED_BLINK_CHECK_BYPASS; + + return 0; +} + +static int qca808x_led_hw_control_enable(struct phy_device *phydev, u8 index) +{ + u16 reg; + + if (index > 2) + return -EINVAL; + + reg = QCA808X_MMD7_LED_FORCE_CTRL(index); + + return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg, + QCA808X_LED_FORCE_MASK); +} + +static int qca808x_led_hw_is_supported(struct phy_device *phydev, u8 index, + unsigned long rules) +{ + u16 offload_trigger = 0; + + if (index > 2) + return -EINVAL; + + return qca808x_led_parse_netdev(phydev, rules, &offload_trigger); +} + +static int qca808x_led_hw_control_set(struct phy_device *phydev, u8 index, + unsigned long rules) +{ + u16 reg, offload_trigger = 0; + int ret; + + if (index > 2) + return -EINVAL; + + reg = QCA808X_MMD7_LED_CTRL(index); + + ret = qca808x_led_parse_netdev(phydev, rules, &offload_trigger); + if (ret) + return ret; + + ret = qca808x_led_hw_control_enable(phydev, index); + if (ret) + return ret; + + return phy_modify_mmd(phydev, MDIO_MMD_AN, reg, + QCA808X_LED_PATTERN_MASK, + offload_trigger); +} + +static bool qca808x_led_hw_control_status(struct phy_device *phydev, u8 index) +{ + u16 reg; + int val; + + if (index > 2) + return false; + + reg = QCA808X_MMD7_LED_FORCE_CTRL(index); + + val = phy_read_mmd(phydev, MDIO_MMD_AN, reg); + + return !(val & QCA808X_LED_FORCE_MASK); +} + +static int qca808x_led_hw_control_get(struct phy_device *phydev, u8 index, + unsigned long *rules) +{ + u16 reg; + int val; + + if (index > 2) + return -EINVAL; + + /* Check if we have hw control enabled */ + if (qca808x_led_hw_control_status(phydev, index)) + return -EINVAL; + + reg = QCA808X_MMD7_LED_CTRL(index); + + val = phy_read_mmd(phydev, MDIO_MMD_AN, reg); + if (val & QCA808X_LED_TX_BLINK) + set_bit(TRIGGER_NETDEV_TX, rules); + if (val & QCA808X_LED_RX_BLINK) + set_bit(TRIGGER_NETDEV_RX, rules); + if (val & QCA808X_LED_SPEED10_ON) + set_bit(TRIGGER_NETDEV_LINK_10, rules); + if (val & QCA808X_LED_SPEED100_ON) + set_bit(TRIGGER_NETDEV_LINK_100, rules); + if (val & QCA808X_LED_SPEED1000_ON) + set_bit(TRIGGER_NETDEV_LINK_1000, rules); + if (val & QCA808X_LED_SPEED2500_ON) + set_bit(TRIGGER_NETDEV_LINK_2500, rules); + if (val & QCA808X_LED_HALF_DUPLEX_ON) + set_bit(TRIGGER_NETDEV_HALF_DUPLEX, rules); + if (val & QCA808X_LED_FULL_DUPLEX_ON) + set_bit(TRIGGER_NETDEV_FULL_DUPLEX, rules); + + return 0; +} + +static int qca808x_led_hw_control_reset(struct phy_device *phydev, u8 index) +{ + u16 reg; + + if (index > 2) + return -EINVAL; + + reg = QCA808X_MMD7_LED_CTRL(index); + + return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg, + QCA808X_LED_PATTERN_MASK); +} + +static int qca808x_led_brightness_set(struct phy_device *phydev, + u8 index, enum led_brightness value) +{ + u16 reg; + int ret; + + if (index > 2) + return -EINVAL; + + if (!value) { + ret = qca808x_led_hw_control_reset(phydev, index); + if (ret) + return ret; + } + + reg = QCA808X_MMD7_LED_FORCE_CTRL(index); + + return phy_modify_mmd(phydev, MDIO_MMD_AN, reg, + QCA808X_LED_FORCE_MASK, + value ? QCA808X_LED_FORCE_ON : + QCA808X_LED_FORCE_OFF); +} + +static int qca808x_led_blink_set(struct phy_device *phydev, u8 index, + unsigned long *delay_on, + unsigned long *delay_off) +{ + u16 reg; + int ret; + + if (index > 2) + return -EINVAL; + + reg = QCA808X_MMD7_LED_FORCE_CTRL(index); + + ret = phy_modify_mmd(phydev, MDIO_MMD_AN, reg, + QCA808X_LED_FORCE_MASK, + QCA808X_LED_FORCE_BLINK_4HZ); + if (ret) + return ret; + + /* We set blink to 4Hz, aka 250ms */ + *delay_on = 250 / 2; + *delay_off = 250 / 2; + + return 0; +} + +static int qca808x_led_polarity_set(struct phy_device *phydev, int index, + bool active_low) +{ + int ret; + + /* Ignore calling LED polarity set for LED node */ + if (index >= 0) + return 0; + + if (active_low) { + ret = phy_clear_bits_mmd(phydev, MDIO_MMD_AN, + QCA808X_MMD7_LED_POLARITY_CTRL, + QCA808X_LED_ACTIVE_HIGH); + } else { + ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, + QCA808X_MMD7_LED_POLARITY_CTRL, + QCA808X_LED_ACTIVE_HIGH); + } + + return ret; +} + static struct phy_driver at803x_driver[] = { { /* Qualcomm Atheros AR8035 */ @@ -2227,6 +2504,12 @@ static struct phy_driver at803x_driver[] = { .cable_test_start = qca808x_cable_test_start, .cable_test_get_status = qca808x_cable_test_get_status, .link_change_notify = qca808x_link_change_notify, + .led_brightness_set = qca808x_led_brightness_set, + .led_blink_set = qca808x_led_blink_set, + .led_hw_is_supported = qca808x_led_hw_is_supported, + .led_hw_control_set = qca808x_led_hw_control_set, + .led_hw_control_get = qca808x_led_hw_control_get, + .led_polarity_set = qca808x_led_polarity_set, }, }; module_phy_driver(at803x_driver);