From patchwork Mon Dec 11 21:37:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 13488112 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CC810C4332F for ; Mon, 11 Dec 2023 21:38:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1AD2210E158; Mon, 11 Dec 2023 21:38:30 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7A32110E0FB for ; Mon, 11 Dec 2023 21:38:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1702330707; x=1733866707; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=bzK5eNSOrHeGL8ouJnrLvyRmV1Ppxynx+Z+R/vu2bak=; b=Rmj7p47/V85Xx9WAe0pm30voc+nR6Y6311VOPvMfU2ueCGx5p+RQLo+O l0wZa31kW3mwCQtRO5z88KLFiHRh1WUfK3JaI8EhZnVyhSY+GE+oATfLC CNuJIT88KX5JZuyV5C67EDZN1hs8m/px1iBm3J3J4222pIpBCNzMM92W7 jqkxe11eWNmI8s/HVw1DFUhRISOWUlQo3EYeZrRWx71MEEXQ/FUkUb5D6 fV25kTHPw6zrquX//JO+3IExNqKzo3ZJgWjOPdvrqTOBvclLh6FI0Pbp9 4LxdLDRVhNP6fP1VU9tlJispj3k87bkkmEife8CTV5WinUMuwzATA3mlo w==; X-IronPort-AV: E=McAfee;i="6600,9927,10921"; a="379712231" X-IronPort-AV: E=Sophos;i="6.04,268,1695711600"; d="scan'208";a="379712231" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Dec 2023 13:37:56 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10921"; a="766547032" X-IronPort-AV: E=Sophos;i="6.04,268,1695711600"; d="scan'208";a="766547032" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by orsmga007.jf.intel.com with SMTP; 11 Dec 2023 13:37:54 -0800 Received: by stinkbox (sSMTP sendmail emulation); Mon, 11 Dec 2023 23:37:53 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 1/4] drm/i915/dmc: Don't enable any pipe DMC events Date: Mon, 11 Dec 2023 23:37:47 +0200 Message-ID: <20231211213750.27109-2-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231211213750.27109-1-ville.syrjala@linux.intel.com> References: <20231211213750.27109-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: stable@vger.kernel.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä The pipe DMC seems to be making a mess of things in ADL. Various weird symptoms have been observed such as missing vblank irqs, typicalle happening when using multiple displays. Keep all pipe DMC event handlers disabled until needed (which is never atm). This is also what Windows does on ADL+. We can also drop DG2 from disable_all_flip_queue_events() since on DG2 the pipe DMC is the one that handles the flip queue events. Cc: stable@vger.kernel.org Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8685 Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dmc.c | 43 ++++++++++++++++++++++-- 1 file changed, 41 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c index 63e080e07023..073b85b57679 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc.c +++ b/drivers/gpu/drm/i915/display/intel_dmc.c @@ -389,7 +389,7 @@ disable_all_flip_queue_events(struct drm_i915_private *i915) enum intel_dmc_id dmc_id; /* TODO: check if the following applies to all D13+ platforms. */ - if (!IS_DG2(i915) && !IS_TIGERLAKE(i915)) + if (!IS_TIGERLAKE(i915)) return; for_each_dmc_id(dmc_id) { @@ -493,6 +493,45 @@ void intel_dmc_disable_pipe(struct drm_i915_private *i915, enum pipe pipe) intel_de_rmw(i915, PIPEDMC_CONTROL(pipe), PIPEDMC_ENABLE, 0); } +static bool is_dmc_evt_ctl_reg(struct drm_i915_private *i915, + enum intel_dmc_id dmc_id, i915_reg_t reg) +{ + u32 offset = i915_mmio_reg_offset(reg); + u32 start = i915_mmio_reg_offset(DMC_EVT_CTL(i915, dmc_id, 0)); + u32 end = i915_mmio_reg_offset(DMC_EVT_CTL(i915, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12)); + + return offset >= start && offset < end; +} + +static bool disable_dmc_evt(struct drm_i915_private *i915, + enum intel_dmc_id dmc_id, + i915_reg_t reg, u32 data) +{ + if (!is_dmc_evt_ctl_reg(i915, dmc_id, reg)) + return false; + + /* keep all pipe DMC events disabled by default */ + if (dmc_id != DMC_FW_MAIN) + return true; + + return false; +} + +static u32 dmc_mmiodata(struct drm_i915_private *i915, + struct intel_dmc *dmc, + enum intel_dmc_id dmc_id, int i) +{ + if (disable_dmc_evt(i915, dmc_id, + dmc->dmc_info[dmc_id].mmioaddr[i], + dmc->dmc_info[dmc_id].mmiodata[i])) + return REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK, + DMC_EVT_CTL_TYPE_EDGE_0_1) | + REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK, + DMC_EVT_CTL_EVENT_ID_FALSE); + else + return dmc->dmc_info[dmc_id].mmiodata[i]; +} + /** * intel_dmc_load_program() - write the firmware from memory to register. * @i915: i915 drm device. @@ -532,7 +571,7 @@ void intel_dmc_load_program(struct drm_i915_private *i915) for_each_dmc_id(dmc_id) { for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) { intel_de_write(i915, dmc->dmc_info[dmc_id].mmioaddr[i], - dmc->dmc_info[dmc_id].mmiodata[i]); + dmc_mmiodata(i915, dmc, dmc_id, i)); } } From patchwork Mon Dec 11 21:37:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 13488113 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CA80EC4332F for ; Mon, 11 Dec 2023 21:38:35 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3308010E506; Mon, 11 Dec 2023 21:38:33 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id C192210E506 for ; Mon, 11 Dec 2023 21:38:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1702330710; x=1733866710; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=DqQiTWmi9AHvG9GJFdwNwYAwjyVd+0k9nQ740uhSm6k=; b=BC8pRqISXNStvIMPWJZZP/kaRO4nOWZovj6EjzTTzOreEdtUBkpKZpN/ viMLbhxsIGziXXfQCLyQtbK09noR8TA0TgvYtEYkATGFPRRt1A79T5xUA JwI+7Os29LDL67bpmW+e+7JsCFKqNTWC4/Pc1qu1tD1D+oPDbtUkAGpzy kGzeXY+R9Dhg/Ie0Zz1A6cQhUzmaeu+MB3p8t4gpqG8PRynwmav/mmbMe /PkKZl9LXlAyIRG+UHRmAcrgNCQcD0OY4C/nNAjQsyBVk4zxXNqTyI+8A 0IWawB6oanRrkmkC8xZL7azQONva8HmaX2PlRdYH0KJvEAdhaCmMD1Y8x w==; X-IronPort-AV: E=McAfee;i="6600,9927,10921"; a="379712248" X-IronPort-AV: E=Sophos;i="6.04,268,1695711600"; d="scan'208";a="379712248" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Dec 2023 13:37:59 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10921"; a="766547048" X-IronPort-AV: E=Sophos;i="6.04,268,1695711600"; d="scan'208";a="766547048" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by orsmga007.jf.intel.com with SMTP; 11 Dec 2023 13:37:57 -0800 Received: by stinkbox (sSMTP sendmail emulation); Mon, 11 Dec 2023 23:37:56 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 2/4] drm/i915/dmc: Also disable the flip queue event on TGL main DMC Date: Mon, 11 Dec 2023 23:37:48 +0200 Message-ID: <20231211213750.27109-3-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231211213750.27109-1-ville.syrjala@linux.intel.com> References: <20231211213750.27109-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Unlike later platforms TGL has its flip queue event (CLK_MSEC) on the main DMC (as opposed to the pipe DMC). Currently we're doing a second pass to disable that, but let's just follow the same approach as the later platforms and never even enable the event in the first place. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dmc.c | 83 ++---------------------- 1 file changed, 5 insertions(+), 78 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c index 073b85b57679..9385898e3aa5 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc.c +++ b/drivers/gpu/drm/i915/display/intel_dmc.c @@ -335,77 +335,6 @@ static void disable_event_handler(struct drm_i915_private *i915, intel_de_write(i915, htp_reg, 0); } -static void -disable_flip_queue_event(struct drm_i915_private *i915, - i915_reg_t ctl_reg, i915_reg_t htp_reg) -{ - u32 event_ctl; - u32 event_htp; - - event_ctl = intel_de_read(i915, ctl_reg); - event_htp = intel_de_read(i915, htp_reg); - if (event_ctl != (DMC_EVT_CTL_ENABLE | - DMC_EVT_CTL_RECURRING | - REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK, - DMC_EVT_CTL_TYPE_EDGE_0_1) | - REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK, - DMC_EVT_CTL_EVENT_ID_CLK_MSEC)) || - !event_htp) { - drm_dbg_kms(&i915->drm, - "Unexpected DMC event configuration (control %08x htp %08x)\n", - event_ctl, event_htp); - return; - } - - disable_event_handler(i915, ctl_reg, htp_reg); -} - -static bool -get_flip_queue_event_regs(struct drm_i915_private *i915, enum intel_dmc_id dmc_id, - i915_reg_t *ctl_reg, i915_reg_t *htp_reg) -{ - if (dmc_id == DMC_FW_MAIN) { - if (DISPLAY_VER(i915) == 12) { - *ctl_reg = DMC_EVT_CTL(i915, dmc_id, 3); - *htp_reg = DMC_EVT_HTP(i915, dmc_id, 3); - - return true; - } - } else if (dmc_id >= DMC_FW_PIPEA && dmc_id <= DMC_FW_PIPED) { - if (IS_DG2(i915)) { - *ctl_reg = DMC_EVT_CTL(i915, dmc_id, 2); - *htp_reg = DMC_EVT_HTP(i915, dmc_id, 2); - - return true; - } - } - - return false; -} - -static void -disable_all_flip_queue_events(struct drm_i915_private *i915) -{ - enum intel_dmc_id dmc_id; - - /* TODO: check if the following applies to all D13+ platforms. */ - if (!IS_TIGERLAKE(i915)) - return; - - for_each_dmc_id(dmc_id) { - i915_reg_t ctl_reg; - i915_reg_t htp_reg; - - if (!has_dmc_id_fw(i915, dmc_id)) - continue; - - if (!get_flip_queue_event_regs(i915, dmc_id, &ctl_reg, &htp_reg)) - continue; - - disable_flip_queue_event(i915, ctl_reg, htp_reg); - } -} - static void disable_all_event_handlers(struct drm_i915_private *i915) { enum intel_dmc_id dmc_id; @@ -514,6 +443,11 @@ static bool disable_dmc_evt(struct drm_i915_private *i915, if (dmc_id != DMC_FW_MAIN) return true; + /* also disable the flip queue event on the main DMC on TGL */ + if (IS_TIGERLAKE(i915) && + REG_FIELD_GET(DMC_EVT_CTL_EVENT_ID_MASK, data) == DMC_EVT_CTL_EVENT_ID_CLK_MSEC) + return true; + return false; } @@ -579,13 +513,6 @@ void intel_dmc_load_program(struct drm_i915_private *i915) gen9_set_dc_state_debugmask(i915); - /* - * Flip queue events need to be disabled before enabling DC5/6. - * i915 doesn't use the flip queue feature, so disable it already - * here. - */ - disable_all_flip_queue_events(i915); - pipedmc_clock_gating_wa(i915, false); } From patchwork Mon Dec 11 21:37:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 13488114 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5A6E6C4167B for ; Mon, 11 Dec 2023 21:38:37 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2A7F110E507; Mon, 11 Dec 2023 21:38:34 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9B31010E506 for ; Mon, 11 Dec 2023 21:38:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1702330712; x=1733866712; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=dwNzBbmGeCJxpcV5sWkwoXNH/Qd81Tc47MCl6BaHmRk=; b=fPc3FrpMs9CHFWSG3zuMu40PGYBe7m5TUu3fVYvg24W0yOzC/Uz1Rmdb V7hPTYL91wVUa2gFpRID5Up7sL2QVSiyD9ZLpwZIJE9Ys0KRFHhbVNJE4 b7dlYoFQce4allmO1i42k7KIXaE7wZ+S2rtatAWeTMTyojdT37Mw/rGXN oPw7JEK8vWt9AT1p3bqa3h+U5BZzHmihrmSl0fGVX7NFMOLanUxdI7GLE spcc6PB9STpFp90qOKzGBZiDD4kXFBHE2ngHjASmELslgea6go8rexy5u 1ldz3EJJa/giM25Nl6JtXdWqqVuE01IQ34MUBeYwdehc6vbe6OhTrGx83 w==; X-IronPort-AV: E=McAfee;i="6600,9927,10921"; a="379712264" X-IronPort-AV: E=Sophos;i="6.04,268,1695711600"; d="scan'208";a="379712264" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Dec 2023 13:38:03 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10921"; a="766547061" X-IronPort-AV: E=Sophos;i="6.04,268,1695711600"; d="scan'208";a="766547061" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by orsmga007.jf.intel.com with SMTP; 11 Dec 2023 13:38:00 -0800 Received: by stinkbox (sSMTP sendmail emulation); Mon, 11 Dec 2023 23:37:59 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 3/4] drm/i915/dmc: Also disable HRR event on TGL main DMC Date: Mon, 11 Dec 2023 23:37:49 +0200 Message-ID: <20231211213750.27109-4-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231211213750.27109-1-ville.syrjala@linux.intel.com> References: <20231211213750.27109-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Unlike later platforms TGL has the half refresh rate (HRR) event on the main DMC (as opposed to the pipe DMC). Since we're disabling that event on all later platforms already let's do the same on TGL as well. There is supposedly a bit somewhere (DMC_CHICKEN on TGL) to make the handler not do anything, but we don't currently have code to frob it. Though that bit should be off by default, the ADL+ experience has shown us that trusting any of this isn't a good idea. So seems safer to just disable all event handlers we know that we don't need. Also the TGL DMC firmware is apparently using the wrong event (undelayed vblank) here anyway. It should be using the delayed vblank event instead (like ADL+ firmware does), but they didn't release a firmware fix for this and instead just hacked around this in the Windows driver code :/ Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dmc.c | 5 +++++ drivers/gpu/drm/i915/display/intel_dmc_regs.h | 1 + 2 files changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c index 9385898e3aa5..0722d322ec63 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc.c +++ b/drivers/gpu/drm/i915/display/intel_dmc.c @@ -448,6 +448,11 @@ static bool disable_dmc_evt(struct drm_i915_private *i915, REG_FIELD_GET(DMC_EVT_CTL_EVENT_ID_MASK, data) == DMC_EVT_CTL_EVENT_ID_CLK_MSEC) return true; + /* also disable the HRR event on the main DMC on TGL */ + if (IS_TIGERLAKE(i915) && + REG_FIELD_GET(DMC_EVT_CTL_EVENT_ID_MASK, data) == DMC_EVT_CTL_EVENT_ID_VBLANK_A) + return true; + return false; } diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h b/drivers/gpu/drm/i915/display/intel_dmc_regs.h index cf10094acae3..90d0dbb41cfe 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc_regs.h +++ b/drivers/gpu/drm/i915/display/intel_dmc_regs.h @@ -60,6 +60,7 @@ #define DMC_EVT_CTL_EVENT_ID_MASK REG_GENMASK(15, 8) #define DMC_EVT_CTL_EVENT_ID_FALSE 0x01 +#define DMC_EVT_CTL_EVENT_ID_VBLANK_A 0x32 /* main DMC */ /* An event handler scheduled to run at a 1 kHz frequency. */ #define DMC_EVT_CTL_EVENT_ID_CLK_MSEC 0xbf From patchwork Mon Dec 11 21:37:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 13488115 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D2B70C4332F for ; Mon, 11 Dec 2023 21:38:38 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3739310E509; Mon, 11 Dec 2023 21:38:37 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 95C0B10E507 for ; Mon, 11 Dec 2023 21:38:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1702330713; x=1733866713; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=kKsFEykA3/N6FJnv9Ijf8fCD/PMwPjL8wh9aRLD3Oa4=; b=NkPxEyT0I1+KcqJIp4kLslQ3Dwk5YVu0Gw98TiXgjjOwBiVqKzmiXiln umUH2TzMDWfl12NPSEHTNt8HZkDtlBOb2/k3MAsnFzYnSrLFnwvGIRUMJ cw3okBH3Z2Qd6VoUfdPyL9q9N9xbvKUGc9O/JPot5CBhRdt6s5c0IUx0A 4w2N/ZVAbA/88akRM1fSYbzKCmz/zWv4gIXdVJSmfq83fRLwr1ILnZDJq yaw2w+BHTbGRVPx2e1cflv7OoxkTDZrp3k5FqaiC37a2+hgUpCofclcOF e4tOQHVkNhsXv21SRHlxAV71ET4QtQBmwrj1IQ7pYc0kH41ronMsSVzaV g==; X-IronPort-AV: E=McAfee;i="6600,9927,10921"; a="379712279" X-IronPort-AV: E=Sophos;i="6.04,268,1695711600"; d="scan'208";a="379712279" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Dec 2023 13:38:05 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10921"; a="766547075" X-IronPort-AV: E=Sophos;i="6.04,268,1695711600"; d="scan'208";a="766547075" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by orsmga007.jf.intel.com with SMTP; 11 Dec 2023 13:38:03 -0800 Received: by stinkbox (sSMTP sendmail emulation); Mon, 11 Dec 2023 23:38:02 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 4/4] drm/i915/dmc: Print out the DMC mmio register list at fw load time Date: Mon, 11 Dec 2023 23:37:50 +0200 Message-ID: <20231211213750.27109-5-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231211213750.27109-1-ville.syrjala@linux.intel.com> References: <20231211213750.27109-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä To help with debugging print out the mmio list contained in the DMC firmware. Also highlight the event registers, and whether we're going to disable them or not. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dmc.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c index 0722d322ec63..85759e1ed146 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc.c +++ b/drivers/gpu/drm/i915/display/intel_dmc.c @@ -432,6 +432,16 @@ static bool is_dmc_evt_ctl_reg(struct drm_i915_private *i915, return offset >= start && offset < end; } +static bool is_dmc_evt_htp_reg(struct drm_i915_private *i915, + enum intel_dmc_id dmc_id, i915_reg_t reg) +{ + u32 offset = i915_mmio_reg_offset(reg); + u32 start = i915_mmio_reg_offset(DMC_EVT_HTP(i915, dmc_id, 0)); + u32 end = i915_mmio_reg_offset(DMC_EVT_HTP(i915, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12)); + + return offset >= start && offset < end; +} + static bool disable_dmc_evt(struct drm_i915_private *i915, enum intel_dmc_id dmc_id, i915_reg_t reg, u32 data) @@ -713,9 +723,17 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc, return 0; } + drm_dbg_kms(&i915->drm, "DMC %d:\n", dmc_id); for (i = 0; i < mmio_count; i++) { dmc_info->mmioaddr[i] = _MMIO(mmioaddr[i]); dmc_info->mmiodata[i] = mmiodata[i]; + + drm_dbg_kms(&i915->drm, " mmio[%d]: 0x%x = 0x%x%s%s\n", + i, mmioaddr[i], mmiodata[i], + is_dmc_evt_ctl_reg(i915, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_CTL)" : + is_dmc_evt_htp_reg(i915, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_HTP)" : "", + disable_dmc_evt(i915, dmc_id, dmc_info->mmioaddr[i], + dmc_info->mmiodata[i]) ? " (disabling)" : ""); } dmc_info->mmio_count = mmio_count; dmc_info->start_mmioaddr = start_mmioaddr;