From patchwork Tue Dec 12 16:34:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 13489625 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="MJdEjsFp" Received: from relay9-d.mail.gandi.net (relay9-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::229]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3F72710B; Tue, 12 Dec 2023 08:35:26 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPSA id 1185FFF809; Tue, 12 Dec 2023 16:35:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1702398924; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=F1EYqlVYF1fJ33cC2a0Mertg3uhTJJ/NIkImZDHepJg=; b=MJdEjsFpVJ8ioDiw5His3fbeOd2bjIxm4S8sl0YNzERg/it60cuiPt/dVohY1zArlA7RPd J/LPXx9OPkZopk+jPGol+vP9nY2NPZEaFcWrjAF64ytr48w3FwE8H2Tzo7TeFiyHBvI0ML 0gyE6P1LJySEyPz9tEiKyCR/8DY/1ZgtHdpE/i3buNqi1bbeagMTRUNHutjCyfKwGxUgs7 ehc+A4gcnYxxG7Swuz36Zc5coOMuvHIMJrMjOzFkJU73Pcpb6KnZamxbPyxqFM3aO+fQtW EmHU0yGnK9ZMOCnuJ4XWbjp5h1Ies5nloy/gr64dj0CPMpdrAOtuMWjitwmSZg== From: Gregory CLEMENT To: Paul Burton , Thomas Bogendoerfer , linux-mips@vger.kernel.org, Jiaxun Yang , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Vladimir Kondratiev , Tawfik Bayouk , Alexandre Belloni , =?utf-8?q?Th=C3=A9o_Lebr?= =?utf-8?q?un?= , Thomas Petazzoni , Gregory CLEMENT , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Florian Fainelli Subject: [PATCH v5 01/22] MIPS: compressed: Use correct instruction for 64 bit code Date: Tue, 12 Dec 2023 17:34:33 +0100 Message-ID: <20231212163459.1923041-2-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231212163459.1923041-1-gregory.clement@bootlin.com> References: <20231212163459.1923041-1-gregory.clement@bootlin.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: gregory.clement@bootlin.com The code clearing BSS already use macro or use correct instruction depending if the CPU is 32 bits or 64 bits. However, a few instructions remained 32 bits only. By using the accurate MACRO, it is now possible to deal with memory address beyond 32 bits. As a side effect, when using 64bits processor, it also divides the loop number needed to clear the BSS by 2. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Florian Fainelli Signed-off-by: Gregory CLEMENT --- arch/mips/boot/compressed/head.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/boot/compressed/head.S b/arch/mips/boot/compressed/head.S index 5795d0af1e1b2..d237a834b85ee 100644 --- a/arch/mips/boot/compressed/head.S +++ b/arch/mips/boot/compressed/head.S @@ -25,8 +25,8 @@ /* Clear BSS */ PTR_LA a0, _edata PTR_LA a2, _end -1: sw zero, 0(a0) - addiu a0, a0, 4 +1: PTR_S zero, 0(a0) + PTR_ADDIU a0, a0, PTRSIZE bne a2, a0, 1b PTR_LA a0, (.heap) /* heap address */ From patchwork Tue Dec 12 16:34:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 13489627 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="pM3zmtSl" Received: from relay6-d.mail.gandi.net (relay6-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::226]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 20656118; Tue, 12 Dec 2023 08:35:27 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPSA id 21F4DC0002; Tue, 12 Dec 2023 16:35:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1702398925; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=1f+FndhwKpT84ogIpFFowDtfhlo7ZPzn2H3k9c4MjvQ=; b=pM3zmtSlclr+D1O/xCkzLaAjtI/B72lxCilVSaiuiSSCUG7EzetyTCB7pOG1Yy8WSqyG81 arsA8Q1c8A1TpE0B9PMhO9aWdW6coq3yWFsFoEpJahjVQNXFFyfpxaN1SltHyBmR5cA9Xk U8lXpJWOm5UafZMAclHkoTO4pwtkzPp7HBIgUNBa8PNrGGV3RZFG9EDIaQ67hQpM2E6ghS Ici687NvFqfQxZXDUgOucl7+7J+OTbQVEZ9ADkJUpZwhAhzNAfN8TnVl2XcP994NxXBbW4 yco/O0bmEUwpjh4nLjHNGmPRZgURf7W7u5mtjpXt71pGwJgMjtLFVGRBCg7GTA== From: Gregory CLEMENT To: Paul Burton , Thomas Bogendoerfer , linux-mips@vger.kernel.org, Jiaxun Yang , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Vladimir Kondratiev , Tawfik Bayouk , Alexandre Belloni , =?utf-8?q?Th=C3=A9o_Lebr?= =?utf-8?q?un?= , Thomas Petazzoni Subject: [PATCH v5 02/22] MIPS: Export higher/highest relocation functions in uasm Date: Tue, 12 Dec 2023 17:34:34 +0100 Message-ID: <20231212163459.1923041-3-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231212163459.1923041-1-gregory.clement@bootlin.com> References: <20231212163459.1923041-1-gregory.clement@bootlin.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: gregory.clement@bootlin.com From: Jiaxun Yang Export uasm_rel_{higher,highest} functions. Those functions can be helpful in dealing with 64bit immediates. Signed-off-by: Jiaxun Yang --- arch/mips/include/asm/uasm.h | 2 ++ arch/mips/mm/uasm.c | 6 ++++-- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h index 296bcf31abb57..12db6d2fca070 100644 --- a/arch/mips/include/asm/uasm.h +++ b/arch/mips/include/asm/uasm.h @@ -196,6 +196,8 @@ void uasm_build_label(struct uasm_label **lab, u32 *addr, #ifdef CONFIG_64BIT int uasm_in_compat_space_p(long addr); #endif +int uasm_rel_highest(long val); +int uasm_rel_higher(long val); int uasm_rel_hi(long val); int uasm_rel_lo(long val); void UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr); diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c index 125140979d62c..6846bf2084c5e 100644 --- a/arch/mips/mm/uasm.c +++ b/arch/mips/mm/uasm.c @@ -425,7 +425,7 @@ int uasm_in_compat_space_p(long addr) } UASM_EXPORT_SYMBOL(uasm_in_compat_space_p); -static int uasm_rel_highest(long val) +int uasm_rel_highest(long val) { #ifdef CONFIG_64BIT return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000; @@ -433,8 +433,9 @@ static int uasm_rel_highest(long val) return 0; #endif } +UASM_EXPORT_SYMBOL(uasm_rel_highest); -static int uasm_rel_higher(long val) +int uasm_rel_higher(long val) { #ifdef CONFIG_64BIT return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000; @@ -442,6 +443,7 @@ static int uasm_rel_higher(long val) return 0; #endif } +UASM_EXPORT_SYMBOL(uasm_rel_higher); int uasm_rel_hi(long val) { From patchwork Tue Dec 12 16:34:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 13489630 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="hV61DdsZ" Received: from relay8-d.mail.gandi.net (relay8-d.mail.gandi.net [217.70.183.201]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 63CB7CF; Tue, 12 Dec 2023 08:35:28 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPSA id EC60D1BF206; Tue, 12 Dec 2023 16:35:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1702398926; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=lKcme3eaH65euvc/e2P73RSdLcgnsk0eRcbckWPUCdg=; b=hV61DdsZAAj98ndi9omfMHJ64OQ103h1zci1b7xPMPI1LEe6X2UpwRXzSwRTP/3K71WgTO 4xbWq2ONnAmjcVGBPXj8Ed3viBxklngetrxWiKpw3UpPk1GG262+vfczvzm4jeAj14H5FK cg/ZVreDQSR7LUJ+457DJdUb6m9Sm8PEMrTrULk3xsBQ0OqFDaXd8wCwPcGX4mn7riw6JP rcSkchf6mhbGT9zrClx1kSOVargaobSp0kX9ciKayh2lW/t1HQtlwZd13tBauicNAC7QzA RZ9fT/zbzPwTfbpvNhw6XmMgi6aoy89132BttBKG0Wt9FXXKyezjYx15F9UMfQ== From: Gregory CLEMENT To: Paul Burton , Thomas Bogendoerfer , linux-mips@vger.kernel.org, Jiaxun Yang , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Vladimir Kondratiev , Tawfik Bayouk , Alexandre Belloni , =?utf-8?q?Th=C3=A9o_Lebr?= =?utf-8?q?un?= , Thomas Petazzoni , Gregory CLEMENT Subject: [PATCH v5 03/22] MIPS: spaces: Define a couple of handy macros Date: Tue, 12 Dec 2023 17:34:35 +0100 Message-ID: <20231212163459.1923041-4-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231212163459.1923041-1-gregory.clement@bootlin.com> References: <20231212163459.1923041-1-gregory.clement@bootlin.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: gregory.clement@bootlin.com Define KSEGX_SIZE to represent the size of each KSEG segment. Introduce TO_CAC and TO_UNCAC specifically for 32-bit builds, pointing to KSEG0 and KSEG1. TO_PHYS remains exclusive to 64-bit builds to encourage the use of __pa and prevent compatibility address space confusion. KSEGX_SIZE is defined to size of each KSEG segment. Co-developed-by: Jiaxun Yang Signed-off-by: Gregory CLEMENT --- arch/mips/include/asm/addrspace.h | 5 +++++ arch/mips/include/asm/mach-generic/spaces.h | 2 ++ 2 files changed, 7 insertions(+) diff --git a/arch/mips/include/asm/addrspace.h b/arch/mips/include/asm/addrspace.h index 59a48c60a065c..03a5e2c8b5dc9 100644 --- a/arch/mips/include/asm/addrspace.h +++ b/arch/mips/include/asm/addrspace.h @@ -47,6 +47,11 @@ */ #define KSEGX(a) ((_ACAST32_(a)) & _ACAST32_(0xe0000000)) +/* + * Gives the size of each kernel segment + */ +#define KSEGX_SIZE 0x20000000 + /* * Returns the physical address of a CKSEGx / XKPHYS address */ diff --git a/arch/mips/include/asm/mach-generic/spaces.h b/arch/mips/include/asm/mach-generic/spaces.h index b247575c5e699..c502bdd98aad0 100644 --- a/arch/mips/include/asm/mach-generic/spaces.h +++ b/arch/mips/include/asm/mach-generic/spaces.h @@ -49,6 +49,8 @@ #define HIGHMEM_START _AC(0x20000000, UL) #endif +#define TO_UNCAC(x) CKSEG1ADDR(x) +#define TO_CAC(x) CKSEG0ADDR(x) #endif /* CONFIG_32BIT */ #ifdef CONFIG_64BIT From patchwork Tue Dec 12 16:34:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 13489628 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="kY+6zB9s" Received: from relay5-d.mail.gandi.net (relay5-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::225]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4F09D106; Tue, 12 Dec 2023 08:35:29 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPSA id 209671C0004; Tue, 12 Dec 2023 16:35:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1702398927; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=AagYqurduAd05kHY0ow9kHcvI+mUo3FUEEyQW1aeXWI=; b=kY+6zB9s1rabD6l04MICojRVNhyiCEEhBssxMcg1X+ZVrIUR6KcrtPnNtjvFgg3BplaAup 0S9DxFPZop5D/ZIvrWUseLESjUb5ZCGcM5eG0DoahEGyg96axhs/Xe+zALd7ASjWWagXNG w/XzpcDPZdoim46eJvVqResHZXtgOIbPJH84VRvMOQosvRup7c8D51zOTPdTN4UJwXSBSd c2ZeTeI7rfKjdSBhcPspmybPuNTxDowIEHPMeXgH+AzC9VWGbNumt+125/d4eJQNEXKNwU AJsFZx71k6rL1zrx0rvNAaRSLcaLAQJm5HqQwKOQGXOugmCTTWickyi4fVQXmg== From: Gregory CLEMENT To: Paul Burton , Thomas Bogendoerfer , linux-mips@vger.kernel.org, Jiaxun Yang , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Vladimir Kondratiev , Tawfik Bayouk , Alexandre Belloni , =?utf-8?q?Th=C3=A9o_Lebr?= =?utf-8?q?un?= , Thomas Petazzoni , Vladimir Kondratiev , Gregory CLEMENT Subject: [PATCH v5 04/22] MIPS: genex: Fix except_vec_vi for kernel in XKPHYS Date: Tue, 12 Dec 2023 17:34:36 +0100 Message-ID: <20231212163459.1923041-5-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231212163459.1923041-1-gregory.clement@bootlin.com> References: <20231212163459.1923041-1-gregory.clement@bootlin.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: gregory.clement@bootlin.com From: Jiaxun Yang Use {highest, higher, hi, lo} immediate loading sequence to load 64 bit jump address for handler when kernel is loaded to XKPHYS. Co-developed-by: Vladimir Kondratiev Signed-off-by: Vladimir Kondratiev Co-developed-by: Gregory CLEMENT Signed-off-by: Jiaxun Yang Signed-off-by: Gregory CLEMENT --- arch/mips/kernel/genex.S | 19 +++++++++++++++---- arch/mips/kernel/traps.c | 34 ++++++++++++++++++++++++---------- 2 files changed, 39 insertions(+), 14 deletions(-) diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S index b6de8e88c1bd4..fd765ad9ecac0 100644 --- a/arch/mips/kernel/genex.S +++ b/arch/mips/kernel/genex.S @@ -272,11 +272,22 @@ NESTED(except_vec_vi, 0, sp) .set push .set noreorder PTR_LA v1, except_vec_vi_handler -FEXPORT(except_vec_vi_lui) - lui v0, 0 /* Patched */ +#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32) +FEXPORT(except_vec_vi_hi) + lui v0, 0 /* Patched */ +#else +FEXPORT(except_vec_vi_highest) + lui v0, 0 /* Patched */ +FEXPORT(except_vec_vi_higher) + daddiu v0, 0 /* Patched */ + dsll v0, 16 +FEXPORT(except_vec_vi_hi) + daddiu v0, 0 /* Patched */ + dsll v0, 16 +#endif jr v1 -FEXPORT(except_vec_vi_ori) - ori v0, 0 /* Patched */ +FEXPORT(except_vec_vi_lo) + PTR_ADDIU v0, 0 /* Patched */ .set pop END(except_vec_vi) EXPORT(except_vec_vi_end) diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 246c6a6b02614..60c513c51684f 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -2091,18 +2091,26 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) * If no shadow set is selected then use the default handler * that does normal register saving and standard interrupt exit */ - extern const u8 except_vec_vi[], except_vec_vi_lui[]; - extern const u8 except_vec_vi_ori[], except_vec_vi_end[]; + extern const u8 except_vec_vi[], except_vec_vi_hi[]; + extern const u8 except_vec_vi_lo[], except_vec_vi_end[]; +#if defined(CONFIG_64BIT) && !defined(KBUILD_64BIT_SYM32) + extern const u8 except_vec_vi_highest[], except_vec_vi_higher[]; +#endif extern const u8 rollback_except_vec_vi[]; const u8 *vec_start = using_rollback_handler() ? rollback_except_vec_vi : except_vec_vi; #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN) - const int lui_offset = except_vec_vi_lui - vec_start + 2; - const int ori_offset = except_vec_vi_ori - vec_start + 2; + const int imm_offset = 2; #else - const int lui_offset = except_vec_vi_lui - vec_start; - const int ori_offset = except_vec_vi_ori - vec_start; + const int imm_offset = 0; +#endif +#if defined(CONFIG_64BIT) && !defined(KBUILD_64BIT_SYM32) + const int highest_offset = except_vec_vi_highest - vec_start + imm_offset; + const int higher_offset = except_vec_vi_higher - vec_start + imm_offset; #endif + const int hi_offset = except_vec_vi_hi - vec_start + imm_offset; + const int lo_offset = except_vec_vi_lo - vec_start + imm_offset; + const int handler_len = except_vec_vi_end - vec_start; if (handler_len > VECTORSPACING) { @@ -2119,10 +2127,16 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) #else handler_len); #endif - h = (u16 *)(b + lui_offset); - *h = (handler >> 16) & 0xffff; - h = (u16 *)(b + ori_offset); - *h = (handler & 0xffff); +#if defined(CONFIG_64BIT) && !defined(KBUILD_64BIT_SYM32) + h = (u16 *)(b + highest_offset); + *h = uasm_rel_highest(handler); + h = (u16 *)(b + higher_offset); + *h = uasm_rel_higher(handler); +#endif + h = (u16 *)(b + hi_offset); + *h = uasm_rel_hi(handler); + h = (u16 *)(b + lo_offset); + *h = uasm_rel_lo(handler); local_flush_icache_range((unsigned long)b, (unsigned long)(b+handler_len)); } From patchwork Tue Dec 12 16:34:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 13489629 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="Ch3z9zB4" Received: from relay4-d.mail.gandi.net (relay4-d.mail.gandi.net [217.70.183.196]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AF4BA110; Tue, 12 Dec 2023 08:35:30 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPSA id 48ED3E0003; Tue, 12 Dec 2023 16:35:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1702398929; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=D5cCBpjLVQJIEyNHt7kbmGhJLdSXgsITn2458HFNHoY=; b=Ch3z9zB4RfHk6MKx0YDBteFeS7lmL3PQi6ptvM+2yfXzfwg0lvT/drOiiKQG0bjH5mLVpa cys/hkO9rn4Qc6k7GtEsdRdJYEhLHFJ2rTGnrgfdPvs+Gyq36bHYt5agBmyZNF69bhjXH4 Tg5Q5rupmYUy2pYZFtNYVdfyfhQkY/nEQZDWUDI6cT0E6tcmMgnLMIPETXHXN8POQa45N9 CSpu5Rgeg7C5oY2hOjUNYEIdQPRGv3pAGWHY0JIgl3Z1Cb54g/M+gxUpdc6H6rBqxlH7YB uiLGgwb8fDhiw+GEJovOacpEiIf+ABroJmV+BuEW5TuVLISbzEpluTBqFbELkw== From: Gregory CLEMENT To: Paul Burton , Thomas Bogendoerfer , linux-mips@vger.kernel.org, Jiaxun Yang , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Vladimir Kondratiev , Tawfik Bayouk , Alexandre Belloni , =?utf-8?q?Th=C3=A9o_Lebr?= =?utf-8?q?un?= , Thomas Petazzoni , Vladimir Kondratiev , Gregory CLEMENT Subject: [PATCH v5 05/22] MIPS: Fix set_uncached_handler for ebase in XKPHYS Date: Tue, 12 Dec 2023 17:34:37 +0100 Message-ID: <20231212163459.1923041-6-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231212163459.1923041-1-gregory.clement@bootlin.com> References: <20231212163459.1923041-1-gregory.clement@bootlin.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: gregory.clement@bootlin.com From: Jiaxun Yang ebase might reside in XKPHYS if memblock is unable to allocate memory within the KSEG0 physical range. To map EBASE into uncached space, we convert it back to its physical address and utilize the platform's TO_UNCAC helper for mapping. Co-developed-by: Vladimir Kondratiev Signed-off-by: Vladimir Kondratiev Co-developed-by: Gregory CLEMENT Signed-off-by: Jiaxun Yang Signed-off-by: Gregory CLEMENT --- arch/mips/kernel/traps.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 60c513c51684f..230728d76d11f 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -2346,7 +2346,7 @@ static const char panic_null_cerr[] = void set_uncached_handler(unsigned long offset, void *addr, unsigned long size) { - unsigned long uncached_ebase = CKSEG1ADDR(ebase); + unsigned long uncached_ebase = TO_UNCAC(__pa(ebase)); if (!addr) panic(panic_null_cerr); From patchwork Tue Dec 12 16:34:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 13489634 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="ZxEtWPIm" Received: from relay2-d.mail.gandi.net (relay2-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::222]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 81EF0EB; Tue, 12 Dec 2023 08:35:31 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPSA id 53BD940009; Tue, 12 Dec 2023 16:35:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1702398929; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=f2MzbyPn8rMX/70hHyFKQ1kdGPyPC7EdKYb9ZGPjSt0=; b=ZxEtWPImiBHuhNGhjGYqvvmMWz8cL0tIPFjnXe+IL9T6lewgaSVU4JFZIITULs3A1enU3O vEZdpj8Z7Rbgmh6rxbBoTOD22jssfxDWAaoFfql6uDRVyw9RYzv/0isH1WCFcua6Mo5y43 8RmCryhnim8jhwgIHNQtlJDBaDWNz+uAXl1JicMSoh8pWgLSlesLGWljxeAqlTUjRdjyZw cIyyOMsrhGlixzJmfkKmAkLK1zHEh8mLSF3ML/4EL0pckEEqmv9fhQ12YDS4LcSPnpyUu5 x1WEnmu2yJfvx35h+FyJv7iLDX1q6tRirkV5ybrPpNgILcXyreWaU7DSnNpilA== From: Gregory CLEMENT To: Paul Burton , Thomas Bogendoerfer , linux-mips@vger.kernel.org, Jiaxun Yang , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Vladimir Kondratiev , Tawfik Bayouk , Alexandre Belloni , =?utf-8?q?Th=C3=A9o_Lebr?= =?utf-8?q?un?= , Thomas Petazzoni Subject: [PATCH v5 06/22] MIPS: Refactor mips_cps_core_entry implementation Date: Tue, 12 Dec 2023 17:34:38 +0100 Message-ID: <20231212163459.1923041-7-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231212163459.1923041-1-gregory.clement@bootlin.com> References: <20231212163459.1923041-1-gregory.clement@bootlin.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: gregory.clement@bootlin.com From: Jiaxun Yang Now the exception vector for CPS systems are allocated on-fly with memblock as well. It will try to allocate from KSEG1 first, and then try to allocate in low 4G if possible. The main reset vector is now generated by uasm, to avoid tons of patches to the code. Other vectors are copied to the location later. Signed-off-by: Jiaxun Yang --- arch/mips/include/asm/mips-cm.h | 1 + arch/mips/include/asm/smp-cps.h | 4 +- arch/mips/kernel/cps-vec.S | 110 ++++++++------------- arch/mips/kernel/smp-cps.c | 167 +++++++++++++++++++++++++++----- arch/mips/kernel/traps.c | 2 + 5 files changed, 186 insertions(+), 98 deletions(-) diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips/include/asm/mips-cm.h index 23c67c0871b17..15d8d69de4550 100644 --- a/arch/mips/include/asm/mips-cm.h +++ b/arch/mips/include/asm/mips-cm.h @@ -311,6 +311,7 @@ GCR_CX_ACCESSOR_RW(32, 0x018, other) /* GCR_Cx_RESET_BASE - Configure where powered up cores will fetch from */ GCR_CX_ACCESSOR_RW(32, 0x020, reset_base) #define CM_GCR_Cx_RESET_BASE_BEVEXCBASE GENMASK(31, 12) +#define CM_GCR_Cx_RESET_BASE_MODE BIT(1) /* GCR_Cx_ID - Identify the current core */ GCR_CX_ACCESSOR_RO(32, 0x028, id) diff --git a/arch/mips/include/asm/smp-cps.h b/arch/mips/include/asm/smp-cps.h index 22a572b70fe31..39a602e5fecc4 100644 --- a/arch/mips/include/asm/smp-cps.h +++ b/arch/mips/include/asm/smp-cps.h @@ -24,7 +24,7 @@ struct core_boot_config { extern struct core_boot_config *mips_cps_core_bootcfg; -extern void mips_cps_core_entry(void); +extern void mips_cps_core_boot(int cca, void __iomem *gcr_base); extern void mips_cps_core_init(void); extern void mips_cps_boot_vpes(struct core_boot_config *cfg, unsigned vpe); @@ -32,8 +32,6 @@ extern void mips_cps_boot_vpes(struct core_boot_config *cfg, unsigned vpe); extern void mips_cps_pm_save(void); extern void mips_cps_pm_restore(void); -extern void *mips_cps_core_entry_patch_end; - #ifdef CONFIG_MIPS_CPS extern bool mips_cps_smp_in_use(void); diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S index 64ecfdac6580b..8870a2dbc35aa 100644 --- a/arch/mips/kernel/cps-vec.S +++ b/arch/mips/kernel/cps-vec.S @@ -4,6 +4,8 @@ * Author: Paul Burton */ +#include + #include #include #include @@ -81,40 +83,48 @@ nop .endm + __INIT +LEAF(excep_tlbfill) + DUMP_EXCEP("TLB Fill") + b . + nop + END(excep_tlbfill) -.balign 0x1000 +LEAF(excep_xtlbfill) + DUMP_EXCEP("XTLB Fill") + b . + nop + END(excep_xtlbfill) -LEAF(mips_cps_core_entry) - /* - * These first several instructions will be patched by cps_smp_setup to load the - * CCA to use into register s0 and GCR base address to register s1. - */ - .rept CPS_ENTRY_PATCH_INSNS - nop - .endr +LEAF(excep_cache) + DUMP_EXCEP("Cache") + b . + nop + END(excep_cache) - .global mips_cps_core_entry_patch_end -mips_cps_core_entry_patch_end: +LEAF(excep_genex) + DUMP_EXCEP("General") + b . + nop + END(excep_genex) - /* Check whether we're here due to an NMI */ - mfc0 k0, CP0_STATUS - and k0, k0, ST0_NMI - beqz k0, not_nmi +LEAF(excep_intex) + DUMP_EXCEP("Interrupt") + b . nop + END(excep_intex) - /* This is an NMI */ - PTR_LA k0, nmi_handler +LEAF(excep_ejtag) + PTR_LA k0, ejtag_debug_handler jr k0 nop + END(excep_ejtag) + __FINIT -not_nmi: - /* Setup Cause */ - li t0, CAUSEF_IV - mtc0 t0, CP0_CAUSE - - /* Setup Status */ - li t0, ST0_CU1 | ST0_CU0 | ST0_BEV | STATUS_BITDEPS - mtc0 t0, CP0_STATUS +LEAF(mips_cps_core_boot) + /* Save CCA and GCR base */ + move s0, a0 + move s1, a1 /* We don't know how to do coherence setup on earlier ISA */ #if MIPS_ISA_REV > 0 @@ -178,49 +188,7 @@ not_nmi: PTR_L sp, VPEBOOTCFG_SP(v1) jr t1 nop - END(mips_cps_core_entry) - -.org 0x200 -LEAF(excep_tlbfill) - DUMP_EXCEP("TLB Fill") - b . - nop - END(excep_tlbfill) - -.org 0x280 -LEAF(excep_xtlbfill) - DUMP_EXCEP("XTLB Fill") - b . - nop - END(excep_xtlbfill) - -.org 0x300 -LEAF(excep_cache) - DUMP_EXCEP("Cache") - b . - nop - END(excep_cache) - -.org 0x380 -LEAF(excep_genex) - DUMP_EXCEP("General") - b . - nop - END(excep_genex) - -.org 0x400 -LEAF(excep_intex) - DUMP_EXCEP("Interrupt") - b . - nop - END(excep_intex) - -.org 0x480 -LEAF(excep_ejtag) - PTR_LA k0, ejtag_debug_handler - jr k0 - nop - END(excep_ejtag) + END(mips_cps_core_boot) LEAF(mips_cps_core_init) #ifdef CONFIG_MIPS_MT_SMP @@ -428,7 +396,7 @@ LEAF(mips_cps_boot_vpes) /* Calculate a pointer to the VPEs struct vpe_boot_config */ li t0, VPEBOOTCFG_SIZE mul t0, t0, ta1 - addu t0, t0, ta3 + PTR_ADDU t0, t0, ta3 /* Set the TC restart PC */ lw t1, VPEBOOTCFG_PC(t0) @@ -603,10 +571,10 @@ dcache_done: lw $1, TI_CPU(gp) sll $1, $1, LONGLOG PTR_LA \dest, __per_cpu_offset - addu $1, $1, \dest + PTR_ADDU $1, $1, \dest lw $1, 0($1) PTR_LA \dest, cps_cpu_state - addu \dest, \dest, $1 + PTR_ADDU \dest, \dest, $1 .set pop .endm diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c index dd55d59b88db3..9aad678a32bd7 100644 --- a/arch/mips/kernel/smp-cps.c +++ b/arch/mips/kernel/smp-cps.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -25,7 +26,33 @@ #include #include +#define BEV_VEC_SIZE 0x500 +#define BEV_VEC_ALIGN 0x1000 + +#define A0 4 +#define A1 5 +#define T9 25 +#define K0 26 +#define K1 27 + +#define C0_STATUS 12, 0 +#define C0_CAUSE 13, 0 + +#define ST0_NMI_BIT 19 +#ifdef CONFIG_64BIT +#define ST0_KX_IF_64 ST0_KX +#else +#define ST0_KX_IF_64 0 +#endif + +enum label_id { + label_not_nmi = 1, +}; + +UASM_L_LA(_not_nmi) + static DECLARE_BITMAP(core_power, NR_CPUS); +static uint32_t core_entry_reg; struct core_boot_config *mips_cps_core_bootcfg; @@ -34,10 +61,113 @@ static unsigned __init core_vpe_count(unsigned int cluster, unsigned core) return min(smp_max_threads, mips_cps_numvps(cluster, core)); } +static void __init *mips_cps_build_core_entry(void *addr) +{ + extern void (*nmi_handler)(void); + u32 *p = addr; + u32 val; + struct uasm_label labels[2]; + struct uasm_reloc relocs[2]; + struct uasm_label *l = labels; + struct uasm_reloc *r = relocs; + + memset(labels, 0, sizeof(labels)); + memset(relocs, 0, sizeof(relocs)); + + uasm_i_mfc0(&p, K0, C0_STATUS); + if (cpu_has_mips_r2_r6) + uasm_i_ext(&p, K0, K0, ST0_NMI_BIT, 1); + else { + uasm_i_srl(&p, K0, K0, ST0_NMI_BIT); + uasm_i_andi(&p, K0, K0, 0x1); + } + + uasm_il_bnez(&p, &r, K0, label_not_nmi); + uasm_i_nop(&p); + UASM_i_LA(&p, K0, (long)&nmi_handler); + + uasm_l_not_nmi(&l, p); + + val = CAUSEF_IV; + uasm_i_lui(&p, K0, val >> 16); + uasm_i_ori(&p, K0, K0, val & 0xffff); + uasm_i_mtc0(&p, K0, C0_CAUSE); + val = ST0_CU1 | ST0_CU0 | ST0_BEV | ST0_KX_IF_64; + uasm_i_lui(&p, K0, val >> 16); + uasm_i_ori(&p, K0, K0, val & 0xffff); + uasm_i_mtc0(&p, K0, C0_STATUS); + uasm_i_ehb(&p); + uasm_i_ori(&p, A0, 0, read_c0_config() & CONF_CM_CMASK); + UASM_i_LA(&p, A1, (long)mips_gcr_base); +#if defined(KBUILD_64BIT_SYM32) || defined(CONFIG_32BIT) + UASM_i_LA(&p, T9, CKSEG1ADDR(__pa_symbol(mips_cps_core_boot))); +#else + UASM_i_LA(&p, T9, TO_UNCAC(__pa_symbol(mips_cps_core_boot))); +#endif + uasm_i_jr(&p, T9); + uasm_i_nop(&p); + + uasm_resolve_relocs(relocs, labels); + + return p; +} + +static int __init setup_cps_vecs(void) +{ + extern void excep_tlbfill(void); + extern void excep_xtlbfill(void); + extern void excep_cache(void); + extern void excep_genex(void); + extern void excep_intex(void); + extern void excep_ejtag(void); + phys_addr_t cps_vec_pa; + void *cps_vec; + + /* Try to allocate in KSEG1 first */ + cps_vec_pa = memblock_phys_alloc_range(BEV_VEC_SIZE, BEV_VEC_ALIGN, + 0x0, KSEGX_SIZE - 1); + + if (cps_vec_pa) + core_entry_reg = CKSEG1ADDR(cps_vec_pa) & + CM_GCR_Cx_RESET_BASE_BEVEXCBASE; + + if (!cps_vec_pa && mips_cm_is64) { + cps_vec_pa = memblock_phys_alloc_range(BEV_VEC_SIZE, BEV_VEC_ALIGN, + 0x0, SZ_4G - 1); + if (cps_vec_pa) + core_entry_reg = (cps_vec_pa & CM_GCR_Cx_RESET_BASE_BEVEXCBASE) | + CM_GCR_Cx_RESET_BASE_MODE; + } + + if (!cps_vec_pa) + return -ENOMEM; + + /* We want to ensure cache is clean before writing uncached mem */ + blast_dcache_range(TO_CAC(cps_vec_pa), TO_CAC(cps_vec_pa) + BEV_VEC_SIZE); + bc_wback_inv(TO_CAC(cps_vec_pa), BEV_VEC_SIZE); + __sync(); + + cps_vec = (void *)TO_UNCAC(cps_vec_pa); + mips_cps_build_core_entry(cps_vec); + + memcpy(cps_vec + 0x200, &excep_tlbfill, 0x80); + memcpy(cps_vec + 0x280, &excep_xtlbfill, 0x80); + memcpy(cps_vec + 0x300, &excep_cache, 0x80); + memcpy(cps_vec + 0x380, &excep_genex, 0x80); + memcpy(cps_vec + 0x400, &excep_intex, 0x80); + memcpy(cps_vec + 0x480, &excep_ejtag, 0x80); + + /* Make sure no prefetched data in cache */ + blast_inv_dcache_range(TO_CAC(cps_vec_pa), TO_CAC(cps_vec_pa) + BEV_VEC_SIZE); + bc_inv(TO_CAC(cps_vec_pa), BEV_VEC_SIZE); + __sync(); + + return 0; +} + static void __init cps_smp_setup(void) { unsigned int nclusters, ncores, nvpes, core_vpes; - unsigned long core_entry; int cl, c, v; /* Detect & record VPE topology */ @@ -94,10 +224,11 @@ static void __init cps_smp_setup(void) /* Make core 0 coherent with everything */ write_gcr_cl_coherence(0xff); - if (mips_cm_revision() >= CM_REV_CM3) { - core_entry = CKSEG1ADDR((unsigned long)mips_cps_core_entry); - write_gcr_bev_base(core_entry); - } + if (setup_cps_vecs()) + pr_err("Failed to setup CPS vectors\n"); + + if (core_entry_reg && mips_cm_revision() >= CM_REV_CM3) + write_gcr_bev_base(core_entry_reg); #ifdef CONFIG_MIPS_MT_FPAFF /* If we have an FPU, enroll ourselves in the FPU-full mask */ @@ -110,10 +241,14 @@ static void __init cps_prepare_cpus(unsigned int max_cpus) { unsigned ncores, core_vpes, c, cca; bool cca_unsuitable, cores_limited; - u32 *entry_code; mips_mt_set_cpuoptions(); + if (!core_entry_reg) { + pr_err("core_entry address unsuitable, disabling smp-cps\n"); + goto err_out; + } + /* Detect whether the CCA is unsuited to multi-core SMP */ cca = read_c0_config() & CONF_CM_CMASK; switch (cca) { @@ -145,20 +280,6 @@ static void __init cps_prepare_cpus(unsigned int max_cpus) (cca_unsuitable && cpu_has_dc_aliases) ? " & " : "", cpu_has_dc_aliases ? "dcache aliasing" : ""); - /* - * Patch the start of mips_cps_core_entry to provide: - * - * s0 = kseg0 CCA - */ - entry_code = (u32 *)&mips_cps_core_entry; - uasm_i_addiu(&entry_code, 16, 0, cca); - UASM_i_LA(&entry_code, 17, (long)mips_gcr_base); - BUG_ON((void *)entry_code > (void *)&mips_cps_core_entry_patch_end); - blast_dcache_range((unsigned long)&mips_cps_core_entry, - (unsigned long)entry_code); - bc_wback_inv((unsigned long)&mips_cps_core_entry, - (void *)entry_code - (void *)&mips_cps_core_entry); - __sync(); /* Allocate core boot configuration structs */ ncores = mips_cps_numcores(0); @@ -213,7 +334,7 @@ static void boot_core(unsigned int core, unsigned int vpe_id) mips_cm_lock_other(0, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL); /* Set its reset vector */ - write_gcr_co_reset_base(CKSEG1ADDR((unsigned long)mips_cps_core_entry)); + write_gcr_co_reset_base(core_entry_reg); /* Ensure its coherency is disabled */ write_gcr_co_coherence(0); @@ -290,7 +411,6 @@ static int cps_boot_secondary(int cpu, struct task_struct *idle) unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]); struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core]; struct vpe_boot_config *vpe_cfg = &core_cfg->vpe_config[vpe_id]; - unsigned long core_entry; unsigned int remote; int err; @@ -314,8 +434,7 @@ static int cps_boot_secondary(int cpu, struct task_struct *idle) if (cpu_has_vp) { mips_cm_lock_other(0, core, vpe_id, CM_GCR_Cx_OTHER_BLOCK_LOCAL); - core_entry = CKSEG1ADDR((unsigned long)mips_cps_core_entry); - write_gcr_co_reset_base(core_entry); + write_gcr_co_reset_base(core_entry_reg); mips_cm_unlock_other(); } diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 230728d76d11f..ea59d321f713e 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -74,6 +74,8 @@ #include "access-helper.h" +#define MAX(a, b) ((a) >= (b) ? (a) : (b)) + extern void check_wait(void); extern asmlinkage void rollback_handle_int(void); extern asmlinkage void handle_int(void); From patchwork Tue Dec 12 16:34:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 13489632 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="hIA5vBGh" Received: from relay8-d.mail.gandi.net (relay8-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::228]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 459A810E; Tue, 12 Dec 2023 08:35:31 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPSA id 1460E1BF20A; Tue, 12 Dec 2023 16:35:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1702398930; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=csnOaxSt7JZQCahT2bN5IGKlGaknLCMr5TUNqVz3qJ8=; b=hIA5vBGh5rMpBv0vKsUu7Rg7W7AO/jBlwSka/ljxzqaiEaB2ZkNbWXZAKSd5qB6VefULty LPCLV5sxclUHKu9XCVjae1NgsUuyK3AbUb5+z+svtLAHbND+JEILQC6UsVpXBB2qe89JFH ceDLGQUtQQh7Wg0QgeZu0u6EnoZzksEGwBAchn2SVLtg339fB1lCSfv4/4LZpCyReoF35w jgsgW7It+BOpuvuYSUGWLwwfzZXVOw8PiyLscZGbqmu1x0uM+W9KjGpDWS2XGPKSz3MEB7 HLIaXe6dSzxVuairq4z54zjYUbC6hqU6YsVv7ZVSl7Cmj9b/dUrsSSjdUqm2Tg== From: Gregory CLEMENT To: Paul Burton , Thomas Bogendoerfer , linux-mips@vger.kernel.org, Jiaxun Yang , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Vladimir Kondratiev , Tawfik Bayouk , Alexandre Belloni , =?utf-8?q?Th=C3=A9o_Lebr?= =?utf-8?q?un?= , Thomas Petazzoni , Gregory CLEMENT Subject: [PATCH v5 07/22] MIPS: Fix cache issue with mips_cps_core_entry Date: Tue, 12 Dec 2023 17:34:39 +0100 Message-ID: <20231212163459.1923041-8-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231212163459.1923041-1-gregory.clement@bootlin.com> References: <20231212163459.1923041-1-gregory.clement@bootlin.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: gregory.clement@bootlin.com Split setup_cps_vecs and move back the cache management latter in cps_smp_setup when the cache subsystem had been initialized. Without this the blast_inv_dcache_range() call can lead to a crash. Signed-off-by: Gregory CLEMENT --- arch/mips/kernel/smp-cps.c | 32 ++++++++++++++++++-------------- 1 file changed, 18 insertions(+), 14 deletions(-) diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c index 9aad678a32bd7..6cbdff917d147 100644 --- a/arch/mips/kernel/smp-cps.c +++ b/arch/mips/kernel/smp-cps.c @@ -53,6 +53,7 @@ UASM_L_LA(_not_nmi) static DECLARE_BITMAP(core_power, NR_CPUS); static uint32_t core_entry_reg; +static phys_addr_t cps_vec_pa; struct core_boot_config *mips_cps_core_bootcfg; @@ -112,17 +113,8 @@ static void __init *mips_cps_build_core_entry(void *addr) return p; } -static int __init setup_cps_vecs(void) +static int __init allocate_cps_vecs(void) { - extern void excep_tlbfill(void); - extern void excep_xtlbfill(void); - extern void excep_cache(void); - extern void excep_genex(void); - extern void excep_intex(void); - extern void excep_ejtag(void); - phys_addr_t cps_vec_pa; - void *cps_vec; - /* Try to allocate in KSEG1 first */ cps_vec_pa = memblock_phys_alloc_range(BEV_VEC_SIZE, BEV_VEC_ALIGN, 0x0, KSEGX_SIZE - 1); @@ -142,6 +134,19 @@ static int __init setup_cps_vecs(void) if (!cps_vec_pa) return -ENOMEM; + return 0; +} + +static void __init setup_cps_vecs(void) +{ + extern void excep_tlbfill(void); + extern void excep_xtlbfill(void); + extern void excep_cache(void); + extern void excep_genex(void); + extern void excep_intex(void); + extern void excep_ejtag(void); + void *cps_vec; + /* We want to ensure cache is clean before writing uncached mem */ blast_dcache_range(TO_CAC(cps_vec_pa), TO_CAC(cps_vec_pa) + BEV_VEC_SIZE); bc_wback_inv(TO_CAC(cps_vec_pa), BEV_VEC_SIZE); @@ -161,8 +166,6 @@ static int __init setup_cps_vecs(void) blast_inv_dcache_range(TO_CAC(cps_vec_pa), TO_CAC(cps_vec_pa) + BEV_VEC_SIZE); bc_inv(TO_CAC(cps_vec_pa), BEV_VEC_SIZE); __sync(); - - return 0; } static void __init cps_smp_setup(void) @@ -224,8 +227,8 @@ static void __init cps_smp_setup(void) /* Make core 0 coherent with everything */ write_gcr_cl_coherence(0xff); - if (setup_cps_vecs()) - pr_err("Failed to setup CPS vectors\n"); + if (allocate_cps_vecs()) + pr_err("Failed to allocate CPS vectors\n"); if (core_entry_reg && mips_cm_revision() >= CM_REV_CM3) write_gcr_bev_base(core_entry_reg); @@ -280,6 +283,7 @@ static void __init cps_prepare_cpus(unsigned int max_cpus) (cca_unsuitable && cpu_has_dc_aliases) ? " & " : "", cpu_has_dc_aliases ? "dcache aliasing" : ""); + setup_cps_vecs(); /* Allocate core boot configuration structs */ ncores = mips_cps_numcores(0); From patchwork Tue Dec 12 16:34:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 13489631 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="obJtsQ/L" Received: from relay9-d.mail.gandi.net (relay9-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::229]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7BAB0115; Tue, 12 Dec 2023 08:35:32 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPSA id A86D2FF81C; Tue, 12 Dec 2023 16:35:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1702398931; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=7Hs8erXZl4NlWl7+f8VZWG3NaOSPZoMSP8HqcLsJyRM=; b=obJtsQ/LHcmycBwrOwk4+lNBMUbkfe7xBCh1X6nSMCVKfdqaokSlUAR6jnhZTxNTDT63Tp fRw1gWxHEtB0HO4Mbg52NgKSt+KIMV5iXhOc0uUrO5KTADI8e8qkftwCxVD7erTkaNUCOC q7BVeaV0BgK7SRoT9CaYql+kDxgmODUYXiXfQS+Pz+3Z5aib0vw5GYYhVnwfYH/z2cMPlR q0gNU4GLFWZLejxjLwwP3uuZ4K/bkLPS/RS43MQAgkYdOvhGOf7Drf+/5UjqYEUuEZ9AuT LZ0hbzIKHozNBgXXbQ3Q4yq70uQTU4irE0Oebaz+PsM3jONMNWm5sNBEf4vGMQ== From: Gregory CLEMENT To: Paul Burton , Thomas Bogendoerfer , linux-mips@vger.kernel.org, Jiaxun Yang , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Vladimir Kondratiev , Tawfik Bayouk , Alexandre Belloni , =?utf-8?q?Th=C3=A9o_Lebr?= =?utf-8?q?un?= , Thomas Petazzoni Subject: [PATCH v5 08/22] MIPS: Allow kernel base to be set from Kconfig for all platforms Date: Tue, 12 Dec 2023 17:34:40 +0100 Message-ID: <20231212163459.1923041-9-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231212163459.1923041-1-gregory.clement@bootlin.com> References: <20231212163459.1923041-1-gregory.clement@bootlin.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: gregory.clement@bootlin.com From: Jiaxun Yang There are some platforms in wild that generic loading address won't work with them due to memory layout. Allow PHYSICAL_START to be override from Kconfig, introduce PHYSICAL_START_BOOL symbol as powerpc did. Signed-off-by: Jiaxun Yang --- arch/mips/Kconfig | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 2480a2cdddf1e..518376d578b70 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -2868,12 +2868,22 @@ config ARCH_SUPPORTS_KEXEC config ARCH_SUPPORTS_CRASH_DUMP def_bool y +config PHYSICAL_START_BOOL + bool "Set physical address where the kernel is loaded" + default y if CRASH_DUMP + help + This gives the CKSEG0, KSEG0 or XKPHYS address where the kernel + is loaded. + + Say N here unless you know what you are doing. + config PHYSICAL_START - hex "Physical address where the kernel is loaded" - default "0xffffffff84000000" - depends on CRASH_DUMP + hex "Physical address where the kernel is loaded" if PHYSICAL_START_BOOL + default "0xffffffff84000000" if CRASH_DUMP + default "0xffffffff80100000" help - This gives the CKSEG0 or KSEG0 address where the kernel is loaded. + This gives the CKSEG0, KSEG0 or XKPHYS address where the kernel + is loaded. If you plan to use kernel for capturing the crash dump change this value to start of the reserved region (the "X" value as specified in the "crashkernel=YM@XM" command line boot parameter From patchwork Tue Dec 12 16:34:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 13489633 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="Tf9jdRrS" Received: from relay8-d.mail.gandi.net (relay8-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::228]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4939CE3; Tue, 12 Dec 2023 08:35:33 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPSA id 678F01BF20E; Tue, 12 Dec 2023 16:35:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1702398931; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=s2HCa2+WQTWUMv9knwwE3fae1I7Q3ql8eVrDv9QUTaY=; b=Tf9jdRrSxXhoqOSFjwX/EXp1SxnnFjE15jIf+AR/W97xv7LdNXNXSiQKMPBtJBaI8jsM8u SOqyEZyudl2wAnWdTGS8im3yKZxp+EcuYsmEaTHSQoDPcQtO9bWp5CcsVK16xiTHfNJxf4 zK8EtY1PpfaouL3na3P0lEvbAVjnjLTMiYV5AY1DdBmYzc951qg3qT12Ck1zmx/613V4In oKEV3dQ3SZyMlhdXo1SxKXirl8s7fIPySmjxznNgRtwEoGdoHfdARgmJK/llgpF2DEg2Jw B996h7VjwNbbVaLSn4EzA0gIxTTZFkggUFXU5Sm4VJEPZQNfi0QNnbFHoml5cA== From: Gregory CLEMENT To: Paul Burton , Thomas Bogendoerfer , linux-mips@vger.kernel.org, Jiaxun Yang , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Vladimir Kondratiev , Tawfik Bayouk , Alexandre Belloni , =?utf-8?q?Th=C3=A9o_Lebr?= =?utf-8?q?un?= , Thomas Petazzoni Subject: [PATCH v5 09/22] MIPS: traps: Handle CPU with non standard vint offset Date: Tue, 12 Dec 2023 17:34:41 +0100 Message-ID: <20231212163459.1923041-10-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231212163459.1923041-1-gregory.clement@bootlin.com> References: <20231212163459.1923041-1-gregory.clement@bootlin.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: gregory.clement@bootlin.com From: Jiaxun Yang Some BMIPS cpus has none standard start offset for vector interrupts. Handle those CPUs in vector size calculation and handler setup process. Signed-off-by: Jiaxun Yang --- arch/mips/kernel/traps.c | 32 +++++++++++++++++++++++--------- 1 file changed, 23 insertions(+), 9 deletions(-) diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index ea59d321f713e..7e6e6df59e6d7 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -74,7 +74,6 @@ #include "access-helper.h" -#define MAX(a, b) ((a) >= (b) ? (a) : (b)) extern void check_wait(void); extern asmlinkage void rollback_handle_int(void); @@ -2005,6 +2004,7 @@ void __noreturn nmi_exception_handler(struct pt_regs *regs) unsigned long ebase; EXPORT_SYMBOL_GPL(ebase); unsigned long exception_handlers[32]; +static unsigned long vi_vecbase; unsigned long vi_handlers[64]; void reserve_exception_space(phys_addr_t addr, unsigned long size) @@ -2074,7 +2074,7 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) handler = (unsigned long) addr; vi_handlers[n] = handler; - b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING); + b = (unsigned char *)(vi_vecbase + n * VECTORSPACING); if (srs >= srssets) panic("Shadow register set %d not supported", srs); @@ -2370,20 +2370,33 @@ void __init trap_init(void) extern char except_vec3_generic; extern char except_vec4; extern char except_vec3_r4000; - unsigned long i, vec_size; + unsigned long i, vec_size, vi_vec_offset; phys_addr_t ebase_pa; check_wait(); + if (cpu_has_veic || cpu_has_vint) { + switch (current_cpu_type()) { + case CPU_BMIPS3300: + case CPU_BMIPS4380: + vi_vec_offset = 0x400; + break; + case CPU_BMIPS5000: + vi_vec_offset = 0x1000; + break; + default: + vi_vec_offset = 0x200; + break; + } + vec_size = vi_vec_offset + VECTORSPACING * 64; + } else { + vec_size = 0x400; + } + if (!cpu_has_mips_r2_r6) { ebase = CAC_BASE; - vec_size = 0x400; } else { - if (cpu_has_veic || cpu_has_vint) - vec_size = 0x200 + VECTORSPACING*64; - else - vec_size = PAGE_SIZE; - + vec_size = max(vec_size, PAGE_SIZE); ebase_pa = memblock_phys_alloc(vec_size, 1 << fls(vec_size)); if (!ebase_pa) panic("%s: Failed to allocate %lu bytes align=0x%x\n", @@ -2450,6 +2463,7 @@ void __init trap_init(void) * Initialise interrupt handlers */ if (cpu_has_veic || cpu_has_vint) { + vi_vecbase = ebase + vi_vec_offset; int nvec = cpu_has_veic ? 64 : 8; for (i = 0; i < nvec; i++) set_vi_handler(i, NULL); From patchwork Tue Dec 12 16:34:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 13489635 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="j8SL/s+J" Received: from relay6-d.mail.gandi.net (relay6-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::226]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C6C6DA8; Tue, 12 Dec 2023 08:35:33 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPSA id 0D15CC000E; Tue, 12 Dec 2023 16:35:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1702398932; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ktTTyr0RlfRgBEvWUnjy95sG7EHyWXVrxSqbNjLTqqU=; b=j8SL/s+JKqdFRUq4rxjHbv1Z8aQfOG3Fdr9Qg4doJZaumc4gPtzMh1tBVHQbn00yFNV2i7 GR3B6rX16ranQs/MUIYpA1L4oT29ig96JQdIPyA5Jx8wwyYZNtMAWXAPERuGvUtPa+bWcp FjyamVci/1mfHZCxT7MKIKMK0CDzhdk9S6MO6QBGOvyYhe6c2j1wF4d1/EA7MVfWCAffcq B1fo0OTuTSaj+Fy0EdDlx5lppR/4q18dvBGWrNd3ogpopioHf4jBEX8W/cfjEuTeKuLSvN MQ7VcP0o9dwkgBRcuD8TUTDSfB60oHRAjSj2AU7fnBsJXyxPv9DreBjcAio+RA== From: Gregory CLEMENT To: Paul Burton , Thomas Bogendoerfer , linux-mips@vger.kernel.org, Jiaxun Yang , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Vladimir Kondratiev , Tawfik Bayouk , Alexandre Belloni , =?utf-8?q?Th=C3=A9o_Lebr?= =?utf-8?q?un?= , Thomas Petazzoni Subject: [PATCH v5 10/22] MIPS: Avoid unnecessary reservation of exception space Date: Tue, 12 Dec 2023 17:34:42 +0100 Message-ID: <20231212163459.1923041-11-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231212163459.1923041-1-gregory.clement@bootlin.com> References: <20231212163459.1923041-1-gregory.clement@bootlin.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: gregory.clement@bootlin.com From: Jiaxun Yang Nowadays we allocate exception base from memblock for r2_r6, so we don't need to reverse exception space at the start of the memory for r2_r6 processors. For older processors the reservation is moved to traps_init where we have knowledge of exact size we need. We also add a sanity check to detect possible overlap with kernel. Signed-off-by: Jiaxun Yang --- arch/mips/include/asm/traps.h | 1 - arch/mips/kernel/cpu-probe.c | 5 ----- arch/mips/kernel/cpu-r3k-probe.c | 2 -- arch/mips/kernel/traps.c | 12 +++++++----- 4 files changed, 7 insertions(+), 13 deletions(-) diff --git a/arch/mips/include/asm/traps.h b/arch/mips/include/asm/traps.h index 15cde638b4070..d3dddd1c083a9 100644 --- a/arch/mips/include/asm/traps.h +++ b/arch/mips/include/asm/traps.h @@ -24,7 +24,6 @@ extern void (*board_ebase_setup)(void); extern void (*board_cache_error_setup)(void); extern int register_nmi_notifier(struct notifier_block *nb); -extern void reserve_exception_space(phys_addr_t addr, unsigned long size); extern char except_vec_nmi[]; #define VECTORSPACING 0x100 /* for EI/VI mode */ diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index b406d8bfb15a3..54e8b0fd4a2ab 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -1570,7 +1570,6 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) c->cputype = CPU_BMIPS3300; __cpu_name[cpu] = "Broadcom BMIPS3300"; set_elf_platform(cpu, "bmips3300"); - reserve_exception_space(0x400, VECTORSPACING * 64); break; case PRID_IMP_BMIPS43XX: { int rev = c->processor_id & PRID_REV_MASK; @@ -1581,7 +1580,6 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) __cpu_name[cpu] = "Broadcom BMIPS4380"; set_elf_platform(cpu, "bmips4380"); c->options |= MIPS_CPU_RIXI; - reserve_exception_space(0x400, VECTORSPACING * 64); } else { c->cputype = CPU_BMIPS4350; __cpu_name[cpu] = "Broadcom BMIPS4350"; @@ -1598,7 +1596,6 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) __cpu_name[cpu] = "Broadcom BMIPS5000"; set_elf_platform(cpu, "bmips5000"); c->options |= MIPS_CPU_ULRI | MIPS_CPU_RIXI; - reserve_exception_space(0x1000, VECTORSPACING * 64); break; } } @@ -1996,8 +1993,6 @@ void cpu_probe(void) if (cpu == 0) __ua_limit = ~((1ull << cpu_vmbits) - 1); #endif - - reserve_exception_space(0, 0x1000); } void cpu_report(void) diff --git a/arch/mips/kernel/cpu-r3k-probe.c b/arch/mips/kernel/cpu-r3k-probe.c index be93469c0e0ec..05410b743e571 100644 --- a/arch/mips/kernel/cpu-r3k-probe.c +++ b/arch/mips/kernel/cpu-r3k-probe.c @@ -137,8 +137,6 @@ void cpu_probe(void) cpu_set_fpu_opts(c); else cpu_set_nofpu_opts(c); - - reserve_exception_space(0, 0x400); } void cpu_report(void) diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 7e6e6df59e6d7..a6d0ae12b3c4c 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -2007,10 +2007,6 @@ unsigned long exception_handlers[32]; static unsigned long vi_vecbase; unsigned long vi_handlers[64]; -void reserve_exception_space(phys_addr_t addr, unsigned long size) -{ - memblock_reserve(addr, size); -} void __init *set_except_vector(int n, void *addr) { @@ -2394,7 +2390,13 @@ void __init trap_init(void) } if (!cpu_has_mips_r2_r6) { - ebase = CAC_BASE; + ebase_pa = 0x0; + ebase = CKSEG0ADDR(ebase_pa); + + if (__pa_symbol(_stext) < (ebase_pa + vec_size)) + pr_err("Insufficient space for exception vectors\n"); + + memblock_reserve(ebase_pa, vec_size); } else { vec_size = max(vec_size, PAGE_SIZE); ebase_pa = memblock_phys_alloc(vec_size, 1 << fls(vec_size)); From patchwork Tue Dec 12 16:34:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 13489636 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="LbdYo6lR" Received: from relay5-d.mail.gandi.net (relay5-d.mail.gandi.net [217.70.183.197]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D21F5F5; Tue, 12 Dec 2023 08:35:34 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPSA id ACB801C0007; Tue, 12 Dec 2023 16:35:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1702398933; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=zLrp9lcJ5PQW92KPtBpFPcB6UQzVTee0sSxnR5o7EZA=; b=LbdYo6lRPpwdkiC1qRLoOCK7PkZyJJ8wPXnnbyNgoAFGmOwuqvKikSrMRM7k5MIp4LySGy YltKy8oLdARmXSzPt/H2hjukhd4OrjJaL90nUzQoc/XOYGoZSl39h43pNxRnZ+FZvOZ/yW nBXl1fK+nBShY7Yhc31I8JtVQyC1oKSjYcGXIuym6db2d0DUx6fWaQybMqwO+/5+F+Sj9k e6vFs040Q8Zg5Rio2cwx+YrTk0Q5GCoM27leEtGxSMEHRD200gsQZ0JcSLEzcnCjKnlpdY r0PxkoWG1gZU/K/S+KTqQQSlG/Qowm/QoQFB05Irb75f8kS5V5mDf395KD+MmA== From: Gregory CLEMENT To: Paul Burton , Thomas Bogendoerfer , linux-mips@vger.kernel.org, Jiaxun Yang , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Vladimir Kondratiev , Tawfik Bayouk , Alexandre Belloni , =?utf-8?q?Th=C3=A9o_Lebr?= =?utf-8?q?un?= , Thomas Petazzoni Subject: [PATCH v5 11/22] MIPS: traps: Enhance memblock ebase allocation process Date: Tue, 12 Dec 2023 17:34:43 +0100 Message-ID: <20231212163459.1923041-12-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231212163459.1923041-1-gregory.clement@bootlin.com> References: <20231212163459.1923041-1-gregory.clement@bootlin.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: gregory.clement@bootlin.com From: Jiaxun Yang We try to allocate from KSEG0 accessible space first, and then if we really can't allocate any memory from KSEG0 and we are sure that we support ebase in higher segment, give it another go without restriction. This can maximize the possibility of having ebase in KSEG0. Signed-off-by: Jiaxun Yang --- arch/mips/kernel/traps.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index a6d0ae12b3c4c..089247555c752 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -2399,7 +2399,12 @@ void __init trap_init(void) memblock_reserve(ebase_pa, vec_size); } else { vec_size = max(vec_size, PAGE_SIZE); - ebase_pa = memblock_phys_alloc(vec_size, 1 << fls(vec_size)); + ebase_pa = memblock_phys_alloc_range(vec_size, 1 << fls(vec_size), + 0x0, KSEGX_SIZE - 1); + + if (!ebase_pa && (IS_ENABLED(CONFIG_EVA) || cpu_has_ebase_wg)) + ebase_pa = memblock_phys_alloc(vec_size, 1 << fls(vec_size)); + if (!ebase_pa) panic("%s: Failed to allocate %lu bytes align=0x%x\n", __func__, vec_size, 1 << fls(vec_size)); From patchwork Tue Dec 12 16:34:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 13489640 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="Bl13/Lkl" Received: from relay3-d.mail.gandi.net (relay3-d.mail.gandi.net [217.70.183.195]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1435610B; Tue, 12 Dec 2023 08:35:35 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPSA id 876196000A; Tue, 12 Dec 2023 16:35:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1702398934; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=xbVhFI1ZSGx1syULTaPHmMoUG7Z8rPeb2O8T42Bf6J0=; b=Bl13/LklFdMlZCq+xi34hEBNI5XOCfoKecmZRoJXC0V5Zv+kC/4dg46+mSjU8SyCDtxHVz Z7RK4V2/JNx2nRT0EL69glSn0cYryHwTptJOcVKlVCyJzhLqqo4U4+JmVXuWVsGUtrQuVi 9D7SJCJwZ1QYsYP8A93mIk3ZkHzyu9B1aE77yRtuVtOJA9zxh10NXzRBGfylvxOLOq9VNA BDNOmIlYgacBoH0iwJZiYQXz4GH4Ls/oko06JFt7cnSIACm7/KhBs89msQTT70im/Zb40V gj42J1SlWOdHfbKofcofYWordNIeTKdJLtBJlJ+bCaDUixbNyAugpGF9U0XBMA== From: Gregory CLEMENT To: Paul Burton , Thomas Bogendoerfer , linux-mips@vger.kernel.org, Jiaxun Yang , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Vladimir Kondratiev , Tawfik Bayouk , Alexandre Belloni , =?utf-8?q?Th=C3=A9o_Lebr?= =?utf-8?q?un?= , Thomas Petazzoni Subject: [PATCH v5 12/22] MIPS: Get rid of CONFIG_NO_EXCEPT_FILL Date: Tue, 12 Dec 2023 17:34:44 +0100 Message-ID: <20231212163459.1923041-13-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231212163459.1923041-1-gregory.clement@bootlin.com> References: <20231212163459.1923041-1-gregory.clement@bootlin.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: gregory.clement@bootlin.com From: Jiaxun Yang NO_EXCEPT_FILL is employed to signal the platform that there is no requirement to reserve EBASE memory at the beginning of the kernel. This holds true for all R2+ platforms, as they dynamically allocate ebase memory. It is also applicable to any platform that doesn't load the kernel at the start of physical memory. Eliminate this Kconfig symbol by employing a macro to identify the mentioned conditions. gc: use KSEG0 only for 32 bit configuration Signed-off-by: Jiaxun Yang --- arch/mips/Kconfig | 8 -------- arch/mips/kernel/head.S | 7 +++++-- 2 files changed, 5 insertions(+), 10 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 518376d578b70..59bc956859292 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -150,7 +150,6 @@ config MIPS_GENERIC_KERNEL select MIPS_CPU_SCACHE select MIPS_GIC select MIPS_L1_CACHE_SHIFT_7 - select NO_EXCEPT_FILL select PCI_DRIVERS_GENERIC select SMP_UP if SMP select SWAP_IO_SPACE @@ -244,7 +243,6 @@ config BMIPS_GENERIC select ARCH_HAS_RESET_CONTROLLER select ARCH_HAS_SYNC_DMA_FOR_CPU_ALL select BOOT_RAW - select NO_EXCEPT_FILL select USE_OF select CEVT_R4K select CSRC_R4K @@ -288,7 +286,6 @@ config BCM47XX select HAVE_PCI select IRQ_MIPS_CPU select SYS_HAS_CPU_MIPS32_R1 - select NO_EXCEPT_FILL select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_SUPPORTS_MIPS16 @@ -424,7 +421,6 @@ config LANTIQ select IRQ_MIPS_CPU select CEVT_R4K select CSRC_R4K - select NO_EXCEPT_FILL select SYS_HAS_CPU_MIPS32_R1 select SYS_HAS_CPU_MIPS32_R2 select SYS_SUPPORTS_BIG_ENDIAN @@ -474,7 +470,6 @@ config MACH_LOONGSON64 select ISA select I8259 select IRQ_MIPS_CPU - select NO_EXCEPT_FILL select NR_CPUS_DEFAULT_64 select USE_GENERIC_EARLY_PRINTK_8250 select PCI_DRIVERS_GENERIC @@ -1157,9 +1152,6 @@ config PCI_GT64XXX_PCI0 config PCI_XTALK_BRIDGE bool -config NO_EXCEPT_FILL - bool - config MIPS_SPRAM bool diff --git a/arch/mips/kernel/head.S b/arch/mips/kernel/head.S index b825ed4476c70..51a0ad49ac388 100644 --- a/arch/mips/kernel/head.S +++ b/arch/mips/kernel/head.S @@ -59,10 +59,13 @@ #endif .endm -#ifndef CONFIG_NO_EXCEPT_FILL +#if (MIPS_ISA_REV < 2) && \ + ((!defined( CONFIG_64BIT) && (VMLINUX_LOAD_ADDRESS == KSEG0)) || \ + (VMLINUX_LOAD_ADDRESS == CKSEG0)) /* * Reserved space for exception handlers. - * Necessary for machines which link their kernels at KSEG0. + * Necessary for machines which link their kernels at KSEG0 + * and incapable of moving ebase. */ .fill 0x400 #endif From patchwork Tue Dec 12 16:34:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 13489637 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="YbcdPJ4z" Received: from relay9-d.mail.gandi.net (relay9-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::229]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4435E113; Tue, 12 Dec 2023 08:35:36 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPSA id 6CB22FF817; Tue, 12 Dec 2023 16:35:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1702398934; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=7XY5RosXYCLwcWB1g4w/xI8Tyluf+oMKzZZFQCrss2s=; b=YbcdPJ4zbavgv4jdwBSz0ZDghLADAlyp17PeUykF/oogpxrztDatpkFG9+jDAu6NO/WL+C Qjr58YFL2xpy7DS10OV2aytcLP3Gv1bk9NUgh4U2Hlvya3glyMpNge9OJyunPYyNCuI/KY aPZ+KflXA9kcjQg9AVQFdRuq2wjxhgmUIum+hmyUVJrQVSj/YWSqmoQvTAo+NuaeC4nlnA t08SySZ4cau+sgrdudi5CI6ki9Fr7c1LYOzuwFcBBmLB0FmHBlEnpqw/XtkIzgsSfMKTRo KXBYMdbYwWweEB+48LtTqm8t8yTqEqC/sjyzdRJq+RysWmVJWR4zzvcX9hY9kw== From: Gregory CLEMENT To: Paul Burton , Thomas Bogendoerfer , linux-mips@vger.kernel.org, Jiaxun Yang , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Vladimir Kondratiev , Tawfik Bayouk , Alexandre Belloni , =?utf-8?q?Th=C3=A9o_Lebr?= =?utf-8?q?un?= , Thomas Petazzoni , Gregory CLEMENT Subject: [PATCH v5 13/22] MIPS: traps: Give more explanations if ebase doesn't belong to KSEG0 Date: Tue, 12 Dec 2023 17:34:45 +0100 Message-ID: <20231212163459.1923041-14-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231212163459.1923041-1-gregory.clement@bootlin.com> References: <20231212163459.1923041-1-gregory.clement@bootlin.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: gregory.clement@bootlin.com With the expanded support for placing the kernel in XPHYS rather than just KSEG0, scenarios where ebase doesn't belong to KSEG0 are more likely to occur. In such cases, we currently experience a substantial and perplexing stack dump without any accompanying explanation. To rectify this, we aim to replace the uninformative stack dump with a warning that offers a clear explanation of the issue. Signed-off-by: Gregory CLEMENT --- arch/mips/kernel/traps.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 089247555c752..67c7c23fe4f73 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -2420,10 +2420,13 @@ void __init trap_init(void) * EVA is special though as it allows segments to be rearranged * and to become uncached during cache error handling. */ - if (!IS_ENABLED(CONFIG_EVA) && !WARN_ON(ebase_pa >= 0x20000000)) + if (!IS_ENABLED(CONFIG_EVA) && ebase_pa < 0x20000000) ebase = CKSEG0ADDR(ebase_pa); else ebase = (unsigned long)phys_to_virt(ebase_pa); + if (ebase_pa >= 0x20000000) + pr_warn("ebase(%pa) should better be in KSeg0", + &ebase_pa); } if (cpu_has_mmips) { From patchwork Tue Dec 12 16:34:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 13489638 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="i/TqscSh" Received: from relay1-d.mail.gandi.net (relay1-d.mail.gandi.net [217.70.183.193]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8542011D; Tue, 12 Dec 2023 08:35:37 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPSA id 3B2E3240007; Tue, 12 Dec 2023 16:35:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1702398935; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=gZ7oKcw0eqw6lprpX+dDIOb31hPprI1Sem1ITgrbMiU=; b=i/TqscShoWirFV4LQ9T1aqY64nGNRhC5H7PYstoLwNdsGWs4TAaJoGfj7f+k20cJiU0fL1 dCeSyLhzwMSkK5vORdafkBseYAM+6oJlSKVSrSehnH2Mpn7WU/Js+gK1QHUSuEmY6nq/Nr OJCmwdlkD+5KqYcCaF6uGiwBd2EVDN7T6CmnJkddLWmlxb3wreEfOI8mOmF2JOugOrU0S7 Kg5wcax+1sJ7tFhyxwILZaZ7SaFeIXc8Lct6NMNbYAMms1p4wEtk8Eom2uqZ0lD34B9ibZ /X9v/9+dFMxgiLlMkIs8J4x3bQ/vAT6GKfbyPRd2uX2LCcsIZCmysPpxZo/+vA== From: Gregory CLEMENT To: Paul Burton , Thomas Bogendoerfer , linux-mips@vger.kernel.org, Jiaxun Yang , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Vladimir Kondratiev , Tawfik Bayouk , Alexandre Belloni , =?utf-8?q?Th=C3=A9o_Lebr?= =?utf-8?q?un?= , Thomas Petazzoni , Gregory CLEMENT , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Rob Herring Subject: [PATCH v5 14/22] dt-bindings: Add vendor prefix for Mobileye Vision Technologies Ltd. Date: Tue, 12 Dec 2023 17:34:46 +0100 Message-ID: <20231212163459.1923041-15-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231212163459.1923041-1-gregory.clement@bootlin.com> References: <20231212163459.1923041-1-gregory.clement@bootlin.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: gregory.clement@bootlin.com Mobileye Vision Technologies Ltd. is a company developing autonomous driving technologies and advanced driver-assistance systems (ADAS) including cameras, computer chips and software. Reviewed-by: Philippe Mathieu-Daudé Acked-by: Rob Herring Signed-off-by: Gregory CLEMENT --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 309b94c328c84..b45279bc97c14 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -897,6 +897,8 @@ patternProperties: description: Miyoo "^mntre,.*": description: MNT Research GmbH + "^mobileye,.*": + description: Mobileye Vision Technologies Ltd. "^modtronix,.*": description: Modtronix Engineering "^moortec,.*": From patchwork Tue Dec 12 16:34:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 13489639 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="eAcAYqpz" Received: from relay9-d.mail.gandi.net (relay9-d.mail.gandi.net [217.70.183.199]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E048011F; Tue, 12 Dec 2023 08:35:37 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPSA id EAA3CFF805; Tue, 12 Dec 2023 16:35:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1702398936; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=hweC77A4qTiukJmzDsKWoV1ZESOCwoXMkWKMnWM/4uQ=; b=eAcAYqpzCyJ6Pgu0gB32DTZHOIYSBLAyhc646XLgwPTGHNzKongQHmhlVesMLH0SsgyT+J nsQSuadYTIlRbwtM97Bj/47XIURU5ssOyakg6ujAVKxiCAbumXK9LL0AQ0V80IKgoVVduk rK7SOEQDgi7+w3m5U59cs3E6AEg2AVPUkrQs2jsCpTX/8mM1gEzA9J9Vg3HyydvqexJ/cD mGDXL+5dScpK9HK8HQ6i/laAQCSAcMFmH8Ve8+EcWdzx6Wzlr9LiaivdspI8FX0yz1R2Pg D7r+S72+4wEgj/aUMuidO4v0unvHtnh5ltu9kYdbsgEGPpatgyWSYxEdXY5Epw== From: Gregory CLEMENT To: Paul Burton , Thomas Bogendoerfer , linux-mips@vger.kernel.org, Jiaxun Yang , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Vladimir Kondratiev , Tawfik Bayouk , Alexandre Belloni , =?utf-8?q?Th=C3=A9o_Lebr?= =?utf-8?q?un?= , Thomas Petazzoni , Gregory CLEMENT , Serge Semin , Krzysztof Kozlowski Subject: [PATCH v5 15/22] dt-bindings: mips: cpus: Sort the entries Date: Tue, 12 Dec 2023 17:34:47 +0100 Message-ID: <20231212163459.1923041-16-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231212163459.1923041-1-gregory.clement@bootlin.com> References: <20231212163459.1923041-1-gregory.clement@bootlin.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: gregory.clement@bootlin.com The entries were nearly sorted but there were still some entries at the wrong places. Let's fix it. Reviewed-by: Serge Semin Acked-by: Krzysztof Kozlowski Signed-off-by: Gregory CLEMENT --- Documentation/devicetree/bindings/mips/cpus.yaml | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/mips/cpus.yaml b/Documentation/devicetree/bindings/mips/cpus.yaml index cf382dea3922c..9bc47868d28b6 100644 --- a/Documentation/devicetree/bindings/mips/cpus.yaml +++ b/Documentation/devicetree/bindings/mips/cpus.yaml @@ -23,22 +23,22 @@ properties: - brcm,bmips4380 - brcm,bmips5000 - brcm,bmips5200 - - ingenic,xburst-mxu1.0 - ingenic,xburst-fpu1.0-mxu1.1 - ingenic,xburst-fpu2.0-mxu2.0 + - ingenic,xburst-mxu1.0 - ingenic,xburst2-fpu2.1-mxu2.1-smt - loongson,gs264 - mips,m14Kc - - mips,mips4Kc - - mips,mips4KEc - - mips,mips24Kc + - mips,mips1004Kc - mips,mips24KEc + - mips,mips24Kc + - mips,mips4KEc + - mips,mips4Kc - mips,mips74Kc - - mips,mips1004Kc - mti,interaptiv - - mti,mips24KEc - mti,mips14KEc - mti,mips14Kc + - mti,mips24KEc reg: maxItems: 1 From patchwork Tue Dec 12 16:34:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 13489642 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="Vy3ckR3V" Received: from relay2-d.mail.gandi.net (relay2-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::222]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 307EA110; Tue, 12 Dec 2023 08:35:38 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPSA id A83564000F; Tue, 12 Dec 2023 16:35:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1702398937; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=/+KygOxw7upzFkFkKPQuC0aojbbTgfulc0YH1c5kUVo=; b=Vy3ckR3VwxVy0nDMIHY7AbZzMDkQZukS+BXdEbip5cfNtQrRqzzJidZAC9WKKRjuPI/7FV WDmR1yOTMW2lvj9umhgtO/iiHhcw/MnCB2tpgiCz0rZZfB1lej3l0JdMPmcPj3uK+D/zip q5fp30z/i10h9oIXr5cyzoX9S/T4WRUMKyMZ4rNM9Hc6X+CgUJotDjQCMSzDvuflElwkpW vQKyT+aYfcLEW/0qwup9Y1qKS6nEmeasmEtPXC5XHWbh52z0Eqrkohnt7Ivk4mwoGoruMu LggSuEKd9Gw8mOy8aD7D8ZRqucPweJaFGt1vjDa7o7ZSQXrhxJ1u/0u8csVeYg== From: Gregory CLEMENT To: Paul Burton , Thomas Bogendoerfer , linux-mips@vger.kernel.org, Jiaxun Yang , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Vladimir Kondratiev , Tawfik Bayouk , Alexandre Belloni , =?utf-8?q?Th=C3=A9o_Lebr?= =?utf-8?q?un?= , Thomas Petazzoni , Gregory CLEMENT , Arnd Bergmann , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Serge Semin , Krzysztof Kozlowski Subject: [PATCH v5 16/22] dt-bindings: mips: cpu: Add I-Class I6500 Multiprocessor Core Date: Tue, 12 Dec 2023 17:34:48 +0100 Message-ID: <20231212163459.1923041-17-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231212163459.1923041-1-gregory.clement@bootlin.com> References: <20231212163459.1923041-1-gregory.clement@bootlin.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: gregory.clement@bootlin.com The MIPS Warrior I-class I6500 was announced by Imagination Technologies in 2016 and is used in the Mobileye SoC EyeQ5. Acked-by: Arnd Bergmann Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Serge Semin Acked-by: Krzysztof Kozlowski Signed-off-by: Gregory CLEMENT --- Documentation/devicetree/bindings/mips/cpus.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mips/cpus.yaml b/Documentation/devicetree/bindings/mips/cpus.yaml index 9bc47868d28b6..a85137add6689 100644 --- a/Documentation/devicetree/bindings/mips/cpus.yaml +++ b/Documentation/devicetree/bindings/mips/cpus.yaml @@ -23,6 +23,7 @@ properties: - brcm,bmips4380 - brcm,bmips5000 - brcm,bmips5200 + - img,i6500 - ingenic,xburst-fpu1.0-mxu1.1 - ingenic,xburst-fpu2.0-mxu2.0 - ingenic,xburst-mxu1.0 From patchwork Tue Dec 12 16:34:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 13489641 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="nM6Zxk3x" Received: from relay1-d.mail.gandi.net (relay1-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::221]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9C337130; Tue, 12 Dec 2023 08:35:39 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPSA id 97CC0240006; Tue, 12 Dec 2023 16:35:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1702398938; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=5J0TpG59q99eDXCElU/oJiTiWId7juQenPAyUFsRAno=; b=nM6Zxk3xxsfQigUYavYo3KaKY60bKbBc5QudIz5BVjlewN2F0WI6Jf/ndk3jAE7o4OL2/S 0uizhL7NT+V+QWBB/JgeKva9lm/rg0uQTdsEpLz+5EoaQbT37tSaJxviVWenepU8f6R0zR 5zghUE5yyXsQRpSSMNYyREQA4BCF96awPxx8YkBa5qiyw/+Vn4prsy0rwqB5YfjHHtB1Yz NbU9VnFCUUxxG5SACePwPV5Rnq5R12qGdbmkJXcozhoszhgx9ZE9OXBLkZxFcUmb7CmLlS Qaq3vdmJRX0kv2ZC3PmIk1O1+INl4E9R9RI1UMcNoHECPw0s2ybcRTmXruBKoA== From: Gregory CLEMENT To: Paul Burton , Thomas Bogendoerfer , linux-mips@vger.kernel.org, Jiaxun Yang , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Vladimir Kondratiev , Tawfik Bayouk , Alexandre Belloni , =?utf-8?q?Th=C3=A9o_Lebr?= =?utf-8?q?un?= , Thomas Petazzoni , Gregory CLEMENT , Rob Herring Subject: [PATCH v5 17/22] dt-bindings: mips: Add bindings for Mobileye SoCs Date: Tue, 12 Dec 2023 17:34:49 +0100 Message-ID: <20231212163459.1923041-18-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231212163459.1923041-1-gregory.clement@bootlin.com> References: <20231212163459.1923041-1-gregory.clement@bootlin.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: gregory.clement@bootlin.com Add the yaml bindings for Mobileye SoCs. Currently only EyeQ5 is supported Reviewed-by: Rob Herring Signed-off-by: Gregory CLEMENT --- .../devicetree/bindings/mips/mobileye.yaml | 32 +++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 Documentation/devicetree/bindings/mips/mobileye.yaml diff --git a/Documentation/devicetree/bindings/mips/mobileye.yaml b/Documentation/devicetree/bindings/mips/mobileye.yaml new file mode 100644 index 0000000000000..831975f6b479f --- /dev/null +++ b/Documentation/devicetree/bindings/mips/mobileye.yaml @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +# Copyright 2023 Mobileye Vision Technologies Ltd. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mips/mobileye.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mobileye SoC series + +maintainers: + - Vladimir Kondratiev + - Gregory CLEMENT + - Théo Lebrun + +description: + Boards with a Mobileye SoC shall have the following properties. + +properties: + $nodename: + const: '/' + + compatible: + oneOf: + - description: Boards with Mobileye EyeQ5 SoC + items: + - enum: + - mobileye,eyeq5-epm5 + - const: mobileye,eyeq5 + +additionalProperties: true + +... From patchwork Tue Dec 12 16:34:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 13489643 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="be2euZz7" Received: from relay9-d.mail.gandi.net (relay9-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::229]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 47E84E9; Tue, 12 Dec 2023 08:35:40 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPSA id 51793FF819; Tue, 12 Dec 2023 16:35:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1702398938; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=CCkW8mMra/OC394XuBHllm2zOVLtoeHjnt7KGkK+CU0=; b=be2euZz7xzQtYIH2FICjS7NGoVdb8qwxryMGyfqWcP/ijmZVTfAR5jJIE4hZOt32uZ2AxS oYEsL29k/qGL3rzX80nigvkeDU0Mq+pfvjBMiH9krieVjts6vpvDKaBoCaJTfVX8npEpiH 9v8Hf8GtEndpYDKb221qCWJxKMZ/iLKKmNbSbyoi/cr7Fwr5/oYfkyW0mX/dXRFrI+t9WL VeaciV7+YqnxAeCgwLPWqmIZV13LBypwmfKMuQw0t87tYmqd6i8kCCzpVTMXBuXF2ySLhu Ow59ii35bZMTyOIg7OA6aJVXvhpx9ShLMQQifQ3GxfLeu5LVP+Cv/5l9+4wu7w== From: Gregory CLEMENT To: Paul Burton , Thomas Bogendoerfer , linux-mips@vger.kernel.org, Jiaxun Yang , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Vladimir Kondratiev , Tawfik Bayouk , Alexandre Belloni , =?utf-8?q?Th=C3=A9o_Lebr?= =?utf-8?q?un?= , Thomas Petazzoni , Gregory CLEMENT , Krzysztof Kozlowski Subject: [PATCH v5 18/22] dt-bindings: mfd: syscon: Document EyeQ5 OLB Date: Tue, 12 Dec 2023 17:34:50 +0100 Message-ID: <20231212163459.1923041-19-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231212163459.1923041-1-gregory.clement@bootlin.com> References: <20231212163459.1923041-1-gregory.clement@bootlin.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: gregory.clement@bootlin.com Document Mobileye EyeQ5 compatibles for OLB registers that are miscellaneous SoC related registers. It is used to expose SoC specific configuration such as for example reset, clock or pinctrl. Acked-by: Krzysztof Kozlowski Signed-off-by: Gregory CLEMENT --- Documentation/devicetree/bindings/mfd/syscon.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml index 084b5c2a2a3c2..c90633460eeca 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -55,6 +55,7 @@ properties: - mediatek,mt8135-pctl-a-syscfg - mediatek,mt8135-pctl-b-syscfg - mediatek,mt8365-syscfg + - mobileye,eyeq5-olb - microchip,lan966x-cpu-syscon - microchip,sparx5-cpu-syscon - mstar,msc313-pmsleep From patchwork Tue Dec 12 16:34:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 13489645 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="XLZzoBPL" Received: from relay7-d.mail.gandi.net (relay7-d.mail.gandi.net [217.70.183.200]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6647A136; Tue, 12 Dec 2023 08:35:41 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPSA id 4119620003; Tue, 12 Dec 2023 16:35:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1702398939; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=nfmmkPLG/ll5NZfOYiII8ssFiuAZWR9wcDBKqL8DiFA=; b=XLZzoBPLuTYtdYVeQxybUA2re125RE9xwJ8R12YqVwLAEWQKaeQBQT3kR8lMarUebkNCjB FTO5mg5GFGfWXHhTOEIPSz8xTbpWCz/jwovjOKeJNqvq7SgzT1k1GyTXUtC8QhIz7AbIJ4 hh5h2V8hmegVgx2xKKC0Y50YU+QFG/ZsUT5iDC8x012qmGEKEgzube63p6nrnBcrOs7Pid Ht14umsaz/E62OvI22dcim3y/jqF87eQOV+iLDpLI/bEIIuh1E4OAMqkblEM9wHktJ1lO9 bZFGaR3h/PG/Om2xiwZX/eT1o+Gmoq7mugHZT1LhDUs0VfkT0C4Qbxd2Ch/TJA== From: Gregory CLEMENT To: Paul Burton , Thomas Bogendoerfer , linux-mips@vger.kernel.org, Jiaxun Yang , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Vladimir Kondratiev , Tawfik Bayouk , Alexandre Belloni , =?utf-8?q?Th=C3=A9o_Lebr?= =?utf-8?q?un?= , Thomas Petazzoni , Gregory CLEMENT Subject: [PATCH v5 19/22] MIPS: mobileye: Add EyeQ5 dtsi Date: Tue, 12 Dec 2023 17:34:51 +0100 Message-ID: <20231212163459.1923041-20-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231212163459.1923041-1-gregory.clement@bootlin.com> References: <20231212163459.1923041-1-gregory.clement@bootlin.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: gregory.clement@bootlin.com Add a device tree include file for the Mobileye EyeQ5 SoC. Based on the work of Slava Samsonov Signed-off-by: Gregory CLEMENT --- arch/mips/boot/dts/Makefile | 1 + .../boot/dts/mobileye/eyeq5-fixed-clocks.dtsi | 292 ++++++++++++++++++ arch/mips/boot/dts/mobileye/eyeq5.dtsi | 134 ++++++++ 3 files changed, 427 insertions(+) create mode 100644 arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi create mode 100644 arch/mips/boot/dts/mobileye/eyeq5.dtsi diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile index 928f38a79dff9..edb8e8dee7583 100644 --- a/arch/mips/boot/dts/Makefile +++ b/arch/mips/boot/dts/Makefile @@ -8,6 +8,7 @@ subdir-$(CONFIG_LANTIQ) += lantiq subdir-$(CONFIG_MACH_LOONGSON64) += loongson subdir-$(CONFIG_SOC_VCOREIII) += mscc subdir-$(CONFIG_MIPS_MALTA) += mti +subdir-$(CONFIG_SOC_EYEQ5) += mobileye subdir-$(CONFIG_LEGACY_BOARD_SEAD3) += mti subdir-$(CONFIG_FIT_IMAGE_FDT_NI169445) += ni subdir-$(CONFIG_MACH_PIC32) += pic32 diff --git a/arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi b/arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi new file mode 100644 index 0000000000000..78f5533a95c67 --- /dev/null +++ b/arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi @@ -0,0 +1,292 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright 2023 Mobileye Vision Technologies Ltd. + */ + +/ { + /* Fixed clock */ + pll_cpu: pll-cpu { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1500000000>; + }; + + pll_vdi: pll-vdi { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1280000000>; + }; + + pll_per: pll-per { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <2000000000>; + }; + + pll_ddr0: pll-ddr0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1857210000>; + }; + + pll_ddr1: pll-ddr1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1857210000>; + }; + +/* PLL_CPU derivatives */ + occ_cpu: occ-cpu { + compatible = "fixed-factor-clock"; + clocks = <&pll_cpu>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + si_css0_ref_clk: si-css0-ref-clk { /* gate ClkRstGen_si_css0_ref */ + compatible = "fixed-factor-clock"; + clocks = <&occ_cpu>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + cpc_clk: cpc-clk { + compatible = "fixed-factor-clock"; + clocks = <&si_css0_ref_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + core0_clk: core0-clk { + compatible = "fixed-factor-clock"; + clocks = <&si_css0_ref_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + core1_clk: core1-clk { + compatible = "fixed-factor-clock"; + clocks = <&si_css0_ref_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + core2_clk: core2-clk { + compatible = "fixed-factor-clock"; + clocks = <&si_css0_ref_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + core3_clk: core3-clk { + compatible = "fixed-factor-clock"; + clocks = <&si_css0_ref_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + cm_clk: cm-clk { + compatible = "fixed-factor-clock"; + clocks = <&si_css0_ref_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + mem_clk: mem-clk { + compatible = "fixed-factor-clock"; + clocks = <&si_css0_ref_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + occ_isram: occ-isram { + compatible = "fixed-factor-clock"; + clocks = <&pll_cpu>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + }; + isram_clk: isram-clk { /* gate ClkRstGen_isram */ + compatible = "fixed-factor-clock"; + clocks = <&occ_isram>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + occ_dbu: occ-dbu { + compatible = "fixed-factor-clock"; + clocks = <&pll_cpu>; + #clock-cells = <0>; + clock-div = <10>; + clock-mult = <1>; + }; + si_dbu_tp_pclk: si-dbu-tp-pclk { /* gate ClkRstGen_dbu */ + compatible = "fixed-factor-clock"; + clocks = <&occ_dbu>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; +/* PLL_VDI derivatives */ + occ_vdi: occ-vdi { + compatible = "fixed-factor-clock"; + clocks = <&pll_vdi>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + }; + vdi_clk: vdi-clk { /* gate ClkRstGen_vdi */ + compatible = "fixed-factor-clock"; + clocks = <&occ_vdi>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + occ_can_ser: occ-can-ser { + compatible = "fixed-factor-clock"; + clocks = <&pll_vdi>; + #clock-cells = <0>; + clock-div = <16>; + clock-mult = <1>; + }; + can_ser_clk: can-ser-clk { /* gate ClkRstGen_can_ser */ + compatible = "fixed-factor-clock"; + clocks = <&occ_can_ser>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + i2c_ser_clk: i2c-ser-clk { + compatible = "fixed-factor-clock"; + clocks = <&pll_vdi>; + #clock-cells = <0>; + clock-div = <20>; + clock-mult = <1>; + }; +/* PLL_PER derivatives */ + occ_periph: occ-periph { + compatible = "fixed-factor-clock"; + clocks = <&pll_per>; + #clock-cells = <0>; + clock-div = <16>; + clock-mult = <1>; + }; + periph_clk: periph-clk { + compatible = "fixed-factor-clock"; + clocks = <&occ_periph>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + can_clk: can-clk { + compatible = "fixed-factor-clock"; + clocks = <&occ_periph>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + spi_clk: spi-clk { + compatible = "fixed-factor-clock"; + clocks = <&occ_periph>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + uart_clk: uart-clk { + compatible = "fixed-factor-clock"; + clocks = <&occ_periph>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + i2c_clk: i2c-clk { + compatible = "fixed-factor-clock"; + clocks = <&occ_periph>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "i2c_clk"; + }; + timer_clk: timer-clk { + compatible = "fixed-factor-clock"; + clocks = <&occ_periph>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "timer_clk"; + }; + gpio_clk: gpio-clk { + compatible = "fixed-factor-clock"; + clocks = <&occ_periph>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "gpio_clk"; + }; + emmc_sys_clk: emmc-sys-clk { + compatible = "fixed-factor-clock"; + clocks = <&pll_per>; + #clock-cells = <0>; + clock-div = <10>; + clock-mult = <1>; + clock-output-names = "emmc_sys_clk"; + }; + ccf_ctrl_clk: ccf-ctrl-clk { + compatible = "fixed-factor-clock"; + clocks = <&pll_per>; + #clock-cells = <0>; + clock-div = <4>; + clock-mult = <1>; + clock-output-names = "ccf_ctrl_clk"; + }; + occ_mjpeg_core: occ-mjpeg-core { + compatible = "fixed-factor-clock"; + clocks = <&pll_per>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "occ_mjpeg_core"; + }; + hsm_clk: hsm-clk { /* gate ClkRstGen_hsm */ + compatible = "fixed-factor-clock"; + clocks = <&occ_mjpeg_core>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "hsm_clk"; + }; + mjpeg_core_clk: mjpeg-core-clk { /* gate ClkRstGen_mjpeg_gen */ + compatible = "fixed-factor-clock"; + clocks = <&occ_mjpeg_core>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "mjpeg_core_clk"; + }; + fcmu_a_clk: fcmu-a-clk { + compatible = "fixed-factor-clock"; + clocks = <&pll_per>; + #clock-cells = <0>; + clock-div = <20>; + clock-mult = <1>; + clock-output-names = "fcmu_a_clk"; + }; + occ_pci_sys: occ-pci-sys { + compatible = "fixed-factor-clock"; + clocks = <&pll_per>; + #clock-cells = <0>; + clock-div = <8>; + clock-mult = <1>; + clock-output-names = "occ_pci_sys"; + }; + pclk: pclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <250000000>; /* 250MHz */ + }; + tsu_clk: tsu-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; /* 125MHz */ + }; +}; diff --git a/arch/mips/boot/dts/mobileye/eyeq5.dtsi b/arch/mips/boot/dts/mobileye/eyeq5.dtsi new file mode 100644 index 0000000000000..2968c467a0552 --- /dev/null +++ b/arch/mips/boot/dts/mobileye/eyeq5.dtsi @@ -0,0 +1,134 @@ +// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* +* Copyright 2023 Mobileye Vision Technologies Ltd. +*/ + +#include + +/memreserve/ 0x40000000 0xc0000000; /* DDR32 */ +/memreserve/ 0x08000000 0x08000000; /* DDR_LOW */ + +#include "eyeq5-fixed-clocks.dtsi" + +/ { + #address-cells = <2>; + #size-cells = <2>; + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + device_type = "cpu"; + compatible = "img,i6500"; + reg = <0>; + clocks = <&core0_clk>; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* These reserved memory regions are also defined in bootmanager + * for configuring inbound translation for BARS, don't change + * these without syncing with bootmanager + */ + shmem0_reserved: shmem@804000000 { + reg = <0x8 0x04000000 0x0 0x1000000>; + }; + shmem1_reserved: shmem@805000000 { + reg = <0x8 0x05000000 0x0 0x1000000>; + }; + pci0_msi_reserved: pci0-msi@806000000 { + reg = <0x8 0x06000000 0x0 0x100000>; + }; + pci1_msi_reserved: pci1-msi@806100000 { + reg = <0x8 0x06100000 0x0 0x100000>; + }; + + mini_coredump0_reserved: mini-coredump0@806200000 { + reg = <0x8 0x06200000 0x0 0x100000>; + }; + mhm_reserved_0: the-mhm-reserved-0@0 { + reg = <0x8 0x00000000 0x0 0x0000800>; + }; + }; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + }; + + cpu_intc: interrupt-controller { + compatible = "mti,cpu-interrupt-controller"; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + + soc: soc { + #address-cells = <2>; + #size-cells = <2>; + ranges; + compatible = "simple-bus"; + + uart0: serial@800000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0 0x800000 0x0 0x1000>; + reg-io-width = <4>; + interrupt-parent = <&gic>; + interrupts = ; + clocks = <&uart_clk>, <&occ_periph>; + clock-names = "uartclk", "apb_pclk"; + }; + + uart1: serial@900000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0 0x900000 0x0 0x1000>; + reg-io-width = <4>; + interrupt-parent = <&gic>; + interrupts = ; + clocks = <&uart_clk>, <&occ_periph>; + clock-names = "uartclk", "apb_pclk"; + }; + + uart2: serial@a00000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0 0xa00000 0x0 0x1000>; + reg-io-width = <4>; + interrupt-parent = <&gic>; + interrupts = ; + clocks = <&uart_clk>, <&occ_periph>; + clock-names = "uartclk", "apb_pclk"; + }; + + olb: olb@e00000 { + compatible = "mobileye,eyeq5-olb", "syscon", "simple-mfd"; + reg = <0 0xe00000 0x0 0x400>; + reg-io-width = <4>; + }; + + gic: interrupt-controller@140000 { + compatible = "mti,gic"; + reg = <0x0 0x140000 0x0 0x20000>; + interrupt-controller; + #interrupt-cells = <3>; + + /* + * Declare the interrupt-parent even though the mti,gic + * binding doesn't require it, such that the kernel can + * figure out that cpu_intc is the root interrupt + * controller & should be probed first. + */ + interrupt-parent = <&cpu_intc>; + + timer { + compatible = "mti,gic-timer"; + interrupts = ; + clocks = <&core0_clk>; + }; + }; + }; +}; + From patchwork Tue Dec 12 16:34:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 13489644 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="TIDEvDgw" Received: from relay4-d.mail.gandi.net (relay4-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::224]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0E5F713A; Tue, 12 Dec 2023 08:35:41 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPSA id 33D8AE0016; Tue, 12 Dec 2023 16:35:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1702398940; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=PyCSrF1JgQ4iScyRiIk/6IapzgqC+RV3b88nNkBvQYI=; b=TIDEvDgw2yuYZbXXFk0d6ROsLrMNBOvNBM4JO52VcOElKGJVIY03bvidKHC1s9B+KBPhAD ZJ/OJ3gIfx3BhfEp9ffb0X3tC098J2nkgdHMeqr4UoDec1wN4ZvtWfw0VYqQmWok7DdzXD 6f4x4E4A40tMGajywikPIDdmva2B6JptlcA9hYshHCk1PFLSzcLBE7ywPEnOhy+tfZbApS MOoG3CjdSWwiLDGA6YhZzmnbvkZnCLUQn1FpjO6oyN5zKBmBVrS5slYzn4RLIH4rN8e0d9 jCDSUGnfRTyG3KvLdldZxj9Jiqh1s8cDKJiw77nWXlGF1GeXqKkWR6T1jnDXNw== From: Gregory CLEMENT To: Paul Burton , Thomas Bogendoerfer , linux-mips@vger.kernel.org, Jiaxun Yang , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Vladimir Kondratiev , Tawfik Bayouk , Alexandre Belloni , =?utf-8?q?Th=C3=A9o_Lebr?= =?utf-8?q?un?= , Thomas Petazzoni , Gregory CLEMENT Subject: [PATCH v5 20/22] MIPS: mobileye: Add EPM5 device tree Date: Tue, 12 Dec 2023 17:34:52 +0100 Message-ID: <20231212163459.1923041-21-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231212163459.1923041-1-gregory.clement@bootlin.com> References: <20231212163459.1923041-1-gregory.clement@bootlin.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: gregory.clement@bootlin.com Add a device tree for the Mobileye EPM5 evaluation board. Signed-off-by: Gregory CLEMENT --- arch/mips/boot/dts/mobileye/Makefile | 4 ++++ arch/mips/boot/dts/mobileye/eyeq5-epm5.dts | 24 ++++++++++++++++++++++ 2 files changed, 28 insertions(+) create mode 100644 arch/mips/boot/dts/mobileye/Makefile create mode 100644 arch/mips/boot/dts/mobileye/eyeq5-epm5.dts diff --git a/arch/mips/boot/dts/mobileye/Makefile b/arch/mips/boot/dts/mobileye/Makefile new file mode 100644 index 0000000000000..b6fa261f0a3a0 --- /dev/null +++ b/arch/mips/boot/dts/mobileye/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only +# Copyright 2023 Mobileye Vision Technologies Ltd. + +dtb-$(CONFIG_SOC_EYEQ5) += eyeq5-epm5.dtb diff --git a/arch/mips/boot/dts/mobileye/eyeq5-epm5.dts b/arch/mips/boot/dts/mobileye/eyeq5-epm5.dts new file mode 100644 index 0000000000000..ff16c3c760a19 --- /dev/null +++ b/arch/mips/boot/dts/mobileye/eyeq5-epm5.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright 2023 Mobileye Vision Technologies Ltd. + */ + +/dts-v1/; + +#include "eyeq5.dtsi" + +/ { + compatible = "mobileye,eyeq5-epm5", "mobileye,eyeq5"; + model = "Mobile EyeQ5 MP5 Evaluation board"; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial2:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x08000000 0x0 0x08000000>, + <0x8 0x00000000 0x0 0x78000000>; + }; +}; From patchwork Tue Dec 12 16:34:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 13489646 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="ECU3izDz" Received: from relay6-d.mail.gandi.net (relay6-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::226]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C972D182; Tue, 12 Dec 2023 08:35:42 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPSA id EEDE0C0002; Tue, 12 Dec 2023 16:35:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1702398941; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=4e+9fOmpE4/IwZbJIJGAaMmx3iR6uUYWvdhHh8JnvMg=; b=ECU3izDzrr5b8h90ffNyzCOwGcNweM42CctUvGlGzXcaSc3afQ86TVHIDYdAUZMNV7n2Ia FrCwj3J/4BSaUh9omYPL7W9ZaHSftFNdCz9U/HBwWkFcnr3k1FYSwES3XgkND9+hdS+HE8 ePWvCmi1UrYoif0YNX1TIdP4KyRznjV+FbMOd2/jBgYHhSmmlVxV9FCKUs8HaW+aps7nHt 9o/sj/CxcDr2ZzNNgstM2ifAMq8c1G94+V7RsFrsjVDGrhwOU6ujOu56wXm5zrITEs8U/b z/0gSi8HfBt/OwTMCLh9hvCgfDmMYYcjRaTSh13vEF/7tL1WNYcLZTBCN3hjhw== From: Gregory CLEMENT To: Paul Burton , Thomas Bogendoerfer , linux-mips@vger.kernel.org, Jiaxun Yang , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Vladimir Kondratiev , Tawfik Bayouk , Alexandre Belloni , =?utf-8?q?Th=C3=A9o_Lebr?= =?utf-8?q?un?= , Thomas Petazzoni , Gregory CLEMENT Subject: [PATCH v5 21/22] MIPS: generic: Add support for Mobileye EyeQ5 Date: Tue, 12 Dec 2023 17:34:53 +0100 Message-ID: <20231212163459.1923041-22-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231212163459.1923041-1-gregory.clement@bootlin.com> References: <20231212163459.1923041-1-gregory.clement@bootlin.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: gregory.clement@bootlin.com Introduce support for the MIPS based Mobileye EyeQ5 SoCs. Signed-off-by: Gregory CLEMENT --- arch/mips/configs/generic/board-eyeq5.config | 42 ++++++++++++++++++++ arch/mips/generic/Kconfig | 15 +++++++ arch/mips/generic/Platform | 2 + arch/mips/generic/board-epm5.its.S | 24 +++++++++++ 4 files changed, 83 insertions(+) create mode 100644 arch/mips/configs/generic/board-eyeq5.config create mode 100644 arch/mips/generic/board-epm5.its.S diff --git a/arch/mips/configs/generic/board-eyeq5.config b/arch/mips/configs/generic/board-eyeq5.config new file mode 100644 index 0000000000000..d94e408145389 --- /dev/null +++ b/arch/mips/configs/generic/board-eyeq5.config @@ -0,0 +1,42 @@ +CONFIG_HIGH_RES_TIMERS=y +CONFIG_TASKSTATS=y +CONFIG_FIT_IMAGE_FDT_EPM5=y +CONFIG_BOARD_EYEQ5=y +CONFIG_PHYSICAL_START=0xa800000808000000 +CONFIG_CPU_HAS_MSA=y +CONFIG_SPARSEMEM_MANUAL=y +CONFIG_NET_KEY=y +CONFIG_CAN=y +CONFIG_PCI=y +CONFIG_PCI_MSI=y +CONFIG_PCI_DEBUG=y +CONFIG_PCI_ENDPOINT=y +CONFIG_CONNECTOR=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_RAM=y +CONFIG_MTD_ROM=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_PHYSMAP_OF=y +CONFIG_MTD_BLOCK2MTD=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BLOCK=y +CONFIG_NETDEVICES=y +CONFIG_MACVLAN=y +CONFIG_IPVLAN=y +CONFIG_MACB=y +CONFIG_MARVELL_PHY=y +CONFIG_MICREL_PHY=y +CONFIG_CAN_M_CAN=y +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_PINCTRL=y +CONFIG_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_CADENCE=y +CONFIG_RESET_CONTROLLER=y +CONFIG_FANOTIFY=y +CONFIG_ROMFS_FS=y +CONFIG_ROMFS_BACKED_BY_BOTH=y +CONFIG_PAGE_SIZE_16KB=y \ No newline at end of file diff --git a/arch/mips/generic/Kconfig b/arch/mips/generic/Kconfig index 7dc5b3821cc6e..04e1fc6f789b5 100644 --- a/arch/mips/generic/Kconfig +++ b/arch/mips/generic/Kconfig @@ -48,6 +48,13 @@ config SOC_VCOREIII config MSCC_OCELOT bool +config SOC_EYEQ5 + select ARM_AMBA + select WEAK_ORDERING + select WEAK_REORDERING_BEYOND_LLSC + select PHYSICAL_START_BOOL + bool + comment "FIT/UHI Boards" config FIT_IMAGE_FDT_BOSTON @@ -124,4 +131,12 @@ config VIRT_BOARD_RANCHU Android emulator. Android emulator is based on Qemu, and contains the support for the same set of virtual devices. +config FIT_IMAGE_FDT_EPM5 + bool "Include FDT for Mobileye EyeQ5 development platforms" + select SOC_EYEQ5 + default n + help + Enable this to include the FDT for the EyeQ5 development platforms + from Mobileye in the FIT kernel image. + This requires u-boot on the platform. endif diff --git a/arch/mips/generic/Platform b/arch/mips/generic/Platform index 0c03623f38970..45db9824a11d6 100644 --- a/arch/mips/generic/Platform +++ b/arch/mips/generic/Platform @@ -24,3 +24,5 @@ its-$(CONFIG_FIT_IMAGE_FDT_JAGUAR2) += board-jaguar2.its.S its-$(CONFIG_FIT_IMAGE_FDT_SERVAL) += board-serval.its.S its-$(CONFIG_FIT_IMAGE_FDT_XILFPGA) += board-xilfpga.its.S its-$(CONFIG_FIT_IMAGE_FDT_MARDUK) += board-marduk.its.S +its-$(CONFIG_FIT_IMAGE_FDT_EPM5) += board-epm5.its.S + diff --git a/arch/mips/generic/board-epm5.its.S b/arch/mips/generic/board-epm5.its.S new file mode 100644 index 0000000000000..08e8c4f183d63 --- /dev/null +++ b/arch/mips/generic/board-epm5.its.S @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/ { + images { + fdt-mobileye-epm5 { + description = "Mobileeye MP5 Device Tree"; + data = /incbin/("boot/dts/mobileye/eyeq5-epm5.dtb"); + type = "flat_dt"; + arch = "mips"; + compression = "none"; + hash { + algo = "sha1"; + }; + }; + }; + + configurations { + default = "conf-1"; + conf-1 { + description = "Mobileye EPM5 Linux kernel"; + kernel = "kernel"; + fdt = "fdt-mobileye-epm5"; + }; + }; +}; From patchwork Tue Dec 12 16:34:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 13489647 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="oqQEgVe/" Received: from relay4-d.mail.gandi.net (relay4-d.mail.gandi.net [217.70.183.196]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 620C412A; Tue, 12 Dec 2023 08:35:43 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPSA id BA11DE000F; Tue, 12 Dec 2023 16:35:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1702398942; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=SUlSGy+v8U/B/CDpSFqLosOixqHv6uGhrQGTRWI6pDQ=; b=oqQEgVe/Dd/JReCgjC5wwGG9MR6+X388hmrdrkSJtD5LOLPOc5QWrlVNeZGEu10wOUCvJj IHv6Q72yaX6rSiZu1DiS0azddfC/Nhl3Sz+TckBokeLjRxn++eBD2njei09oPqtRAcZShC hSsH9GPohbyzcGr01czNchzc5+2mTclRhB8lqBSC8v/5Wg2Nwj65AM3zdEOeVquSdxFTBx c7DYLPUKKY1F1VrnbTdUUszK8bQKiiBxX7GFe2eftPWSEWJPP6KpeDRtndhRdQ004e7+ay f/xTU3r+LZ56lkpDPE71awFmjnhMa/p6AAqNohqa8bWa4m0D401njEGGw4S1DA== From: Gregory CLEMENT To: Paul Burton , Thomas Bogendoerfer , linux-mips@vger.kernel.org, Jiaxun Yang , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Vladimir Kondratiev , Tawfik Bayouk , Alexandre Belloni , =?utf-8?q?Th=C3=A9o_Lebr?= =?utf-8?q?un?= , Thomas Petazzoni , Gregory CLEMENT Subject: [PATCH v5 22/22] MAINTAINERS: Add entry for Mobileye MIPS SoCs Date: Tue, 12 Dec 2023 17:34:54 +0100 Message-ID: <20231212163459.1923041-23-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231212163459.1923041-1-gregory.clement@bootlin.com> References: <20231212163459.1923041-1-gregory.clement@bootlin.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: gregory.clement@bootlin.com Add Vlad, Théo and myself as co-maintainers for the Mobileye MIPS SoCs. Signed-off-by: Vladimir Kondratiev Signed-off-by: Théo Lebrun Signed-off-by: Gregory CLEMENT --- MAINTAINERS | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index e2c6187a3ac80..4a7bd6b40d740 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14546,6 +14546,18 @@ W: https://linuxtv.org Q: http://patchwork.linuxtv.org/project/linux-media/list/ F: drivers/media/dvb-frontends/mn88473* +MOBILEYE MIPS SOCS +M: Vladimir Kondratiev +M: Gregory CLEMENT +M: Théo Lebrun +L: linux-mips@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/mips/mobileye.yaml +F: arch/mips/boot/dts/mobileye/ +F: arch/mips/configs/generic/board-eyeq5.config +F: arch/mips/generic/board-epm5.its.S +F: include/dt-bindings/soc/mobileye,eyeq5.h + MODULE SUPPORT M: Luis Chamberlain L: linux-modules@vger.kernel.org