From patchwork Tue Dec 12 22:25:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 13490064 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EECE1C4332F for ; Tue, 12 Dec 2023 22:24:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=XBjoBhHWcY7rqhJHr8J18OvR8jtjVNCXt+wrwT9G0jA=; b=percJuA6WPz38V xTs3HgGo1HIH5TsAOfpwu9gX9Ag9bUyXKkVQkMfsx1iaSe8YGdYLy0K167WhKxlQm8cHkGnIng3Xd Bg/0nwAvXw6yTWuZyuBu6STwQLG/XH10+TgLJOHe3Qp5U/UTdn6E6Rzzaju2w+Z6fO9D3sandgmqy SIVDdvtRPn6lj93FK9bsqFoxvG7+7EeV6MjtBJdA9F79QGLI3FVRVKkZ6gQLFHFv2DKPVMjK7NhTV Rh9v24Erscu5JKBM+FXwToMZZGEsexYyJMD6IYY9Gvby5KS0slk9l1cMnmfxEXLz9JDrZ9zp62m5n kvwMpR5QAhTbZPLkEhYQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1rDBAC-00CvA6-2M; Tue, 12 Dec 2023 22:23:40 +0000 Received: from mgamail.intel.com ([192.198.163.10]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1rDBAA-00Cv83-2g for linux-arm-kernel@lists.infradead.org; Tue, 12 Dec 2023 22:23:40 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1702419819; x=1733955819; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=ozp3JOHCZkR8rjYbeX9k9xgnEnDFYEFFgWgRZ7ytBZk=; b=FRXMVXqYfNzTIptM9B4jVTS1ZRwCOYVg7vLnH4o7NC8XiQmC3tXxBBSk 5NKISPKfpKpwAwlM7nQSIk2V090iRYD+fbPLd1nqWODUYIRmq5FyPeum3 wdL5LRhV83xrOGqFNINyg7UnYGCquZuiwZkfXK/JN0CDiMDC+V9HiKa7l K3w/77uc8TV0FQ2RrPhxsPb7fNnfaqxa42ShvLjXZTV4187akc2FBJkfM tuTdcrkX57eT448PvirGpPTXdU56+d9enlHogpP1/WaQIfNzy0WNLwf51 HUPFfN6R9566gOE1ZClonTm9Z+/3x/iJpTZYlZoQ9NDYysrt7FTr7zt3y w==; X-IronPort-AV: E=McAfee;i="6600,9927,10922"; a="2049307" X-IronPort-AV: E=Sophos;i="6.04,271,1695711600"; d="scan'208";a="2049307" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Dec 2023 14:23:36 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10922"; a="802631185" X-IronPort-AV: E=Sophos;i="6.04,271,1695711600"; d="scan'208";a="802631185" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by orsmga008.jf.intel.com with ESMTP; 12 Dec 2023 14:23:35 -0800 From: Ricardo Neri To: x86@kernel.org Cc: Andreas Herrmann , Catalin Marinas , Chen Yu , Len Brown , Radu Rendec , Pierre Gondois , Pu Wen , "Rafael J. Wysocki" , Sudeep Holla , Srinivas Pandruvada , Will Deacon , Zhang Rui , Huang Ying , "Ravi V. Shankar" , stable@vger.kernel.org, linux-kernel@vger.kernel.org, Ricardo Neri , linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 1/4] cacheinfo: Check for null last-level cache info Date: Tue, 12 Dec 2023 14:25:16 -0800 Message-Id: <20231212222519.12834-2-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231212222519.12834-1-ricardo.neri-calderon@linux.intel.com> References: <20231212222519.12834-1-ricardo.neri-calderon@linux.intel.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231212_142338_876424_D77B5DF7 X-CRM114-Status: GOOD ( 10.65 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Before determining the validity of the last-level cache info, ensure that it has been allocated. Simply checking for non-zero cache_leaves() is not sufficient, as some architectures (e.g., Intel processors) have non-zero cache_leaves() before allocation. Dereferencing NULL cacheinfo can occur in update_per_cpu_data_slice_size(). This function iterates over all online CPUs. However, a CPU may have come online recently, but its cacheinfo may not have been allocated yet. Cc: Andreas Herrmann Cc: Catalin Marinas Cc: Chen Yu Cc: Huang Ying Cc: Len Brown Cc: Radu Rendec Cc: Pierre Gondois Cc: Pu Wen Cc: "Rafael J. Wysocki" Cc: Sudeep Holla Cc: Srinivas Pandruvada Cc: Will Deacon Cc: Zhang Rui Cc: linux-arm-kernel@lists.infradead.org Cc: stable@vger.kernel.org Signed-off-by: Ricardo Neri Reviewed-by: Sudeep Holla --- Changes since v3: * Introduced this patch. Changes since v2: * N/A Changes since v1: * N/A --- The dereference of a NULL cacheinfo is not observed today because cache_leaves(cpu) is zero until after init_cache_level() is called (during the CPU hotplug callback). A subsequent changeset will set the number of cache leaves earlier and the NULL-pointer dereference will be observed. --- drivers/base/cacheinfo.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c index f1e79263fe61..967c5cf3fb1d 100644 --- a/drivers/base/cacheinfo.c +++ b/drivers/base/cacheinfo.c @@ -61,6 +61,9 @@ bool last_level_cache_is_valid(unsigned int cpu) if (!cache_leaves(cpu)) return false; + if (!per_cpu_cacheinfo(cpu)) + return false; + llc = per_cpu_cacheinfo_idx(cpu, cache_leaves(cpu) - 1); return (llc->attributes & CACHE_ID) || !!llc->fw_token; From patchwork Tue Dec 12 22:25:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 13490065 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 01DB9C4167B for ; Tue, 12 Dec 2023 22:24:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=6NhsfKa9kw6RJj1E+e46M8M0jjaNx0AdL5k+CIlsasg=; b=uoVsvJI254VPg+ ggPnPc7b3jO1tVL97M5gXbO1iN60Ifo7DwlJGFOnjyvGS+uDywHo7dRCr2rHM/xooioNPDZigTMdL 2CIqrZx9El+CV9iW+GDNEohuP3NIZf6cNaJ84xrdNW9+IlTAbRaeuJd/Xxb7Wfm99FT8f8RYBB1yK A9EevsCjpjjVogVUJm/2JBMyrscyl7C5w4zbHlQYV08IWjcRcGjfCiJNmlUdCNgCN/GclJikt9Tfo bLcHhuCjlG8YInAu/NdC0kfI0mIJSypst9mcf0eiEFFYx5LCnwzXrispyVOda+aeiMSBKuL4kS1df c/t+lW8iqIUMeUj6GMPg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1rDBAH-00CvCr-1b; Tue, 12 Dec 2023 22:23:45 +0000 Received: from mgamail.intel.com ([192.198.163.10]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1rDBAA-00Cv8A-2k for linux-arm-kernel@lists.infradead.org; Tue, 12 Dec 2023 22:23:40 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1702419819; x=1733955819; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=W4YA1C9BueESa8/SGirgrSDyXjHGqZ5rFE/K4wRbmoQ=; b=AhE9n6WWMqy7t3ZXjZ1jCEJosUokrTH29z4YKJ8uaCLGQ36WQKKbvMOp ZTPkfkhtgrjTwbVE8aqMuoE/T6lZzmSNdgEyRUzgFI+h162QJQsxRbwuP rHnPK5mOSKA18+N6KgB+Qua8/I1C+Jm30CC7GfBFIASMRTHvp2YoG/0g3 0tIEQxSQjN6FtHgvfCgro6bfF9SjsDxDBN/qpBj7AI/yP0xrqAE04H0yi Ptr20PyQCSdfi4/tIbHgtdO5TuRJ7IYE593fRb2FM+hEmxOpzy5j5/86E JED05Wt+snJXU9eEeu65eCoiEriBKP+SZRx+b5ycTcPXQzbzrW/0TR5fi Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10922"; a="2049309" X-IronPort-AV: E=Sophos;i="6.04,271,1695711600"; d="scan'208";a="2049309" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Dec 2023 14:23:36 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10922"; a="802631188" X-IronPort-AV: E=Sophos;i="6.04,271,1695711600"; d="scan'208";a="802631188" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by orsmga008.jf.intel.com with ESMTP; 12 Dec 2023 14:23:36 -0800 From: Ricardo Neri To: x86@kernel.org Cc: Andreas Herrmann , Catalin Marinas , Chen Yu , Len Brown , Radu Rendec , Pierre Gondois , Pu Wen , "Rafael J. Wysocki" , Sudeep Holla , Srinivas Pandruvada , Will Deacon , Zhang Rui , Huang Ying , "Ravi V. Shankar" , stable@vger.kernel.org, linux-kernel@vger.kernel.org, Ricardo Neri , linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 2/4] cacheinfo: Allocate memory for memory if not done from the primary CPU Date: Tue, 12 Dec 2023 14:25:17 -0800 Message-Id: <20231212222519.12834-3-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231212222519.12834-1-ricardo.neri-calderon@linux.intel.com> References: <20231212222519.12834-1-ricardo.neri-calderon@linux.intel.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231212_142338_897238_E02792B0 X-CRM114-Status: GOOD ( 15.58 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Commit 5944ce092b97 ("arch_topology: Build cacheinfo from primary CPU") adds functionality that architectures can use to optionally allocate and build cacheinfo early during boot. Commit 6539cffa9495 ("cacheinfo: Add arch specific early level initializer") lets secondary CPUs correct (and reallocate memory) cacheinfo data if needed. If the early build functionality is not used and cacheinfo does not need correction, memory for cacheinfo is never allocated. x86 does not use the early build functionality. Consequently, during the cacheinfo CPU hotplug callback, last_level_cache_is_valid() attempts to dereference a NULL pointer: BUG: kernel NULL pointer dereference, address: 0000000000000100 #PF: supervisor read access in kernel mode #PF: error_code(0x0000) - not present page PGD 0 P4D 0 Oops: 0000 [#1] PREEPMT SMP NOPTI CPU: 0 PID 19 Comm: cpuhp/0 Not tainted 6.4.0-rc2 #1 RIP: 0010: last_level_cache_is_valid+0x95/0xe0a Allocate memory for cacheinfo during the cacheinfo CPU hotplug callback if not done earlier. Cc: Andreas Herrmann Cc: Catalin Marinas Cc: Chen Yu Cc: Huang Ying Cc: Len Brown Cc: Radu Rendec Cc: Pierre Gondois Cc: Pu Wen Cc: "Rafael J. Wysocki" Cc: Sudeep Holla Cc: Srinivas Pandruvada Cc: Will Deacon Cc: Zhang Rui Cc: linux-arm-kernel@lists.infradead.org Cc: stable@vger.kernel.org Reviewed-by: Radu Rendec Reviewed-by: Sudeep Holla Fixes: 6539cffa9495 ("cacheinfo: Add arch specific early level initializer") Signed-off-by: Ricardo Neri --- The motivation for commit 5944ce092b97 was to prevent a BUG splat in PREEMPT_RT kernels during memory allocation. This splat is not observed on x86 because the memory allocation for cacheinfo happens in detect_cache_attributes() from the cacheinfo CPU hotplug callback. The dereference of a NULL pointer is not observed today because cache_leaves(cpu) is zero until after init_cache_level() is called (also during the CPU hotplug callback). A subsequent changeset will set the number of cache leaves earlier and the NULL-pointer dereference will be observed. --- Changes since v3: * Added Reviewed-by tag from Radu and Sudeep. Thanks! Changes since v2: * Introduced this patch. Changes since v1: * N/A --- drivers/base/cacheinfo.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c index 967c5cf3fb1d..735ccead190e 100644 --- a/drivers/base/cacheinfo.c +++ b/drivers/base/cacheinfo.c @@ -557,7 +557,11 @@ static inline int init_level_allocate_ci(unsigned int cpu) */ ci_cacheinfo(cpu)->early_ci_levels = false; - if (cache_leaves(cpu) <= early_leaves) + /* + * Some architectures (e.g., x86) do not use early initialization. + * Allocate memory now in such case. + */ + if (cache_leaves(cpu) <= early_leaves && per_cpu_cacheinfo(cpu)) return 0; kfree(per_cpu_cacheinfo(cpu)); From patchwork Tue Dec 12 22:25:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 13490066 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CC9A5C4332F for ; Tue, 12 Dec 2023 22:24:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=mlt+HNDLYQ1g8sulW4P+gy3S76ID5PYNpoRMh59dpWk=; b=0pEjT/n8NU87X8 TVCZmKB6ggPXGNnGqXuC1yjK9rUZhjtCmw3Fmno56j7gPWqkjaT82UGgBRelMK48PMyHCoH+rE6vg +zM0KBYHTZesOQr1cee3ObsWxjhmUSGSYlZRH8eQJkfuieXJJqHBlHIoAFY4mFp9gwWTRhagSvxpf T7kk+wcD2qmMWp4R6kp9yYiLgO86fOfk1GRqjf8mx2vJV0hfHUZNfAEHlbs/tZaijm8EytFCaFVgc /QhtWnHpezUyBBAfoWACQvGWUDDIV4LDiLqMecQV5l6WL5b5aXqeWANRbSNQJ/KdlhXxV8GsQIkwV ZhnYJX2H8CiiDIG3T4Yg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1rDBAI-00CvDt-20; Tue, 12 Dec 2023 22:23:46 +0000 Received: from mgamail.intel.com ([192.198.163.10]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1rDBAC-00Cv83-0h for linux-arm-kernel@lists.infradead.org; Tue, 12 Dec 2023 22:23:42 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1702419820; x=1733955820; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=LzXsCuISW2NJNxUNXM2y/VHhkHK/HUDcaHaJHLyVxtw=; b=f8/17XvDi8Mn+XTn0Na4Xx724Dfj99dJHGraIUOK7hNdF6BV1Rm/01Dp v4mE7N9CydnB1ZKJz8zaxMGTQ/jZfuU0YNwxlAXnIrQRTmlhkxUp5pyYT C0Wo52yPI4gvAnID6qqo4lWAIz3z+ZkxbivJqlnFB/mS1q55UNb42z+xa C01oQYjrZD0DX+4f2MqqWy6WATho9kHOMkq0z8J+BXfiuVhoN6m51e9OX 6F6GM4KfiFxcEMZU7ZGADTHz0LiJYWhWQkisv6GlCr4Ij/jEuy2kp7mch ynHI6cQTft/9vUdn3smULq7Q4zeKYAySNJqJK9OYnKDOPtjqiD6wrJjJz Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10922"; a="2049316" X-IronPort-AV: E=Sophos;i="6.04,271,1695711600"; d="scan'208";a="2049316" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Dec 2023 14:23:37 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10922"; a="802631193" X-IronPort-AV: E=Sophos;i="6.04,271,1695711600"; d="scan'208";a="802631193" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by orsmga008.jf.intel.com with ESMTP; 12 Dec 2023 14:23:36 -0800 From: Ricardo Neri To: x86@kernel.org Cc: Andreas Herrmann , Catalin Marinas , Chen Yu , Len Brown , Radu Rendec , Pierre Gondois , Pu Wen , "Rafael J. Wysocki" , Sudeep Holla , Srinivas Pandruvada , Will Deacon , Zhang Rui , Huang Ying , "Ravi V. Shankar" , stable@vger.kernel.org, linux-kernel@vger.kernel.org, Ricardo Neri , linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 3/4] x86/cacheinfo: Delete global num_cache_leaves Date: Tue, 12 Dec 2023 14:25:18 -0800 Message-Id: <20231212222519.12834-4-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231212222519.12834-1-ricardo.neri-calderon@linux.intel.com> References: <20231212222519.12834-1-ricardo.neri-calderon@linux.intel.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231212_142340_283225_99A766DB X-CRM114-Status: GOOD ( 24.04 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Linux remembers cpu_cachinfo::num_leaves per CPU, but x86 initializes all CPUs from the same global "num_cache_leaves". This is erroneous on systems such as Meteor Lake, where each CPU has a distinct num_leaves value. Delete the global "num_cache_leaves" and initialize num_leaves on each CPU. Cc: Andreas Herrmann Cc: Catalin Marinas Cc: Chen Yu Cc: Huang Ying Cc: Len Brown Cc: Radu Rendec Cc: Pierre Gondois Cc: Pu Wen Cc: "Rafael J. Wysocki" Cc: Sudeep Holla Cc: Srinivas Pandruvada Cc: Will Deacon Cc: Zhang Rui Cc: linux-arm-kernel@lists.infradead.org Cc: stable@vger.kernel.org Reviewed-by: Len Brown Signed-off-by: Ricardo Neri --- After this change, all CPUs will traverse CPUID leaf 0x4 when booted for the first time. On systems with symmetric cache topologies this is useless work. Creating a list of processor models that have asymmetric cache topologies was considered. The burden of maintaining such list would outweigh the performance benefit of skipping this extra step. --- Changes since v3: * Rebased on v6.7-rc5. Changes since v2: * None Changes since v1: * Do not make num_cache_leaves a per-CPU variable. Instead, reuse the existing per-CPU ci_cpu_cacheinfo variable. (Dave Hansen) --- arch/x86/kernel/cpu/cacheinfo.c | 44 +++++++++++++++++++-------------- 1 file changed, 26 insertions(+), 18 deletions(-) diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinfo.c index c131c412db89..4125e53a5ef7 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -178,7 +178,16 @@ struct _cpuid4_info_regs { struct amd_northbridge *nb; }; -static unsigned short num_cache_leaves; +static inline unsigned int get_num_cache_leaves(unsigned int cpu) +{ + return get_cpu_cacheinfo(cpu)->num_leaves; +} + +static inline void +set_num_cache_leaves(unsigned int nr_leaves, unsigned int cpu) +{ + get_cpu_cacheinfo(cpu)->num_leaves = nr_leaves; +} /* AMD doesn't have CPUID4. Emulate it here to report the same information to the user. This makes some assumptions about the machine: @@ -718,19 +727,21 @@ void cacheinfo_hygon_init_llc_id(struct cpuinfo_x86 *c) void init_amd_cacheinfo(struct cpuinfo_x86 *c) { + unsigned int cpu = c->cpu_index; + if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { - num_cache_leaves = find_num_cache_leaves(c); + set_num_cache_leaves(find_num_cache_leaves(c), cpu); } else if (c->extended_cpuid_level >= 0x80000006) { if (cpuid_edx(0x80000006) & 0xf000) - num_cache_leaves = 4; + set_num_cache_leaves(4, cpu); else - num_cache_leaves = 3; + set_num_cache_leaves(3, cpu); } } void init_hygon_cacheinfo(struct cpuinfo_x86 *c) { - num_cache_leaves = find_num_cache_leaves(c); + set_num_cache_leaves(find_num_cache_leaves(c), c->cpu_index); } void init_intel_cacheinfo(struct cpuinfo_x86 *c) @@ -742,19 +753,19 @@ void init_intel_cacheinfo(struct cpuinfo_x86 *c) unsigned int l2_id = 0, l3_id = 0, num_threads_sharing, index_msb; if (c->cpuid_level > 3) { - static int is_initialized; - - if (is_initialized == 0) { - /* Init num_cache_leaves from boot CPU */ - num_cache_leaves = find_num_cache_leaves(c); - is_initialized++; - } + /* + * There should be at least one leaf. A non-zero value means + * that the number of leaves has been initialized. + */ + if (!get_num_cache_leaves(c->cpu_index)) + set_num_cache_leaves(find_num_cache_leaves(c), + c->cpu_index); /* * Whenever possible use cpuid(4), deterministic cache * parameters cpuid leaf to find the cache details */ - for (i = 0; i < num_cache_leaves; i++) { + for (i = 0; i < get_num_cache_leaves(c->cpu_index); i++) { struct _cpuid4_info_regs this_leaf = {}; int retval; @@ -790,14 +801,14 @@ void init_intel_cacheinfo(struct cpuinfo_x86 *c) * Don't use cpuid2 if cpuid4 is supported. For P4, we use cpuid2 for * trace cache */ - if ((num_cache_leaves == 0 || c->x86 == 15) && c->cpuid_level > 1) { + if ((!get_num_cache_leaves(c->cpu_index) || c->x86 == 15) && c->cpuid_level > 1) { /* supports eax=2 call */ int j, n; unsigned int regs[4]; unsigned char *dp = (unsigned char *)regs; int only_trace = 0; - if (num_cache_leaves != 0 && c->x86 == 15) + if (get_num_cache_leaves(c->cpu_index) && c->x86 == 15) only_trace = 1; /* Number of times to iterate */ @@ -993,12 +1004,9 @@ int init_cache_level(unsigned int cpu) { struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); - if (!num_cache_leaves) - return -ENOENT; if (!this_cpu_ci) return -EINVAL; this_cpu_ci->num_levels = 3; - this_cpu_ci->num_leaves = num_cache_leaves; return 0; } From patchwork Tue Dec 12 22:25:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 13490067 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F1174C4332F for ; Tue, 12 Dec 2023 22:24:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=6t972eOu6zyLiQPAhUyQpHkev85p6ofa3lUbJxnGmGU=; b=xQrBC8VYJzNuCg kFEJhyj74UKERy6EN0h85GeVdkOUItKog/7lF+ZtfrL60GPicn+rqqoTumC/b0krPpTu8loOwI153 JXzofTV+5hNs8y0M6kjHuNW/gXDbPnd4/iTIleSbg1pSrGOma9+hpiVntNiJE8dDQ+9M5YN+a8ThP dQwrlhL9+ZJuc1l3RgsB0kfeMEfYqN8clkFr+KDVh2i4Ej86SKlW2t68efPyC8XeHqNqHzjp/6+rl PvIc6OUqraCkZVHI4aX5kV98u/fSgVsAk/fZmexcZO0rxnsdH1Z3Kxa6WuKsjNyWPwW7Xg8hjfawA 0EJu+wCn6hM/i/F2YIMg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1rDBAI-00CvDD-09; Tue, 12 Dec 2023 22:23:46 +0000 Received: from mgamail.intel.com ([192.198.163.10]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1rDBAC-00Cv9R-18 for linux-arm-kernel@lists.infradead.org; Tue, 12 Dec 2023 22:23:41 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1702419820; x=1733955820; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=JjzpfRR25ptOiQcPUOjeLG2ZsPBSBKfEfUSAHzk+JdM=; b=Xw5Mnkee4gYjOyNcmhlVGHfvrHfPFB3jlRU/brnOVAZJMt1eDZFanGP+ 0u2eRqD3fKiPui+Z7Of8V0MDNCEjRdGMh1+77v3T7ReUH1qUN4SshHVvg G1uZ7E1IaHKNdGXawAezw23wxVPZ24ZmzMAqzKQDy5CW1HgYYdK2V5Ey1 tZiuoCiTWluGDH2zp8EZgH8zUZvsdi2VWeh3oWJnSF7EyyuYsV4MjgnJ+ SO5V+shkx0YqwCo3wkmS0/i9Ln5X1vEMe16szRHnpyy1sblDyKYMed1jp jtvwsa9PA2M0qw5CMnVKeCJH45CS1HVx6XY8VnSCmZfOkSDV80PB5NEEt w==; X-IronPort-AV: E=McAfee;i="6600,9927,10922"; a="2049326" X-IronPort-AV: E=Sophos;i="6.04,271,1695711600"; d="scan'208";a="2049326" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Dec 2023 14:23:37 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10922"; a="802631196" X-IronPort-AV: E=Sophos;i="6.04,271,1695711600"; d="scan'208";a="802631196" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by orsmga008.jf.intel.com with ESMTP; 12 Dec 2023 14:23:37 -0800 From: Ricardo Neri To: x86@kernel.org Cc: Andreas Herrmann , Catalin Marinas , Chen Yu , Len Brown , Radu Rendec , Pierre Gondois , Pu Wen , "Rafael J. Wysocki" , Sudeep Holla , Srinivas Pandruvada , Will Deacon , Zhang Rui , Huang Ying , "Ravi V. Shankar" , stable@vger.kernel.org, linux-kernel@vger.kernel.org, Ricardo Neri , linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 4/4] x86/cacheinfo: Clean out init_cache_level() Date: Tue, 12 Dec 2023 14:25:19 -0800 Message-Id: <20231212222519.12834-5-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231212222519.12834-1-ricardo.neri-calderon@linux.intel.com> References: <20231212222519.12834-1-ricardo.neri-calderon@linux.intel.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231212_142340_429151_E92A1CDC X-CRM114-Status: GOOD ( 10.41 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org init_cache_level() no longer has a purpose on x86. It no longer needs to set num_leaves, and it never had to set num_levels, which was unnecessary on x86. Replace it with "return 0" simply to override the weak function, which would return an error. Cc: Andreas Herrmann Cc: Catalin Marinas Cc: Chen Yu CC: Huang Ying Cc: Len Brown Cc: Radu Rendec Cc: Pierre Gondois Cc: Pu Wen Cc: "Rafael J. Wysocki" Cc: Sudeep Holla Cc: Srinivas Pandruvada Cc: Will Deacon Cc: Zhang Rui Cc: linux-arm-kernel@lists.infradead.org Cc: stable@vger.kernel.org Reviewed-by: Len Brown Signed-off-by: Ricardo Neri --- Changes since v3: * Rebased on v6.7-rc5. Changes since v2: * None Changes since v1: * Introduced this patch. --- arch/x86/kernel/cpu/cacheinfo.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinfo.c index 4125e53a5ef7..1cfe0921ac67 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -1002,11 +1002,6 @@ static void ci_leaf_init(struct cacheinfo *this_leaf, int init_cache_level(unsigned int cpu) { - struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); - - if (!this_cpu_ci) - return -EINVAL; - this_cpu_ci->num_levels = 3; return 0; }