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Example of configuring the corresponding dts property under the PCI node: wake-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>; Signed-off-by: Sherry Sun Reviewed-by: Richard Zhu --- drivers/pci/controller/dwc/pci-imx6.c | 60 +++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 74703362aeec..0cf7f21adff8 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -72,6 +72,7 @@ struct imx6_pcie_drvdata { struct imx6_pcie { struct dw_pcie *pci; int reset_gpio; + int host_wake_irq; bool gpio_active_high; bool link_is_up; struct clk *pcie_bus; @@ -1237,11 +1238,44 @@ static int imx6_pcie_resume_noirq(struct device *dev) return 0; } +static int imx6_pcie_suspend(struct device *dev) +{ + struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); + + if (imx6_pcie->host_wake_irq >= 0) + enable_irq_wake(imx6_pcie->host_wake_irq); + + return 0; +} + +static int imx6_pcie_resume(struct device *dev) +{ + struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); + + if (imx6_pcie->host_wake_irq >= 0) + disable_irq_wake(imx6_pcie->host_wake_irq); + + return 0; +} + static const struct dev_pm_ops imx6_pcie_pm_ops = { NOIRQ_SYSTEM_SLEEP_PM_OPS(imx6_pcie_suspend_noirq, imx6_pcie_resume_noirq) + SYSTEM_SLEEP_PM_OPS(imx6_pcie_suspend, imx6_pcie_resume) }; +irqreturn_t host_wake_irq_handler(int irq, void *priv) +{ + struct imx6_pcie *imx6_pcie = priv; + struct device *dev = imx6_pcie->pci->dev; + + /* Notify PM core we are wakeup source */ + pm_wakeup_event(dev, 0); + pm_system_wakeup(); + + return IRQ_HANDLED; +} + static int imx6_pcie_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -1250,6 +1284,7 @@ static int imx6_pcie_probe(struct platform_device *pdev) struct device_node *np; struct resource *dbi_base; struct device_node *node = dev->of_node; + struct gpio_desc *host_wake_gpio; int ret; u16 val; @@ -1457,6 +1492,26 @@ static int imx6_pcie_probe(struct platform_device *pdev) val |= PCI_MSI_FLAGS_ENABLE; dw_pcie_writew_dbi(pci, offset + PCI_MSI_FLAGS, val); } + + /* host wakeup support */ + imx6_pcie->host_wake_irq = -1; + host_wake_gpio = devm_gpiod_get_optional(dev, "wake", GPIOD_IN); + if (IS_ERR(host_wake_gpio)) + return PTR_ERR(host_wake_gpio); + + if (host_wake_gpio != NULL) { + imx6_pcie->host_wake_irq = gpiod_to_irq(host_wake_gpio); + ret = devm_request_threaded_irq(dev, imx6_pcie->host_wake_irq, NULL, + host_wake_irq_handler, + IRQF_ONESHOT | IRQF_TRIGGER_FALLING, + "host_wake", imx6_pcie); + if (ret) + return dev_err_probe(dev, ret, "Failed to request host_wake_irq\n"); + + ret = device_init_wakeup(dev, true); + if (ret) + return dev_err_probe(dev, ret, "Failed to init host_wake_irq\n"); + } } return 0; @@ -1466,6 +1521,11 @@ static void imx6_pcie_shutdown(struct platform_device *pdev) { struct imx6_pcie *imx6_pcie = platform_get_drvdata(pdev); + if (imx6_pcie->host_wake_irq >= 0) { + device_init_wakeup(&pdev->dev, false); + disable_irq(imx6_pcie->host_wake_irq); + } + /* bring down link, so bootloader gets clean state in case of reboot */ imx6_pcie_assert_core_reset(imx6_pcie); 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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add wake-gpios property that can be used to wakeup the host processor. Signed-off-by: Sherry Sun Reviewed-by: Richard Zhu --- Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml index 81bbb8728f0f..fba757d937e1 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml @@ -72,6 +72,12 @@ properties: L=operation state) (optional required). type: boolean + wake-gpios: + description: If present this property specifies WAKE# sideband signaling + to implement wakeup functionality. This is an input GPIO pin for the Root + Port mode here. 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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The host wake pin is a standard feature in the PCIe bus specification, so we add this property under PCI dts node to enable the host wake function. Signed-off-by: Sherry Sun Reviewed-by: Richard Zhu --- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index f87fa5a948cc..4378b9c1308c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -542,6 +542,7 @@ &pcie { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie0>; reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>; + wake-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>; vpcie-supply = <®_pcie0>; status = "okay"; }; @@ -772,6 +773,7 @@ pinctrl_pcie0: pcie0grp { fsl,pins = < MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x60 /* open drain, pull up */ MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x40 + MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x1c4 >; }; From patchwork Wed Dec 13 09:28:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sherry Sun X-Patchwork-Id: 13490594 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EA437C4332F for ; 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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The host wake pin is a standard feature in the PCIe bus specification, so we add this property under PCI dts node to enable the host wake function. Signed-off-by: Sherry Sun Reviewed-by: Richard Zhu --- arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index 7507548cdb16..b8463ef230c5 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -367,6 +367,7 @@ &pcie1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie1>; reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>; + wake-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, <&pcie0_refclk>, <&clk IMX8MQ_CLK_PCIE2_PHY>, @@ -545,6 +546,7 @@ pinctrl_pcie1: pcie1grp { fsl,pins = < MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x76 MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x16 + MX8MQ_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x41 >; };