From patchwork Wed Dec 13 18:00:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Hasemeyer X-Patchwork-Id: 13491718 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="e/xVOQ/f" Received: from mail-io1-xd2f.google.com (mail-io1-xd2f.google.com [IPv6:2607:f8b0:4864:20::d2f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 525D7107 for ; Wed, 13 Dec 2023 10:01:36 -0800 (PST) Received: by mail-io1-xd2f.google.com with SMTP id ca18e2360f4ac-7b7876fe9f0so18642939f.2 for ; Wed, 13 Dec 2023 10:01:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1702490495; x=1703095295; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XHJkvyGkozEZfAn1foMxSDGndxq7Z3rvVOkqL1kGsfY=; b=e/xVOQ/fNvuwsoyIMhGmxORiCBN5toQu+SfZ1PYaIIv1/IROHvZzj3qqMGEguy1YnU 8y6C+HjiIotuBoYZffehxPy0eoKlaAwZIDUWHutN7y2EIXivn+ubz4B3TTA9oeoPziB7 DHGVvlv4xv/XkwztWmoZiWLimbUlwMZ8s00yc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702490495; x=1703095295; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XHJkvyGkozEZfAn1foMxSDGndxq7Z3rvVOkqL1kGsfY=; b=pcKk79cLQpITe/QXA3t8GOYGoNA0ikIv2qyzmLvUpHAnYA89aQjpaY5zYFIgDvEeVB p2dj9zm6k8Cg7F44e90pNSiaKi/iXN3cbRKkaw1TmDUzeZkHfF+pZjrleEYxipLufnWm 44AUiSjC07IjXUHk96gLdbuQfP+lXSjUpFLAvazaM2PiIFB2hFqPMm65hOK+HKbExYS2 /YnqsOWeQBP6kxQyq2Kf0kW1G1yujzBI0py6TIWgapwGXO1ryL6xBmjSWvxUwsnIg+jk IGKQ9BOWmQpxTYdW6aPKfg5yOryU/+xrsZbG3W28Nu8xhCGx8+Z5KSh6bWe3GVoWWBQc Hy4A== X-Gm-Message-State: AOJu0Yxvff5eOHGEa0KnDR6bzFGbzwxGwUWk+OfpshFtxwQY7395TSmk j3J8rP6V+YyWI9+8nlDpqdaFwA== X-Google-Smtp-Source: AGHT+IFlYJgoIT3A6azjL3KGWGM2LFNYIuooaQV3GC7pc2NQaP0QcsiTJdhp9S5ZzNvKJJo5ucv2Lg== X-Received: by 2002:a5d:948e:0:b0:7b7:70fe:2913 with SMTP id v14-20020a5d948e000000b007b770fe2913mr2509400ioj.19.1702490495596; Wed, 13 Dec 2023 10:01:35 -0800 (PST) Received: from markhas1.corp.google.com ([100.107.108.224]) by smtp.gmail.com with ESMTPSA id o28-20020a02cc3c000000b0046671f9717csm3161206jap.109.2023.12.13.10.01.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Dec 2023 10:01:35 -0800 (PST) From: Mark Hasemeyer To: LKML Cc: Raul Rangel , Mark Hasemeyer , Alim Akhtar , Andre Przywara , Andy Gross , AngeloGioacchino Del Regno , Baruch Siach , Bjorn Andersson , Claudiu Beznea , Conor Dooley , Heiko Stuebner , Jesper Nilsson , Jisheng Zhang , Jonathan Hunter , Konrad Dybcio , Krzysztof Kozlowski , Matthias Brugger , Michal Simek , Paul Barker , Rob Herring , Sudeep Holla , Thierry Reding , cros-qcom-dts-watchers@chromium.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v1 2/6] arm: arm64: dts: Enable cros-ec-spi as wake source Date: Wed, 13 Dec 2023 11:00:20 -0700 Message-ID: <20231213110009.v1.2.I274b2d2255eb539cc9d251c9d65a385cc4014c79@changeid> X-Mailer: git-send-email 2.43.0.472.g3155946c3a-goog In-Reply-To: <20231213110009.v1.1.Ifd0903f1c351e84376d71dbdadbd43931197f5ea@changeid> References: <20231213110009.v1.1.Ifd0903f1c351e84376d71dbdadbd43931197f5ea@changeid> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The cros_ec driver currently assumes that cros-ec-spi compatible device nodes are a wakeup-source even though the wakeup-source property is not defined. Add the wakeup-source property to all cros-ec-spi compatible device nodes to match expected behavior. Signed-off-by: Mark Hasemeyer --- arch/arm/boot/dts/nvidia/tegra124-nyan.dtsi | 1 + arch/arm/boot/dts/nvidia/tegra124-venice2.dts | 1 + arch/arm/boot/dts/rockchip/rk3288-veyron-chromebook.dtsi | 1 + arch/arm/boot/dts/samsung/exynos5420-peach-pit.dts | 1 + arch/arm/boot/dts/samsung/exynos5800-peach-pi.dts | 1 + arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi | 1 + arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 1 + arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi | 1 + arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi | 1 + arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi | 1 + arch/arm64/boot/dts/nvidia/tegra132-norrin.dts | 1 + arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 1 + arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 1 + arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi | 1 + arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi | 1 + arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 1 + 16 files changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/nvidia/tegra124-nyan.dtsi b/arch/arm/boot/dts/nvidia/tegra124-nyan.dtsi index a2ee371802004..8125c1b3e8d79 100644 --- a/arch/arm/boot/dts/nvidia/tegra124-nyan.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra124-nyan.dtsi @@ -338,6 +338,7 @@ cros_ec: cros-ec@0 { interrupt-parent = <&gpio>; interrupts = ; reg = <0>; + wakeup-source; google,cros-ec-spi-msg-delay = <2000>; diff --git a/arch/arm/boot/dts/nvidia/tegra124-venice2.dts b/arch/arm/boot/dts/nvidia/tegra124-venice2.dts index 3924ee385dee0..df98dc2a67b85 100644 --- a/arch/arm/boot/dts/nvidia/tegra124-venice2.dts +++ b/arch/arm/boot/dts/nvidia/tegra124-venice2.dts @@ -857,6 +857,7 @@ cros_ec: cros-ec@0 { interrupt-parent = <&gpio>; interrupts = ; reg = <0>; + wakeup-source; google,cros-ec-spi-msg-delay = <2000>; diff --git a/arch/arm/boot/dts/rockchip/rk3288-veyron-chromebook.dtsi b/arch/arm/boot/dts/rockchip/rk3288-veyron-chromebook.dtsi index 092316be67f74..1554fe36e60fe 100644 --- a/arch/arm/boot/dts/rockchip/rk3288-veyron-chromebook.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3288-veyron-chromebook.dtsi @@ -112,6 +112,7 @@ cros_ec: ec@0 { pinctrl-names = "default"; pinctrl-0 = <&ec_int>; spi-max-frequency = <3000000>; + wakeup-source; i2c_tunnel: i2c-tunnel { compatible = "google,cros-ec-i2c-tunnel"; diff --git a/arch/arm/boot/dts/samsung/exynos5420-peach-pit.dts b/arch/arm/boot/dts/samsung/exynos5420-peach-pit.dts index 4e757b6e28e1c..3759742d38cac 100644 --- a/arch/arm/boot/dts/samsung/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/samsung/exynos5420-peach-pit.dts @@ -967,6 +967,7 @@ cros_ec: cros-ec@0 { reg = <0>; spi-max-frequency = <3125000>; google,has-vbc-nvram; + wakeup-source; controller-data { samsung,spi-feedback-delay = <1>; diff --git a/arch/arm/boot/dts/samsung/exynos5800-peach-pi.dts b/arch/arm/boot/dts/samsung/exynos5800-peach-pi.dts index f91bc4ae008e4..9bbbdce9103a6 100644 --- a/arch/arm/boot/dts/samsung/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/samsung/exynos5800-peach-pi.dts @@ -949,6 +949,7 @@ cros_ec: cros-ec@0 { reg = <0>; spi-max-frequency = <3125000>; google,has-vbc-nvram; + wakeup-source; controller-data { samsung,spi-feedback-delay = <1>; diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi index 4dd21dd317026..f0395da659a86 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi @@ -1168,6 +1168,7 @@ cros_ec: ec@0 { interrupt-parent = <&pio>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; google,cros-ec-spi-msg-delay = <500>; + wakeup-source; i2c_tunnel: i2c-tunnel0 { compatible = "google,cros-ec-i2c-tunnel"; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi index 44647d462e20b..359859f23b1fd 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -1013,6 +1013,7 @@ cros_ec: cros-ec@0 { interrupts = <151 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; pinctrl-0 = <&ec_ap_int_odl>; + wakeup-source; i2c_tunnel: i2c-tunnel { compatible = "google,cros-ec-i2c-tunnel"; diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi b/arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi index 5f62dc83013f0..74c534d475cb0 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi @@ -1918,6 +1918,7 @@ cros_ec: ec@0 { interrupts = <13 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; pinctrl-0 = <&ec_ap_int>; + wakeup-source; i2c_tunnel: i2c-tunnel { compatible = "google,cros-ec-i2c-tunnel"; diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi index a29da53d17894..4594287d60926 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -1454,6 +1454,7 @@ cros_ec: ec@0 { spi-max-frequency = <3000000>; pinctrl-names = "default"; pinctrl-0 = <&cros_ec_int>; + wakeup-source; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi index 37a3e9de90ff7..a5ace1b02c3d2 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -1034,6 +1034,7 @@ cros_ec: ec@0 { pinctrl-names = "default"; pinctrl-0 = <&cros_ec_int>; spi-max-frequency = <3000000>; + wakeup-source; keyboard-backlight { compatible = "google,cros-kbd-led-backlight"; diff --git a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts index bbc2e9bef08da..14d58859bb55c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts +++ b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts @@ -762,6 +762,7 @@ ec: cros-ec@0 { interrupt-parent = <&gpio>; interrupts = ; reg = <0>; + wakeup-source; google,cros-ec-spi-msg-delay = <2000>; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index 5a33e16a8b677..e6a2ed0463997 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -650,6 +650,7 @@ cros_ec: ec@0 { pinctrl-names = "default"; pinctrl-0 = <&ap_ec_int_l>; spi-max-frequency = <3000000>; + wakeup-source; cros_ec_pwm: pwm { compatible = "google,cros-ec-pwm"; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi index 9ea6636125ad9..2ba4ea60cb147 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi @@ -548,6 +548,7 @@ cros_ec: ec@0 { pinctrl-names = "default"; pinctrl-0 = <&ap_ec_int_l>; spi-max-frequency = <3000000>; + wakeup-source; cros_ec_pwm: pwm { compatible = "google,cros-ec-pwm"; diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi index ebae545c587c4..fbfac7534d3c6 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi @@ -19,6 +19,7 @@ cros_ec: ec@0 { pinctrl-names = "default"; pinctrl-0 = <&ap_ec_int_l>; spi-max-frequency = <3000000>; + wakeup-source; cros_ec_pwm: pwm { compatible = "google,cros-ec-pwm"; diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi index f86e7acdfd99f..d8eb45662c931 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi @@ -838,6 +838,7 @@ cros_ec: ec@0 { pinctrl-names = "default"; pinctrl-0 = <&ec_ap_int_l>; spi-max-frequency = <3000000>; + wakeup-source; cros_ec_pwm: pwm { compatible = "google,cros-ec-pwm"; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi index c9bf1d5c3a426..69a0b34f0615b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi @@ -602,6 +602,7 @@ cros_ec: ec@0 { pinctrl-names = "default"; pinctrl-0 = <&ec_ap_int_l>; spi-max-frequency = <3000000>; + wakeup-source; i2c_tunnel: i2c-tunnel { compatible = "google,cros-ec-i2c-tunnel";