From patchwork Fri Dec 15 23:15:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Jiang X-Patchwork-Id: 13495180 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F1C8D18EBF for ; Fri, 15 Dec 2023 23:16:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="CvWi+9f/" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1702682162; x=1734218162; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=QYObpw6p7KHb1NxebZDfugC3ycW39PhpsMsysnstxKw=; b=CvWi+9f/GXrpIod2PwDccyYS3F04NbWRe2OG2/jGLQjn/vjGfDOMBTgp GLRej6wqqvvLCzMQnBrNYlE59V4c/1+rrXAqz4Qfnr0OIfLCMuyd5tjry s4loS8Tglf6HW6f4gh6rGgJpPfWxbPpnzjln8S192voGvV02ex32VURTB S9LMddemH+Lt9ff0mmCU92GqsE23mpwt9Us7bz3rDCTgFd2X74pAvAIBi YhfyVkfZjJHylYdWD3MHUDKYSKv6s7Tq6ZbPENFa44n6kJelRui81+nfQ 6PlKPELeWAqUE//XH/BLsx92R3pMHpeYGU5/V6SMYPMZvDStyHBAcMPeW A==; X-IronPort-AV: E=McAfee;i="6600,9927,10925"; a="2191998" X-IronPort-AV: E=Sophos;i="6.04,280,1695711600"; d="scan'208";a="2191998" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Dec 2023 15:16:01 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10925"; a="1022091008" X-IronPort-AV: E=Sophos;i="6.04,280,1695711600"; d="scan'208";a="1022091008" Received: from djiang5-mobl3.amr.corp.intel.com (HELO [192.168.1.177]) ([10.213.188.77]) by fmsmga006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Dec 2023 15:16:00 -0800 Subject: [PATCH v2 1/3] cxl/region: Calculate performance data for a region From: Dave Jiang To: linux-cxl@vger.kernel.org Cc: dan.j.williams@intel.com, ira.weiny@intel.com, vishal.l.verma@intel.com, alison.schofield@intel.com, jonathan.cameron@huawei.com, dave@stgolabs.net, brice.goglin@gmail.com, nifan.cxl@gmail.com Date: Fri, 15 Dec 2023 16:15:59 -0700 Message-ID: <170268215975.1381493.16321994239389305102.stgit@djiang5-mobl3> In-Reply-To: <170268206638.1381493.3891165173978942658.stgit@djiang5-mobl3> References: <170268206638.1381493.3891165173978942658.stgit@djiang5-mobl3> User-Agent: StGit/1.5 Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Calculate and store the performance data for a CXL region. Find the worst read and write latency for all the included ranges from each of the devices that attributes to the region and designate that as the latency data. Sum all the read and write bandwidth data for each of the device region and that is the total bandwidth for the region. The perf list is expected to be constructed before the endpoint decoders are registered and thus there should be no early reading of the entries from the region assemble action. The calling of the region qos calculate function is under the protection of cxl_dpa_rwsem and will ensure that all DPA associated work has completed. Signed-off-by: Dave Jiang Reviewed-by: Jonathan Cameron --- v2: - Move cxled declaration (Fan) - Move calculate function to core/cdat.c - Make cxlr->coord a struct instead of allocated (Dan) - Remove list_empty() check (Dan) - Move calculation to cxl_region_attach() under cxl_dpa_rwsem (Dan) - Normalize perf numbers to HMAT coords (Brice, Dan) --- drivers/cxl/core/cdat.c | 53 +++++++++++++++++++++++++++++++++++++++++++++ drivers/cxl/core/region.c | 2 ++ drivers/cxl/cxl.h | 5 ++++ 3 files changed, 60 insertions(+) diff --git a/drivers/cxl/core/cdat.c b/drivers/cxl/core/cdat.c index 5fe57fe5e2ee..29bba04306e9 100644 --- a/drivers/cxl/core/cdat.c +++ b/drivers/cxl/core/cdat.c @@ -547,3 +547,56 @@ void cxl_switch_parse_cdat(struct cxl_port *port) EXPORT_SYMBOL_NS_GPL(cxl_switch_parse_cdat, CXL); MODULE_IMPORT_NS(CXL); + +void cxl_region_perf_data_calculate(struct cxl_region *cxlr, + struct cxl_endpoint_decoder *cxled) +{ + struct list_head *perf_list; + struct cxl_memdev *cxlmd = cxled_to_memdev(cxled); + struct cxl_dev_state *cxlds = cxlmd->cxlds; + struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlds); + struct range dpa = { + .start = cxled->dpa_res->start, + .end = cxled->dpa_res->end, + }; + struct cxl_dpa_perf *perf; + bool found = false; + + switch (cxlr->mode) { + case CXL_DECODER_RAM: + perf_list = &mds->ram_perf_list; + break; + case CXL_DECODER_PMEM: + perf_list = &mds->pmem_perf_list; + break; + default: + return; + } + + list_for_each_entry(perf, perf_list, list) { + if (range_contains(&perf->dpa_range, &dpa)) { + found = true; + break; + } + } + + if (!found) + return; + + /* Get total bandwidth and the worst latency for the cxl region */ + cxlr->coord.read_latency = max_t(unsigned int, + cxlr->coord.read_latency, + perf->coord.read_latency); + cxlr->coord.write_latency = max_t(unsigned int, + cxlr->coord.write_latency, + perf->coord.write_latency); + cxlr->coord.read_bandwidth += perf->coord.read_bandwidth; + cxlr->coord.write_bandwidth += perf->coord.write_bandwidth; + + /* + * Convert latency to nanosec from picosec to be consistent with HMAT + * attributes. + */ + cxlr->coord.read_latency = DIV_ROUND_UP(cxlr->coord.read_latency, 1000); + cxlr->coord.write_latency = DIV_ROUND_UP(cxlr->coord.write_latency, 1000); +} diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index 56e575c79bb4..be7383e74ef5 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -1721,6 +1721,8 @@ static int cxl_region_attach(struct cxl_region *cxlr, return -EINVAL; } + cxl_region_perf_data_calculate(cxlr, cxled); + if (test_bit(CXL_REGION_F_AUTO, &cxlr->flags)) { int i; diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 492dbf63935f..4639d0d6ef54 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -519,6 +519,7 @@ struct cxl_region_params { * @cxlr_pmem: (for pmem regions) cached copy of the nvdimm bridge * @flags: Region state flags * @params: active + config params for the region + * @coord: QoS access coordinates for the region */ struct cxl_region { struct device dev; @@ -529,6 +530,7 @@ struct cxl_region { struct cxl_pmem_region *cxlr_pmem; unsigned long flags; struct cxl_region_params params; + struct access_coordinate coord; }; struct cxl_nvdimm_bridge { @@ -879,6 +881,9 @@ void cxl_switch_parse_cdat(struct cxl_port *port); int cxl_endpoint_get_perf_coordinates(struct cxl_port *port, struct access_coordinate *coord); +void cxl_region_perf_data_calculate(struct cxl_region *cxlr, + struct cxl_endpoint_decoder *cxled); + /* * Unit test builds overrides this to __weak, find the 'strong' version * of these symbols in tools/testing/cxl/. From patchwork Fri Dec 15 23:16:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Jiang X-Patchwork-Id: 13495181 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C345313B124 for ; Fri, 15 Dec 2023 23:16:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="MPAwRoKP" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1702682167; x=1734218167; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=JENTZPeCVTUyrzfz8NtGgBjzVAuC0yqW7jxOchOZ3Ak=; b=MPAwRoKP+7/Tr5snb/zIlRYFoBlUN78Fn32La+tuKGAbTIOxTgZu9Bq7 4j+UWhKtkZVTOMnV1ydoV2FyV0LOG1r63I072JY/fuFvdp2CMz3/kTSXy f8GUB5Ngt7AzP5XPVbnAvOCCA2PrDFLAD/gcG3H7qISkLFjKrcYl4XUcB SwkdJL9PKfGErsm38epFCZp5F47DrzioTkoT4oA2aMITyb490sngysqe+ Jgmm0Ve9lq9q+0pDDhR/0s7WZCGM3YwPqgZM4fqRbEfl2D3WYDxwBxdrH NOdhJTcafeR+x8i4NSag+6LJQbFch9vK2e8JmWNzqc4ko0kMtb1tPIKbo w==; X-IronPort-AV: E=McAfee;i="6600,9927,10925"; a="2192019" X-IronPort-AV: E=Sophos;i="6.04,280,1695711600"; d="scan'208";a="2192019" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Dec 2023 15:16:07 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10925"; a="1022091032" X-IronPort-AV: E=Sophos;i="6.04,280,1695711600"; d="scan'208";a="1022091032" Received: from djiang5-mobl3.amr.corp.intel.com (HELO [192.168.1.177]) ([10.213.188.77]) by fmsmga006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Dec 2023 15:16:06 -0800 Subject: [PATCH v2 2/3] cxl/region: Add sysfs attribute for locality attributes of CXL regions From: Dave Jiang To: linux-cxl@vger.kernel.org Cc: dan.j.williams@intel.com, ira.weiny@intel.com, vishal.l.verma@intel.com, alison.schofield@intel.com, jonathan.cameron@huawei.com, dave@stgolabs.net, brice.goglin@gmail.com, nifan.cxl@gmail.com Date: Fri, 15 Dec 2023 16:16:05 -0700 Message-ID: <170268216573.1381493.1848451783927736490.stgit@djiang5-mobl3> In-Reply-To: <170268206638.1381493.3891165173978942658.stgit@djiang5-mobl3> References: <170268206638.1381493.3891165173978942658.stgit@djiang5-mobl3> User-Agent: StGit/1.5 Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add read/write latencies and bandwidth sysfs attributes for the enabled CXL region. The bandwidth is the aggregated bandwidth of all devices that contribute to the CXL region. The latency is the worst latency of the device amongst all the devices that contribute to the CXL region. Signed-off-by: Dave Jiang --- v2: - Add units for documentation (Brice, Dan) - Add explanation initiator/target relation. (Brice) - Fix issue in commit log (Fan) --- Documentation/ABI/testing/sysfs-bus-cxl | 56 +++++++++++++++++++++++++++++++ drivers/cxl/core/region.c | 24 +++++++++++++ 2 files changed, 80 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-cxl b/Documentation/ABI/testing/sysfs-bus-cxl index fff2581b8033..e859f466a6b5 100644 --- a/Documentation/ABI/testing/sysfs-bus-cxl +++ b/Documentation/ABI/testing/sysfs-bus-cxl @@ -552,3 +552,59 @@ Description: attribute is only visible for devices supporting the capability. The retrieved errors are logged as kernel events when cxl_poison event tracing is enabled. + + +What: /sys/bus/cxl/devices/regionZ/read_bandwidth +Date: Apr, 2023 +KernelVersion: v6.8 +Contact: linux-cxl@vger.kernel.org +Description: + (RO) The aggregated read bandwidth of the region. The number is + the accumulated read bandwidth of all CXL memory devices that + contributes to the region in MB/s. Should be equivalent to + attributes in /sys/devices/system/node/nodeX/accessY/. See + Documentation/ABI/stable/sysfs-devices-node. + The host bus latency in the calculation is from proximity + domain 0 to the host bus proximity domain. + + +What: /sys/bus/cxl/devices/regionZ/write_bandwidth +Date: Apr, 2023 +KernelVersion: v6.8 +Contact: linux-cxl@vger.kernel.org +Description: + (RO) The aggregated write bandwidth of the region. The number is + the accumulated write bandwidth of all CXL memory devices that + contributes to the region in MB/s. Should be equivalent to + attributes in /sys/devices/system/node/nodeX/accessY/. See + Documentation/ABI/stable/sysfs-devices-node. + The host bus latency in the calculation is from proximity + domain 0 to the host bus proximity domain. + + +What: /sys/bus/cxl/devices/regionZ/read_latency +Date: Apr, 2023 +KernelVersion: v6.8 +Contact: linux-cxl@vger.kernel.org +Description: + (RO) The read latency of the region. The number is + the worst read latency of all CXL memory devices that + contributes to the region in nanoseconds. Should be + equivalent to attributes in /sys/devices/system/node/nodeX/accessY/. + See Documentation/ABI/stable/sysfs-devices-node. + The host bus latency in the calculation is from proximity + domain 0 to the host bus proximity domain. + + +What: /sys/bus/cxl/devices/regionZ/write_latency +Date: Apr, 2023 +KernelVersion: v6.8 +Contact: linux-cxl@vger.kernel.org +Description: + (RO) The write latency of the region. The number is + the worst write latency of all CXL memory devices that + contributes to the region in nanoseconds. Should be + equivalent to attributes in /sys/devices/system/node/nodeX/accessY/. + See Documentation/ABI/stable/sysfs-devices-node. + The host bus latency in the calculation is from proximity + domain 0 to the host bus proximity domain. diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index be7383e74ef5..d97fa5f32e86 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -645,6 +645,26 @@ static ssize_t size_show(struct device *dev, struct device_attribute *attr, } static DEVICE_ATTR_RW(size); +#define ACCESS_ATTR(attrib) \ +static ssize_t attrib##_show(struct device *dev, \ + struct device_attribute *attr, \ + char *buf) \ +{ \ + struct cxl_region *cxlr = to_cxl_region(dev); \ + \ + if (cxlr->coord.write_bandwidth == 0) \ + return 0; \ + \ + return sysfs_emit(buf, "%u\n", \ + cxlr->coord.attrib); \ +} \ +static DEVICE_ATTR_RO(attrib) + +ACCESS_ATTR(read_bandwidth); +ACCESS_ATTR(read_latency); +ACCESS_ATTR(write_bandwidth); +ACCESS_ATTR(write_latency); + static struct attribute *cxl_region_attrs[] = { &dev_attr_uuid.attr, &dev_attr_commit.attr, @@ -653,6 +673,10 @@ static struct attribute *cxl_region_attrs[] = { &dev_attr_resource.attr, &dev_attr_size.attr, &dev_attr_mode.attr, + &dev_attr_read_bandwidth.attr, + &dev_attr_write_bandwidth.attr, + &dev_attr_read_latency.attr, + &dev_attr_write_latency.attr, NULL, }; From patchwork Fri Dec 15 23:16:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Jiang X-Patchwork-Id: 13495182 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2695913B124 for ; Fri, 15 Dec 2023 23:16:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Cz2fcoKv" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1702682188; x=1734218188; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=lhh6h6VpcnNzOx7mMq5yvLv3XcBlAd+IWi1ASlHnI7A=; b=Cz2fcoKvA16h+HfN7roGFQINknc5eecAw2tNaqWw8MOobxjxHywB/v/K 0qdYmLYiZMnyDBMWfiL2+593vOMXzDKcoijzYHXRH6RwuuYo4ZnvBQpRN kpjd22Z0qLQlVCin7GPOHw+IKidXcOyjMqtE3CWhw2DYCYmIb2uU4z3To mM3KWNPVzVNM9wsGNwP4QXrcdfKpCQBMemY3YrHlqo5dRD+M41X3k+ine sWDRojkehYMz9hZo6mAOHbHCNZ9HVfpKOT21Xca+Qy5ZB/LiGRKJogUi6 aLb7mRAt7LtATYR7Bf1CT5LEQQizdEZUfp+BAEnFqAvmsitTMULw+4zrp g==; X-IronPort-AV: E=McAfee;i="6600,9927,10925"; a="2192036" X-IronPort-AV: E=Sophos;i="6.04,280,1695711600"; d="scan'208";a="2192036" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Dec 2023 15:16:13 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10925"; a="1022091049" X-IronPort-AV: E=Sophos;i="6.04,280,1695711600"; d="scan'208";a="1022091049" Received: from djiang5-mobl3.amr.corp.intel.com (HELO [192.168.1.177]) ([10.213.188.77]) by fmsmga006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Dec 2023 15:16:11 -0800 Subject: [PATCH v2 3/3] cxl: Add memory hotplug notifier for cxl region From: Dave Jiang To: linux-cxl@vger.kernel.org Cc: Greg Kroah-Hartman , "Rafael J. Wysocki" , "Huang, Ying" , dan.j.williams@intel.com, ira.weiny@intel.com, vishal.l.verma@intel.com, alison.schofield@intel.com, jonathan.cameron@huawei.com, dave@stgolabs.net, brice.goglin@gmail.com, nifan.cxl@gmail.com Date: Fri, 15 Dec 2023 16:16:11 -0700 Message-ID: <170268217159.1381493.10875292326564731198.stgit@djiang5-mobl3> In-Reply-To: <170268206638.1381493.3891165173978942658.stgit@djiang5-mobl3> References: <170268206638.1381493.3891165173978942658.stgit@djiang5-mobl3> User-Agent: StGit/1.5 Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 When the CXL region is formed, the driver would computed the performance data for the region. However this data is not available at the node data collection that has been populated by the HMAT during kernel initialization. Add a memory hotplug notifier to update the performance data to the node hmem_attrs to expose the newly calculated region performance data. The CXL region is created under specific CFMWS. The node for the CFMWS is created during SRAT parsing by acpi_parse_cfmws(). The notifier will run once only and turn itself off after the initial run. Additional regions may overwrite the initial data, but since this is for the same poximity domain it's a don't care for now. node_set_perf_attrs() is exported to allow update of perf attribs for a node. Given that only CXL is using this, export only to CXL namespace. Cc: Greg Kroah-Hartman Cc: Rafael J. Wysocki Reviewed-by: "Huang, Ying" Signed-off-by: Dave Jiang --- v2: - Fix notifier return values (Dan) - Use devm_add_action_or_reset() instead of adding a remove callback (Dan) - Add Ying review tag --- drivers/base/node.c | 1 + drivers/cxl/core/region.c | 42 ++++++++++++++++++++++++++++++++++++++++++ drivers/cxl/cxl.h | 3 +++ 3 files changed, 46 insertions(+) diff --git a/drivers/base/node.c b/drivers/base/node.c index cb2b6cc7f6e6..f5b5a3f11894 100644 --- a/drivers/base/node.c +++ b/drivers/base/node.c @@ -215,6 +215,7 @@ void node_set_perf_attrs(unsigned int nid, struct access_coordinate *coord, } } } +EXPORT_SYMBOL_NS_GPL(node_set_perf_attrs, CXL); /** * struct node_cache_info - Internal tracking for memory node caches diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index d97fa5f32e86..1765bf716484 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -4,6 +4,7 @@ #include #include #include +#include #include #include #include @@ -2960,6 +2961,42 @@ static int is_system_ram(struct resource *res, void *arg) return 1; } +static int cxl_region_perf_attrs_callback(struct notifier_block *nb, + unsigned long action, void *arg) +{ + struct cxl_region *cxlr = container_of(nb, struct cxl_region, + memory_notifier); + struct cxl_region_params *p = &cxlr->params; + struct cxl_endpoint_decoder *cxled = p->targets[0]; + struct cxl_decoder *cxld = &cxled->cxld; + struct memory_notify *mnb = arg; + int nid = mnb->status_change_nid; + int region_nid; + + if (nid == NUMA_NO_NODE || action != MEM_ONLINE) + return NOTIFY_DONE; + + region_nid = phys_to_target_node(cxld->hpa_range.start); + if (nid != region_nid) + return NOTIFY_DONE; + + /* Don't set if there's no coordinate information */ + if (!cxlr->coord.write_bandwidth) + return NOTIFY_DONE; + + node_set_perf_attrs(nid, &cxlr->coord, 0); + node_set_perf_attrs(nid, &cxlr->coord, 1); + + return NOTIFY_OK; +} + +static void remove_coord_notifier(void *data) +{ + struct cxl_region *cxlr = data; + + unregister_memory_notifier(&cxlr->memory_notifier); +} + static int cxl_region_probe(struct device *dev) { struct cxl_region *cxlr = to_cxl_region(dev); @@ -2985,6 +3022,11 @@ static int cxl_region_probe(struct device *dev) goto out; } + cxlr->memory_notifier.notifier_call = cxl_region_perf_attrs_callback; + cxlr->memory_notifier.priority = HMAT_CALLBACK_PRI; + register_memory_notifier(&cxlr->memory_notifier); + rc = devm_add_action_or_reset(&cxlr->dev, remove_coord_notifier, cxlr); + /* * From this point on any path that changes the region's state away from * CXL_CONFIG_COMMIT is also responsible for releasing the driver. diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 4639d0d6ef54..2498086c8edc 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -6,6 +6,7 @@ #include #include +#include #include #include #include @@ -520,6 +521,7 @@ struct cxl_region_params { * @flags: Region state flags * @params: active + config params for the region * @coord: QoS access coordinates for the region + * @memory_notifier: notifier for setting the access coordinates to node */ struct cxl_region { struct device dev; @@ -531,6 +533,7 @@ struct cxl_region { unsigned long flags; struct cxl_region_params params; struct access_coordinate coord; + struct notifier_block memory_notifier; }; struct cxl_nvdimm_bridge {